Pixel

Abstract

A pixel comprises: a light-emitting element; a first transistor comprising a first electrode and a second electrode respectively connected to a power supply and the light-emitting element, the first transistor controlling a driving current; a first capacitor between a second node and a third node; a second transistor between the third node and a data line and turned on by a scan signal; a third transistor between the first node and the second node and turned on by a control signal; a fourth transistor between the power supply and the third node and turned on by an emission control signal; a fifth transistor between the power supply and the first electrode and turned on by the emission control signal; a sixth transistor between the second node and the light-emitting element and turned on by another emission control signal; and a second capacitor between the power supply and the first node, wherein during a non-emission period, the fourth transistor, the fifth transistor and the sixth transistor are turned on / off at least four times.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0088450 filed on July 22, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to a display device, and more particularly, to a pixel and a display device including the pixel. Background Art

[0004] A display device is an output device for presenting information in a visual form. Typically, a display device includes a plurality of pixels. Each of the pixels can emit light based on a data signal supplied to a drive transistor.

[0005] A method of driving a display device using a low frequency (e.g., 1 Hz) can be used to minimize power consumption. However, when a display device is driven at a low frequency, the displayed image may flicker. In order to prevent the image from flickering, a technique of minimizing the leakage of the data signal stored in each pixel can be used.

[0006] In addition to low-frequency driving, the display device can be driven at a high frequency (e.g., 120 Hz) to achieve high resolution or three-dimensional images. However, in order to ensure image quality at a predetermined level or higher under high-speed driving conditions, a sufficient amount of time should be given to compensate for the threshold voltage of the driving transistor. Summary of the invention

[0007] An exemplary embodiment of the present invention may provide a pixel, comprising: a light emitting element; a first transistor, comprising a first electrode electrically coupled to a first power source and a second electrode electrically coupled to the light emitting element, the first transistor being configured to control a driving current; a first capacitor, coupled between a second node and a third node, wherein the second node is connected to the second electrode of the first transistor; a second transistor, coupled between the third node and a data line, and configured to be turned on by a scan signal; a third transistor, coupled between the first node and the second node, and configured to be turned on by a control signal, wherein the first node is connected to the gate electrode of the first transistor; a fourth transistor, coupled between the first power supply and the third node, and configured to be turned on by the first emission control signal; a fifth transistor, coupled between the first power supply and the first electrode of the first transistor, and configured to be turned on by the first emission control signal; a sixth transistor, coupled between the second node and the light emitting element, and configured to be turned on by the second emission control signal; and a second capacitor, coupled between the first power supply and the first node, wherein, during a non-emission period in a frame, each of the fourth transistor, the fifth transistor and the sixth transistor repeats a turn-on operation and a turn-off operation at least four times in response to the first emission control signal or the second emission control signal.

[0008] During the non-emission period, each of the first emission control signal and the second emission control signal may include a plurality of gate-on periods and a plurality of gate-off periods.

[0009] The non-emission period may include a turn-on bias period in which each of the second emission control signal and the control signal has a gate-off level and the first emission control signal has a gate-on level.

[0010] During the on-bias period, the third transistor and the sixth transistor may be turned off, and the fourth transistor and the fifth transistor may be turned on.

[0011] When the third transistor, the fourth transistor, and the fifth transistor are turned on, the second transistor and the sixth transistor may be turned off.

[0012] The pixel may further include: a seventh transistor coupled between the light emitting element and the initialization power source and configured to be turned on by the control signal.

[0013] The non-emission period may include a first initialization period in which an initialization power supply is supplied to a fourth node between the light emitting element and the seventh transistor, a second initialization period in which an initialization power supply is supplied to the fourth node and the first node, an on-bias period in which the first transistor has an on-bias state, a compensation period in which the first transistor is diode-connected based on the voltage of the first power supply, and a writing period in which the second transistor is turned on so that a data signal is supplied through the data line.

[0014] In response to the control signal, the third transistor may be turned on during the second initialization period, the compensation period, and the writing period, and may be turned off during the on-bias period.

[0015] During the non-emission period, at least one of the second initialization period, the on-bias period, and the compensation period may be repeated at least twice.

[0016] During each of the first initialization period, the second initialization period, the on-bias period, and the compensation period, a switching operation of each of the fourth transistor and the fifth transistor may be performed opposite to a switching operation of the sixth transistor.

[0017] During the second initialization period, the third transistor, the sixth transistor, and the seventh transistor may be turned on, and the fourth transistor and the fifth transistor may be turned off, so that the first transistor has a turned-off bias state.

[0018] During the compensation period, the third, fourth and fifth transistors may be turned on and the second and sixth transistors may be turned off, and during the writing period, the second and third transistors may be turned on and the fourth, fifth and sixth transistors may be turned off.

[0019] The length of the compensation period may be greater than the length of the writing period.

[0020] During the writing period, a gate-off period of the control signal may overlap a portion of a gate-on period of the scan signal, and the third transistor may be turned off while the second transistor remains turned on during the writing period.

[0021] The first emission control signal may be obtained by shifting the second emission control signal by k horizontal periods, where k is an integer greater than or equal to three.

[0022] An exemplary embodiment of the present invention may provide a display device, comprising: a display panel including a plurality of pixels; a first scan driver configured to supply scan signals to the pixels through a plurality of scan lines; a second scan driver configured to supply control signals to the pixels through a plurality of control lines; an emission driver configured to supply emission control signals to the pixels through a plurality of emission control lines; and a data driver configured to supply data voltages to the display panel through a plurality of data lines, wherein each of the pixels comprises: a light emitting element; a first transistor comprising a first electrode electrically coupled to a first power source and a second electrode electrically coupled to the light emitting element, the first transistor being configured to control a driving current; a first capacitor coupled between a second node and a third node, wherein the second node is connected to the second electrode of the first transistor; a second transistor coupled between the third node and a corresponding one of the data lines, and and is configured to be turned on by a scan signal; a third transistor, coupled between the first node and the second node, and configured to be turned on by a control signal, wherein the first node is connected to the gate electrode of the first transistor; a fourth transistor, coupled between the first power supply and the third node, and configured to be turned on by an emission control signal; a fifth transistor, coupled between the first power supply and the first electrode of the first transistor, and configured to be turned on by an emission control signal; a sixth transistor, coupled between the second node and the light emitting element, and configured to be turned on by a prior emission control signal; a seventh transistor, coupled between the light emitting element and the initialization power supply, and configured to be turned on by a control signal; and a second capacitor, coupled between the first power supply and the first node, wherein, during a non-emission period in a frame, each of the fourth transistor, the fifth transistor, and the sixth transistor repeats a turn-on operation and a turn-off operation at least four times.

[0023] The non-emission period may include a conduction bias period in which each of the previous emission control signal and the control signal has a gate-off level and the emission control signal has a gate-on level, and during the conduction bias period, the third transistor and the sixth transistor may be turned off, and the fourth transistor and the fifth transistor may be turned on.

[0024] The emission driver may simultaneously supply the emission control signal to the fourth transistor and the fifth transistor of the nth pixel disposed on the nth pixel row and the fourth transistor and the fifth transistor of the n+1th pixel disposed on the n+1th pixel row.

[0025] The second scan driver may simultaneously supply control signals to the third transistor and the seventh transistor of the n-th pixel and the third transistor and the seventh transistor of the (n+1)-th pixel.

[0026] The non-emission period may include a cut-off bias period in which each of the prior emission control signal and the control signal has a gate-on level and the emission control signal has a gate-off level, and during the cut-off bias period, the third transistor and the sixth transistor may be turned on, the fourth transistor and the fifth transistor may be turned off, and the first transistor may have a cut-off bias state.

[0027] An exemplary embodiment of the present invention may provide a pixel, comprising: a light emitting element; a first transistor, comprising a first electrode electrically coupled to a first power source and a second electrode electrically coupled to the light emitting element, the first transistor being configured to control a driving current; a first capacitor coupled to the second electrode of the first transistor; a second transistor coupled between a data line and the first capacitor and configured to be turned on by a scan signal; a third transistor coupled between a gate electrode of the first transistor and the second electrode of the first transistor; a fourth transistor coupled between the first power source and the second capacitor and configured to be turned on by a first emission control signal; a fifth transistor coupled between the first power source and the first electrode of the first transistor and configured to be turned on by the first emission control signal; a sixth transistor coupled between the second electrode of the first transistor and the light emitting element and configured to be turned on by a second emission control signal; and a second capacitor coupled between the first power source and the gate electrode of the first transistor, wherein during a non-emission period in a frame, each of the fourth transistor, the fifth transistor and the sixth transistor repeatedly performs a turn-on operation and a turn-off operation at least four times in response to the first emission control signal or the second emission control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0029] Figure 2A is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0030] Figure 2B is used to describe the supply to Figure 2A Circuit diagram of the pixel signals shown in FIG.

[0031] Figure 3 Is used to describe Figure 2A and Figure 2B A timing diagram of an example of a pixel operation.

[0032] Figure 4 Is used to describe Figure 1 A timing diagram of an example of the operation of a display device.

[0033] Figure 5 Is used to describe Figure 2A and Figure 2BA timing diagram of an example of a pixel operation.

[0034] Figure 6 Is used to describe Figure 2A and Figure 2B A timing diagram of an example of a pixel operation.

[0035] Fig. 7A Is used to describe Figure 2A A timing diagram of an example of a pixel operation.

[0036] Figure 7B Is used to describe Figure 2A A timing diagram of an example of a pixel operation.

[0037] Figure 8 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0038] Fig. 9 Is used to describe Figure 8 A timing diagram of an example of a pixel operation.

[0039] Fig.10 Is used to describe Figure 8 A timing diagram of an example of a pixel operation.

[0040] Fig.11 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0041] Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the accompanying drawings, the same or similar elements may be represented by the same reference numerals, and therefore, repeated description of the same or similar elements may be omitted.

[0042] Figure 1 is a block diagram illustrating a display apparatus 1000 according to an exemplary embodiment of the present invention.

[0043] refer to Figure 1 , the display device 1000 may include a display panel 100 , a first scan driver 200 , a second scan driver 300 , an emission driver 400 , a data driver 500 , and a timing controller 600 .

[0044] In an exemplary embodiment of the present invention, the display device 1000 may further include a power supply configured to control the voltage of the first power supply VDD, the voltage of the second power supply VSS, and the voltage of the third power supply (or initialization power supply Vint) applied to the display panel 100. The power supply may apply a low power supply and a high power supply to the first scan driver 200, the second scan driver 300, and / or the emission driver 400. The low power supply and the high power supply may determine whether the level of the scan signal, the control signal, and / or the emission control signal is a gate-on level or a gate-off level. The low power supply may have a voltage level lower than the voltage level of the high power supply. However, this is merely exemplary. At least one of the first power supply VDD, the second power supply VSS, the initialization power supply Vint, the low power supply, and the high power supply may be supplied from the timing controller 600 or the data driver 500.

[0045] In an exemplary embodiment of the present invention, the first power supply VDD and the second power supply VSS may generate a voltage for driving the light emitting element. In an exemplary embodiment of the present invention, the voltage of the second power supply VSS may be lower than the voltage of the first power supply VDD. For example, the voltage of the first power supply VDD may be a positive voltage, and the voltage of the second power supply VSS may be a negative voltage.

[0046] The initialization power source Vint may be a power source for initializing the pixel PX. For example, a driving transistor and / or a light emitting element included in the pixel PX may be initialized by the voltage of the initialization power source Vint. The initialization power source Vint may be a negative voltage.

[0047] The display panel 100 may include a plurality of scan lines SL, a plurality of control lines CL, a plurality of emission control lines EL, and a plurality of data lines DL. The display panel 100 may further include a plurality of pixels PX coupled to the scan lines SL, the control lines CL, the emission control lines EL, and the data lines DL. In an exemplary embodiment of the present invention, the pixels PX disposed on the nth row and the mth column (where n and m are each a natural number) may be coupled to the scan line SLn corresponding to the nth pixel row, the control line CLn corresponding to the nth pixel row, the emission control line ELn corresponding to the nth pixel row, the emission control line ELn-k corresponding to the nkth pixel row (k is a natural number equal to or less than 10), and the data line DLm corresponding to the mth pixel column.

[0048] The timing controller 600 may generate a first drive control signal SCS1, a second drive control signal SCS2, a third drive control signal ECS, and a fourth drive control signal DCS in response to a synchronization signal supplied from an external device. The first drive control signal SCS1 may be supplied to the first scan driver 200. The second drive control signal SCS2 may be supplied to the second scan driver 300. The third drive control signal ECS may be supplied to the emission driver 400. The fourth drive control signal DCS may be supplied to the data driver 500. The timing controller 600 may rearrange the input image data supplied from the external device to generate image data RGB, and then supply the image data RGB to the data driver 500.

[0049] The first driving control signal SCS1 may include a first scanning start pulse and a clock signal. The first scanning start pulse may control a first timing of the scanning signal. The clock signal of the first driving control signal SCS1 may be used to shift the first scanning start pulse.

[0050] The second drive control signal SCS2 may include a second scan start pulse (e.g., a start pulse of the control signal) and a clock signal. The second scan start pulse may control the first timing of the control signal. The clock signal of the second drive control signal SCS2 may be used to shift the second scan start pulse. In an exemplary embodiment of the present invention, the control signal may be a scan signal (e.g., a second scan signal) different from the scan signal (e.g., a first scan signal) output from the first scan driver 200.

[0051] The third driving control signal ECS may include an emission control start pulse and a clock signal. The emission control start pulse may control the first timing of the emission control signal. The clock signal of the third driving control signal ECS may be used to shift the emission control start pulse.

[0052] The fourth driving control signal DCS may include a source start pulse and a clock signal. The source start pulse may control the time when data sampling starts. The clock signal of the fourth driving control signal DCS may be used to control the sampling operation.

[0053] The first scan driver 200 may receive a first drive control signal SCS1 from the timing controller 600, and supply a scan signal to the scan line SL based on the first drive control signal SCS1. For example, the first scan driver 200 may sequentially supply a scan signal (e.g., a first scan signal) to the scan line SL (e.g., a first scan line) at intervals of one horizontal period (1H). When the scan signal is sequentially supplied, the pixel PX may be selected based on a horizontal line (or based on a pixel row), and a data signal may be supplied to the pixel PX. The scan signal is used to write data.

[0054] Each scan signal may be set to a gate-on level (eg, a low voltage). When the scan signal is supplied to a transistor included in each pixel PX and receiving the scan signal, the transistor may be turned on.

[0055] In an exemplary embodiment of the present invention, the first scan driver 200 may supply a scan signal to each of the scan lines SL once during one frame period.

[0056] The second scan driver 300 may receive a second drive control signal SCS2 from the timing controller 600, and supply a control signal (e.g., a second scan signal) to the control line CL (e.g., a second scan line) based on the second drive control signal SCS2. For example, the second scan driver 300 may supply the control signal to the control line CL in sequence at intervals longer than one horizontal period (1H) (e.g., corresponding to two horizontal periods). When the control signal is supplied, the pixels PX may each perform a threshold voltage compensation and / or initialization operation. For example, a threshold voltage compensation operation may be performed to compensate for the threshold voltage of the driving transistor of the pixel PX.

[0057] In an exemplary embodiment of the present invention, the second scan driver 300 may supply control signals to consecutive pixel rows simultaneously. For example, the second scan driver 300 may supply the same control signal to the nth control line CLn and the n+1th control line CLn+1 simultaneously (see Figure 2B ). In other words, the second scan driver 300 may shift a control signal and supply the control signal to each of two or more control lines, and consecutive pixel rows corresponding to the control lines may share the same control signal.

[0058] In this case, the number of stages included in the second scan driver 300 to shift and output the control signal may be smaller than the number of stages included in the first scan driver 200 .

[0059] The control signal may be set to a gate-on level (eg, a low voltage). When the control signal is supplied to a transistor included in each pixel PX and receiving the control signal, the transistor may be turned on.

[0060] The control signal may be supplied for initialization and / or threshold voltage compensation of the pixel PX.

[0061] The emission driver 400 may receive the third driving control signal ECS from the timing controller 600 and supply the emission control signal to the emission control line EL based on the third driving control signal ECS. For example, the emission driver 400 may sequentially supply the emission control signal to the emission control line EL.

[0062] In an exemplary embodiment of the present invention, the emission driver 400 may supply the emission control signal to consecutive pixel rows at the same time. For example, the emission driver 400 may supply the same emission control signal to the nth emission control line ELn and the n+1th emission control line ELn+1 at the same time (see Figure 2B ). In other words, the emission driver 400 may shift the emission control signal and supply the emission control signal to each of two or more emission control lines, and consecutive pixel rows corresponding to the emission control lines may share the same emission control signal.

[0063] In this case, the number of stages included in the emission driver 400 to shift and output the emission control signal may be smaller than the number of stages included in the first scan driver 200 .

[0064] The emission control signal may be set to a gate-on level (e.g., a low voltage). When the emission control signal is supplied to a transistor included in each pixel PX and receiving the emission control signal, the transistor may be turned on, and may be turned off in other cases. For example, when the emission control signal is not supplied to the transistor, the transistor may be turned off.

[0065] The emission control signal is used to control the emission time of the pixel PX. In an exemplary embodiment of the present invention, the emission control signal may have a width greater than that of the scan signal.

[0066] In an exemplary embodiment of the present invention, during one frame period, the emission control signal may have multiple gate-off level (e.g., high voltage) periods. For example, the emission control signal may include multiple gate-on periods and multiple gate-off periods for bias state control, initialization, and threshold voltage compensation of the driving transistor.

[0067] The first scan driver 200, the second scan driver 300, and the emission driver 400 may each be mounted on a substrate by a thin film process. The first scan driver 200 and the second scan driver 300 may be disposed on opposite sides of the display panel 100, respectively. The emission driver 400 may also be disposed on opposite sides of the display panel 100. However, the present invention is not limited thereto, and as Figure 1 As shown in FIG. 1 , the first scan driver 200 and the second scan driver 300 may be disposed on the same side of the display panel 100 .

[0068] The data driver 500 may receive a fourth drive control signal DCS and image data RGB from the timing controller 600. The data driver 500 may supply a data signal to the data line DL in response to the fourth drive control signal DCS. The data signal supplied to the data line DL may be supplied to the pixel PX selected by the scan signal. To do this, the data driver 500 may supply the data signal to the data line DL in synchronization with the scan signal.

[0069] Figure 2A is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0070] Figure 2A The pixels 10 disposed on an n-th horizontal line (or an n-th pixel row) and coupled to an m-th data line DLm are shown.

[0071] In an exemplary embodiment of the present invention, the previous emission control line ELn-k may supply the same emission control signal as the emission control signal to be supplied to the emission control line coupled to the nk-th pixel row.

[0072] refer to Figure 2A , the pixel 10 may include a light emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

[0073] In an exemplary embodiment of the present invention, the first to seventh transistors T1 to T7 may be of the same type. For example, each of the first to seventh transistors T1 to T7 may be a P-channel metal oxide semiconductor (PMOS) transistor. Each of the first to seventh transistors T1 to T7 may include an active layer formed of a polysilicon semiconductor. For example, the active layer of each of the first to seventh transistors T1 to T7 may be formed by a low temperature polysilicon (LTPS) process.

[0074] The first electrode of the light emitting element LD may be electrically coupled to the second electrode (e.g., drain electrode) of the first transistor T1, and the second electrode of the light emitting element LD may be coupled to the second power supply VSS. For example, the first electrode of the light emitting element LD may be coupled to the fourth node N4, and one electrode of the sixth transistor T6 and one electrode of the seventh transistor T7 may be commonly coupled to the fourth node N4.

[0075] The light emitting element LD may emit light having a predetermined brightness corresponding to the amount of current (e.g., a driving current) supplied from the first transistor T1. In an exemplary embodiment of the present invention, the light emitting element LD may be an organic light emitting diode including an organic light emitting layer. In this case, the first electrode of the light emitting element LD is an anode electrode, and the second electrode of the light emitting element LD is a cathode electrode. Alternatively, the first electrode of the light emitting element LD may be a cathode electrode, and the second electrode of the light emitting element LD may be an anode electrode.

[0076] In an exemplary embodiment of the present invention, the light emitting element LD may be an inorganic light emitting element formed of an inorganic material. The light emitting element LD may include a plurality of inorganic light emitting elements coupled in parallel and / or in series between the second power source VSS and the second electrode of the first transistor T1.

[0077] The first transistor T1 may be electrically coupled between the first power source VDD and the first electrode of the light emitting element LD. The first transistor T1 may generate a driving current and provide the driving current to the light emitting element LD. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may be used as a driving transistor of the pixel 10. The first transistor T1 may control the amount of current flowing from the first power source VDD to the second power source VSS via the light emitting element LD in response to a voltage applied to the first node N1.

[0078] The first capacitor C1 may be coupled between the second node N2 corresponding to the second electrode of the first transistor T1 and the third node N3. For example, the second node N2 may be connected to the second electrode of the first transistor T1. The first capacitor C1 may store a voltage corresponding to a voltage difference between the second node N2 and the third node N3.

[0079] The second capacitor C2 may be coupled between the first power source VDD and the first node N1. The second capacitor C2 may store a voltage corresponding to a voltage difference between the first power source VDD and the first node N1.

[0080] In the case where a data signal is written to the pixel 10 , the first node N1 and the second node N2 may have voltages determined according to a capacitance ratio between the first capacitor C1 and the second capacitor C2 through charge sharing between the first capacitor C1 and the second capacitor C2 .

[0081] The second transistor T2 may be coupled between the data line DLm and the third node N3. The second transistor T2 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the second transistor T2 may be coupled to a scan line SLn (e.g., an nth scan line). When the scan signal is supplied to the scan line SLn, the second transistor T2 may be turned on so that the data line DLm may be electrically coupled to the third node N3. Therefore, the data voltage (or data signal) may be transmitted to the third node N3.

[0082] The third transistor T3 may be coupled between a first node N1 corresponding to the gate electrode of the first transistor T1 and a second node N2 (e.g., a drain electrode of the first transistor T1). The first node N1 may be connected to the gate electrode of the first transistor T1. The third transistor T3 may include a gate electrode for receiving a control signal. For example, the gate electrode of the third transistor T3 may be coupled to a control line CLn (e.g., an nth control line). When the control signal is supplied to the control line CLn, the third transistor T3 may be turned on so that the first node N1 may be electrically coupled to the second node N2. When the third transistor T3 is turned on, the voltage of the initialization power supply Vint may be supplied to the first node N1, or the first transistor T1 may have a diode connection form. In the case where the first transistor T1 has a diode connection form (in other words, is diode-connected), the threshold voltage of the first transistor T1 may be compensated.

[0083] Therefore, the first transistor T1 may generate a driving current listed by the following [Equation 1] based on the data signal and the first and second capacitors C1 and C2.

[0084] [Equation 1]

[0085] Id=k[a(Vdd-Vdata)] 2 , a=CC2 / (CC1+CC2),

[0086] Here, Id may represent a driving current, k may represent a characteristic value of the first transistor T1, Vdd may represent a voltage of a first power supply VDD, Vdata may represent a data signal, CC1 may represent a capacitance of a first capacitor C1, and CC2 may represent a capacitance of a second capacitor C2. The light emitting element LD may emit light with a brightness corresponding to the driving current Id.

[0087] exist Figure 2A In the description of FIG. 1 , the signal line coupled to the gate electrode of the third transistor T3 and the signal supplied thereto are respectively referred to as the control line CLn and the control signal, and it should be understood that the control line CLn may be a scan line different from the scan line SLn. The scan signal of the scan line SLn may be supplied from the first scan driver 200, and the control signal of the control line CLn may be supplied from the second scan driver 300.

[0088] The fourth transistor T4 may be coupled between the first power source VDD and the third node N3. The fourth transistor T4 may include a gate electrode for receiving an emission control signal.

[0089] In an exemplary embodiment of the present invention, the gate electrode of the fourth transistor T4 may be coupled to an emission control line ELn (e.g., an nth emission control line). When an emission control signal is supplied to the emission control line ELn, the fourth transistor T4 may be turned on so that the voltage of the first power supply VDD may be supplied to the third node N3. Therefore, the voltage of the third node N3 may be initialized to the voltage of the first power supply VDD.

[0090] During a period in which the threshold voltage compensation of the first transistor T1 is performed, the fourth transistor T4 may be turned on. Therefore, the voltage of the first power source VDD (eg, a direct current (DC) voltage) may be used for the threshold voltage compensation of the first transistor T1.

[0091] The fifth transistor T5 may be coupled between the first power supply VDD and the first electrode of the first transistor T1. The fifth transistor T5 may include a gate electrode for receiving an emission control signal. For example, the gate electrode of the fifth transistor T5 may be coupled to the emission control line ELn. When the emission control signal is supplied to the fifth transistor T5, the fifth transistor T5 may be turned on. In this case, the first electrode of the first transistor T1 may be coupled to the first power supply VDD.

[0092] When the fourth transistor T4 and the fifth transistor T5 are turned on and the third transistor T3 is turned off, the high voltage of the first power source VDD is supplied to the first electrode of the first transistor T1 so that the first transistor T1 may have an on bias state.

[0093] The sixth transistor T6 may be coupled between the second node N2 corresponding to the second electrode of the first transistor T1 and the light emitting element LD. For example, the sixth transistor T6 may be connected to the first electrode of the light emitting element LD. The sixth transistor T6 may include a gate electrode for receiving a prior emission control signal. For example, the gate electrode of the sixth transistor T6 may be coupled to a prior emission control line ELn-k (e.g., a nk-th emission control line).

[0094] For example, the prior emission control line ELn-k may be a line branched from the n-6th emission control line. In this case, each of the threshold voltage compensation period and the initialization period may correspond to approximately six horizontal periods (6H). Alternatively, the prior emission control line ELn-k may be the n-3rd emission control line. In this case, each of the threshold voltage compensation period and the initialization period may correspond to approximately three horizontal periods (3H). Hereinafter, description will be made based on the assumption that the prior emission control line ELn-k is the n-6th emission control line.

[0095] However, this is for illustration purposes only, and therefore the emission control line from which the prior emission control line branches is not limited to the aforementioned example. For example, the prior emission control line may be determined by the time required for threshold voltage compensation, the number of pixel rows controlled at the same time, the resolution, the length of one horizontal period (1H), etc.

[0096] When the emission control signal is supplied to the previous emission control line ELn-k, the sixth transistor T6 is turned on so that the second node N2 may be electrically coupled to the fourth node N4.

[0097] When both the fifth transistor T5 and the sixth transistor T6 are turned on, the light emitting element LD can emit light at a brightness corresponding to the voltage of the first node N1. In an exemplary embodiment of the present invention, when the fifth transistor T5 is turned on and the sixth transistor T6 is turned off, threshold voltage compensation of the first transistor T1 can be performed, or a turn-on bias can be applied to the first transistor T1.

[0098] The seventh transistor T7 may be coupled between the light emitting element LD and the initialization power supply Vint. The fourth node N4 may be located on a path between the seventh transistor T7 and the light emitting element LD. The seventh transistor T7 may include a gate electrode for receiving a control signal. In an exemplary embodiment of the present invention, the gate electrode of the seventh transistor T7 may be coupled to the control line CLn. Therefore, the seventh transistor T7 and the third transistor T3 may be operated in substantially the same manner by the same control signal.

[0099] When the control signal is supplied to the control line CLn, the seventh transistor T7 may be turned on so that the voltage of the initialization power source Vint may be supplied to the fourth node N4. Therefore, the voltage of the fourth node N4 may be initialized to the voltage of the initialization power source Vint.

[0100] The period during which the second transistor T2 is turned on and the period during which the fourth transistor T4 and the fifth transistor T5 are turned on may not overlap with each other. For example, when the third to fifth transistors T3 to T5 are turned on, the threshold voltage compensation of the first transistor T1 is performed. When the second transistor T2 and the third transistor T3 are turned on, a data write operation may be performed. Therefore, the threshold voltage compensation period and the data write period may be separated from each other.

[0101] Due to the repetition of supply of the emission control signal, threshold voltage compensation and pixel initialization operations (eg, operations of initializing the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1) may be repeatedly performed.

[0102] Will refer to Figure 3 A detailed method of driving the pixel 10 is described.

[0103] Figure 2B is used to describe the supply to Figure 2A Circuit diagram of the pixel signal.

[0104] refer to Figure 2A and Figure 2B , an n-th pixel PXn disposed on an n-th pixel row and an n+1-th pixel PXn+1 disposed on an n+1-th pixel row may have substantially the same pixel structure.

[0105] The following description will be made on the assumption that both the n-th pixel PXn and the (n+1)-th pixel PXn+1 are coupled to the m-th data line DLm.

[0106] The nth scan signal Sn may be supplied to the nth scan line SLn, and the n+1th scan signal Sn+1 may be supplied to the n+1th scan line SLn+1. The n+1th scan signal Sn+1 may be a scan signal obtained by shifting (e.g., delaying) the nth scan signal Sn by one horizontal period (1H).

[0107] The pth (p is a natural number) emission control signal Ep may be commonly supplied to the nth emission control line ELn and the n+1th emission control line ELn+1. In other words, the nth pixel PXn and the n+1th pixel PXn+1 may be commonly controlled by the same emission control signal Ep. Therefore, during one frame period, the number of emission control signals to be supplied to the display panel 100 may be less than the number of scan signals to be supplied to the display panel 100.

[0108] For example, in the case where one emission control signal is commonly supplied to two emission control lines, the number of emission control signals may be half the number of scan signals.

[0109] In an exemplary embodiment of the present invention, the p-th emission control signal Ep may be obtained by shifting (eg, delaying) the p-1-th emission control signal by two or more horizontal periods (eg, 2H or more).

[0110] The pqth emission control signal Ep-q may be commonly supplied to the nkth emission control line ELn-k and the n-k+1th emission control line ELn-k+1. In addition, the pth emission control signal Ep may be obtained by shifting the pqth emission control signal Ep-q by q*2 or more horizontal periods (e.g., 2qH or more).

[0111] Hereinafter, the description will be made under the assumption that n is greater than k and p is greater than q. However, the relationship between n and k and the relationship between p and q are arbitrarily set for the purpose of explaining the signal supply timing. Therefore, it should be understood that even when n is greater than k, Figure 3 The supply timing of the emission control signals of ELn, ELn-k, etc. is also shifted, and the emission control signals are supplied to the corresponding emission control lines (for example, ELn and ELn-k).

[0112] The pth control signal Cp may be commonly supplied to the nth control line CLn and the n+1th control line CLn+1. In other words, the nth pixel PXn and the n+1th pixel PXn+1 may be commonly controlled by the same control signal Cp.

[0113] For example, in the case where one control signal is commonly supplied to two control lines, the number of control signals may be half the number of scan signals.

[0114] In an exemplary embodiment of the present invention, the p-th control signal Cp may be obtained by shifting (eg, delaying) the p-1-th control signal by two or more horizontal periods (eg, 2H or more).

[0115] In other words, the scan line can be controlled in pixel row units, and the emission control line and the control line can be commonly controlled in preset continuous pixel row units. Therefore, a high-speed driving operation of the display device 1000 having a driving frequency greater than 60 Hz can be easily achieved.

[0116] Figure 3 Is used to describe Figure 2A and Figure 2B A timing diagram of an example of a pixel operation.

[0117] refer to Figure 2A , Figure 2B and Figure 3, the pth emission control signal Ep may be supplied to the nth emission control line ELn, the nth scan signal Sn may be supplied to the nth scan line SLn, and the pth control signal Cp may be supplied to the nth control line CLn. In addition, the previous emission control signal Ep-q may be supplied to the previous emission control line ELn-k. The n+1th scan signal Sn+1 may be supplied to the n+1th scan line SLn+1.

[0118] Hereinafter, for the sake of explanation, the term “nth emission control line ELn” may be used interchangeably with the term “emission control line ELn”, the term “pth emission control signal Ep” may be used interchangeably with the term “emission control signal Ep”, the term “nth scan line SLn” may be used interchangeably with the term “scan line SLn”, the term “nth scan signal Sn” may be used interchangeably with the term “scan signal Sn”, the term “nth control line CLn” may be used interchangeably with the term “control line CLn”, and the term “pth control signal Cp” may be used interchangeably with the term “control signal Cp”.

[0119] The emission control signal Ep, the previous emission control signal Ep-q, and the control signal Cp may be commonly supplied to the n-th pixel PXn and the (n+1)-th pixel PXn+1.

[0120] In an exemplary embodiment of the present invention, the emission control signal Ep can be obtained by shifting the previous emission control signal Ep-q by about six horizontal periods (6H). In addition, the previous emission control signal Ep-q can be the same as the emission control signal supplied to the n-6th pixel (e.g., the n-6th emission control line).

[0121] Figure 3 The timing diagram of FIG. 1 shows a portion of a waveform during one frame period. During a period (e.g., the ninth period P9) in which each of the emission control signal Ep and the previous emission control signal Ep-q has a gate-on level (e.g., a low voltage), the nth pixel PXn and the n+1th pixel PXn+1 may emit light.

[0122] like Figure 3 As shown in , the emission control signal Ep may have four gate-off periods (e.g., periods in which the emission control signal Ep has a logic high voltage). However, this is for illustration purposes only. For example, during one frame period, the emission control signal Ep may have five or more gate-off periods. In addition, the emission control signal Ep may have less than four gate-off periods.

[0123] A gate-on level of each of the scan signal Sn, the control signal Cp, and the emission control signals Ep and Ep-q may be a low voltage.

[0124] At the first time t1, the prior emission control signal Ep-q may transition from the gate-on level to the gate-off level. Thus, the sixth transistor T6 may be turned off. The anode electrode of the light emitting element LD may float from the fourth node N4 by turning off the sixth transistor T6. Therefore, a recoil phenomenon regarding the anode voltage may occur. In this case, a pixel with a black grayscale may be bright, not black.

[0125] To prevent this from happening, at the first time t1, the control signal Cp may transition from the gate-off level to the gate-on level. Therefore, at the first time t1, the third transistor T3 and the seventh transistor T7 may be turned on. The initialization power source Vint may be supplied to the fourth node N4.

[0126] Since the fourth transistor T4 remains turned on, the voltage of the first power source VDD may be supplied to the third node N3 .

[0127] During the first period P1 from the first time t1 to the second time t2, the voltage of the initialization power source Vint may be supplied to the fourth node N4. In other words, the first period P1 may be a first initialization period in which the anode voltage of the light emitting element LD is initialized.

[0128] Although Figure 3 It is shown that the transition time of the first emission control signal Ep-q is the same as the transition time of the control signal Cp, but the control signal Cp can transition to the gate-on level at the time between the first time t1 and the second time t2. In other words, the control signal Cp can transition to the gate-on level after the first emission control signal Ep-q transitions to the gate-off level.

[0129] In an exemplary embodiment of the present invention, the control signal Cp may be maintained at a gate-on level before the emission time of the pixels PXn and PXn+1, and the third transistor T3 and the seventh transistor T7 may be turned on before the emission time of the pixels PXn and PXn+1. For example, the third transistor T3 and the seventh transistor T7 may remain turned on from the first time t1 to the tenth time t10.

[0130] At the second time t2, the previous emission control signal Ep-q can be changed from the gate-off level to the gate-on level, and the emission control signal Ep can be changed from the gate-on level to the gate-off level. At the second time t2, the fourth transistor T4 and the fifth transistor T5 can be turned off, and the sixth transistor T6 can be turned on. Here, the third transistor T3 and the seventh transistor T7 can remain turned on. Therefore, the voltage of the initialization power supply Vint can be supplied to the gate electrode (e.g., the first node N1) of the first transistor T1 through the third transistor T3 and the sixth transistor T6.

[0131] During the second period P2 from the second time t2 to the third time t3, the previous emission control signal En-k and the emission control signal En may have waveforms opposite to each other. Therefore, the second period P2 may be a second initialization period in which the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 are initialized. During the second period P2, the gate voltage and drain voltage of the first transistor T1 (e.g., the voltage of the second node N2) may correspond to the voltage of the initialization power supply Vint.

[0132] In addition, since the fifth transistor T5 is in the off state during the second period P2, the source electrode (e.g., the first electrode) of the first transistor T1 may have a voltage corresponding to the sum of the voltage of the initialization power supply Vint and the threshold voltage of the first transistor T1. Therefore, during the second period P2, the first transistor T1 may have a cut-off bias state. Therefore, the second initialization period may be a cut-off bias period of the first transistor T1.

[0133] The second initialization period may correspond to a period in which the previous emission control signal Ep-q and the control signal Cp have the gate-on level and the emission control signal Ep has the gate-off level.

[0134] At the third time t3, the previous emission control signal Ep-q can be changed from the gate-on level to the gate-off level, and the emission control signal Ep can be changed from the gate-off level to the gate-on level. Therefore, the fourth transistor T4 and the fifth transistor T5 can be turned on, and the sixth transistor T6 can be turned off. Since the third transistor T3 is in the on state, the first transistor T1 can have a diode connection form. The voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the second capacitor C2.

[0135] Since the first transistor T1 has a diode connection form during the third period P3 from the third time t3 to the fourth time t4, the threshold voltage of the first transistor T1 may be compensated. In other words, the third period P3 may be a threshold voltage compensation period.

[0136] During the third period P3, threshold voltage compensation can be performed by the voltage of the first power supply VDD as a constant voltage source. Therefore, the threshold voltage compensation operation can be performed based on a fixed voltage rather than based on a data signal (eg, data voltage) that can be changed according to pixels and / or frames.

[0137] At the fourth time t4, the previous emission control signal Ep-q may again transition from the gate-off level to the gate-on level, and the emission control signal Ep may again transition from the gate-on level to the gate-off level. At the fourth time t4, the fourth transistor T4 and the fifth transistor T5 may be turned off, and the sixth transistor T6 may be turned on. Therefore, the voltage of the initialization power supply Vint may again be supplied to the gate electrode (e.g., the first node N1) of the first transistor T1 through the third transistor T3 and the sixth transistor T6.

[0138] During the fourth period P4 from the fourth time t4 to the fifth time t5, a driving operation substantially the same as that of the second period P2 may be performed. In other words, the fourth period P4 may correspond to the second initialization period (and the off bias period) in which the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 are initialized and the off bias is applied to the first transistor T1.

[0139] At the fifth time t5, the previous emission control signal Ep-q may transition from the gate-on level to the gate-off level, and the emission control signal Ep may transition from the gate-off level to the gate-on level. At the fifth time t5, the fourth transistor T4 and the fifth transistor T5 may be turned on, and the sixth transistor T6 may be turned off. Therefore, the fifth period P5 from the fifth time t5 to the sixth time t6 may be a threshold voltage compensation period substantially the same as the threshold voltage compensation period of the third period P3.

[0140] The driving current of the first transistor T1 may vary according to the grayscale of light emitted by the corresponding pixel (e.g., the nth pixel PXn) during the previous frame period (in other words, according to the level of the data signal). Therefore, according to the data signal of the previous frame period, a deviation in the compensation of the threshold voltage of the first transistor T1 may occur. In the pixel (e.g., Figure 2A 10) and the display device 1000 including the pixel, the number of threshold voltage compensation operations can be increased, so that the threshold voltage compensation time accumulated in one frame period can be increased. Therefore, the deviation generated by the compensation of the threshold voltage of the first transistor T1 according to the level of the data signal during the previous frame period can be removed.

[0141] For example, the pixel 10 may perform a threshold voltage compensation operation during the third period P3, the fifth period P5, and the seventh period P7. In this case, the compensation deviation may be removed by repeated threshold voltage compensation operations. However, it should be understood that the threshold voltage compensation operation may be performed more or less than three times during a frame period.

[0142] At the sixth time t6, the previous emission control signal Ep-q may again transition from the gate-off level to the gate-on level, and the emission control signal Ep may again transition from the gate-on level to the gate-off level. During the sixth period P6 from the sixth time t6 to the seventh time t7, a driving operation substantially the same as that of the second period P2 may be performed. In other words, the sixth period P6 may correspond to the second initialization period in which the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 are initialized.

[0143] At the seventh time t7, the previous emission control signal Ep-q may transition from the gate-on level to the gate-off level, and the emission control signal Ep may transition from the gate-off level to the gate-on level. At the eighth time t8, the emission control signal Ep may transition to the gate-off level. Therefore, the seventh period P7 from the seventh time t7 to the eighth time t8 may be a threshold voltage compensation period substantially the same as the threshold voltage compensation period of the third period P3.

[0144] In this way, the emission control signal Ep may have a gate-on level during the first period P1, the third period P3, the fifth period P5, and the seventh period P7, and a gate-off level during the second period P2, the fourth period P4, and the sixth period P6. During the first to seventh periods P1 to P7, the previous emission control signal Ep-q may have a waveform opposite to the waveform of the emission control signal Ep, and is supplied to the pixels PXn and PXn+1. Therefore, the threshold voltage compensation period and the initialization period (e.g., the second initialization period) may be repeated alternately multiple times. Therefore, the deviation caused by the compensation of the threshold voltage of the first transistor T1 according to the level of the data signal during the previous frame period can be removed. In addition, since the cut-off bias is periodically applied to the first transistor T1, the hysteresis characteristic of the first transistor T1 can be improved.

[0145] Due to the kickback phenomenon caused by the repeated change of the levels of the emission control signals Ep and Ep-q used for the repetition of the threshold voltage compensation period and the initialization period, the gate voltage of the first transistor T1 may fluctuate. However, since the third transistor T3 is maintained in the on state, the data voltage can be stored in the second capacitor C2 by charge sharing between the first capacitor C1 and the second capacitor C2. Therefore, the gate voltage of the first transistor T1 can be stably changed based on the capacitance ratio between the first capacitor C1 and the second capacitor C2.

[0146] At the ninth time t9, the scan signal Sn may transition from the gate-off level to the gate-on level, and the second transistor T2 may be turned on. Thus, the data signal DV may be supplied to the third node N3. During the eighth period P8 from the ninth time t9 to the tenth time t10, the data signal DV may be written into the nth pixel PXn, and a voltage corresponding to the threshold voltage (Vth) and the data signal DV may be stored in the first capacitor C1 and the second capacitor C2 by charge sharing. In other words, the eighth period P8 may be a data writing period.

[0147] In an exemplary embodiment of the present invention, in the eighth period P8, the length (e.g., pulse width) of the scan signal Sn may correspond to one horizontal period 1H. In addition, the n+1th scan signal Sn+1 is sequentially supplied to the n+1th scan line SLn+1, and an operation of writing data to the n+1th pixel PXn+1 may be performed in response to the n+1th scan signal Sn+1.

[0148] However, this is for illustration purposes only. For example, during a period in which each of the previous emission control signal Ep-q and the emission control signal Ep has a gate-off level, the number of scan signals to be supplied may increase. In this case, three or more pixel rows may be controlled together by one emission control signal Ep and one control signal Cp.

[0149] After that, the control signal Cp can transition to the gate-off level. In other words, the control signal Cp can transition to the gate-off level after the data writing period. In addition, the previous emission control signal Ep-q can transition to the gate-on level. Therefore, the sixth transistor T6 can be turned on, and the third transistor T3 and the seventh transistor T7 can be turned off.

[0150] In an exemplary embodiment of the present invention, the first to eighth periods P1 to P8 may be included in a non-emission period of one frame period of the pixel 10 .

[0151] Subsequently, at the eleventh time t11, the emission control signal Ep may transition from the gate-off level to the gate-on level, and the fourth transistor T4 and the fifth transistor T5 may be turned on. Therefore, the light-emitting element LD may emit light based on the voltage stored in the second capacitor C2. For example, the light-emitting element LD may emit light corresponding to the driving current defined by [Equation 1]. The ninth period P9 in which each of the emission control signal Ep and the previous emission control signal Ep-q has a gate-on level may correspond to a period in which the pixels PXn and PXn+1 emit light.

[0152] As described above, in a pixel according to an exemplary embodiment of the present invention, a threshold voltage compensation operation (e.g., the third period P3) and a data write operation (e.g., the eighth period P8) of the first transistor T1 (e.g., the driving transistor) can be performed separately. For example, the threshold voltage compensation operation can be performed before the data write operation. By adjusting the waveform of the emission control signal Ep, the threshold voltage compensation period can be easily controlled. Therefore, a sufficient amount of time required to compensate for the threshold voltage of the display device 1000 performing high-speed driving is ensured. Due to the exemplary embodiments of the present invention, the demultiplexer generally required for supplying data signals for high-speed driving in the conventional technology can be omitted. Therefore, the dead zone (e.g., border) and production cost of the display device 1000 can be reduced. In addition, the threshold voltage compensation period and the initialization period (e.g., the second initialization period) can be repeated alternately for multiple times. Therefore, the deviation caused by the compensation of the threshold voltage of the first transistor T1 according to the level of the data signal during the previous frame period may not occur.

[0153] Figure 4 Is used to describe Figure 1 A timing diagram of an example of the operation of a display device.

[0154] refer to Figure 1 , Figure 2B , Figure 3 and Figure 4 , the emission control signal and the control signal may be supplied to two pixels. In addition, the emission control signal and the control signal may be sequentially output at a predetermined shift interval SP.

[0155] It should be understood that the kth signal line (eg, emission control line, control line or scan line) for supplying a kth signal (eg, emission control signal, control signal or scan signal) is a signal line coupled to pixels included in the kth pixel row.

[0156] The first emission control signal E1 may be supplied to the first emission control line EL1 and the second emission control line EL2 in common. Similarly, the first control signal C1 may be supplied to the first control line CL1 and the second control line CL2. Therefore, the shift interval SP may be about two horizontal periods (2H). However, this is for illustration purposes only, and the shift interval SP may be determined according to the number of pixel rows to which the emission control signal (and the control signal) are supplied in common. For example, in the case where the first emission control signal E1 is supplied in common to the first to third emission control lines EL1, EL2, and EL3, the shift interval SP may correspond to about three horizontal periods (3H). Figure 4It is further shown that the second emission control signal E2 can be commonly supplied to the third emission control line EL3 and the fourth emission control line EL4, the third emission control signal E3 can be commonly supplied to the fifth emission control line EL5 and the sixth emission control line EL6, and the fourth emission control signal E4 can be commonly supplied to the seventh emission control line EL7 and the eighth emission control line EL8. In addition, Figure 4 It is shown that the second control signal C2 may be commonly supplied to the third control line CL3 and the fourth control line CL4 , the third control signal C3 may be commonly supplied to the fifth control line CL5 and the sixth control line CL6 , and the fourth control signal C4 may be commonly supplied to the seventh control line CL7 and the eighth control line CL8 .

[0157] The scan signals S1 to S8 may be sequentially supplied to each of the scan lines SL1 to SL8 at intervals of one horizontal period (1H). In other words, the shift interval SP of the emission control signal and the control signal may be longer than that of the scan signal.

[0158] In the case where the display device 1000 includes i pixel rows (here, i is a natural number), the first scan driver 200 may output i scan signals, the second scan driver 300 may output i / 2 control signals, and the emission driver 400 may output i / 2 emission control signals. Therefore, the power consumption of the display device 1000 driven at a high speed can be reduced.

[0159] Figure 5 Is used to describe Figure 2A and Figure 2B A timing diagram of an example of a pixel operation.

[0160] In addition to the length of the scan signal, Figure 5 The pixel operation is Figure 3 Therefore, the same reference numerals may be used to refer to the same Figure 3 The components are the same or similar components, and therefore, repeated explanations may be omitted.

[0161] refer to Figure 2B and Figure 5 , the length (eg, pulse width) of the scan signal Sn or Sn+1 may be equal to or greater than two horizontal periods 2H.

[0162] For example, the eighth period P8 may correspond to two horizontal periods 2H. In response to the nth scan signal Sn, the n-1th data signal Dn-1 and the nth data signal Dn may be sequentially supplied to the third node N3 of the nth pixel PXn. Since the second transistor T2 is turned off after the nth data signal Dn has been supplied, the light emitting element LD of the nth pixel PXn may emit light in response to the nth data signal Dn.

[0163] Furthermore, since the nth data signal Dn subsequent to the n-1th data signal Dn-1 is supplied while the nth scan signal Sn is maintained at the gate-on level, a sufficient amount of time required to properly supply the nth data signal Dn is ensured.

[0164] A portion of the n+1th scan signal Sn+1 may overlap a portion of the nth scan signal Sn. In other words, the n+1th scan signal Sn+1 and the nth scan signal Sn may have a gate-on level at the same time. For example, in the case where the length of each of the scan signals Sn and Sn+1 corresponds to two horizontal periods (e.g., 2H), the n+1th scan signal Sn+1 and the nth scan signal Sn may overlap each other during one horizontal period (1H). In response to the n+1th scan signal Sn+1, the nth data signal Dn and the n+1th data signal Dn+1 may be sequentially supplied to the third node N3 of the n+1th pixel PXn+1. Thus, the light-emitting element LD of the n+1th pixel PXn+1 may emit light in response to the n+1th data signal Dn+1.

[0165] In an exemplary embodiment of the present invention, the length of the third period P3 which is the threshold voltage compensation period may be longer than the length of the eighth period P8 which is the data writing period. Therefore, a sufficient amount of time required for threshold voltage compensation may be ensured.

[0166] However, this is only for illustrative purposes, and according to the driving frequency and / or resolution of the display device 1000, the eighth period P8 may be equal to or longer than three horizontal periods (e.g., 3H) or four horizontal periods (e.g., 4H). Since the eighth period P8 is equal to or longer than two horizontal periods (e.g., 2H), the driving periods of multiple adjacent pixel rows may overlap each other. Therefore, the pixel and the method for driving the pixel according to the exemplary embodiment of the present invention can be easily applied to a high-resolution display device and can be used to easily realize high-speed driving.

[0167] Figure 6 Is used to describe Figure 2A and Figure 2B A timing diagram of an example of a pixel operation.

[0168] In addition to the operations in the first period P1' and the third period P3' and the waveform of the control signal Cp, Figure 6 The pixel operation and reference Figure 3 or Figure 5 Therefore, the same reference numerals may be used to refer to the same pixels as those described above. Figure 3 or Figure 5 The components are the same or similar components, and therefore, repeated explanations may be omitted.

[0169] refer to Figure 2A and Figure 6 , one frame period may include first to ninth periods P1 ′, P2 , P3 ′, P4 , P5 , P6 , P7 , P8 , and P9 .

[0170] In an exemplary embodiment of the present invention, the control signal Cp may have a gate-on level during the second period P2, the fourth period P4, the fifth period P5, the sixth period P6, the seventh period P7 and the eighth period P8, and have a gate-off level during the first period P1', the third period P3' and the ninth period P9.

[0171] During the first period P1 ′, emission of the light emitting element LD may be suspended by turning off the third transistor T3 , the sixth transistor T6 , and the seventh transistor T7 .

[0172] During the second period P2, the fourth period P4 and the sixth period P6, the sixth transistor T6 may be turned on, and the fourth transistor T4 and the fifth transistor T5 may be turned off. Therefore, during the second period P2, the fourth period P4 and the sixth period P6, the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 may be initialized. In addition, since the connection between the first electrode (e.g., source electrode) of the first transistor T1 and the first power supply VDD is interrupted, the first transistor T1 may have a cut-off bias state.

[0173] During the fifth period P5 and the seventh period P7, the sixth transistor T6 may be turned off, and the fourth transistor T4 and the fifth transistor T5 may be turned on. Therefore, during the fifth period P5 and the seventh period P7, the threshold voltage of the first transistor T1 may be compensated.

[0174] During the third period P3', the control signal Cp may have a gate-off level. Therefore, during the third period P3', the third transistor T3 and the seventh transistor T7 may be turned off. During the third period P3', the fourth transistor T4 and the fifth transistor T5 may be turned on, and the sixth transistor T6 may be turned off.

[0175] During the second period P2, the voltage of the initialization power supply Vint is applied to the gate electrode (e.g., the first node N1) of the first transistor T1. Therefore, when the third period P3' starts, the voltage of the first node N1 may be a low voltage corresponding to the voltage of the initialization power supply Vint. During the third period P3', the high voltage of the first power supply VDD may be supplied to the first electrode of the first transistor T1 by turning on the fourth transistor T4 and the fifth transistor T5. Therefore, during the third period P3', the conduction bias may be applied to the first transistor T1.

[0176] After the second period P2 in which initialization is performed and the off bias is applied to the first transistor T1, a third period P3' in which the on bias is applied to the first transistor T1 may be provided. In addition, in the subsequent period, the off bias application and the threshold voltage compensation operation are repeatedly performed. Therefore, the hysteresis characteristic (e.g., threshold voltage shift) of the first transistor T1 may be improved.

[0177] Therefore, in reference Figure 6 In the described pixel and display device, the deviation of the threshold voltage of the first transistor T1 can be removed, and its hysteresis characteristic can be removed or mitigated. Therefore, image failure (e.g., flickering, color shift phenomenon, or brightness reduction) in high-frequency driving (e.g., using a driving frequency equal to or greater than 70 Hz) or low-frequency driving (e.g., using a driving frequency equal to or less than 30 Hz) can be mitigated.

[0178] Fig. 7A Is used to describe Figure 2A A timing diagram of an example of a pixel operation. Figure 7B Is used to describe Figure 2A A timing diagram of an example of a pixel operation.

[0179] In addition to the number of on-bias periods P_B, Fig. 7A and Figure 7B The operation of pixels is based on Figure 6 Therefore, the same reference numerals may be used to refer to the same Figure 6 The components are the same or similar components, and therefore, repeated explanations may be omitted.

[0180] refer to Figure 2A , Fig. 7A and Figure 7B , one frame period may include a plurality of initialization periods P_I, a plurality of on-bias periods P_B, a plurality of compensation periods P_C, a writing period P_W, and an emission period P_E.

[0181] In an exemplary embodiment of the present invention, Fig. 7A and Figure 7B As shown in FIG, during one frame period, after four initialization (and off-bias) operations, two on-bias operations, and two threshold voltage compensation operations have been performed, the data signal may be written to the pixel 10. However, this is for illustration purposes only, and the number of initialization operations, on-bias operations, or threshold voltage compensation operations is not limited thereto.

[0182] In an exemplary embodiment of the present invention, during each of the initialization period P_I, the on-bias period P_B, and the compensation period P_C, the switching operation of each of the fourth transistor T4 and the fifth transistor T5 may be performed opposite to the switching operation of the sixth transistor T6. For example, when the fourth transistor T4 and the fifth transistor T5 are turned on, the sixth transistor T6 may be turned off. When the fourth transistor T4 and the fifth transistor T5 are turned off, the sixth transistor T6 may be turned on.

[0183] During each initialization period P_I, each of the previous emission control signal Ep-q and the control signal Cp may have a gate-on level. During the initialization period P_I, the emission control signal Ep may have a gate-off level. Therefore, during the initialization period P_I, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 may be turned on, so that the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 may be initialized by the voltage of the initialization power supply Vint. During the initialization period P_I, both the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 may be initialized. In an exemplary embodiment of the present invention, during the initialization period P_I, the first transistor T1 may enter a cut-off bias state.

[0184] During each of the conduction bias periods P_B, each of the previous emission control signal Ep-q and the control signal Cp may have a gate-off level. During the conduction bias period P_B, the emission control signal Ep may have a gate-on level. Therefore, during the conduction bias period P_B, the first transistor T1 may have a conduction bias state.

[0185] During each compensation period P_C, each of the emission control signal Ep and the control signal Cp may have a gate-on level. During the compensation period P_C, the previous emission control signal Ep-q may have a gate-off level. Therefore, during the compensation period P_C, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be turned on, the sixth transistor T6 may be turned off, and the threshold voltage compensation operation of the first transistor T1 may be performed. The compensation period P_C may be adjusted according to the length of the gate-on period of the emission control signal Ep.

[0186] During the write period P_W, each of the scan signal Sn and the control signal Cp may have a gate-on level. During the write period P_W, each of the prior emission control signal Ep-q and the emission control signal Ep may have a gate-off level. Therefore, the second transistor T2 and the third transistor T3 may be turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be turned off. During the write period P_W, the voltage of the data signal may be stored in the pixel 10. In an exemplary embodiment of the present invention, the write period P_W and the scan signal Sn may each have a length equal to or greater than two horizontal periods 2H.

[0187] During the emission period P_E, each of the previous emission control signal Ep-q and the emission control signal Ep may have a gate-on level. During the emission period P_E, each of the scan signal Sn and the control signal Cp may have a gate-off level. During the emission period P_E, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be turned on, and the second transistor T2, the third transistor T3, and the seventh transistor T7 may be turned off. Thus, the light emitting element LD may emit light in response to the current data signal.

[0188] In this way, in the non-emission period of each frame, the initialization (and off-bias application) operation, the on-bias application operation, and the threshold voltage compensation operation may each be performed a plurality of times.

[0189] like Figure 7B As shown in , the non-emission period of each frame may further include an anode initialization period P_I′ before the first initialization period P_I.

[0190] During each compensation period P_C, each of the emission control signal Ep and the control signal Cp may have a gate-on level. During the anode initialization period P_I', the previous emission control signal Ep-q may have a gate-off level. Therefore, during the anode initialization period P_I', the anode voltage of the light emitting element LD may be initialized by the turned-on seventh transistor T7 and the turned-off sixth transistor T6.

[0191] Figure 8 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention. Fig. 9 Is used to describe Figure 8 A timing diagram of an example of a pixel operation.

[0192] In addition to the configuration of the third transistor T3 and the seventh transistor T7, Figure 8 The configuration and operation of pixels is similar to Figure 2A Therefore, the same reference numerals may be used to refer to the same pixels. Figure 2AThe components are the same or similar components, and therefore, repeated explanations may be omitted.

[0193] refer to Figure 8 and Fig. 9 , the pixel 11 may include a light emitting element LD, first to seventh transistors T1 to T7 , a first capacitor C1 , and a second capacitor C2 .

[0194] In an exemplary embodiment of the present invention, each of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be a P-channel metal oxide semiconductor (PMOS) transistor, and each of the third transistor T3 and the seventh transistor T7 may be an N-channel metal oxide semiconductor (NMOS) transistor. For example, the PMOS transistor may be an LTPS thin film transistor, and the NMOS transistor may be an oxide semiconductor thin film transistor. In other words, the NMOS transistor may include an active layer formed of an oxide semiconductor.

[0195] In this configuration, leakage current in the third transistor T3 and the seventh transistor T7 can be significantly reduced. Therefore, during a driving operation performed at a low frequency of 30 Hz or less, image flicker can be alleviated.

[0196] like Fig. 9 As shown in FIG. 1 , the operation of the pixel 11 can be Figure 7B In other words, since each of the third transistor T3 and the seventh transistor T7 is an NMOS transistor, Figure 8 The control signal Cp can be relative to Figure 7B The control signal Cp is an inverted signal. Figure 8 The gate-on level of the control signal Cp may be a high voltage.

[0197] Each frame may include an emission period P_E and a non-emission period P_NE. The non-emission period P_NE may include a first initialization period P_I1, a second initialization period P_I2, a turn-on bias period P_B, a compensation period P_C, and a writing period P_W.

[0198] During the first initialization period P_I1, the anode voltage of the light emitting element LD may be initialized. The first initialization period P_I1 may correspond to Figure 5 The first period P1.

[0199] During the second initialization period P_I2, the anode voltage of the light emitting element LD and the gate voltage of the first transistor T1 may be initialized. The second initialization period P_I2 may correspond to Figure 5 and Figure 6During the second initialization period P_I2, the first transistor T1 may have a turned-off bias state.

[0200] During the on bias period P_B, the first transistor T1 may have an on bias state. The on bias period P_B may correspond to Figure 6 The third period P3'.

[0201] During the compensation period P_C, the threshold voltage of the first transistor T1 may be compensated. The compensation period P_C may correspond to Figure 6 The fifth period P5 and the seventh period P7.

[0202] During the writing period P_W, the data signal DV may be written into the pixel 11. The writing period P_W may correspond to Figure 6 The eighth period P8.

[0203] During the emission period P_E, the light emitting element LD may emit light in response to the data signal DV. The emission period P_E may correspond to Figure 6 The ninth period P9.

[0204] Fig.10 Is used to describe Figure 8 A timing diagram of an example of a pixel operation.

[0205] In addition to controlling the voltage level of the signal Cp and the length of the scan signal Sn during the write period P_W, Fig.10 The pixel operation is Fig. 9 Therefore, the same reference numerals may be used to refer to the same Fig. 9 The components are the same or similar components, and therefore, repeated explanations may be omitted.

[0206] refer to Figure 8 and Fig.10 Each frame may include an emission period P_E and a non-emission period P_NE. The non-emission period P_NE may include a first initialization period P_I1, a second initialization period P_I2, a conduction bias period P_B, a compensation period P_C, and a writing period P_W.

[0207] In an exemplary embodiment of the present invention, the scan signal Sn may have a length equal to or greater than three horizontal periods 3H. However, this is for illustration purposes only, and the length of the scan signal Sn is not limited thereto. For example, the scan signal Sn may be longer than three horizontal periods 3H.

[0208] In an exemplary embodiment of the present invention, the gate-off period of the control signal Cp may overlap a portion of the gate-on period of the scan signal Sn. The gate-off period of the control signal Cp may be a period in which the control signal Cp has a gate-off level. The gate-on period of the scan signal Sn may be a period in which the scan signal Sn has a gate-on level. For example, during the write period P_W, the control signal Cp may transition from the gate-on level to the gate-off level.

[0209] Therefore, when the second transistor T2 is in the on state, the third transistor T3 may be turned off. Therefore, the gate voltage of the first transistor T1 may not change after the data writing operation.

[0210] Fig.11 is a circuit diagram illustrating a pixel according to an exemplary embodiment of the present invention.

[0211] In addition to the configuration of the seventh transistor T7, Fig.11 The configuration and operation of pixels is similar to Figure 8 Therefore, the same reference numerals may be used to refer to the same pixels. Figure 8 The components are the same or similar components, and therefore, repeated explanations may be omitted.

[0212] refer to Fig.11 , the pixel 12 may include a light emitting element LD, first to seventh transistors T1 to T7 , a first capacitor C1 , and a second capacitor C2 .

[0213] In an exemplary embodiment of the present invention, each of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be a PMOS transistor, and the third transistor T3 may be an NMOS transistor. For example, the PMOS transistor may be an LTPS thin film transistor, and the NMOS transistor may be an oxide semiconductor thin film transistor.

[0214] Different control lines CLn and CL'n may be coupled to gate electrodes of the third transistor T3 and the seventh transistor T7, respectively. Control signals inverted with respect to each other may be supplied to the control lines CLn and CL'n, respectively.

[0215] As described above, in the pixel 10, 11 or 12 according to an exemplary embodiment of the present invention and the display device 1000 including the pixel 10, 11 or 12, the threshold voltage compensation operation can be performed using the voltage of the first power supply VDD, and the threshold voltage compensation operation and the data write operation can be performed separately. Therefore, the threshold voltage compensation period can be easily adjusted. In addition, in the pixel 10, 11 or 12 according to an exemplary embodiment of the present invention and the display device 1000 including the pixel 10, 11 or 12, during the non-emission period of each frame, the initialization of the gate voltage (and the anode voltage) and the threshold voltage compensation operation are alternately and repeatedly performed. Therefore, the compensation deviation of the first transistor T1 caused by the data signal of the previous frame can be removed. In addition, during the non-emission period, the period in which the cut-off bias is applied to the first transistor T1 and the period in which the conduction bias is applied to the first transistor T1 are alternately repeated. Therefore, the threshold voltage deviation can be removed, and the hysteresis characteristic of the first transistor T1 can be removed or improved.

[0216] Therefore, image failures (eg, flickering, color shift phenomenon, or brightness reduction) in high-frequency driving (eg, having a driving frequency equal to or greater than 70 Hz) or low-frequency driving (eg, having a driving frequency equal to or less than 30 Hz) can be alleviated.

[0217] Although the present invention has been described with reference to exemplary embodiments thereof, workers skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the invention as described in the following claims.

Claims

1. A pixel comprising: Light emitting element; a first transistor including a first electrode electrically coupled to a first power source and a second electrode electrically coupled to the light emitting element, the first transistor being configured to control a driving current; a first capacitor coupled between a second node and a third node, wherein the second node is connected to the second electrode of the first transistor; a second transistor coupled between the third node and the data line and configured to be turned on by a scan signal; a third transistor coupled between a first node and the second node and configured to be turned on by a control signal, wherein the first node is connected to a gate electrode of the first transistor; a fourth transistor coupled between the first power source and the third node and configured to be turned on by a first emission control signal; a fifth transistor coupled between the first power source and the first electrode of the first transistor and configured to be turned on by the first emission control signal; a sixth transistor coupled between the second node and the light emitting element and configured to be turned on by a second emission control signal; as well as a second capacitor coupled between the first power source and the first node, During a non-emission period in a frame, each of the fourth transistor, the fifth transistor, and the sixth transistor repeatedly performs a turn-on operation and a turn-off operation at least four times in response to the first emission control signal or the second emission control signal.

2. The pixel according to claim 1, wherein: During the non-emission period, each of the first emission control signal and the second emission control signal includes a plurality of gate-on periods and a plurality of gate-off periods.

3. The pixel according to claim 1, wherein: The non-emission period includes an on-bias period in which each of the second emission control signal and the control signal has a gate-off level and the first emission control signal has a gate-on level.

4. The pixel according to claim 3, wherein: During the on-bias period, the third transistor and the sixth transistor are turned off, and the fourth transistor and the fifth transistor are turned on.

5. The pixel according to claim 1, wherein: When the third transistor, the fourth transistor, and the fifth transistor are turned on, the second transistor and the sixth transistor are turned off.

6. The pixel according to claim 1, further comprising: The seventh transistor is coupled between the light emitting element and an initialization power source and is configured to be turned on by the control signal.

7. A pixel according to claim 6, wherein the non-emission period includes a first initialization period in which the initialization power is supplied to a fourth node between the light emitting element and the seventh transistor, a second initialization period in which the initialization power is supplied to the fourth node and the first node, a conduction bias period in which the first transistor has a conduction bias state, a compensation period in which the first transistor is diode-connected based on the voltage of the first power supply, and a writing period in which the second transistor is turned on so that a data signal is supplied through the data line.

8. The pixel according to claim 7, wherein: In response to the control signal, the third transistor is turned on during the second initialization period, the compensation period, and the writing period, and is turned off during the on-bias period.

9. The pixel according to claim 7, wherein: During the non-transmission period, at least one of the second initialization period, the on-bias period, and the compensation period is repeated at least twice.

10. The pixel according to claim 9, wherein: During each of the first initialization period, the second initialization period, the on-bias period, and the compensation period, a switching operation of each of the fourth transistor and the fifth transistor is performed opposite to a switching operation of the sixth transistor.

11. The pixel according to claim 9, wherein: During the second initialization period, the third transistor, the sixth transistor, and the seventh transistor are turned on, and the fourth transistor and the fifth transistor are turned off, so that the first transistor has a turned-off bias state.

12. The pixel according to claim 9, in, During the compensation period, the third transistor, the fourth transistor, and the fifth transistor are turned on, and the second transistor and the sixth transistor are turned off, and During the writing period, the second transistor and the third transistor are turned on, and the fourth transistor, the fifth transistor and the sixth transistor are turned off.

13. The pixel according to claim 7, wherein: The length of the compensation period is greater than the length of the writing period.

14. The pixel according to claim 7, in, During the writing period, a gate-off period of the control signal overlaps a portion of a gate-on period of the scan signal, and Wherein, when the second transistor remains turned on during the writing period, the third transistor is turned off.

15. The pixel according to claim 7, wherein: The first emission control signal is obtained by shifting the second emission control signal by k horizontal periods, where k is an integer greater than or equal to 3.

Images