Display device including connection plate

Abstract

A display device is provided. The display device includes a display panel and a connection plate, wherein the display panel includes a first panel pad and a second panel pad electrically connected to each other, and the connection plate includes a first connection plate pad and a second connection plate pad respectively connected to the first panel pad and the second panel pad, an output pad, and a drive circuit. The drive circuit includes a pull-up resistor and a comparator, wherein the pull-up resistor is connected between a first voltage terminal and a first node, and the comparator is configured to compare a voltage at the first node with a reference voltage and output a contact test signal corresponding to the comparison result to the output pad. The first connection plate pad is electrically connected to the first node, and the second connection plate pad is connected to the second voltage terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0090380, filed on Jul. 25, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] One or more aspects of embodiments of the present disclosure relate to a display device, for example, to a display device including a connection plate electrically connected to a display panel. Background Art

[0004] Display devices for use in multimedia devices such as televisions, portable phones, tablet computers, navigation systems, and game consoles have been developed. Organic light emitting display devices may display images by using organic light emitting diodes that generate light by recombination of electrons and holes. Organic light emitting display devices may have a fast response speed and may be driven with low power consumption.

[0005] The organic light emitting display device may include a display panel for displaying an image, a host device for providing control signals and image signals to control the operation of the display panel, and a connection board for providing the control signals and image signals from the host device to the display panel.

[0006] The connection board and the display panel may be electrically connected to each other through (eg, via) pads. In order to transmit control signals and image signals to the display panel without distortion, the pads of the connection board should be fully and completely (substantially) connected to the pads of the display panel.

[0007] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0008] One or more exemplary embodiments of the present disclosure are directed to a display device including a connection board capable of testing a connection state (or contact state) of a pad.

[0009] One or more exemplary embodiments of the present disclosure relate to a method for testing a pad connection in a display device capable of testing a connection state (or contact state) of the pad.

[0010] One or more exemplary embodiments of the present disclosure provide a display device, the display device including a display panel and a connection plate, wherein the display panel includes a first panel pad and a second panel pad electrically connected to each other, and the connection plate includes a first connection plate pad and a second connection plate pad electrically connected to the first panel pad and the second panel pad, respectively, an output pad, and a driving circuit. The driving circuit may include a pull-up resistor and a comparator, wherein the pull-up resistor is electrically connected between a first voltage terminal and a first node, and the comparator is configured to compare a voltage at the first node with a reference voltage and output a contact test signal corresponding to the comparison result to the output pad. The first connection plate pad may be electrically connected to the first node, and the second connection plate pad may be electrically connected to the second voltage terminal.

[0011] In an exemplary embodiment, the display device may include a main board, wherein the main board includes a first test pad electrically connected to the output pad and a main controller. The main controller may receive a contact test signal through the first test pad.

[0012] In an exemplary embodiment, the connection board may include an input pad, and the driving circuit may include a switch. The switch may be electrically connected between the first connection board pad and the first node, and may operate in response to a switch control signal input through the input pad.

[0013] In an exemplary embodiment, the display device may include a main board, wherein the main board includes a first test pad and a second test pad electrically connected to the output pad and the input pad, respectively, and a main controller. The main controller may output a switch control signal to the second test pad and may receive a contact test signal through the first test pad.

[0014] In an exemplary embodiment, the first voltage supplied to the first voltage terminal may be higher in level than the second voltage supplied to the second voltage terminal.

[0015] In an exemplary embodiment, when the voltage at the first node is higher in level than a reference voltage, the comparator may output a contact test signal at an activation level, and when the voltage at the first node is lower in level than the reference voltage, the comparator may output a contact test signal at an inactivation level.

[0016] In an exemplary embodiment, the driving circuit may be an integrated circuit, and the connection board may be a chip on film on which the driving circuit is mounted.

[0017] In an exemplary embodiment, the display panel may include a connection line electrically connecting the first panel pad and the second panel pad.

[0018] One or more exemplary embodiments of the present disclosure provide a display device, the display device includes a display panel, a main board and a connection board, wherein the display panel includes a first panel pad and a second panel pad electrically connected to each other, the main board includes a first main board pad to a fourth main board pad, a first test pad and a main controller, and the connection board includes a first connection board pad and a second connection board pad electrically connected to the first panel pad and the second panel pad, respectively, a first main contact pad to a fourth main contact pad electrically connected to the first main board pad to the fourth main board pad, respectively, a first test line and a second test line electrically connecting the first connection board pad and the second connection board pad to the first main contact pad and the second main contact pad, respectively, an intermediate connection line electrically connecting the first main contact pad to the fourth main contact pad, an output pad electrically connected to the first test pad, and a driving circuit. The third main board pad and the fourth main board pad may be electrically connected to each other. The driving circuit may include a pull-up resistor and a comparator, wherein the pull-up resistor is electrically connected between the first voltage terminal and the first node, and the comparator is configured to compare the voltage at the first node with the reference voltage and output a contact test signal corresponding to the comparison result to the output pad. The second main contact pad may be electrically connected to the first node, and the first main contact pad may be electrically connected to the second voltage terminal through the intermediate connection line and the fourth main contact pad. The main controller may receive a contact test signal through the first test pad.

[0019] In an exemplary embodiment, the connection board may include a first input pad, and the main board may include a main connection line and a second test pad, wherein the main connection line electrically connects the third main board pad to the fourth main board pad, and the second test pad is electrically connected to the first input pad. The main controller may be configured to provide the first switch control signal to the drive circuit through the second test pad.

[0020] In an exemplary embodiment, the driving circuit may include a first switch. The first switch may be electrically connected between the second main contact pad and the first node, and may be operated in response to a first switch control signal input through the first input pad.

[0021] In an exemplary embodiment, the connection board may include a second input pad, and the main board may include a third test pad, wherein the third test pad is electrically connected to the second input pad. The main controller may be configured to provide the second switch control signal to the driving circuit through the third test pad.

[0022] In an exemplary embodiment, the driving circuit may include a second switch. The second switch may be electrically connected between the third main contact pad and the first node, and may be operated in response to a second switch control signal input through the second input pad.

[0023] In an exemplary embodiment, the first switch control signal and the second switch control signal may be activated at different time points from each other.

[0024] In an exemplary embodiment, the first voltage supplied to the first voltage terminal may be higher in level than the second voltage supplied to the second voltage terminal.

[0025] In an exemplary embodiment, when the voltage at the first node is higher in level than a reference voltage, the comparator may output a contact test signal at an activation level, and when the voltage at the first node is lower in level than the reference voltage, the comparator may output a contact test signal at an inactivation level.

[0026] In an exemplary embodiment, the main controller may provide the first switch control signal to the driving circuit in a control period after starting the supply of the power supply voltage.

[0027] In an exemplary embodiment, the main controller may provide the first switch control signal to the driving circuit in a blanking period of the synchronization signal.

[0028] In an exemplary embodiment, the driving circuit may be an integrated circuit, and the connection board may be a chip on film on which the driving circuit is mounted.

[0029] In an exemplary embodiment, the display panel may include a connection line electrically connecting the first panel pad and the second panel pad.

[0030] One or more exemplary embodiments of the present disclosure provide a method for testing a pad connection in a display device, and the display device includes a display panel and a connection plate, the display panel includes a first panel pad and a second panel pad electrically connected to each other, and the connection plate includes a first connection plate pad and a second connection plate pad, an input pad, and an output pad, respectively electrically connected to the first panel pad and the second panel pad. The method may include: connecting the first connection plate pad and the second connection plate pad to the first panel pad and the second panel pad of the display panel, respectively; connecting the first connection plate pad to a first node in response to a switch control signal received through the input pad; and comparing a voltage at the first node with a reference voltage, and outputting a contact test signal corresponding to the comparison result to the output pad.

[0031] In an exemplary embodiment, the display device may include a main board, and the main board includes a first test pad and a second test pad electrically connected to the output pad and the input pad, respectively, and a main controller. The main controller may output a switch control signal to the second test pad and may receive a contact test signal through the first test pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are included to provide an understanding of the present disclosure, and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0033] Figure 1 is a perspective view showing a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 2 is an exploded perspective view showing a display device according to an embodiment of the present disclosure;

[0035] Figure 3 is a plan view showing a display panel, a connection board, and a main board of a display device according to an embodiment of the present disclosure;

[0036] Figure 4 is a cross-sectional view showing the connection of a display panel, a connection board, and a main board according to an embodiment of the present disclosure;

[0037] Figure 5 is a plan view showing connection between a display panel and a connection board and connection between the connection board and a main board in a display device according to an embodiment of the present disclosure;

[0038] Figure 6 It is shown Figure 5 A circuit diagram of a circuit configuration of a driving circuit;

[0039] Figure 7 is a plan view showing connection between a display panel and a connection board and connection between the connection board and a main board in a display device according to an embodiment of the present disclosure;

[0040] Figure 8 It is shown Figure 7 A circuit diagram of a circuit configuration of a driving circuit;

[0041] Fig. 9 is a plan view showing connection between a display panel and a connection board and connection between the connection board and a main board in a display device according to an embodiment of the present disclosure;

[0042] Fig.10 It is shown Fig. 9 A circuit diagram of a circuit configuration of a driving circuit;

[0043] Fig.11 is a plan view showing connection between a display panel and a connection board and connection between the connection board and a main board in a display device according to an embodiment of the present disclosure;

[0044] Fig.12 It is shown Fig.11 A circuit diagram of a circuit configuration of a driving circuit;

[0045] Fig.13 is a diagram showing transmission signals between a drive circuit and a main controller;

[0046] Fig.14is a plan view showing connection between a display panel and a connection board and connection between the connection board and a main board in a display device according to an embodiment of the present disclosure;

[0047] Fig.15 It is shown Fig.14 A circuit diagram of a circuit configuration of a driving circuit;

[0048] Fig.16 is a plan view showing a display device according to an embodiment of the present disclosure;

[0049] Fig.17 It is shown Fig.16 a circuit diagram of a circuit configuration of a first drive circuit to a fourth drive circuit; and

[0050] Fig.18A and Fig.18B is a timing diagram showing the timing of the first to fourth contact test signals output from the first to fourth drive circuits and the timing of the contact test signals received in the main controller. DETAILED DESCRIPTION

[0051] Now, the present disclosure will be described more fully hereinafter with reference to the accompanying drawings showing various embodiments. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully communicated to those skilled in the art. Throughout the text, similar reference numerals indicate similar elements, and their redundant descriptions may be omitted.

[0052] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, the element can be directly on the other element, or there can be intervening elements. Conversely, the term "directly" indicates that there are no intervening elements. As used herein, the term "electrically connected" means that elements are connected, for example, via direct contact and / or via electrically conductive intermediate lines, layers or elements.

[0053] The professional terms used herein are only for the purpose of describing various aspects of the embodiment and are not intended to be limiting. Unless the content clearly states, the singular forms "one", "an" and "the" as used herein are also intended to include plural forms including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It will also be understood that the terms "include" and / or "include" or "include" and / or "include", when used in this specification, specify the existence of the stated features, regions, integers, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or their clusters.

[0054] Spatially relative terms such as "below", "below", "below", "above", and "on" may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. It will be understood that such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "below" other elements or features will subsequently be oriented to be "above" other elements or features. Therefore, the exemplary term "below" may include both the orientations of above and below. The device may be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0055] It will be understood that although the terms first, second, etc. may be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be alternatively referred to as the second element, component, region, layer or part without departing from the teachings herein.

[0056] As used herein, "about" or "approximately" includes the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

[0057] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary illustrations. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity. Accordingly, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but will include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle may have rounded or curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0058] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0059] Figure 1 is a perspective view showing a display device DD according to an embodiment of the present disclosure.

[0060] Reference Figure 1 The display device DD may be a liquid crystal display device, a field emission display device, a plasma display device, or an organic light emitting display device. However, the embodiments of the present disclosure are not limited thereto.

[0061] exist Figure 1 In the embodiment, a flat display device is shown as an example of the display device DD. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the display device DD may be a foldable display device or a rollable display device. The display device DD may be used in large electronic devices (e.g., televisions and monitors) and small and medium-sized electronic devices (e.g., portable phones, tablet computers, car navigation units, game consoles, and smart watches).

[0062] The display device DD may display an image in a third direction DR3 in a display surface IS parallel to the first direction DR1 and the second direction DR2 (for example, in a plane defined by the first direction DR1 and the second direction DR2, and the plane is perpendicular to the third direction DR3). The display surface IS of the display device DD may include a plurality of set areas or design areas. The display surface IS displaying the image may correspond to the front surface of the display device DD. The display device DD may include a display area DD-DA displaying the image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The image may not be displayed in the non-display area DD-NDA. The non-display area DD-NDA may be referred to as a frame area.

[0063] For example, the display area DD-DA may have a quadrilateral shape (e.g., a rectangular shape). The non-display area DD-NDA may surround the display area DD-DA (e.g., an edge thereof). However, the embodiments of the present disclosure are not limited thereto. The display area DD-DA and the non-display area DD-NDA may each have any suitable shape.

[0064] Figure 2 is an exploded perspective view showing a display device DD according to an embodiment of the present disclosure.

[0065] Reference Figure 2 , the display device DD may include a window member WM, an anti-reflection unit ARU, a display panel DPL, a connection board FCB, a main board MCB, a support member SPP and a lower case BC.

[0066] The window member WM may provide a front surface of the display device DD. The window member WM may include a glass substrate, a sapphire substrate, and / or a plastic substrate. In some embodiments, the window member WM may include a functional coating such as an anti-fingerprint layer, an anti-reflection layer, and / or a hard coating. In an exemplary embodiment, Figure 1 A flat window member WM is shown in the display area DD-DA of FIG. However, the shape of the window member WM may be variously modified. In a certain embodiment, edges of the window member WM facing each other in the first direction DR1 may have bent surfaces.

[0067] The front surface (or top surface or first surface) and the rear surface (or bottom surface or second surface) of each member may be defined based on the direction in which the image is displayed. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative and may be interchanged to indicate other sets of directions. In the following, the first direction to the third direction are respectively Figure 1 and Figure 2 The directions indicated by the first direction DR1, the second direction DR2 and the third direction DR3 are shown in FIG.

[0068] The display panel DPL may be arranged on the rear surface of the window member WM (e.g., behind or below the window member WM) to generate an image. In some embodiments, the display panel DPL may also sense a user's touch input. In an exemplary embodiment, a display panel DPL providing a flat display surface is shown as an example. However, the display panel DPL may have any suitable shape, configuration, or curvature. For example, edges of the display panel DPL that are opposite to each other in the first direction DR1 may be bent from a central portion to provide a curved surface.

[0069] The display panel DPL may be a panel for displaying an image, and may be a liquid crystal display (LCD) panel, an electrophoretic display panel, an organic light emitting diode panel, a light emitting diode (LED) panel, an inorganic electroluminescent (EL) display panel, a field emission display (FED) panel, a surface conduction electron emitter display (SED) panel, a plasma display panel (PDP), a cathode ray tube (CRT), a micro-light emitting element display panel, or a micro-LED display panel. Hereinafter, an organic light emitting display device will be described as an example of a display device DD, and an organic light emitting diode panel will be described as an example of a display panel DPL. However, the embodiments of the present disclosure are not limited thereto. Other various types of display devices and display panels may be used as the display device DD and the display panel DPL.

[0070] The anti-reflection unit ARU may be arranged between the window member WM and the display panel DPL. The anti-reflection unit ARU may include a polarizing film and / or a delay film. The number of delay films and the phase delay length (e.g., λ / 4 or λ / 2) of the delay film may be determined based on the operating principle of the anti-reflection unit ARU. The anti-reflection unit ARU may include a color filter. The connecting board FCB may include a flexible printed circuit board. One end of the connecting board FCB may be bonded to a pad arranged in the area of ​​the display panel DPL, and thus the connecting board FCB may be electrically connected to the display panel DPL.

[0071] The connection board FCB may include a driving circuit DIC. In an embodiment, the driving circuit DIC may be an integrated circuit (IC) and may be mounted on the connection board FCB by using a chip on film (COF) method. In some embodiments, additional passive components and active components may be mounted on the connection board FCB. The connection board FCB may provide an electrical signal to the display panel DPL through a signal line. The other end of the connection board FCB may be electrically connected to the main board MCB.

[0072] The main board MCB may include a main controller MC. The main controller MC may be an integrated circuit (IC) and may be mounted on the main board MCB. In some embodiments, additional passive components and active components may be mounted on the main board MCB.

[0073] The support member SPP may be disposed on the rear surface of the display panel DPL to support the display panel DPL. The support member SPP may be a metal plate having a rigidity of a reference value or more. The support member SPP may be a stainless steel plate. The support member SPP may have a black color to block external light incident on the display panel DPL. In some embodiments, the support member SPP may be omitted.

[0074] The window member WM and the lower case BC may be coupled to each other to accommodate (eg, hold or enclose) the display panel DPL.

[0075] Figure 3is a plan view showing a display panel DPL, a connection board FCB, and a main board MCB of a display device DD according to an embodiment of the present disclosure. Figure 4 is a cross-sectional view showing connection of a display panel DPL, a connection board FCB, and a main board MCB according to an embodiment of the present disclosure.

[0076] Reference Figure 3 and Figure 4 , the display device DD may include a display panel DPL, a connection board FCB and a main board MCB.

[0077] The display panel DPL may include a base substrate SUB, a circuit element layer CRL, a light emitting element layer ED, and a thin film encapsulation layer TFE. In some embodiments, the display panel DPL may include at least one functional layer (eg, a refractive index adjustment layer).

[0078] The base substrate SUB may include at least one plastic film. The base substrate SUB may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate. In one embodiment, the base substrate SUB may be made of a flexible material (eg, polyimide).

[0079] The circuit element layer CRL may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit element layer CRL may provide a signal line and / or a control circuit of a pixel.

[0080] The light emitting element layer ED may include at least one organic light emitting diode. The light emitting element layer ED may include an organic layer such as a pixel defining layer.

[0081] The thin film encapsulation layer TFE may encapsulate the light emitting element layer ED. The thin film encapsulation layer TFE may include at least one inorganic layer (hereinafter, referred to as "encapsulation inorganic layer"). The thin film encapsulation layer TFE may include at least one organic layer (hereinafter, referred to as "encapsulation organic layer"). The encapsulation inorganic layer may protect the light emitting element layer ED from moisture / oxygen, and the encapsulation organic layer may protect the light emitting element layer ED from foreign matter and / or contaminants (such as dust particles). The encapsulation inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The encapsulation organic layer may include an acrylic-based organic layer, but is not limited thereto. However, embodiments of the present disclosure are not limited thereto. In an embodiment, the display panel DPL may include an encapsulation substrate that encapsulates the light emitting element layer ED, instead of the thin film encapsulation layer TFE. The encapsulation substrate may be formed of glass, sapphire, or plastic.

[0082] When viewed in a plan view, the display panel DPL may include a display area DA and a non-display area NDA. In some embodiments, the display area DA and the non-display area NDA of the display panel DPL may correspond to display areas DD-DA of the display device DD, respectively (see FIG. Figure 1 ) and non-display area DD-NDA (see Figure 1 In some embodiments, the display area DA and the non-display area NDA of the display panel DPL may not necessarily coincide with the display area DD-DA of the display device DD (see Figure 1 ) and non-display area DD-NDA (see Figure 1 ) are the same, and may be variously modified according to the structure and / or design of the display panel DPL. Figure 4 The light emitting element layer ED may be arranged in the display area DA.

[0083] The display panel DPL may include a plurality of pixels PX. A region where the plurality of pixels PX are arranged may be defined as a display area DA. In an exemplary embodiment, a non-display area NDA may be defined along a boundary (eg, edge) of the display area DA.

[0084] The display panel DPL may include scan lines SL, data lines DL, emission lines EL, scan control lines SCL, initialization voltage lines VINTL, and voltage lines VL.

[0085] A scan driving circuit SDC to which the scan lines SL and the emission lines EL are electrically connected may be disposed in the non-display area NDA at one side of the display area DA.

[0086] The scan line SL may extend from the scan driving circuit SDC in the first direction DR1, and each of the plurality of scan lines SL may be electrically connected to a corresponding pixel PX among the plurality of pixels PX. Each of the plurality of emission lines EL may extend from the scan driving circuit SDC in the first direction DR1, and may be parallel to a corresponding scan line SL among the plurality of scan lines SL. The data line DL may extend in the second direction DR2, and each of the plurality of data lines DL may be electrically connected to a corresponding pixel PX among the plurality of pixels PX. The scan control line SCL may provide a control signal to the scan driving circuit SDC. The initialization voltage line VINTL may provide an initialization voltage to the plurality of pixels PX. The voltage line VL may be electrically connected to the plurality of pixels PX, and may provide a first voltage to the plurality of pixels PX. The voltage line VL may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2.

[0087] Some of the scan lines SL, the data lines DL, the emission lines EL, the scan control lines SCL, the initialization voltage lines VINTL, and the voltage lines VL may be arranged in the same layer, and another one or the others of them may be arranged in a different layer.

[0088] The panel pads BP may be arranged on the circuit element layer CRL of the display panel DPL in the non-display area NDA. A plurality of panel pads BP may be arranged in a first direction DR1. In an exemplary embodiment, the panel pads BP are arranged in a line along the first direction DR1. However, embodiments of the present disclosure are not limited thereto. In some embodiments, a plurality of panel pads BP may be arranged to form two or more rows (lines), or may be arranged in a zigzag form.

[0089] The data line DL, the scan control line SCL, the initialization voltage line VINTL, and the voltage line VL may each be electrically connected to at least one of the plurality of panel pads BP.

[0090] The panel pads BP of the display panel DPL may be electrically connected to (or in contact with) the connection board pads AP of the connection board FCB. The connection board FCB may include a drive circuit DIC. The drive circuit DIC may be provided as an integrated circuit (IC). The connection board FCB may be a flexible printed circuit board on which the drive circuit DIC of the integrated circuit is mounted. Figure 3 In the embodiment, a single driving circuit DIC is mounted on the connection board FCB. As an example, a plurality of integrated circuits may be mounted on the connection board FCB. For example, the driving circuit DIC may include a data driver (or source driver) for driving the data lines DL of the display panel DPL.

[0091] In some embodiments, a plurality of interconnection lines for electrically connecting the connection board pads AP and the driving circuit DIC may be arranged on the connection board FCB.

[0092] Figure 3 The panel pads BP of the display panel DPL shown in may be arranged on the top surface of the display panel DPL, and the connection plate pads AP may be arranged on the bottom surface of the connection board FCB. Therefore, when the panel pads BP are electrically connected to the connection plate pads AP, a portion of the connection board FCB may overlap a portion of the top surface of the display panel DPL.

[0093] When the panel pad BP is electrically connected to the connection plate pad AP, the panel pad BP and the connection plate pad AP cannot be visible in a plan view. Figure 3 , the panel pads BP and the connection plate pads AP are shown by dotted lines. In some embodiments, the panel pads BP may be arranged on the bottom surface of the display panel DPL, and the connection plate pads AP may be arranged on the top surface of the connection board FCB. In this case, when the panel pads BP are electrically connected to the connection plate pads AP, a portion of the display panel DPL may overlap a portion of the top surface of the connection board FCB.

[0094] The connection board FCB may include a main contact pad CP. The main board MCB may include a main board pad DP. In an exemplary embodiment, the main contact pad CP may be arranged on the bottom surface of the connection board FCB, and the main board pad DP may be arranged on the top surface of the main board MCB. The main contact pad CP of the connection board FCB may be electrically connected to (or contact) the main board pad DP of the main board MCB. Therefore, when the main contact pad CP is electrically connected to the main board pad DP, a portion of the connection board FCB may overlap a portion of the top surface of the main board MCB.

[0095] In some embodiments, the main contact pads CP may be arranged on the top surface of the connection board FCB, and the main board pads DP may be arranged on the bottom surface of the main board MCB. In this case, when the main contact pads CP are electrically connected to the main board pads DP, a portion of the main board MCB may overlap a portion of the top surface of the connection board FCB.

[0096] In an exemplary embodiment, the panel pad BP, the connection plate pad AP, the main contact pad CP, and the main board pad DP are terms defined for the purpose of simplicity and convenience of description, and these terms are not intended to limit the scope of the present disclosure.

[0097] The main board MCB may include a main controller MC. The main board MCB may include a signal line for transmitting a control signal and an image signal output from the main controller MC to the main board pad DP. The main board MCB may be a rigid printed circuit board or a flexible printed circuit board.

[0098] exist Figure 3 In order to understand the connection (or contact) of the pads, the panel pad BP is shown as partially offset from the connecting plate pad AP, and the main contact pad CP is shown as partially offset from the main board pad DP. However, the panel pad BP can be fully or completely connected to the connecting plate pad AP, and the main contact pad CP can be fully or completely connected to the main board pad DP. For example, corresponding or paired overlapping pads are aligned without offset so that when multiple pads are pressed together or made vertically connected to each other, contact is made through substantially the entire surface area of ​​the two pads.

[0099] When the main contact pads CP are fully or completely connected to the main board pads DP, the control signals and image signals from the main controller MC can be transmitted to the drive circuit DIC without distortion. In addition, when the panel pads BP are fully or completely connected to the connection board pads AP, the control signals and image signals from the drive circuit DIC can be transmitted to the display panel DPL without distortion.

[0100] Figure 5 1 is a plan view showing connection of a display panel DPL and a connection board FCB1 and connection of the connection board FCB1 and a main board MCB1 in a display device DD1 according to an embodiment of the present disclosure.

[0101] Reference Figure 5 , the display panel DPL may include first to fourth panel pads BP1 to BP4 and panel pads BP. The first to fourth panel pads BP1 to BP4 may be test pads for testing the connection state (or contact state) of the pads of the display panel DPL and the pads of the connection board FCB1. The panel pads BP may be signal pads for receiving control signals and image signals provided from the drive circuit DIC1 to the display panel DPL. The panel pads BP may be electrically connected to Figure 3 The data lines DL, the scan control lines SCL, the initialization voltage lines VINTL and the voltage lines VL are shown in FIG.

[0102] The first panel pad BP1 and the second panel pad BP2 may be arranged adjacent to one side of the display panel DPL, and the third panel pad BP3 and the fourth panel pad BP4 may be arranged adjacent to the other side of the display panel DPL. In other words, the first panel pad BP1 and the second panel pad BP2 may be spaced apart from the third panel pad BP3 and the fourth panel pad BP4 in the first direction DR1.

[0103] The connection board FCB1 may include first to fourth connection board pads AP1 to AP4 and connection board pads AP. The first to fourth connection board pads AP1 to AP4 may be electrically connected to the first to fourth panel pads BP1 to BP4, respectively. The plurality of connection board pads AP may overlap and be electrically connected to the plurality of panel pads BP, respectively.

[0104] exist Figure 5 In an embodiment, the first panel pad BP1 and the second panel pad BP2 may be electrically connected to each other through the first connection line CL1, and the third panel pad BP3 and the fourth panel pad BP4 may be electrically connected to each other through the second connection line CL2. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the first connection line CL1 may be arranged on the connection board FCB1 to electrically connect the first connection board pad AP1 and the second connection board pad AP2. In addition, the second connection line CL2 may be arranged on the connection board FCB1 to electrically connect the third connection board pad AP3 and the fourth connection board pad AP4.

[0105] The connection board FCB1 may include first to fourth panel test lines TL11 to TL14. The driving circuit DIC1 may be electrically connected to first to fourth connection board pads AP1 to AP4 through the first to fourth panel test lines TL11 to TL14, respectively.

[0106] In addition, the connection board FCB1 may include an output pad CPO. The output pad CPO may be electrically connected to the driving circuit DIC1 through the first signal line SL1.

[0107] The main board MCB1 may include a first test pad DPO. The first test pad DPO may overlap and be connected to the output pad CPO. Therefore, the main board MCB1 may be electrically connected to the driving circuit DIC1 through (via) the first test pad DPO and the output pad CPO.

[0108] Figure 6 It is shown Figure 5 A circuit diagram of a circuit configuration of the driving circuit DIC1.

[0109] Reference Figure 5 and Figure 6 , the driving circuit DIC1 may include a first contact test circuit CT11, a second contact test circuit CT12, and an output circuit OUTC. The first contact test circuit CT11 may test the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2, respectively, and may output a first contact test signal CTS1. The second contact test circuit CT12 may test the connection state (or contact state) of the third panel pad BP3 and the fourth panel pad BP4 with the third connection plate pad AP3 and the fourth connection plate pad AP4, respectively, and may output a second contact test signal CTS2. The output circuit OUTC may receive the first contact test signal CTS1 and the second contact test signal CTS2, and may output a contact test signal CTS.

[0110] The first contact test circuit CT11 may include a pull-up resistor Rpu1 and a first comparator CMP11. The pull-up resistor Rpu1 may be electrically connected between a first voltage terminal V1 and a first node N1. The first voltage terminal V1 may receive a power supply voltage VDD. The first connection plate pad AP1 may be electrically connected to the first node N1. The second connection plate pad AP2 may be electrically connected to a second voltage terminal V2. The second voltage terminal V2 may receive a ground voltage VSS. The ground voltage VSS may be a voltage of a level lower than the power supply voltage VDD.

[0111] The first comparator CMP11 may compare the voltage at the first node N1 with the reference voltage VREF received through the third voltage terminal V3, and may output a first contact test signal CTS1 corresponding to the comparison result. When the voltage at the first node N1 is higher in level than the reference voltage VREF, the first comparator CMP11 may output the first contact test signal CTS1 at an activation level (e.g., a low level). In addition, when the voltage at the first node N1 is lower in level than the reference voltage VREF, the first comparator CMP11 may output the first contact test signal CTS1 at an inactive level (e.g., a high level). In an exemplary embodiment, the "low level" or "activation level" of the first contact test signal CTS1 corresponds to the detection of a bad connection (or bad contact), and the "high level" or "inactive level" of the first contact test signal CTS1 corresponds to the detection of a bad connection (or bad contact), that is, a normal connection. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the high level of the first contact test signal CTS1 may be defined as an activation level, and the low level of the first contact test signal CTS1 may be defined as an inactive level.

[0112] like Figure 5 and Figure 6 As shown in , when the first panel pad BP1 and the second panel pad BP2 are electrically connected to the first connection plate pad AP1 and the second connection plate pad AP2, a current path from the first voltage terminal V1 through the first panel test line TL11, the first connection plate pad AP1, the first panel pad BP1, the first connection line CL1, the second panel pad BP2, the second connection plate pad AP2, and the second panel test line TL12 to the second voltage terminal V2 can be formed. Therefore, according to the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2, the voltage divided by the pull-up resistor Rpu1 and the contact resistor CR11 can be set at the first node N1.

[0113] Figure 6 The contact resistance CR11 shown in the figure may be a dummy resistance, and the resistance value of the contact resistance CR11 may change according to the connection state of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2. For example, when the first panel pad BP1 and the second panel pad BP2 are fully or completely connected to the first connection plate pad AP1 and the second connection plate pad AP2, the resistance value of the contact resistance CR11 may be relatively low and less than a set value or a predetermined value. In this case, the voltage at the first node N1 may be lower in level than the reference voltage VREF, and the first comparator CMP11 may output a first contact test signal CTS1 of a non-activation level (e.g., a high level).

[0114] On the contrary, when the first panel pad BP1 and the second panel pad BP2 are not completely connected to or are not connected to the first connection plate pad AP1 and the second connection plate pad AP2, the resistance value of the contact resistor CR11 may be relatively large and higher in level than the set value or the predetermined value (e.g., as compared with VREF according to the equation V=IR). In this case, the voltage at the first node N1 may be higher than the reference voltage VREF, and the first comparator CMP11 may output the first contact test signal CTS1 of the activation level (e.g., low level).

[0115] The second contact test circuit CT12 may include a pull-up resistor Rpu2 and a second comparator CMP12. The pull-up resistor Rpu2 may be electrically connected between the first voltage terminal V1 and the second node N2. The first voltage terminal V1 may receive a power supply voltage VDD. The third connection plate pad AP3 may be electrically connected to the second node N2. The fourth connection plate pad AP4 may be electrically connected to the second voltage terminal V2 receiving the ground voltage VSS.

[0116] The second comparator CMP12 may compare the voltage at the second node N2 with the reference voltage VREF received through the third voltage terminal V3, and may output a second contact test signal CTS2 corresponding to the comparison result. When the voltage at the second node N2 is higher in level than the reference voltage VREF, the second comparator CMP12 may output the second contact test signal CTS2 at an activation level (e.g., a low level). In addition, when the voltage at the second node N2 is lower in level than the reference voltage VREF, the second comparator CMP12 may output the second contact test signal CTS2 at an inactive level (e.g., a high level).

[0117] like Figure 5 and Figure 6 As shown in , when the third panel pad BP3 and the fourth panel pad BP4 are electrically connected to the third connection plate pad AP3 and the fourth connection plate pad AP4, a current path from the first voltage terminal V1 through the third panel test line TL13, the third connection plate pad AP3, the third panel pad BP3, the second connection line CL2, the fourth panel pad BP4, the fourth connection plate pad AP4 and the fourth panel test line TL14 to the second voltage terminal V2 can be formed. Therefore, according to the connection state (or contact state) of the third panel pad BP3 and the fourth panel pad BP4 and the third connection plate pad AP3 and the fourth connection plate pad AP4, the voltage divided by the pull-up resistor Rpu2 and the contact resistor CR12 can be set at the second node N2.

[0118] Figure 6The contact resistor CR12 shown in the figure may be a dummy resistor, and the resistance value of the contact resistor CR12 may change according to the connection state of the third panel pad BP3 and the fourth panel pad BP4 with the third connection plate pad AP3 and the fourth connection plate pad AP4. For example, when the third panel pad BP3 and the fourth panel pad BP4 are fully or completely connected to the third connection plate pad AP3 and the fourth connection plate pad AP4, the resistance value of the contact resistor CR12 may be relatively low and less than a set value or a predetermined value. In this case, the voltage at the second node N2 may be lower than the reference voltage VREF in level, and the second comparator CMP12 may output a second contact test signal CTS2 of a non-activation level (e.g., a high level).

[0119] On the contrary, when the third panel pad BP3 and the fourth panel pad BP4 are not completely connected to or are not connected to the third connection plate pad AP3 and the fourth connection plate pad AP4, the resistance value of the contact resistor CR12 may be relatively large and greater than the set value or the predetermined value in level. In this case, the voltage at the second node N2 may be higher than the reference voltage VREF in level, and the second comparator CMP12 may output the second contact test signal CTS2 of the activation level (e.g., low level).

[0120] The output circuit OUTC may receive the first contact test signal CTS1 and the second contact test signal CTS2, and may output the contact test signal CTS to the output pad CPO through the first signal line SL1. When at least one of the first contact test signal CTS1 and the second contact test signal CTS2 is at an active level (e.g., a low level), the output circuit OUTC may output the contact test signal CTS at an active level (e.g., a low level). When both the first contact test signal CTS1 and the second contact test signal CTS2 are at an inactive level (e.g., a high level simultaneously or concurrently), the output circuit OUTC may output the contact test signal CTS at an inactive level (e.g., a high level).

[0121] In other words, when it is determined that the first panel pad BP1 to the fourth panel pad BP4 are fully or completely connected to the first connection plate pad AP1 to the fourth connection plate pad AP4, the drive circuit DIC1 may output a contact test signal CTS of a non-activation level (e.g., a high level) indicating a normal connection. When it is determined that at least one of the first panel pad BP1 to the fourth panel pad BP4 is not fully connected to at least one of the first connection plate pad AP1 to the fourth connection plate pad AP4, the drive circuit DIC1 may output a contact test signal CTS of an activation level (e.g., a low level) indicating that a poor connection is detected. The contact test signal CTS output from the drive circuit DIC1 may be transmitted to the main controller MC through (via) the first signal line SL1, the output pad CPO, and the first test pad DPO.

[0122] When the display panel DPL is electrically connected to the connection board FCB1, the driving circuit DIC1 according to the embodiment of the present disclosure can test the connection state of the first panel pad BP1 to the fourth panel pad BP4 and the first connection board pad AP1 to the fourth connection board pad AP4, and can output the contact test signal CTS. Therefore, the manufacturer or user of the display device DD1 can easily determine the connection state of the display panel DPL and the connection board FCB1 by using the contact test signal CTS received from the driving circuit DIC1 to the main controller MC. In particular, the connection state of the display panel DPL and the connection board FCB1 can be tested without the need for an additional test device or probe, and thus the manufacturing cost and the test time can be reduced.

[0123] Figure 7 1 is a plan view showing the connection between the display panel DPL and the connection board FCB2 and the connection between the connection board FCB2 and the main board MCB2 in the display device DD2 according to the embodiment of the present disclosure. Figure 7 In the implementation mode, Figure 5 The same components in the embodiments will be indicated by the same figure marks, and their detailed description will be omitted.

[0124] Figure 7 The display panel DPL, the connection board FCB2 and the main board MCB2 of the display device DD2 shown in FIG. Figure 5 The display panel DPL, the connection board FCB1 and the main board MCB1 of the display device DD1 shown in FIG. Figure 7 The connection board FCB2 may include a second signal line SL2 and an input pad CPI. The input pad CPI may be electrically connected to the driving circuit DIC2 through the second signal line SL2.

[0125] The main board MCB2 may include a second test pad DPI. The second test pad DPI may be electrically connected to the input pad CPI. The main board MCB2 may be electrically connected to the driving circuit DIC2 through the second test pad DPI.

[0126] Figure 8 It is shown Figure 7 This is a circuit diagram of the circuit configuration of the driving circuit DIC2. Figure 8 In the implementation mode, Figure 6 The same components in the embodiments will be indicated by the same figure marks, and their detailed description will be omitted.

[0127] Reference Figure 7 and Figure 8, the driving circuit DIC2 may include a first contact test circuit CT21, a second contact test circuit CT22 and an output circuit OUTC. The first contact test circuit CT21 may test the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection pad AP1 and the second connection pad AP2 in response to the switch control signal SC1 input through the input pad CPI, and may output a first contact test signal CTS1. The switch control signal SC1 may be Figure 7 The main controller MC of the main board MCB2 shown in FIG. 1 is output and can be transmitted to the driving circuit DIC2 through (via) the second test pad DPI and the input pad CPI of the connection board FCB2.

[0128] The first contact test circuit CT21 may include a pull-up resistor Rpu1, a switch SW21, and a first comparator CMP21. The pull-up resistor Rpu1 may be electrically connected between the first voltage terminal V1 and the first node N1. The switch SW21 may be electrically connected between the first node N1 and the first connection plate pad AP1, and may be turned on / off in response to a switch control signal SC1. The first voltage terminal V1 may receive a power supply voltage VDD. The second connection plate pad AP2 may be electrically connected to a second voltage terminal V2 that receives a ground voltage VSS.

[0129] When the switch control signal SC1 is at a set level or a predetermined level (e.g., a high level), the switch SW21 may be turned on. In other words, when the switch control signal SC1 is at a high level, a current path may be formed from the first voltage terminal V1 through the switch SW21, the first panel test line TL11, the first connection plate pad AP1, the first panel pad BP1, the first connection line CL1, the second panel pad BP2, the second connection plate pad AP2, and the second panel test line TL12 to the second voltage terminal V2. Therefore, according to the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2, the voltage divided by the pull-up resistor Rpu1 and the contact resistor CR21 may be set at the first node N1.

[0130] The second contact test circuit CT22 may test the connection state (or contact state) of the third panel pad BP3 and the fourth panel pad BP4 with the third connection plate pad AP3 and the fourth connection plate pad AP4 in response to the switch control signal SC1 input through the input pad CPI, and may output a second contact test signal CTS2. The output circuit OUTC may receive the first contact test signal CTS1 and the second contact test signal CTS2, and may output the contact test signal CTS.

[0131] The second contact test circuit CT22 may include a pull-up resistor Rpu2, a switch SW22, and a second comparator CMP22. The pull-up resistor Rpu2 may be electrically connected between the first voltage terminal V1 and the second node N2. The switch SW22 may be electrically connected between the second node N2 and the third connection plate pad AP3, and may be turned on / off in response to a switch control signal SC1. The first voltage terminal V1 may receive a power supply voltage VDD. The fourth connection plate pad AP4 may be electrically connected to a second voltage terminal V2 receiving a ground voltage VSS.

[0132] When the switch control signal SC1 is at a set level or a predetermined level (e.g., a high level), the switch SW22 may be turned on. In other words, when the switch control signal SC1 is at a high level, a current path from the first voltage terminal V1 through the switch SW22, the third panel test line TL13, the third connection plate pad AP3, the third panel pad BP3, the second connection line CL2, the fourth panel pad BP4, the fourth connection plate pad AP4, and the fourth panel test line TL14 to the second voltage terminal V2 may be formed. Therefore, according to the connection state (or contact state) of the third panel pad BP3 and the fourth panel pad BP4 with the third connection plate pad AP3 and the fourth connection plate pad AP4, the voltage divided by the pull-up resistor Rpu2 and the contact resistor CR22 may be set at the second node N2.

[0133] The first contact test circuit CT21 and the second contact test circuit CT22 can operate in response to the switch control signal SC1. In the test mode, Figure 7 The main controller MC may output the switch control signal SC1 at a set level or a predetermined level (eg, a high level) to test the connection state of the display panel DPL and the connection board FCB2.

[0134] Fig. 9 1 is a plan view showing the connection between the display panel DPL and the connection board FCB3 and the connection between the connection board FCB3 and the main board MCB3 in the display device DD3 according to the embodiment of the present disclosure. Fig. 9 In the implementation mode, Figure 5 The same components in the embodiments will be indicated by the same figure marks, and their detailed description will be omitted.

[0135] Fig. 9The connection board FCB3 may include a first main contact pad CP1 and a second main contact pad CP2, a first panel test line TL31 and a second panel test line TL32, a second signal line SL2, and an input pad CPI. The main board MCB3 may include a first main board pad DP1 and a second main board pad DP2, a second test pad DPI, and an intermediate connection line CL31. The intermediate connection line CL31 may electrically connect the first main board pad DP1 and the second main board pad DP2. In some embodiments, the intermediate connection line CL31 may be arranged on or in the connection board FCB3 to electrically connect the first main contact pad CP1 and the second main contact pad CP2.

[0136] Fig.10 It is shown Fig. 9 A circuit diagram of the circuit configuration of the driving circuit DIC3.

[0137] Reference Fig. 9 and Fig.10 , the driving circuit DIC3 may include a contact test circuit CT31. The contact test circuit CT31 may test the connection state (or contact state) of the first main contact pad CP1 and the second main contact pad CP2 with the first main pad DP1 and the second main pad DP2 in response to the switch control signal SC input through the input pad CPI, and may output a contact test signal CTS. The switch control signal SC may be Fig. 9 The main controller MC of the main board MCB3 shown in the figure can be output and can be transmitted to the driving circuit DIC3 through the second test pad DPI and the input pad CPI of the connection board FCB3.

[0138] The contact test circuit CT31 may include a pull-up resistor Rpu, a switch SW31, and a comparator CMP31. The pull-up resistor Rpu may be electrically connected between a first voltage terminal V1 and a first node N1. The first voltage terminal V1 may receive a power supply voltage VDD. The switch SW31 may be electrically connected between the first node N1 and a first main contact pad CP1, and may be turned on / off in response to a switch control signal SC. The second main contact pad CP2 may be electrically connected to a second voltage terminal V2 receiving a ground voltage VSS.

[0139] When the switch control signal SC is at a set level or a predetermined level (e.g., a high level), the switch SW31 can be turned on. In other words, when the switch control signal SC is at a high level, a current path from the first voltage terminal V1 through the switch SW31, the first panel test line TL31, the first main contact pad CP1, the first main board pad DP1, the intermediate connection line CL31, the second main board pad DP2, the second main contact pad CP2, and the second panel test line TL32 to the second voltage terminal V2 can be formed. Therefore, according to the connection state (or contact state) of the first main contact pad CP1 and the second main contact pad CP2 with the first main board pad DP1 and the second main board pad DP2, the voltage divided by the pull-up resistor Rpu and the contact resistor CR31 can be set at the first node N1.

[0140] The contact test circuit CT31 can operate in response to the switch control signal SC. In the test mode, Fig. 9 The main controller MC may output the switch control signal SC at a set level or a predetermined level (eg, a high level) to test the connection status of the connection board FCB3 and the main board MCB3.

[0141] Fig.11 1 is a plan view showing connection of a display panel DPL and a connection board FCB4 and connection of the connection board FCB4 and a main board MCB4 in a display device DD4 according to an embodiment of the present disclosure.

[0142] Reference Fig.11 , the display panel DPL may include first and second panel pads BP1 and BP2, panel pads BP, and connection lines CL1. The first and second panel pads BP1 and BP2 may be test pads for testing the connection state (or contact state) of the pads of the display panel DPL and the pads of the connection board FCB4. The panel pads BP may be signal pads for receiving control signals and image signals provided to the display panel DPL from the drive circuit DIC4. The panel pads BP may be electrically connected to Figure 3 The data lines DL, the scan control lines SCL, the initialization voltage lines VINTL and the voltage lines VL are shown in FIG.

[0143] The connection board FCB4 may include a first connection board pad AP1 and a second connection board pad AP2, a first main contact pad CP1 to a fourth main contact pad CP4, a first panel test line TL41 to a fifth panel test line TL45, a first signal line SL1 to a third signal line SL3, a first input pad CPI1 and a second input pad CPI2, an output pad CPO, an intermediate connection line CL41 and a driving circuit DIC4.

[0144] The first panel test line TL41 and the second panel test line TL42 can electrically connect the first connection plate pad AP1 and the second connection plate pad AP2 to the first main contact pad CP1 and the second main contact pad CP2, respectively. The third panel test line TL43 to the fifth panel test line TL45 can electrically connect the second main contact pad CP2 to the fourth main contact pad CP4 to the driving circuit DIC4.

[0145] The first to third signal lines SL1 to SL3 may electrically connect the output pad CPO and the first and second input pads CPI1 and CPI2 to the driving circuit DIC4. The intermediate connection line CL41 may electrically connect the first main contact pad CP1 to the fourth main contact pad CP4.

[0146] The main board MCB4 may include first to fourth main board pads DP1 to DP4, first test pads DPO, second test pads DPI1, third test pads DPI2, main connection lines CL42, and a main controller MC. The main connection lines CL42 may electrically connect the third main board pad DP3 to the fourth main board pad DP4.

[0147] Fig.12 It is shown Fig.11 A circuit diagram of the circuit configuration of the driving circuit DIC4.

[0148] Reference Fig.11 and Fig.12 , the driving circuit DIC4 may include a contact test circuit CT41. The contact test circuit CT41 may test the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2 in response to the first switch control signal SC1 input through the first input pad CPI1, and may output a contact test signal CTS. The contact test circuit CT41 may also test the connection state (or contact state) of the third main contact pad CP3 and the fourth main contact pad CP4 with the third main board pad DP3 and the fourth main board pad DP4 in response to the second switch control signal SC2 input through the second input pad CPI2, and may output a contact test signal CTS. The first switch control signal SC1 may be input from Fig.11 The second switch control signal SC2 can be output from the main controller MC of the main board MCB4 shown in FIG. 1 and can be transmitted to the drive circuit DIC4 through the second test pad DPI1 and the first input pad CPI1 of the connection board FCB4. Fig.11 The main controller MC of the main board MCB4 shown in the figure can be output and can be transmitted to the driving circuit DIC4 through the third test pad DPI2 and the second input pad CPI2 of the connection board FCB4.

[0149] The contact test circuit CT41 may include a pull-up resistor Rpu, a first switch SW41, a second switch SW42, and a comparator CMP41. The pull-up resistor Rpu may be electrically connected between the first voltage terminal V1 and the first node N1. The first voltage terminal V1 may receive a power supply voltage VDD. The first switch SW41 may be electrically connected between the first node N1 and the second main contact pad CP2, and may be turned on / off in response to a first switch control signal SC1. The second switch SW42 may be electrically connected between the first node N1 and the third main contact pad CP3, and may be turned on / off in response to a second switch control signal SC2. The fourth main contact pad CP4 may be electrically connected to a second voltage terminal V2 receiving a ground voltage VSS. The first main contact pad CP1 may be electrically connected to the second voltage terminal V2 through an intermediate connection line CL41 and the fourth main contact pad CP4.

[0150] When the first switch control signal SC1 is at a set level or a predetermined level (e.g., a high level), the first switch SW41 may be turned on. In other words, when the first switch control signal SC1 is at a high level, a current path from the first voltage terminal V1 through the first switch SW41, the third panel test line TL43, the second main contact pad CP2, the second panel test line TL42, the second connection plate pad AP2, the second panel pad BP2, the connection line CL1, the first panel pad BP1, the first connection plate pad AP1, the first panel test line TL41, the first main contact pad CP1, the middle connection line CL41, the fourth main contact pad CP4 and the fifth panel test line TL45 to the second voltage terminal V2 may be formed. Therefore, according to the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2, the voltage divided by the pull-up resistor Rpu and the contact resistor CR41 may be set at the first node N1.

[0151] When the second switch control signal SC2 is at a set level or a predetermined level (e.g., a high level), the second switch SW42 may be turned on. In other words, when the second switch control signal SC2 is at a high level, a current path from the first voltage terminal V1 through the second switch SW42, the fourth panel test line TL44, the third main contact pad CP3, the third main board pad DP3, the main connection line CL42, the fourth main board pad DP4, the fourth main contact pad CP4, and the fifth panel test line TL45 to the second voltage terminal V2 may be formed. Therefore, according to the connection state (or contact state) of the third main contact pad CP3 and the fourth main contact pad CP4 with the third main board pad DP3 and the fourth main board pad DP4, the voltage divided by the pull-up resistor Rpu and the contact resistor CR42 may be set at the first node N1.

[0152] The comparator CMP41 may compare the voltage at the first node N1 with the reference voltage VREF received through the third voltage terminal V3, and may output a contact test signal CTS corresponding to the comparison result. When the voltage at the first node N1 is higher in level than the reference voltage VREF, the comparator CMP41 may output the contact test signal CTS at an activation level (e.g., a low level). In addition, when the voltage at the first node N1 is lower in level than the reference voltage VREF, the comparator CMP41 may output the contact test signal CTS at an inactive level (e.g., a high level). The contact test circuit CT41 may operate in response to the first switch control signal SC1 and the second switch control signal SC2. In the test mode, Fig.11 The main controller MC may sequentially output the first switch control signal SC1 and the second switch control signal SC2 at a set level or a predetermined level (eg, a high level) to test the connection state between the display panel DPL and the connection board FCB4 and the connection state between the connection board FCB4 and the main board MCB4.

[0153] Fig.13 2 is a diagram showing transmission signals between the drive circuit DIC4 and the main controller MC.

[0154] Reference Fig.11 , Fig.12 and Fig.13 , the driving circuit DIC4 and the main controller MC can be electrically connected to each other through one of various suitable interface methods. The interface method can be a universal serial interface (USI), a CPU interface, an RGB interface, a mobile industry processor interface (MIPI), a mobile display digital interface (MDDI), a compact display port (CDP), a mobile pixel link (MPL), a current mode advanced differential signal (CMADS), a serial peripheral interface (SPI), an inter-integrated circuit (I2C) interface, a display port (DP) and an embedded display port (eDP) interface, a camera control interface (CCI), a camera serial interface (CSI), a microcontroller unit (MCU) interface, a high-definition multimedia interface (HDMI) or an intra-panel interface (IPI). In addition, the interface method can be one of various high-speed serial interface methods.

[0155] The main controller MC may provide the power supply voltage VDD and the transmission data TD to the driving circuit DIC4. After starting the supply of the power supply voltage VDD, the main controller MC may transmit the system clock signal and the reference signal to the driving circuit DIC4 during the training period TRN_P. The main controller MC may output the power supply voltage VDD and the transmission data TD to the Figure 3 The main board pad DP shown in FIG. 4 is a main contact pad DP, and the driving circuit DIC4 can receive the power supply voltage VDD and the transmission data TD by connecting to the main contact pad CP of the main board pad DP.

[0156] The driving circuit DIC4 may reset a clock signal required for the operation of the display panel DPL based on the system clock signal and the reference signal received therein, and may perform an operation for optimizing or improving a receiving operation.

[0157] After the training period TRN_P ends, before the start of the data period DATA_P for starting the reception of the image data signal RGB, in the control period CTRL_P, the main controller MC may provide the first switch control signal SC1 and the second switch control signal SC2 to the driving circuit DIC4. Here, the first activation period AAP1 of the first switch control signal SC1 may be different from the second activation period AAP2 of the second switch control signal SC2.

[0158] The driving circuit DIC4 may test the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2 during the first activation period AAP1 of the first switch control signal SC1, and may output a contact test signal CTS. When the first panel pad BP1 and the second panel pad BP2 are sufficiently or completely connected to the first connection plate pad AP1 and the second connection plate pad AP2, the contact test signal CTS may be at an inactive level (e.g., a high level).

[0159] The drive circuit DIC4 may test the connection state (or contact state) of the third main contact pad CP3 and the fourth main contact pad CP4 with the third main board pad DP3 and the fourth main board pad DP4 during the second activation period AAP2 of the second switch control signal SC2, and may output a contact test signal CTS. When the third main contact pad CP3 and the fourth main contact pad CP4 are fully or completely connected to the third main board pad DP3 and the fourth main board pad DP4, the contact test signal CTS may be at an inactive level (e.g., a high level).

[0160] When the connection state between the display panel DPL and the connection board FCB4 and the connection state between the connection board FCB4 and the main board MCB4 are both in a normal state (for example, at the same time), the contact test signal CTS may be in an inactive level in both the first activation period AAP1 and the second activation period AAP2 (for example, at the same time). When at least one of the connection state between the display panel DPL and the connection board FCB4 or the connection state between the connection board FCB4 and the main board MCB4 is a bad connection state, the contact test signal CTS may be in an active level (for example, a low level) corresponding to the bad connection state in the first activation period AAP1 and / or the second activation period AAP2.

[0161] The main controller MC may check the signal level of the contact test signal CTS in the first activation period AAP1 and the second activation period AAP2 to determine whether the connection status between the display panel DPL and the connection board FCB4 and the connection status between the connection board FCB4 and the main board MCB4 are normal.

[0162] exist Fig.13 In the control period CTRL_P, a test mode for testing the connection state of the display panel DPL and the connection board FCB4 and the connection state of the connection board FCB4 and the main board MCB4 is performed. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the main controller MC may perform a test mode of providing the first switch control signal SC1 and the second switch control signal SC2 to the drive circuit DIC4 in a blanking period (e.g., a horizontal blanking period or a vertical blanking period) of the data period DATA_P for receiving the image data signal RGB.

[0163] Fig.14 1 is a plan view showing connection of a display panel DPL and a connection board FCB5 and connection of the connection board FCB5 and a main board MCB5 in a display device DD5 according to an embodiment of the present disclosure.

[0164] Reference Fig.14 , the display panel DPL may include first and second panel pads BP1 and BP2, panel pads BP, and connection lines CL1. The first and second panel pads BP1 and BP2 may be test pads for testing the connection state (or contact state) of the pads of the display panel DPL and the pads of the connection board FCB5. The panel pads BP may be signal pads for receiving control signals and image signals provided to the display panel DPL from the drive circuit DIC5. The panel pads BP may be electrically connected to Figure 3 The data lines DL, the scan control lines SCL, the initialization voltage lines VINTL and the voltage lines VL are shown in FIG.

[0165] The connection board FCB5 may include a first connection board pad AP1 and a second connection board pad AP2, a first main contact pad CP1 to a third main contact pad CP3, a first panel test line TL51 to a fourth panel test line TL54, a first signal line SL1 and a second signal line SL2, an input pad CPI, an output pad CPO, an intermediate connection line CL51 and a driving circuit DIC5.

[0166] The first panel test line TL51 and the second panel test line TL52 can electrically connect the first connection plate pad AP1 and the second connection plate pad AP2 to the first main contact pad CP1 and the second main contact pad CP2, respectively. The third panel test line TL53 and the fourth panel test line TL54 can electrically connect the second main contact pad CP2 and the third main contact pad CP3 to the driving circuit DIC5.

[0167] The first and second signal lines SL1 and SL2 may electrically connect the output pads CPO and the input pads CPI to the driving circuit DIC5.

[0168] The main board MCB5 may include first to third main board pads DP1 to DP3, first and second test pads DPO and DPI, and a main controller MC. The intermediate connection line CL51 may electrically connect the first to third main contact pads CP1 to CP3.

[0169] Fig.15 It is shown Fig.14 A circuit diagram of the circuit configuration of the driving circuit DIC5.

[0170] Reference Fig.14 and Fig.15 , the driving circuit DIC5 may include a contact test circuit CT51. The contact test circuit CT51 may test the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection pad AP1 and the second connection pad AP2 in response to the switch control signal SC input through the input pad CPI, and may output a contact test signal CTS. The switch control signal SC may be Fig.14 The main controller MC of the main board MCB5 shown in the figure can be output and can be transmitted to the driving circuit DIC5 through the second test pad DPI and the input pad CPI of the connection board FCB5.

[0171] The contact test circuit CT51 may include a pull-up resistor Rpu, a switch SW51, and a comparator CMP51. The pull-up resistor Rpu may be electrically connected between the first voltage terminal V1 and the first node N1. The first voltage terminal V1 may receive a power supply voltage VDD. The switch SW51 may be electrically connected between the first node N1 and the second main contact pad CP2, and may be turned on / off in response to a switch control signal SC. The third main contact pad CP3 may be electrically connected to the second voltage terminal V2 receiving the ground voltage VSS. The first main contact pad CP1 may be electrically connected to the second voltage terminal V2 through the intermediate connection line CL51 and the third main contact pad CP3.

[0172] When the switch control signal SC is at a set level or a predetermined level (e.g., a high level), the switch SW51 can be turned on. In other words, when the switch control signal SC is at a high level, a current path from the first voltage terminal V1 through the switch SW51, the third panel test line TL53, the second main contact pad CP2, the second panel test line TL52, the second connection plate pad AP2, the second panel pad BP2, the connection line CL1, the first panel pad BP1, the first connection plate pad AP1, the first panel test line TL51, the first main contact pad CP1, the middle connection line CL51, the third main contact pad CP3 and the fourth panel test line TL54 to the second voltage terminal V2 can be formed. Therefore, according to the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2, the voltage divided by the pull-up resistor Rpu and the contact resistor CR51 can be set at the first node N1.

[0173] The comparator CMP51 may compare the voltage at the first node N1 with the reference voltage VREF received through the third voltage terminal V3, and may output a contact test signal CTS corresponding to the comparison result. When the voltage at the first node N1 is higher in level than the reference voltage VREF, the comparator CMP51 may output the contact test signal CTS at an activation level (e.g., a low level). In addition, when the voltage at the first node N1 is lower in level than the reference voltage VREF, the comparator CMP51 may output the contact test signal CTS at an inactive level (e.g., a high level).

[0174] In test mode, Fig.14 The main controller MC may output the switch control signal SC at a set level or a predetermined level (eg, a high level) to test the connection state of the display panel DPL and the connection board FCB5.

[0175] Fig.16 is a plan view showing a display device DD6 according to an embodiment of the present disclosure.

[0176] Reference Fig.16, the display device DD6 may include a display panel DPL6, a first connection board FCB11 to a fourth connection board FCB14, and a main board MCB6. The first connection board FCB11 to the fourth connection board FCB14 may include a first drive circuit DIC11 to a fourth drive circuit DIC14, respectively. Each of the first drive circuit DIC11 to the fourth drive circuit DIC14 may be an integrated circuit (IC). The first connection board FCB11 to the fourth connection board FCB14 may be a flexible printed circuit board on which the first drive circuit DIC11 to the fourth drive circuit DIC14 with integrated circuits is mounted. For example, each of the first connection board FCB11 to the fourth connection board FCB14 may be a chip on film (COF). In addition to each of the first drive circuit DIC11 to the fourth drive circuit DIC14, each of the first connection board FCB11 to the fourth connection board FCB14 may include other integrated circuits.

[0177] The display panel DPL6 may include first to fourth panel pads BP1 to BP4 corresponding to the first connection board FCB11. Fig.16 , the first panel pads BP1 to the fourth panel pads BP4 corresponding to the first connection board FCB11 are shown. However, the display panel DPL6 may include the first panel pads BP1 to the fourth panel pads BP4 corresponding to each of the second connection board FCB12 to the fourth connection board FCB14. In some embodiments, the display panel DPL6 may include the first panel pads BP1 to the fourth panel pads BP4 corresponding to one or some of the first connection board FCB11 to the fourth connection board FCB14. For example, the display panel DPL6 may include the first panel pads BP1 to the fourth panel pads BP4 corresponding to the first connection board FCB11 and the first panel pads BP1 to the fourth panel pads BP4 corresponding to the fourth connection board FCB14, but may not include the first panel pads BP1 to the fourth panel pads corresponding to each of the second connection board FCB12 and the third connection board FCB13.

[0178] Fig.16 The display panel DPL6 includes four panel pads (ie, first to fourth panel pads BP1 to BP4) corresponding to the first connection board FCB11. As an example, the display panel DPL6 may include only the first and second panel pads BP1 to BP2.

[0179] The first panel pad BP1 and the second panel pad BP2 may be electrically connected to each other through the connection line CL1. The third panel pad BP3 and the fourth panel pad BP4 may be electrically connected to each other through the connection line CL2.

[0180] The first panel pad BP1 and the second panel pad BP2 may be arranged adjacent to one side of the display panel DPL6, and the third panel pad BP3 and the fourth panel pad BP4 may be arranged adjacent to the other side of the display panel DPL6. In other words, the first panel pad BP1 and the second panel pad BP2 may be spaced apart from the third panel pad BP3 and the fourth panel pad BP4 in the first direction DR1.

[0181] The first connection board FCB11 may include first to fourth connection board pads AP1 to AP4. The first to fourth connection board pads AP1 to AP4 may be electrically connected to first to fourth panel pads BP1 to BP4, respectively. Fig.16 Only the first to fourth connection board pads AP1 to AP4 of the first connection board FCB11 are shown. However, each of the second to fourth connection boards FCB12 to FCB14 may include first to fourth connection board pads substantially the same as the first to fourth connection board pads AP1 to AP4 of the first connection board FCB11.

[0182] The first connection board FCB11 may include first to fourth panel test lines TL11 to TL14. The first driving circuit DIC11 may be electrically connected to first to fourth connection board pads AP1 to AP4 through the first to fourth panel test lines TL11 to TL14, respectively.

[0183] The first driving circuit DIC11 can test the connection state (or contact state) of the first panel pad BP1 and the second panel pad BP2 with the first connection plate pad AP1 and the second connection plate pad AP2. The first driving circuit DIC11 can output the first contact test signal to the output pad CPO1. The second driving circuit DIC12 to the fourth driving circuit DIC14 can output the second contact test signal to the fourth contact test signal to the plurality of output pads CPO2 to CPO4, respectively.

[0184] The main controller MC may receive the contact test signal through the plurality of test pads DPO1 to DPO4 electrically connected to the plurality of output pads CPO1 to CPO4 .

[0185] Fig.16 Each of the first to fourth connection boards FCB11 to FCB14 may include Figure 5 The connecting board FCB1 is substantially the same component. In some embodiments, Fig.16 Each of the first to fourth connection boards FCB11 to FCB14 may include Figure 7 Connection board FCB2, Fig. 9 Connection board FCB3, Fig.11 Connection board FCB4 and / or Fig.14 The connection board FCB5 has essentially the same components.

[0186] Fig.17 It is shown Fig.16 2 is a circuit diagram of a circuit configuration of a first drive circuit DIC11 to a fourth drive circuit DIC14. Fig.18A and Fig.18B : is a timing chart showing the timing of the first to fourth contact test signals CTS01 to CTS04 output from the first to fourth drive circuits DIC11 to DIC14 and the timing of the contact test signal CTS received in the main controller MC.

[0187] Reference Fig.17 , the first drive circuit DIC11 may include a contact test circuit CT01, an inverter IV1, a pull-up resistor Ru1 and a transistor TR1. The contact test circuit CT01 may test the connection state between the display panel DPL6 and the first connection board FCB11 and / or the connection state between the first connection board FCB11 and the main board MCB6, and may output a first contact test signal CTS01. The inverter IV1 may invert the first contact test signal CTS01, and may output the inverted first contact test signal CTS01. The pull-up resistor Ru1 may be electrically connected between a terminal receiving a power supply voltage VDD and an output pad CPO1. The transistor TR1 may include a first electrode electrically connected to the output pad CPO1, a second electrode receiving a ground voltage VSS, and a gate electrode electrically connected to the output terminal of the inverter IV1.

[0188] Each of the second to fourth drive circuits DIC12 to DIC14 may have a similar circuit configuration as the first drive circuit DIC11 (e.g., as indicated by similar but consecutively numbered reference numerals such as CT01, CT02, CT03, CT04, etc.), and additional detailed descriptions thereof will be omitted.

[0189] For example, when the connection state between the display panel DPL6 and the first connection board FCB11 is normal and the connection state between the first connection board FCB11 and the main board MCB6 is normal, the contact test circuit CT01 can output the first contact test signal CTS01 at a high level. Because the transistor TR1 is turned off when the output signal of the inverter IV1 is at a low level, the voltage level of the output pad CPO1 can be maintained at a high level corresponding to the power supply voltage VDD through the pull-up resistor Ru1.

[0190] When the connection state between the display panel DPL6 and the first connection board FCB11 is a bad connection state or the connection state between the first connection board FCB11 and the main board MCB6 is a bad connection state, the contact test circuit CT01 can output the first contact test signal CTS01 at a low level. Because the transistor TR1 is turned on when the output signal of the inverter IV1 is at a high level, the voltage at the output pad CPO1 can be discharged to the ground voltage VSS. Therefore, the voltage level of the output pad CPO1 can be modified to be at a low level corresponding to the ground voltage VSS.

[0191] like Fig.18A As shown in FIG. 1 , when all of the first contact test signals CTS01 to the fourth contact test signals CTS04 output from the plurality of contact test circuits CT01 to CT04 in the first drive circuit DIC11 to the fourth drive circuit DIC14 are at a high level, all of the plurality of transistors TR1 to TR4 may be turned off, and thus the contact test signal CTS provided to the main controller MC may be at a high level. When the contact test signal CTS is at a high level, the main controller MC may determine Fig.16 All of the first connection board FCB11 to the fourth connection board FCB14 are in a normal connection state.

[0192] like Fig.18B As shown in, the first contact test signal CTS01 and the second contact test signal CTS02 output from the plurality of contact test circuits CT01 and CT02 in the first drive circuit DIC11 and the second drive circuit DIC12 may be at a high level, and the third contact test signal CTS03 and the fourth contact test signal CTS04 output from the plurality of contact test circuits CT03 and CT04 in the third drive circuit DIC13 and the fourth drive circuit DIC14 may be at a low level. In this case, the plurality of transistors TR3 and TR4 may be turned on by the third contact test signal CTS03 and the fourth contact test signal CTS04. Because the plurality of output pads CPO1 to CPO4 are electrically connected in common to each other, the contact test signal CTS provided to the main controller MC may be at a low level. When the contact test signal CTS is at a low level, the main controller MC may determine Fig.16 At least one of the first to fourth connection boards FCB11 to FCB14 is in a poor connection state.

[0193] like Fig.18A and Fig.18BAs shown in , the main controller MC may provide the synchronization signal V_SYNC to the first to fourth driving circuits DIC11 to DIC14. The synchronization signal V_SYNC may be a vertical synchronization signal that is transformed in each frame F of the image signal. The first to fourth driving circuits DIC11 to DIC14 may output the first to fourth contact test signals CTS01 to CTS04 in the blanking period V_B of the synchronization signal V_SYNC. In some embodiments, the first to fourth driving circuits DIC11 to DIC14 may be synchronized with other synchronization signals (e.g., a horizontal synchronization signal or a clock signal) instead of the vertical synchronization signal to output the first to fourth contact test signals CTS01 to CTS04.

[0194] The driving circuit of the display device having the above configuration can test whether the display panel and the connection board are normally connected to each other, and can provide a signal corresponding to the test result to the main controller. In addition, the driving circuit of the display device can test whether the connection board and the main board are normally connected to each other, and can provide a signal corresponding to the test result to the main controller. Therefore, the manufacturing process efficiency of the display device can be improved.

[0195] For example, the electronic or electrical devices and / or any other related devices or components (such as, for example, timing controllers, data drivers, and gate drivers) described herein according to the embodiments of the present disclosure can be implemented by utilizing any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, and the computing device executes computer program instructions and interacts with other system components for performing the various functions described herein. Computer program instructions are stored in a memory, and the memory can be implemented in a computing device using a standard storage device (such as, for example, a random access memory (RAM)). Computer program instructions can also be stored in other non-temporary computer-readable media (such as, for example, a CD-ROM or a flash drive). In addition, one of ordinary skill in the art should recognize that the functionality of various computing / electronic devices may be combined or integrated into a single computing / electronic device, or that the functionality of a particular computing / electronic device may be distributed across one or more other computing / electronic devices without departing from the spirit and scope of the present disclosure.

[0196] Although the present disclosure has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Therefore, the scope of the present disclosure will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be restricted or limited by the foregoing description.

Claims

1. A display device, comprising: A display panel, the display panel comprising a first panel pad and a second panel pad electrically connected to each other; as well as A connecting plate, wherein the connecting plate comprises: a first connection plate pad and a second connection plate pad, the first connection plate pad and the second connection plate pad being electrically connected to the first panel pad and the second panel pad, respectively; output pads; and A driving circuit, wherein the driving circuit comprises: a pull-up resistor electrically connected between the first voltage terminal and the first node; and a comparator configured to compare the voltage at the first node with a reference voltage and output a contact test signal corresponding to the comparison result to the output pad; wherein the first connection plate pad is electrically connected to the first node, and the second connection plate pad is electrically connected to a second voltage terminal, The first panel pad and the second panel pad are electrically connected to each other through a first connection line, The connection board further includes a first panel test line and a second panel test line, and the driving circuit is electrically connected to the first connection board pad and the second connection board pad through the first panel test line and the second panel test line, respectively, and A current path is formed between the first voltage terminal and the second voltage terminal, from the first voltage terminal through the pull-up resistor, the first panel test line, the first connecting plate pad, the first panel pad, the first connecting line, the second panel pad, the second connecting plate pad and the second panel test line to the second voltage terminal.

2. The display device according to claim 1, further comprising: a main board, the main board comprising a first test pad electrically connected to the output pad and a main controller, Wherein, the main controller receives the contact test signal through the first test pad.

3. The display device according to claim 1, wherein: The connection board also includes an input pad, Wherein, the driving circuit further includes a switch, and The switch is electrically connected between the first connection plate pad and the first node, and operates in response to a switch control signal input through the input pad.

4. The display device according to claim 3, further comprising: a main board, the main board comprising a first test pad and a second test pad electrically connected to the output pad and the input pad, respectively, and a main controller, The main controller outputs the switch control signal to the second test pad, and receives the contact test signal through the first test pad.

5. The display device according to claim 1, wherein: A first voltage supplied to the first voltage terminal is higher in level than a second voltage supplied to the second voltage terminal.

6. The display device according to claim 5, wherein: When the voltage at the first node is higher in level than the reference voltage, the comparator outputs the contact test signal at an activation level, and Wherein, when the voltage at the first node is lower in level than the reference voltage, the comparator outputs the contact test signal at a non-activation level.

7. A display device, comprising: A display panel, the display panel comprising a first panel pad and a second panel pad electrically connected to each other; A main board, the main board comprising first to fourth main board pads, a first test pad and a main controller; as well as A connecting plate, wherein the connecting plate comprises: a first connection plate pad and a second connection plate pad, the first connection plate pad and the second connection plate pad being electrically connected to the first panel pad and the second panel pad, respectively; first to fourth main contact pads, the first to fourth main contact pads being electrically connected to the first to fourth main board pads, respectively; a first test line and a second test line, the first test line and the second test line electrically connecting the first connection plate pad and the second connection plate pad to the first main contact pad and the second main contact pad, respectively; an intermediate connecting line electrically connecting the first main contact pad to the fourth main contact pad; an output pad electrically connected to the first test pad; and Drive circuit, Wherein, the third mainboard pad and the fourth mainboard pad are electrically connected to each other, Wherein, the driving circuit comprises: a pull-up resistor electrically connected between the first voltage terminal and the first node; and a comparator configured to compare the voltage at the first node with a reference voltage and output a contact test signal corresponding to the comparison result to the output pad; wherein the second main contact pad is electrically connected to the first node, and the first main contact pad is electrically connected to a second voltage terminal through the intermediate connection line and the fourth main contact pad, The main controller receives the contact test signal through the first test pad, The first panel pad and the second panel pad are electrically connected to each other through a connection line, The connection board further includes a third test line and a fifth test line, wherein the third test line and the fifth test line electrically connect the second main contact pad and the fourth main contact pad to the drive circuit, A current path is formed between the first voltage terminal and the second voltage terminal, from the first voltage terminal through the pull-up resistor, the third test line, the second main contact pad, the second test line, the second connecting plate pad, the second panel pad, the connecting line, the first panel pad, the first connecting plate pad, the first test line, the first main contact pad, the intermediate connecting line, the fourth main contact pad and the fifth test line to the second voltage terminal.

8. The display device according to claim 7, wherein: The connection board also includes a first input pad, Wherein, the main board also includes: a main connection line electrically connecting the third main board pad to the fourth main board pad; and a second test pad, the second test pad being electrically connected to the first input pad, and The main controller provides the first switch control signal to the driving circuit through the second test pad.

9. The display device according to claim 8, wherein: The driving circuit further includes a first switch, and The first switch is electrically connected between the second main contact pad and the first node, and operates in response to the first switch control signal input through the first input pad.

10. The display device according to claim 9, wherein: The connection board also includes a second input pad, Wherein, the main board also includes: a third test pad, the third test pad being electrically connected to the second input pad, and The main controller provides the second switch control signal to the driving circuit through the third test pad.

11. The display device according to claim 10, wherein: The driving circuit further includes a second switch, and The second switch is electrically connected between the third main contact pad and the first node, and operates in response to the second switch control signal input through the second input pad.

12. The display device according to claim 11, wherein: The first switch control signal and the second switch control signal are activated at different time points from each other.

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