Non-volatile memory device and method of controlling initialization thereof

Abstract

A method includes performing a first sense operation to sense write set data stored in first memory cells of a first memory plane and storing first read set data in a first page buffer circuit of the first memory plane, performing a second sense operation to sense write set data stored in second memory cells of a second memory plane and storing second read set data in a second page buffer circuit of the second memory plane, and performing a dump operation to store recovery set data corresponding to the write set data in a buffer based on the first read set data and the second read set data.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0092925, filed on July 31, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to non-volatile memory devices and methods for controlling the initialization of non-volatile memory devices. Background Technology

[0004] Non-volatile memory devices, such as flash memory devices and resistive memory devices, can store data by programming each memory cell to have one of two threshold voltage or resistance distributions corresponding to different logic states. Initialization of a non-volatile memory device can include the process of moving stored setup data from one memory device to another. Three-dimensional non-volatile memory devices, such as vertical NAND flash memory devices, are being developed to increase the integration density of memory cells. As the integration density and memory capacity of non-volatile memory devices increase, the time required to initialize them also increases. Summary of the Invention

[0005] On the one hand, it provides a method for initializing non-volatile memory devices and controlling the initialization of non-volatile memory devices, which can perform initialization efficiently.

[0006] According to one or more example embodiments, a method is provided, comprising: performing a first sensing operation to sense write setting data stored in a first memory cell of a first memory plane and storing a first read setting data in a first page buffer circuit of the first memory plane; performing a second sensing operation to sense write setting data stored in a second memory cell of a second memory plane and storing a second read setting data in a second page buffer circuit of the second memory plane; and performing a dump-down operation to store recovery setting data corresponding to the write setting data in a buffer based on the first read setting data and the second read setting data.

[0007] According to another aspect of one or more example embodiments, a method is provided, comprising: performing a first sensing operation to sense write setting data stored in a first memory cell on a first memory plane and storing the first read setting data in a first page buffer circuit on the first memory plane; performing a second sensing operation to sense write setting data stored in a second memory cell on a second memory plane and storing the second read setting data in a second page buffer circuit on the second memory plane; using a first verification circuit connected to the first page buffer circuit to verify the validity of each of a plurality of first data units, the plurality of first data units corresponding to first read setting data divided by a number of bits; using a second verification circuit connected to the second page buffer circuit to verify the validity of each of a plurality of second data units, the plurality of second data units corresponding to second read setting data divided by a number of bits; selectively enabling the first verification circuit and the second verification circuit based on the validity verification results of each of the plurality of first data units and the validity verification results of each of the plurality of second data units; and storing a valid data unit corresponding to one of the first data unit and the second data unit in a buffer based on the validity verification results of each of the plurality of first data units and the validity verification results of each of the plurality of second data units.

[0008] According to another aspect of one or more example embodiments, a non-volatile memory device is provided, comprising: a first memory surface including a first memory cell storing write setting data and a first page buffer circuit storing first read setting data sensed from the first memory cell; a second memory surface including a second memory cell storing write setting data and a second page buffer circuit storing second read setting data sensed from the second memory cell; a first verification circuit connected to the first page buffer circuit, the first verification circuit being configured to verify the validity of the first read setting data; a second verification circuit connected to the second page buffer circuit, the second verification circuit being configured to verify the validity of the second read setting data; dump control logic configured to determine valid data corresponding to one of the first read setting data and the second read setting data based on the validity verification result of the first read setting data and the validity verification result of the second read setting data; and a buffer configured to store valid data provided from the dump control logic. Attached Figure Description

[0009] The exemplary embodiments of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a flowchart illustrating a method for controlling the initialization of a non-volatile memory device according to an example embodiment;

[0011] Figure 2 This is a block diagram illustrating a memory system according to an example embodiment;

[0012] Figure 3 This is a block diagram illustrating a non-volatile memory device according to an example embodiment;

[0013] Figure 4 This illustrates the inclusion of examples according to the embodiment. Figure 3 A block diagram of an example memory cell array in a non-volatile memory device;

[0014] Figure 5 It is shown Figure 4 The circuit diagram of the equivalent circuit of the memory block in the memory;

[0015] Figure 6 This is a diagram illustrating a non-volatile memory device according to an example embodiment;

[0016] Figure 7 , Figure 8 and Figure 9 This is a diagram illustrating an example embodiment of a verification operation suitable for a method of controlling the initialization of a non-volatile memory device according to an example embodiment;

[0017] Figure 10 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment;

[0018] Figures 11 to 18 It is shown that... Figure 10 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data;

[0019] Figure 19 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment;

[0020] Figures 20 to 23 It is shown that... Figure 19 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data;

[0021] Figure 24 This is a diagram illustrating a non-volatile memory device according to an example embodiment;

[0022] Figure 25 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment;

[0023] Figure 26 and Figure 27 It is shown that... Figure 25 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data;

[0024] Figure 28 This is a diagram illustrating a non-volatile memory device according to an example embodiment;

[0025] Figure 29 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment;

[0026] Figure 30 It is shown that... Figure 29 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data;

[0027] Figure 31 This is a flowchart illustrating a method for initializing a non-volatile memory device according to an example embodiment; and

[0028] Figure 32 This is a block diagram illustrating a solid-state drive (SSD) according to an example embodiment. Detailed Implementation

[0029] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. In the drawings, the same reference numerals consistently refer to the same elements. For the sake of brevity, repeated descriptions may be omitted.

[0030] The non-volatile memory device and the method for controlling the initialization of the non-volatile memory device according to various exemplary embodiments can reduce the time of the dump sequence and the overall initialization time for initializing the non-volatile memory device by reading multiple write setting data in parallel and verifying the validity of multiple read setting data by means of complementary schemes.

[0031] Furthermore, the non-volatile memory device and the method for controlling the initialization of the non-volatile memory device according to various exemplary embodiments can reduce the possibility of dump failure and improve the performance of the non-volatile memory device by reading multiple write setting data in parallel and verifying the validity of multiple read setting data by means of complementary schemes.

[0032] Figure 1 This is a flowchart illustrating a method for controlling the initialization of a non-volatile memory device according to an example embodiment.

[0033] Reference Figure 1 The first sensing operation is performed to sense the write setting data stored in the first memory cell of the first memory surface, and the first read setting data is stored in the first page buffer circuit of the first memory surface (S100).

[0034] A second sensing operation is performed to sense write setting data stored in the second memory cell of the second memory surface, and the second read setting data is stored in the second page buffer circuit of the second memory surface (S200).

[0035] A dump operation is performed to store the recovery setting data corresponding to the written setting data in a buffer based on the first read setting data and the second read setting data (S300).

[0036] Setup data includes information used for initializing the non-volatile memory device; this setup data may be referred to as Information Data Read (IDR) data. The same setup data can be stored in multiple memory regions of the non-volatile memory device. Hereinafter, setup data to be stored in a memory region may be referred to as write setup data, and setup data provided by reading the stored write setup data may be referred to as read setup data. Although the same setup data is stored in the multiple memory regions, read setup data may be distorted and differ from write setup data due to deviations in programming operations, deviations in read operations, memory cell degradation, etc. Therefore, when read setup data from one memory region contains uncorrectable errors, read setup data can be loaded from another memory region.

[0037] The setup data replication scheme varies depending on the product. Generally, setup data may include plane copy data for correcting bit line defects and SSL copy data for correcting string select line (SSL) defects.

[0038] An initialization sequence or IDR sequence may include "sensing" to read setting data from memory cells into page buffer circuitry, "dumping" to verify the validity of data stored in the page buffer circuitry and store valid setting data in a buffer, and "follow-up processing" to set the operating conditions of the non-volatile memory device based on the valid setting data in the buffer. For example, "follow-up processing" may include setting the level of the operating voltage, performing a WOR scan to exclude failed columns from pass / fail operations, etc.

[0039] Product booting time is directly affected by initialization time, and reducing initialization time is important. To reduce initialization time or IDR time, it is beneficial to execute the dump sequence efficiently, as the dump sequence accounts for a large portion of the initialization time.

[0040] According to the example embodiment, multiple write setting data are read in parallel from multiple memory regions, and multiple read setting data are used to perform a dump operation with a complementary scheme, such that if the verification operation of one read setting data fails, another read setting data can be used.

[0041] In the example product using 16 kilobytes (KB) per page, the setup data is approximately 2300 bytes. If any bit within these 2300 bytes is determined to be invalid, the entire setup data will be invalid, and the sensing and dumping operations must be repeated based on setup data stored in other memory areas. In related solutions, the dumping operation proceeds to the last bit of the setup data without storing invalid bits. If the setup data stored in the buffer is faulty, the buffer is reset, and the same operation is repeated based on setup data stored in other memory areas.

[0042] The amount of setup data increases with the integration density and memory capacity of the non-volatile memory device, and therefore the initialization time increases proportionally with the amount of setup data. This is especially true when the product uses a face-independent read-only (PIR) or face-independent core (PIC) scheme, where the amount of setup data increases further due to setup per face.

[0043] The non-volatile memory device and the method for controlling the initialization of the non-volatile memory device according to various example embodiments can reduce the dump sequence time and the overall initialization time for initializing the non-volatile memory device by reading multiple write setting data in parallel and verifying the validity of multiple read setting data using a complementary scheme. Furthermore, the non-volatile memory device and the method for controlling the initialization of the non-volatile memory device according to various example embodiments can reduce the possibility of dump failure and improve the performance of the non-volatile memory device by reading multiple write setting data in parallel and verifying the validity of multiple read setting data using a complementary scheme.

[0044] Figure 2 This is a block diagram illustrating a memory system according to an example embodiment.

[0045] Reference Figure 2 The memory system 10 may include a memory controller 20 and a non-volatile memory device (NVM) 30. The non-volatile memory device 30 may include multiple memory planes MPL1 to MPLN, and Figure 2 The memory system 10 can be a memory card, a universal serial bus (USB) memory, a solid-state drive (SSD), etc.

[0046] The non-volatile memory device 30 can perform read, erase, program, or write operations under the control of the memory controller 20. The non-volatile memory device 30 can receive commands CMD, address ADDR, and data DATA from the memory controller 20 via input / output lines for performing read, erase, program, or write operations. Furthermore, the non-volatile memory device 30 can receive control signals CTRL from the memory controller 20 via control lines and power supply PWR from the memory controller 20 via power supply lines.

[0047] The non-volatile memory device 30 may include a dump circuit DDC 100, a buffer BUFF 200, and a ROM 300. The dump circuit 100 may be configured to perform as described in the reference. Figure 1 The method described is for initializing a non-volatile memory device. Buffer memory 200 can be implemented using volatile memory to store data used in various operations of the non-volatile memory device 30. ROM 300 can store data that will be retained after the non-volatile memory device 30 is powered off.

[0048] Figure 3 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0049] Reference Figure 3 The non-volatile memory device 30 may include multiple memory surfaces 401, 402, and 403, each memory surface including its own memory cell array and page buffer circuit PBC. The non-volatile memory device 30 may also include a row decoder 430, multiple column gate Y-GATEs 411, 412, and 413, a data input-output circuit IOC, a control circuit 450, and a voltage generator 460.

[0050] Each memory cell array can be connected to the row decoder 430 via multiple string select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). Furthermore, each memory cell array can be connected to a corresponding page buffer circuit (PBC) via multiple bit lines (not shown). Each memory cell array may include multiple memory cells (described in more detail later) connected to the multiple word lines (WL) and the multiple bit lines. In some example embodiments, the memory cell array may be a three-dimensional memory cell array that can be formed on a substrate in a three-dimensional (or vertical) structure. In some example embodiments, each memory cell array may include multiple vertically oriented NAND strings or multiple cell strings, such that at least one memory cell is located above another memory cell.

[0051] Control circuit 450 can be from Figure 2The memory controller 20 receives a command (signal) CMD and an address (signal) ADD, and controls erase, program, write, and / or read operations of the non-volatile memory device 30 based on the command signal CMD and the address signal ADD. Erasing operations may include executing a series of erase cycles, and programming operations may include executing a series of programming cycles. Each programming cycle may include a programming period and a programming verification period. Each erase cycle may include an erase period and an erase verification period. Read operations may include normal read operations and data recovery read operations.

[0052] Based on the command signal CMD, the control circuit 450 can generate the control signal VCTL for controlling the voltage generator 460, and the page buffer control signal PCTL for controlling the page buffer circuit PBC. Based on the address signal ADD, the control circuit 450 can generate the row address R_ADDR and the column address C_ADDR. The control circuit 450 can provide the row address R_ADDR to the row decoder 430, and the column address C_ADDR to column gates 411, 412, and 413. The row decoder 430 can be connected to the memory cell array through the multiple serial select lines SSL, the multiple word lines WL, and the multiple ground select lines GSL.

[0053] During programming or reading operations, based on the row address R_ADDR, the row decoder 430 can determine that one of the word lines WL is the selected word line and determine that the remaining word lines WL besides the selected word line are the unselected word lines.

[0054] Furthermore, during programming or reading operations, based on the row address R_ADDR, the row decoder 430 can determine that one of the string select lines SSL is the selected string select line and determine that the remaining string select lines SSL are not selected string select lines.

[0055] Voltage generator 460 can generate the word line voltage VWL that may be required for the operation of the memory cell array of non-volatile memory device 30 based on the control signal VCTL. Voltage generator 460 can receive power from memory controller 20. Word line voltage VWL can be applied to word line WL by row decoder 430.

[0056] For example, during programming operations, voltage generator 460 can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Furthermore, during programming verification operations, voltage generator 460 can apply a programming verification voltage to the selected word line and a verification pass voltage to the unselected word line.

[0057] Furthermore, during normal read operations, voltage generator 460 can apply a read voltage to the selected word line and can also apply a read pass voltage to unselected word lines. During data recovery read operations, voltage generator 460 can apply a read voltage to the word line adjacent to the selected word line and can also apply a recovery read voltage to the selected word line.

[0058] Each page buffer circuit (PBC) can be connected to the memory cell array via a bit line. A page buffer circuit (PBC) may include multiple page buffers. In some example embodiments, each page buffer may be connected to only one bit line. In other example embodiments, each page buffer may be connected to two or more bit lines. The page buffer circuit (PBC) may temporarily store data to be programmed into a selected page or data read from a selected page of the memory cell array 100.

[0059] Each data input / output circuit (IOC) can be connected to its corresponding page buffer circuit (PBC) via a data line. During programming operations, the IOC receives programming data DATA from the memory controller 20 and provides the programming data DATA to the page buffer circuit PBC based on the column address C_ADDR received from the control circuit 450. During read operations, the IOC provides the read data DATA, which has been read from the memory cell array and stored in the page buffer circuit PBC, to the memory controller 20 based on the column address C_ADDR received from the control circuit 450.

[0060] The control circuit 450 may include a dump circuit DDC 100, a buffer BUFF 200, and a ROM 300. The dump circuit 100 may be configured to perform as described in the reference. Figure 1 The method described is for initializing a non-volatile memory device. Buffer memory 200 can be implemented using volatile memory to store data required by the non-volatile memory device 30. ROM 300 can store data that will be retained after the non-volatile memory device 30 is powered off. Although Figure 3 It is shown that the dump circuit 100, buffer 200 and ROM 300 are included in the control circuit 450, but at least one of the dump circuit 100, buffer 200 or ROM 300 can be implemented as a different component from the control circuit 450.

[0061] Figure 4 It is shown Figure 3 A block diagram illustrating an example of a memory cell array included in a non-volatile memory device. Figure 5 It is shown Figure 4 The circuit diagram of the equivalent circuit of the memory block in the image.

[0062] like Figure 4 As shown, the memory cell array 401 may include multiple memory blocks BLK1 to BLKz. Memory blocks BLK1 to BLKz are composed of... Figure 3 The row decoder 430 selects from memory blocks BLK1 to BLKz that correspond to a specific memory block BLK with a block address.

[0063] Figure 5 The memory block BLKi can be formed on the substrate in a three-dimensional (or vertical) structure. For example, multiple NAND strings or cell strings included in the memory block BLKi can be formed in a first direction D1, which is perpendicular to the second direction D2 and the third direction D3, i.e., perpendicular to the upper surface of the substrate.

[0064] Reference Figure 5 The memory block BLKi includes NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the NAND strings NS11 to NS33 includes a string select transistor SST, multiple memory cells MC1 to MC8, and a ground select transistor GST. Figure 5 In the example, each of the NAND strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, the example embodiment is not limited thereto. In some example embodiments, each of the NAND strings NS11 to NS33 may include any number of memory cells.

[0065] Each string select transistor (SST) can be connected to a corresponding string select line (one of SSL1 to SSL3). The plurality of memory cells MC1 to MC8 can be connected to the plurality of gate lines GTL1 to GTL8 respectively. Gate lines GTL1 to GTL8 can be word lines, and some of gate lines GTL1 to GTL8 can be dummy word lines. Each ground select transistor (GST) can be connected to a corresponding ground select line (one of GSL1 to GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1, BL2, and BL3), and each ground select transistor (GST) can be connected to the common source line CSL.

[0066] Word lines with the same height (i.e., level) (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated. Figure 5 In the example, the memory block BLKi is shown as being connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 to BL3. However, the example embodiment is not limited to this.

[0067] Figure 6 This is a diagram illustrating a non-volatile memory device according to an example embodiment. For ease of illustration and description, Figure 6 Only components related to the method of controlling the initialization of non-volatile memory devices are shown. For brevity, components related to [other components] can be omitted in the following text. Figure 3 , Figure 4 and Figure 5 Repeated description.

[0068] Reference Figure 6 The non-volatile memory device 11 may include a first memory plane MPL1, a second memory plane MPL2, a dump circuit 101, and a buffer 200.

[0069] It is possible Figure 3 Under the control of the control circuit 450, data is stored in the first memory plane MPL1 and the second memory plane MPL2, or data is read from the first memory plane MPL1 and the second memory plane MPL2. Each of the first memory plane MPL1 and the second memory plane MPL2 can be divided into an area for storing write setup data (WSD) and an area for storing user data. The write setup data (WSD) may include information for initialization, such as DC information, option information, repair information, bad block information, etc.

[0070] The first memory plane MPL1 may include a first memory cell array MCA1, a first row decoder RDEC1, and a first page buffer circuit PBC1. During a write operation, the first row decoder RDEC1 selects a word line of the first memory cell array MCA1. The first page buffer circuit PBC1 transmits data to the first memory cell array MCA1 via bit lines to store the data in the memory cells connected to the selected word line. During a read operation, the first row decoder RDEC1 selects a word line of the first memory cell array MCA1, and the first page buffer circuit PBC1 senses and stores the data stored in the memory cells connected to the selected word line.

[0071] The second memory plane MPL2 may include a second memory cell array MCA2, a second row decoder RDEC2, and a second page buffer circuit PBC2. During a write operation, the second row decoder RDEC2 selects a word line of the second memory cell array MCA2. The second page buffer circuit PBC2 transmits data to the second memory cell array MCA2 via bit lines to store the data in the memory cells connected to the selected word line. During a read operation, the second row decoder RDEC2 selects a word line of the second memory cell array MCA2, and the second page buffer circuit PBC2 senses and stores the data stored in the memory cells connected to the selected word line.

[0072] In this way, write setup data WSD can be stored in the first memory cell MC1 of the first memory plane MPL1 and the second memory cell MC2 of the second memory plane MPL2. Then, for example, during the startup operation of the non-volatile memory device 11, a first sensing operation can be performed to sense the write setup data WSD stored in the first memory cell MC1 and store the first read setup data RSD1 in the first page buffer circuit PBC1, and a second sensing operation can be performed to sense the write setup data WSD stored in the second memory cell MC2 and store the second read setup data RSD2 in the second page buffer circuit PBC2.

[0073] When power is supplied to the system including the non-volatile memory device 11, the initialization operation of the non-volatile memory device 11 can be performed. Figure 3 The control circuit 450 can receive a power-on signal and, in response to the power-on signal, perform a first sensing operation and a second sensing operation to store the first read setting data RSD1 and the second read setting data RSD2 in the first page buffer circuit PBC1 and the second page buffer circuit PBC2, respectively.

[0074] although Figure 6 For ease of illustration and description, two memory surfaces are shown, but the non-volatile memory device 11 may include three or more memory surfaces or clusters (mats).

[0075] The dump circuit 101 may include a first verification circuit VRFC1, a second verification circuit VRFC2, and dump control logic DDCL.

[0076] The first verification circuit VRFC1 is connected to the first page buffer circuit PBC1. The first verification circuit VRF1 verifies the validity of the first read setting data RSD1 to provide a first verification signal SVRF1 and first valid data DVAL1. The second verification circuit VRFC2 is connected to the second page buffer circuit PBC2. The second verification circuit VRFC2 verifies the validity of the second read setting data RSD2 to provide a second verification signal SVRF2 and second valid data DVAL2.

[0077] The Dump Control Logic (DDCL) can determine the valid data DVAL corresponding to one of the first read setting data RSD1 and the second read setting data RSD2 based on the validity verification results of the first read setting data RSD1 and the second read setting data RSD2. The validity verification results of the first read setting data RSD1 and the second read setting data RSD2 can be represented by the logic levels of the first verification signal SVRF1 and the second verification signal SVRF2, respectively. The valid data DVAL can correspond to one of the first valid data DVAL1 and the second valid data DVAL2. Furthermore, the Dump Control Logic (DDCL) can provide a write pointer or write address indicating the location of the buffer 200 corresponding to the valid data DVAL currently provided to the buffer 200.

[0078] The dump control logic DDCL can generate a first enable signal EN1 and a second enable signal EN2 based on the first verification signal SVRF1 and the second verification signal SVRF2. The first verification circuit VRFC1 can be enabled in response to the activation of the first enable signal EN1, and the second verification circuit VRFC2 can be enabled in response to the activation of the second enable signal EN2.

[0079] Figure 7 , Figure 8 and Figure 9 This is a diagram illustrating an example embodiment of a verification operation suitable for a method of controlling the initialization of a non-volatile memory device according to an example embodiment. For ease of illustration and description, Figure 7 , Figure 8 and Figure 9 Only one data unit of the raw setup data (OSD) and the write setup data (WSD) is shown. It will be understood that the raw setup data (OSD) and the write setup data (WSD) may include multiple data units.

[0080] In the initialization sequence of a non-volatile memory device, setup data stored in memory cells is read, verified, and stored in a buffer. As mentioned above, column repair information is reflected in the WOR scan phase, and column defects must be overcome using an alternative approach during the dump operation. To overcome column defects, write setup data (WSD) can be obtained by copying each bit of the original setup data OSD into multiple copy bits, and the write setup data WSD with copy bits can be stored in the non-volatile memory device. In this case, Figure 6 Each of the first verification circuit VRFC1 and the second verification circuit VRFC2 may include a majority voter circuit configured to determine whether the number of bits with equal values ​​among the plurality of replica bits corresponding to each bit of the original setup data OSD is equal to or greater than a reference number.

[0081] For example, such as Figure 7 As shown, each bit of the original setting data OSD (e.g., Figure 7 The example shown (8 bits of the OSD) can be copied and expanded into eight replica bits to form the write setup data WSD. The WSD is written and then... Figure 8 The RSD shown is read. The eight bits corresponding to each bit of the read setting data RSD[i] can be compared with a reference number. For example, if the reference number is set to six, each bit of RSD[i] can be determined as valid (PASS) when six or more of the eight replica bits overlap, and each bit of RSD[i] can be determined as invalid (FAIL) when five or fewer of the eight replica bits overlap. For example, suppose... Figure 7 The copy bits of FFh shown are written as WSD and then as Figure 8 The RSD[i] shown is read. The top data shows that RSD[i] is valid (PASS) because only one bit is zero (0). The bottom data shows that RSD[i] is invalid (FAIL) because all three bits are zero (0). In other words, in the top data, it can be determined that OSD[i] is 1, while in the bottom data, it cannot be determined that OSD[i] is 1.

[0082] As another example of a verification operation. Figure 9 An example embodiment using parity bits C1~Ck of a cyclic redundancy check (CRC) scheme is shown. The CRC scheme is known, and its detailed description is omitted for brevity. In this case, each of the first verification circuit VRFC1 and the second verification circuit VRFC2 can use the CRC parity bits to verify the validity of the first read setting data RSD1 and the second read setting data RSD2.

[0083] Figure 10 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment.

[0084] Reference Figure 10 The first read setting data RSD1 may include multiple first data units A1~A10 divided by a unit number of bits, and the second read setting data RSD2 may include multiple second data units B1~B10 divided by a unit number of bits. Figure 10 For ease of illustration and description, each of the first read setting data RSD1 and the second read setting data RSD2 is shown to include ten data units, but the example embodiment is not limited thereto. Invalid data units with uncorrectable errors can be represented by being drawn with a shaded line. Figure 10An example is shown where the first data unit A3 of the first read setting data RSD1 is an invalid data unit.

[0085] Figures 11 to 18 It is shown that... Figure 10 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data.

[0086] Reference Figure 11 The first sensing operation SS1 and the second sensing operation SS2 can be executed simultaneously during the sensing time tSS1 corresponding to the time interval T11~T12. Accordingly, the first sensing operation SS1 and the second sensing operation SS2 can start simultaneously, so that the first sensing operation SS1 and the second sensing operation SS2 are completed simultaneously.

[0087] After sensing operations SS1 and SS2 are completed, during the dump time tDD1 corresponding to the time interval T12~T13, as shown in the reference... Figure 6 The first enable signal EN1 and the second enable signal EN2 described herein can be activated simultaneously. Both the first verification circuit VRFC1 and the second verification circuit VRFC2 can be enabled simultaneously in response to the simultaneous activation of the first enable signal EN1 and the second enable signal EN2 to verify the validity of the first read setting data RSD1 and the second read setting data RSD2, respectively.

[0088] The dump control logic DDCL can sequentially store the first valid data units VA1, VA2, and VA4~VA10 in buffer 200 based on the first data units A1, A2, and A4~A10 that are determined to be valid data units. Furthermore, the dump control logic DDCL can sequentially store the second valid data unit VB3 based on the second data unit B3 corresponding to the first data unit A3 that is determined to be invalid data unit (in this case, only one second valid data unit). Note that in... Figure 11 In the example shown, there is only one invalid data unit. However, this is just an example, and in some example embodiments, there may be more than one invalid data unit.

[0089] Accordingly, the first verification circuit VRFC1 and the second verification circuit VRFC2 can be activated simultaneously, so that dump operations on the first valid data units VA1, VA2 and VA4~VA10 and the second valid data unit VB3 can be performed alternately.

[0090] exist Figure 11In this case, the time used for dumping the sequence corresponds to tSS1 + tDD1. The prior art performs a first sensing operation and a dump operation on the first read setting data RSD1. If the result is determined to be a failure, a second sensing operation and a dump operation on the second read setting data RSD2 are repeated, and the time used for dumping the sequence corresponds to 2*(tSS1 + tDD1). Accordingly, according to the example embodiment, the time used for dumping the sequence can be reduced.

[0091] Figure 12 and Figure 13 The timing of the first sensing operation SS1 and the second sensing operation SS2 is shown, in addition to the timing of the other two sensing operations. Figure 11 Similar example embodiments are provided, and repeated descriptions are omitted for brevity.

[0092] Reference Figure 12 The first sensing operation SS1 and the second sensing operation SS2 can be executed sequentially during the sensing time tSS2 corresponding to the time intervals T21~T22 and T22~T23. During the dump time tDD2 corresponding to the time intervals T23~T24, the first enable signal EN1 and the second enable signal EN2 are activated simultaneously, so that the first verification circuit VRFC1 and the second verification circuit VRFC2 can simultaneously verify the validity of the first read setting data RSD1 and the second read setting data RSD2.

[0093] Reference Figure 13 The first sensing operation SS1 and the second sensing operation SS2 can be executed sequentially during the sensing time tSS3 corresponding to the time intervals T31 to T34. That is, the first sensing operation SS1 can be executed during the time intervals T31 to T33, and the second sensing operation SS2 can be executed during the time intervals T32 to T34, where T31 to T33 partially overlap with T32 to T34, and T31 to T34 corresponds to the sensing time tSS3. During the dump time tDD3 corresponding to the time intervals T34 to T35, the first enable signal EN1 and the second enable signal EN2 are activated simultaneously, so that both the first verification circuit VRFC1 and the second verification circuit VRFC2 can simultaneously verify the validity of the first read setting data RSD1 and the second read setting data RSD2.

[0094] like Figure 12 and Figure 13 As shown, the first sensing operation SS1 can begin before the second sensing operation SS2, so that the completion time of the first sensing operation is earlier than the completion time of the second sensing operation. Figure 12 and Figure 13 In both cases, the dump operation can begin at the completion time of the second sensing operation SS2.

[0095] Accordingly, the overlap time intervals T32-T33 between the parallel execution of the first sensing operation SS1 and the second sensing operation SS2 can be adjusted by controlling the start time T32 of the second sensing operation SS2. As the overlap time intervals T32-T33 decrease, the time used for dumping the sequence (i.e., tSSx+tDDx) increases. However, because the peak current in the non-volatile memory device increases during the overlap time intervals T32-T33, power consumption can be reduced as the overlap time intervals T32-T33 decrease.

[0096] Reference Figure 14 The first sensing operation SS1 and the second sensing operation SS2 can be executed simultaneously during the sensing time tSS4 corresponding to the time interval T41~T42. Accordingly, the first sensing operation SS1 and the second sensing operation SS2 can start simultaneously, so that the first sensing operation SS1 and the second sensing operation SS2 are completed simultaneously.

[0097] After sensing operations SS1 and SS2 are completed, during the dump time tDD4 corresponding to the time intervals T42~T45, it is possible to selectively or alternatively activate as described in the reference. Figure 6 The first enable signal EN1 and the second enable signal EN2 are described. In other words, only the first enable signal EN1 can be activated during time intervals T42~T43 and T44~T45, and only the second enable signal EN2 can be activated during time intervals T43~T44.

[0098] In response to the selective activation of the first enable signal EN1 and the second enable signal EN2, the first verification circuit VRFC1 and the second verification circuit VRFC2 may be enabled alternatively to verify the validity of the first read setting data RSD1 and the second read setting data RSD2, respectively.

[0099] As a result, Figure 14 As shown, when the first data unit A3 of the first read setting data RSD1 is determined to be an invalid data unit, the dump operation based on the first read setting data RSD1 can be performed as the main operation, and the dump operation based on the second read setting data RSD2 can be performed as a supplementary operation.

[0100] Reference Figure 15 The first sensing operation SS1 and the second sensing operation SS2 can be executed simultaneously during the sensing time tSS5 corresponding to the time interval T51~T52. Accordingly, the first sensing operation SS1 and the second sensing operation SS2 can start simultaneously, so that the first sensing operation SS1 and the second sensing operation SS2 are completed simultaneously.

[0101] After sensing operations SS1 and SS2 are completed, during the dump time tDD5 corresponding to the time intervals T52~T54, it is possible to selectively or alternatively activate as described in the reference. Figure 6 The first enable signal EN1 and the second enable signal EN2 are described. In other words, only the first enable signal EN1 can be activated during the time interval T52~T53, and only the second enable signal EN2 can be activated during the time interval T53~T54.

[0102] In response to the selective activation of the first enable signal EN1 and the second enable signal EN2, the first verification circuit VRFC1 and the second verification circuit VRFC2 may be enabled alternatively to verify the validity of the first read setting data RSD1 and the second read setting data RSD2, respectively.

[0103] As a result, Figure 15 As shown, when the first data unit A3 of the first read setting data RSD1 is determined to be an invalid data unit, the dump operation based on the first read setting data RSD1 can be performed as the main operation, and the dump operation based on the second read setting data RSD2 can be performed as a supplementary operation.

[0104] Reference Figure 16 The first sensing operation SS1 and the second sensing operation SS2 can be executed simultaneously during the sensing time tSS6 corresponding to the time interval T61~T62. Accordingly, the first sensing operation SS1 and the second sensing operation SS2 can start simultaneously, so that the first sensing operation SS1 and the second sensing operation SS2 are completed simultaneously.

[0105] After sensing operations SS1 and SS2 are completed, during the dump time tDD6 corresponding to the time intervals T62~T64, it is possible to selectively or alternatively activate as described in the reference. Figure 6 The first enable signal EN1 and the second enable signal EN2 are described. In other words, only the first enable signal EN1 can be activated during the time interval T62~T63, and only the second enable signal EN2 can be activated during the time interval T63~T64.

[0106] In response to the selective activation of the first enable signal EN1 and the second enable signal EN2, the first verification circuit VRFC1 and the second verification circuit VRFC2 may be enabled alternatively to verify the validity of the first read setting data RSD1 and the second read setting data RSD2, respectively.

[0107] The Dump Control Logic (DDCL) can sequentially store first valid data units VA1 and VA2 in buffer 200 based on first data units A1 and A2 before first data unit A3 among the plurality of first data units A1 to A10 is determined to be an invalid data unit. Furthermore, the Dump Control Logic (DDCL) can sequentially store second valid data units VB3 to VB10 in buffer 200 based on second data units B3 to B10, starting from the second data unit B3 corresponding to the first data unit A3 that has been determined to be an invalid data unit.

[0108] Accordingly, the first verification circuit VRFC1 can be enabled to perform a dump operation for the first valid data units VA1~VA2, and the second verification circuit VRFC2 can be disabled before the first data unit A3 among the plurality of first data units A1~A10 is determined to be an invalid data unit. Furthermore, after the first data unit A3 is determined to be an invalid data unit, the first verification circuit VRFC1 can be disabled, and the second verification circuit VRFC2 can be enabled to perform a dump operation for the second valid data units VB3~VB10.

[0109] Reference Figure 17 The first sensing operation SS1 can be performed during the sensing time tSS7 corresponding to the time interval T71~T72, and the dumping operation based on the first read setting data RSD1 can begin at the completion time point T72 of the first sensing operation SS1. Furthermore, the second sensing operation SS2 can begin at the completion time point T72 of the first sensing operation SS1.

[0110] If the second sensing operation SS2 is not completed by the time point T73 when the first data unit A3 among the plurality of first data units A1~A10 is determined to be an invalid data unit, both the first enable signal EN1 and the second enable signal EN can be disabled until the completion time point T74 of the second sensing operation SS2. In other words, both the first verification circuit VRFC1 and the second verification circuit VRFC2 can be disabled during the standby time tWT corresponding to the time interval T73~T74 until the second sensing operation SS2 is completed.

[0111] During the first dump time tDD71 corresponding to the time intervals T72~T73 and the second dump time tDD72 corresponding to the time intervals T74~T76, the following can be selectively activated: Figure 6 The first enable signal EN1 and the second enable signal EN2 are described. In other words, only the first enable signal EN1 can be activated during time intervals T72~T73 and T75, and only the second enable signal EN2 can be activated during time intervals T74~T75.

[0112] In response to the selective activation of the first enable signal EN1 and the second enable signal EN2, the first verification circuit VRFC1 and the second verification circuit VRFC2 may be enabled alternatively to verify the validity of the first read setting data RSD1 and the second read setting data RSD2, respectively.

[0113] As a result, Figure 17 As shown, after the second sensing operation SS2 is completed, the dump operation based on the first read setting data RSD1 can be performed as the main operation, and the dump operation based on the second read setting data RSD2 can be performed as a supplementary operation.

[0114] Reference Figure 18 The first sensing operation SS1 can be performed during the sensing time tSS8 corresponding to the time interval T81~T82, and the dumping operation based on the first read setting data RSD1 can start at the completion time point T82 of the first sensing operation SS1. In addition, the second sensing operation SS2 can start at the completion time point T82 of the first sensing operation SS1.

[0115] If the second sensing operation SS2 is not completed by the time point T83 when the first data unit A3 among the plurality of first data units A1~A10 is determined to be an invalid data unit, both the first enable signal EN1 and the second enable signal EN2 can be disabled until the completion time point T84 of the second sensing operation SS2. In other words, both the first verification circuit VRFC1 and the second verification circuit VRFC2 can be disabled during the standby time tWT corresponding to the time interval T83~T84 until the second sensing operation SS2 is completed.

[0116] During the first dump time tDD81 corresponding to the time interval T82~T83 and the second dump time tDD82 corresponding to the time interval T84~T85, the following can be selectively activated: Figure 6 The first enable signal EN1 and the second enable signal EN2 are described. In other words, only the first enable signal EN1 can be activated during the time interval T82~T83, and only the second enable signal EN2 can be activated during the time interval T84~T85.

[0117] In response to the selective activation of the first enable signal EN1 and the second enable signal EN2, the first verification circuit VRFC1 and the second verification circuit VRFC2 may be enabled alternatively to verify the validity of the first read setting data RSD1 and the second read setting data RSD2, respectively.

[0118] Before the first data unit A3 is determined to be an invalid data unit, the dump control logic DDCL can sequentially store the first valid data units VA1 and VA2 in the buffer 200 based on the first data units A1 and A2. Furthermore, the dump control logic DDCL can sequentially store the second valid data units VB3 to VB10 in the buffer 200, starting from the second data unit B3 corresponding to the first data unit A3 that was determined to be invalid, based on the second data units B3 to B10.

[0119] Figure 19 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment. For simplicity, [the following is omitted]. Figure 10 Repeated description.

[0120] exist Figure 19 In this context, invalid data units with uncorrectable errors can be represented by drawing a shaded line. Figure 19 An example is shown where two first data units A3 and A4 of the first read setting data RSD1 are invalid data units and one second data unit B6 of the second read setting data RSD2 is invalid data unit.

[0121] Figures 20 to 23 It is shown that... Figure 19 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data.

[0122] Figure 20 , Figure 21 and Figure 22 The methods, excluding invalid data units, are respectively with Figure 11 , Figure 14 and Figure 15 The methods are basically the same, so for the sake of brevity, repeated descriptions are omitted. The result is as follows: Figure 20 , Figure 21 and Figure 22 As shown, the first valid data units VA1, VA2 and VA5~VA10 and the second valid data units VB3 and VB4 can be stored in the buffer 200 as recovery setting data RESSD.

[0123] Reference Figure 23 The first sensing operation SS1 and the second sensing operation SS2 can be performed simultaneously during the sensing time tSS4 corresponding to the time intervals T41~T42. After the completion of sensing operations SS1 and SS2, during the dump time tDD4 corresponding to the time intervals T42~T45, as shown in the reference can be selectively or alternatively activated. Figure 6The first enable signal EN1 and the second enable signal EN2 are described. In response to the selective activation of the first enable signal EN1 and the second enable signal EN2, the first verification circuit VRFC1 and the second verification circuit VRFC2 may be enabled alternatively to verify the validity of the first read setting data RSD1 and the second read setting data RSD2, respectively.

[0124] The Dump Control Logic (DDCL) can sequentially store first valid data units VA1 and VA2 in buffer 200 based on first data units A1 and A2 before first data unit A3 among the plurality of first data units A1 to A10 is determined to be an invalid data unit. Subsequently, the Dump Control Logic (DDCL) can sequentially store second valid data units VB3 to VB5 in buffer 200 based on second data units B3 to B4 before second data unit B6 among the plurality of second data units B1 to B10 is determined to be an invalid data unit. Furthermore, the Dump Control Logic (DDCL) can sequentially store first valid data units VA6 to VA10 in buffer 200 starting from first data unit A6 corresponding to the second data unit B6 that was determined to be an invalid data unit, based on first data units A6 to A10.

[0125] As a result, Figure 23 As shown, the first valid data units VA1, VA2 and VA6~VA10 and the second valid data units VB3~VB5 can be stored in the buffer 200 as recovery setting data RESSD.

[0126] Figure 24 This is a diagram illustrating a non-volatile memory device according to an example embodiment.

[0127] Reference Figure 24 The non-volatile memory device 12 may include a first memory plane MPL1, a second memory plane MPL2, a dump circuit 102, and a buffer 200. Figure 24 Non-volatile memory devices and Figure 6 Similar to the non-volatile memory device 11, repeated descriptions are omitted for brevity. The following description focuses primarily on... Figure 6 The differences between the embodiments shown.

[0128] The write setup data (WSD) can be stored in the first memory cell MC1 of the first memory plane MPL1 and the second memory cell MC2 of the second memory plane MPL2. Furthermore, the write setup data (WSD) can be stored in the third memory cell MC3 of the first memory plane MPL1 and the fourth memory cell MC4 of the second memory plane MPL2.

[0129] A first sensing operation can be performed to sense the write setting data WSD stored in the first memory cell MC1 and store the first read setting data RSD1 in the first page buffer circuit PBC1. A second sensing operation can also be performed to sense the write setting data WSD stored in the second memory cell MC2 and store the second read setting data RSD2 in the second page buffer circuit PBC2. The aforementioned dump operation can be performed based on the first read setting data RSD1 and the second read setting data RSD2. If the dump operation based on the first read setting data RSD1 and the second read setting data RSD2 is determined to have failed, a third sensing operation can be performed to sense the write setting data WSD stored in the third memory cell MC3 and store the third read setting data RSD3 in the first page buffer circuit PBC1. A fourth sensing operation can also be performed to sense the write setting data WSD stored in the fourth memory cell MC4 and store the fourth read setting data RSD4 in the second page buffer circuit PBC2.

[0130] Accordingly, the first read setting data RSD1 and the second read setting data RSD2 in the first page buffer circuit PBC1 and the second page buffer circuit PBC2 can be replaced with the third read setting data RSD3 and the fourth read setting data RSD4, and the above-mentioned dump operation can be performed based on the third read setting data RSD3 and the fourth read setting data RSD4.

[0131] Figure 25 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment. For simplicity, [the following is omitted]. Figure 10 Repeated description.

[0132] exist Figure 25 In this context, invalid data units with uncorrectable errors can be represented by drawing a shaded line. Figure 25 An example is shown in which two first data units A3 and A5 of the first read setting data RSD1 are invalid data units, one second data unit B5 of the second read setting data RSD2 is invalid data unit, two third data units C2 and C10 of the third read setting data RSD3 are invalid data units, and one fourth data unit D6 of the fourth read setting data RSD4 is invalid data unit.

[0133] Figure 26 and Figure 27 It is shown that... Figure 25 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data.

[0134] Reference Figure 26The first sensing operation SS1 and the second sensing operation SS2 can be executed simultaneously during the first sensing time tSS11 corresponding to the time intervals T11~T12. During the first dump time tDD11 corresponding to the time intervals T12~T13, the first enable signal EN1 and the second enable signal EN2 can be activated simultaneously, and can be performed as described in reference... Figure 11 The dump operation based on the first read setting data RSD1 and the second read setting data RSD2 is performed. At time point T13, it is determined that both the first data unit A5 and the corresponding second data unit B5 of the first read setting data RSD1 are invalid data units, and the dump operation based on the first read setting data RSD1 and the second read setting data RSD2 is determined to have failed.

[0135] The third sensing operation SS3 and the fourth sensing operation SS4 can be performed simultaneously during the second sensing time tSS12 corresponding to the time intervals T13~T14. During the second dump time tDD12 corresponding to the time intervals T14~T15, the first enable signal EN1 and the second enable signal EN2 can be activated simultaneously, and can be performed as described in reference... Figure 11 The operation is performed based on the third read setting data RSD3 and the fourth read setting data RSD4.

[0136] In this case, the first valid data units VA1, VA2 and VA4 and the second valid data unit VB3 have been stored in the buffer 200, and the dump operation based on the third read setting data RSD3 and the fourth read setting data RSD4 can start from the fifth data unit.

[0137] As a result, Figure 26 As shown, the first valid data units VA1, VA2 and VA4, the second valid data unit VB3, the third valid data units VC5~VC9 and the fourth valid data unit VD10 can be stored in the buffer 200 as recovery setting data RESSD.

[0138] Reference Figure 27 During the first sensing time tSS21 corresponding to the time intervals T21~T22, the first sensing operation SS1 and the second sensing operation SS2 can be executed simultaneously. During the first dump time tDD21 corresponding to the time intervals T22~T23, the first enable signal EN1 and the second enable signal EN2 can be activated simultaneously, and can be performed as described in reference... Figure 11The dump operation based on the first read setting data RSD1 and the second read setting data RSD2 is performed. At time point T23, it is determined that both the first data unit A5 and the corresponding second data unit B5 of the first read setting data RSD1 are invalid data units, and the dump operation based on the first read setting data RSD1 and the second read setting data RSD2 is determined to have failed.

[0139] The third sensing operation SS3 and the fourth sensing operation SS4 can be performed simultaneously during the second sensing time tSS22 corresponding to the time intervals T23~T24. During the second dump time tDD22 corresponding to the time intervals T24~T25, the first enable signal EN1 and the second enable signal EN2 can be activated simultaneously, and can be performed as described in reference... Figure 11 The operation is performed based on the third read setting data RSD3 and the fourth read setting data RSD4.

[0140] In this case, buffer 200 can be reset, and the dump operation based on the third read setting data RSD3 and the fourth read setting data RSD4 can restart from the first data unit.

[0141] As a result, Figure 27 As shown, the third valid data units VC1 and VC3~VC9 and the fourth valid data units VD2 and VD10 can be stored in the buffer 200 as recovery setting data RESSD.

[0142] Figure 28 This is a diagram illustrating a non-volatile memory device according to an example embodiment.

[0143] Reference Figure 28 The non-volatile memory device 13 may include a first memory plane MPL1, a second memory plane MPL2, a third memory plane MPL3, a dump circuit 102, and a buffer 200. Figure 28 Non-volatile memory device 13 and Figure 6 Similar to the non-volatile memory device 11, repeated descriptions are omitted for brevity. The following description focuses primarily on... Figure 6 The differences between the embodiments shown.

[0144] The write setup data (WSD) can be stored in the first memory cell MC1 of the first memory plane MPL1, the second memory cell MC2 of the second memory plane MPL2, and the third memory cell MC3 of the third memory plane MPL3. Then, a first sensing operation can be performed to sense the write setup data WSD stored in the first memory cell MC1 and store the first read setup data RSD1 in the first page buffer circuit PBC1. A second sensing operation can be performed to sense the write setup data WSD stored in the second memory cell MC2 and store the second read setup data RSD2 in the second page buffer circuit PBC2. A third sensing operation can be performed to sense the write setup data WSD stored in the third memory cell MC3 and store the third read setup data RSD3 in the third page buffer circuit PBC3. In some example embodiments, the third sensing operation can be performed if the dump operation based on the first read setup data RSD1 and the second read setup data RSD2 is determined to have failed.

[0145] The dump circuit 103 may include a first verification circuit VRFC1, a second verification circuit VRFC2, a third verification circuit VRFC3, and dump control logic DDCL.

[0146] The first verification circuit VRFC1 is connected to the first page buffer circuit PBC1. The first verification circuit VRF1 verifies the validity of the first read setting data RSD1 to provide a first verification signal SVRF1 and first valid data DVAL1. The second verification circuit VRFC2 is connected to the second page buffer circuit PBC2. The second verification circuit VRFC2 verifies the validity of the second read setting data RSD2 to provide a second verification signal SVRF2 and second valid data DVAL2. The third verification circuit VRFC3 is connected to the third page buffer circuit PBC3. The third verification circuit VRFC3 verifies the validity of the third read setting data RSD3 to provide a third verification signal SVRF3 and third valid data DVAL3.

[0147] The Dump Control Logic (DDCL) can determine the valid data DVAL corresponding to one of the first read setting data RSD1, the second read setting data RSD2, and the third read setting data RSD31 based on the validity verification results of the first read setting data RSD1, the second read setting data RSD2, and the third read setting data RSD31, and store the valid data DVAL in the buffer 200.

[0148] The dump control logic DDCL can generate a first enable signal EN1, a second enable signal EN2, and a third enable signal EN3 based on the first verification signal SVRF1, the second verification signal SVRF2, and the third verification signal SVRF3. The first verification circuit VRFC1 can be enabled in response to the activation of the first enable signal EN1, the second verification circuit VRFC2 can be enabled in response to the activation of the second enable signal EN2, and the third verification circuit VRFC3 can be enabled in response to the activation of the third enable signal EN3.

[0149] Figure 29 This is a diagram illustrating an example of read setting data sensed from a non-volatile memory device according to an example embodiment. For simplicity, [the following is omitted]. Figure 10 Repeated description.

[0150] exist Figure 29 In this context, invalid data units with uncorrectable errors can be represented by drawing a shaded line. Figure 29 An example is shown in which two first data units A3 and A5 of the first read setting data RSD1 are invalid data units, one second data unit B5 of the second read setting data RSD2 is invalid data unit, and two third data units C2 and C10 of the third read setting data RSD3 are invalid data units.

[0151] Figure 30 It is shown that... Figure 29 A diagram illustrating an example embodiment of a method for initializing a non-volatile memory device by reading setting data.

[0152] Reference Figure 30 The first sensing operation SS1 and the second sensing operation SS2 can be executed simultaneously during the first sensing time tSS11 corresponding to the time intervals T11~T12. During the first dump time tDD11 corresponding to the time intervals T12~T13, the first enable signal EN1 and the second enable signal EN2 can be activated simultaneously, and can be performed as described in reference... Figure 11 The dump operation based on the first read setting data RSD1 and the second read setting data RSD2 is performed. At time point T13, it is determined that both the first data unit A5 and the corresponding second data unit B5 of the first read setting data RSD1 are invalid data units, and the dump operation based on the first read setting data RSD1 and the second read setting data RSD2 is determined to have failed.

[0153] The third sensing operation SS3 can be performed simultaneously during the second sensing time tSS12 corresponding to the time intervals T13~T14. During the second dump time tDD12 corresponding to the time intervals T14~T15, the second enable signal EN2 and the third enable signal EN3 can be activated simultaneously, and can be performed as described in reference... Figure 11 The operation is performed based on the second read setting data RSD2 and the third read setting data RSD3.

[0154] In this case, the first valid data units VA1, VA2 and VA4 and the second valid data unit VB3 have been stored in the buffer 200, and the dump operation based on the third read setting data RSD3 and the fourth read setting data RSD4 can start from the fifth data unit.

[0155] As a result, Figure 30 As shown, the first valid data units VA1, VA2 and VA4, the second valid data units VB3 and VB10 and the third valid data units VC5~VC9 can be stored in the buffer 200 as recovery setting data RESSD.

[0156] Figure 31 This is a flowchart illustrating a method for controlling the initialization of a non-volatile memory device according to an example embodiment.

[0157] Reference Figure 31 A first sensing operation is performed to sense write setting data stored in a first memory cell on the first memory surface and store the first read setting data in the first page buffer circuit of the first memory surface (S100). A second sensing operation is performed to sense write setting data stored in a second memory cell on the second memory surface and store the second read setting data in the second page buffer circuit of the second memory surface (S200).

[0158] The validity of each of a plurality of first data units is verified using a first verification circuit connected to the first page buffer circuit, wherein the plurality of first data units correspond to first read setting data divided by unit bit number (S310). The validity of each of a plurality of second data units is verified using a second verification circuit connected to the second page buffer circuit, wherein the plurality of second data units correspond to second read setting data divided by unit bit number (S320).

[0159] Based on the validity verification results of each of the plurality of first data units and the validity verification results of each of the plurality of second data units, the first verification circuit and the second verification circuit are selectively enabled (S330).

[0160] Based on the validity verification results of each of the plurality of first data units and the validity verification results of each of the plurality of second data units, the valid data unit corresponding to one of the first data unit and the second data unit is stored in the buffer (S340).

[0161] Figure 32 This is a block diagram illustrating a solid-state drive (SSD) according to an example embodiment.

[0162] Reference Figure 32 The SSD 1000 includes multiple non-volatile memory devices (NVMs) 1100 and an SSD controller 1200.

[0163] The non-volatile memory device 1100 can be configured to receive a high voltage VPP. The non-volatile memory device 1100 may correspond to the non-volatile memory device described above according to the example embodiment. Therefore, the non-volatile memory device 1100 may include the dump circuit described above, and the dump circuit may include multiple verification circuits to implement a method for controlling the initialization of the non-volatile memory device.

[0164] SSD controller 1200 is connected to non-volatile memory device 1100 via multiple channels CH1 to CHi. SSD controller 1200 includes one or more processors 1210, buffer memory 1220, error correction code (ECC) circuitry 1230, host interface 1250, and non-volatile memory interface 1260. Buffer memory 1220 stores data used to drive SSD controller 1200. Buffer memory 1220 includes multiple memory lines, each storing data or commands. ECC circuitry 1230 calculates error correction code values ​​for the data to be programmed during write operations and uses these values ​​to correct errors in the read data during read operations. In data recovery operations, ECC circuitry 1230 corrects errors in the data recovered from non-volatile memory device 1100.

[0165] The inventive concepts based on the various exemplary embodiments described above can be applied to any electronic device and system. For example, the inventive concepts can be applied to systems such as: memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash storage devices (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0166] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting thereto. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the inventive concept.

Claims

1. A method for controlling the initialization of a non-volatile memory device, comprising: Perform a first sensing operation to sense write setting data stored in a first memory cell of a first memory surface of the non-volatile memory device, and store the first read setting data in a first page buffer circuit of the first memory surface; Perform a second sensing operation to sense write setting data stored in a second memory cell on the second memory surface of the non-volatile memory device, and store the second read setting data in the second page buffer circuit on the second memory surface; as well as A dump operation is performed to store the recovery setting data corresponding to the written setting data in the buffer of the non-volatile memory device, based on the validity of the first read setting data and the validity of the second read setting data.

2. The method according to claim 1, wherein, Performing a dump operation includes: The validity of the first read setting data is verified using a first verification circuit connected to the first page buffer circuit. The validity of the second read setting data is verified using a second verification circuit connected to the second page buffer circuit; and Based on the validity verification results of the first read setting data and the second read setting data, the valid data corresponding to one of the first data unit and the second data unit is stored in the buffer.

3. The method according to claim 2, wherein, Verifying the validity of the first read setting data includes: Verify the validity of each of the plurality of first data units corresponding to the first read setup data divided by unit bit number, and Verifying the validity of the second read setting data includes: Verify the validity of each of the multiple second data units corresponding to the second read setting data divided by the number of bits.

4. The method according to claim 3, wherein, The stored valid data includes: Before one of the plurality of first data units is determined to be an invalid data unit, first valid data units are sequentially stored in the buffer based on the first data units; and Starting with the second data unit corresponding to the first data unit that was determined to be an invalid data unit, the second valid data units are sequentially stored in the buffer based on the second data unit.

5. The method according to claim 4, wherein, Before one of the plurality of first data units is determined to be an invalid data unit, a first verification circuit is enabled to verify the validity of the first data unit and a second verification circuit is disabled; and after one of the plurality of first data units is determined to be an invalid data unit, the first verification circuit is disabled and the second verification circuit is enabled to verify the validity of the second data unit.

6. The method according to claim 4, wherein, When the second sensing operation is not completed at the time point when one of the plurality of first data units is determined to be an invalid data unit, both the first verification circuit and the second verification circuit are disabled until the second sensing operation is completed.

7. The method according to claim 4, wherein, Storing valid data also includes: Before one of the plurality of second data units is determined to be an invalid data unit, second valid data units are sequentially stored in the buffer based on the second data units; and Starting with the first data unit corresponding to the second data unit that was determined to be an invalid data unit, the first valid data units are sequentially stored in the buffer based on the first data unit.

8. The method according to claim 3, wherein, The stored valid data includes: Based on the first data unit that has been determined to be a valid data unit, the first valid data unit is stored sequentially; and The second valid data unit is stored sequentially based on the second data unit corresponding to the first data unit that was determined to be an invalid data unit.

9. The method according to claim 8, wherein, Simultaneously activating the first and second verification circuits causes the dump operation for the first valid data unit and the dump operation for the second valid data unit to be performed alternately.

10. The method according to claim 8, wherein, First, the first verification circuit is enabled, and then the second verification circuit is enabled after the first verification circuit is disabled, so that after the dump operation for the first valid data unit is completed, the dump operation for the second valid data unit is performed.

11. The method according to claim 1, wherein, The first sensing operation and the second sensing operation start simultaneously, so that the first sensing operation and the second sensing operation are completed simultaneously.

12. The method according to claim 1, wherein, The first sensing operation begins before the second sensing operation begins, so that the completion time of the first sensing operation is earlier than the completion time of the second sensing operation.

13. The method according to claim 1, wherein, The dump operation begins at the completion time of the second sensing operation.

14. The method according to claim 1, wherein, The dump operation begins at the point when the first sensing operation is completed.

15. The method according to claim 1, further comprising: When the dump operation based on the first read setting data and the second read setting data is determined to be a failure, a third sensing operation is performed to sense the write setting data stored in the third memory cell of the first memory surface and store the third read setting data in the first page buffer circuit of the first memory surface. When the dump operation based on the first read setting data and the second read setting data is determined to be a failure, a fourth sensing operation is performed to sense the write setting data stored in the fourth memory cell of the second memory surface and store the fourth read setting data in the second page buffer circuit of the second memory surface. as well as Perform a dump operation to store the recovery settings data corresponding to the written settings data in the buffer based on the third read settings data and the fourth read settings data.

16. The method according to claim 1, further comprising: When the dump operation based on the first read setting data and the second read setting data is determined to be a failure, a third sensing operation is performed to sense the write setting data stored in the third memory cell of the third memory surface and store the third read setting data in the third page buffer circuit of the third memory surface. as well as Perform a dump operation to store the recovery settings data corresponding to the written settings data in a buffer based on the first read settings data, the second read settings data, and the third read settings data.

17. The method according to claim 2, wherein, Write setup data is obtained by copying each bit of the original setup data into multiple copy bits, and Each of the first verification circuit and the second verification circuit includes a majority voter circuit configured to determine whether the number of bits with equal values ​​among the plurality of replica bits is equal to or greater than a reference number.

18. A method for controlling the initialization of a non-volatile memory device, comprising: Perform a first sensing operation to sense write setting data stored in a first memory cell of a first memory surface of the non-volatile memory device, and store the first read setting data in a first page buffer circuit of the first memory surface; Perform a second sensing operation to sense write setting data stored in a second memory cell on the second memory surface of the non-volatile memory device, and store the second read setting data in the second page buffer circuit on the second memory surface; The validity of each of a plurality of first data units is verified using a first verification circuit connected to the first page buffer circuit, the plurality of first data units corresponding to first read setting data divided by unit bit number; A second verification circuit connected to the second page buffer circuit is used to verify the validity of each of the plurality of second data units, which correspond to second read setting data divided by unit number of bits; Based on the validity verification results of each of the plurality of first data units and the validity verification results of each of the plurality of second data units, the first verification circuit and the second verification circuit are selectively enabled. as well as Based on the validity verification results of each of the plurality of first data units and the validity verification results of each of the plurality of second data units, a valid data unit corresponding to one of the first data unit and the second data unit is stored in the buffer of the non-volatile memory device.

19. A non-volatile memory device, comprising: The first memory surface includes a first memory cell for storing write setting data and a first page buffer circuit for storing first read setting data sensed from the first memory cell. The second memory surface includes a second memory cell for storing write setting data and a second page buffer circuit for storing second read setting data sensed from the second memory cell; A first verification circuit is connected to a first page buffer circuit, and the first verification circuit is configured to verify the validity of the first read setting data. A second verification circuit is connected to a second page buffer circuit, and the second verification circuit is configured to verify the validity of the second read setting data. The dump control logic is configured to determine valid data corresponding to one of the first and second read setting data based on the validity verification results of the first and second read setting data. as well as The buffer is configured to store valid data provided from the dump control logic.

20. The non-volatile memory device according to claim 19, wherein, The non-volatile memory device is a vertical NAND flash memory device, such that each of the first memory plane and the second memory plane includes NAND flash memory cells stacked in a vertical direction to form a cell string.

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