Semiconductor package

Abstract

A semiconductor package includes a semiconductor chip including chip pads, a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pads of the semiconductor chip, a molding layer on at least a portion of the semiconductor chip, and a conductive pillar in the molding layer, the conductive pillar having a bottom surface and a top surface, the bottom surface of the conductive pillar being in contact with the lower redistribution pattern of the lower redistribution structure, and the top surface of the conductive pillar having a concave shape.

Description

Technical Field

[0001] This disclosure relates to semiconductor packaging, and more specifically, to fan-out semiconductor packaging. Background Technology

[0002] With the rapid growth in demand for portable devices in the recent electronics market, there has been a continuous requirement for electronic components mounted on electronic products to be compact and lightweight. To achieve this compactness and lightness, the semiconductor packages mounted on these components can be designed to be small in size and handle large amounts of data. In particular, in highly integrated semiconductor chips with an increased number of input / output (I / O) terminals, the distance between the I / O terminals decreases, thus potentially leading to interference between them. To eliminate interference between I / O terminals, fan-out semiconductor packages that allow for increased spacing between the I / O terminals can be used. Summary of the Invention

[0003] The inventive concept provides a semiconductor package with increased reliability.

[0004] According to one aspect of the inventive concept, a semiconductor package is provided, the semiconductor package comprising: a semiconductor chip including chip pads; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pads of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive pillar in the molding layer, the conductive pillar having a bottom surface and a top surface, the bottom surface of the conductive pillar contacting the lower redistribution pattern of the lower redistribution structure, and the top surface of the conductive pillar having a recessed shape.

[0005] According to another aspect of the inventive concept, a semiconductor package is provided, the semiconductor package comprising: a lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern; a lower semiconductor chip on a first surface of the lower redistribution insulating layer, the lower semiconductor chip being electrically connected to the lower redistribution pattern; a conductive pillar on the first surface of the lower redistribution insulating layer, the conductive pillar being electrically connected to the lower redistribution pattern and having a top surface having a recessed shape; a molding layer on a side surface of the lower semiconductor chip and a side surface of the conductive pillar, the molding layer having a top surface at a level higher than the top surface of the conductive pillar; and an upper redistribution structure on the molding layer and the lower semiconductor chip, the upper redistribution structure including an upper redistribution insulating layer and an upper redistribution pattern, the upper redistribution insulating layer being on the top surface of the conductive pillar, the upper redistribution pattern penetrating a portion of the upper redistribution insulating layer and contacting the conductive pillar.

[0006] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern; a semiconductor chip on a first surface of the lower redistribution insulating layer, the semiconductor chip being electrically connected to the lower redistribution pattern; a molding layer on a side surface of the semiconductor chip; and a conductive pillar in the molding layer, the conductive pillar having a bottom surface and a top surface, the bottom surface of the conductive pillar contacting the lower redistribution pattern of the lower redistribution structure, and the top surface of the conductive pillar being at a level lower than the top surface of the molding layer. The conductive pillar may be on the inner wall of the molding layer. Corner portions of the molding layer may be between the top surface of the molding layer and the inner wall of the molding layer and may be chamfered or rounded. Attached Figure Description

[0007] The embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0009] Figure 2 yes Figure 1 Enlarged sectional view of region II in the image;

[0010] Figure 3 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0011] Figure 4 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0012] Figure 5 yes Figure 4 An enlarged sectional view of region V in the diagram;

[0013] Figure 6 Is with Figure 4 An enlarged sectional view of the portion corresponding to region V in the diagram;

[0014] Figure 7 This is a cross-sectional view of a semiconductor package according to an example embodiment;

[0015] Figure 8 yes Figure 7 An enlarged sectional view of region VIII in the diagram;

[0016] Figures 9A to 9O This is a cross-sectional view of the sequential stages in a method for manufacturing a semiconductor package according to an exemplary embodiment;

[0017] Figure 10 This is a cross-sectional view of a semiconductor package according to an example embodiment; and

[0018] Figure 11 yes Figure 10 An enlarged sectional view of region XI in the diagram. Detailed Implementation

[0019] In the following description, embodiments will be illustrated with reference to the accompanying drawings. In the drawings, the same numbers denote the same elements, and redundant descriptions may be omitted.

[0020] Figure 1 This is a cross-sectional view of a semiconductor package 10 according to an example embodiment. Figure 2 yes Figure 1 An enlarged sectional view of region II in the diagram.

[0021] Reference Figure 1 and Figure 2 The semiconductor package 10 may include a redistribution structure 101, a semiconductor chip 200, conductive pillars 160, and a molding layer 250.

[0022] The redistribution structure 101 may include a redistribution insulating layer 110, a plurality of redistribution patterns (e.g., first to third redistribution patterns 120, 130 and 140) and an external electrode pad 150.

[0023] The redistributed insulating layer 110 may include multiple insulating layers, such as first to third insulating layers 111, 113, and 115. The first to third insulating layers 111, 113, and 115 may be formed from a material film, for example, comprising an organic compound. In an example embodiment, the first to third insulating layers 111, 113, and 115 may be formed from a material layer comprising an organic polymer material. In an example embodiment, the first to third insulating layers 111, 113, and 115 may include a photolithographically imageable dielectric (PID) material capable of photolithography. For example, the first to third insulating layers 111, 113, and 115 may include photosensitive polyimide (PSPI). In an example embodiment, the first to third insulating layers 111, 113, and 115 may include oxides or nitrides. For example, the first to third insulating layers 111, 113, and 115 may include silicon oxide or silicon nitride.

[0024] The first to third redistribution patterns 120, 130, and 140 may respectively include first to third conductive line patterns 121, 131, and 141 and first to third conductive path patterns 123, 133, and 143. Each of the first to third conductive line patterns 121, 131, and 141 may be on at least one of the top and bottom surfaces of a corresponding one of the first to third insulating layers 111, 113, and 115. The first to third conductive path patterns 123, 133, and 143 may penetrate at least one of the first to third insulating layers 111, 113, and 115. The first to third conductive path patterns 123, 133, and 143 may be connected to at least one of the first to third conductive line patterns 121, 131, and 141 and connected to the external electrode pad 150.

[0025] Multiple seed layers (e.g., first to third seed layers 125, 135, and 145) can be respectively disposed between the first to third insulating layers 111, 113, and 115 and the first to third conductive line patterns 121, 131, and 141, and respectively disposed between the first to third insulating layers 111, 113, and 115 and the first to third conductive path patterns 123, 133, and 143. In an exemplary embodiment, the first to third seed layers 125, 135, and 145 can be formed using physical vapor deposition, and the first to third conductive line patterns 121, 131, and 141 and the first to third conductive path patterns 123, 133, and 143 can be formed using electroless plating.

[0026] For example, the first to third seed layers 125, 135, and 145 can be selected from the group consisting of copper (Cu), titanium (Ti), titanium-tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), and aluminum (Al). However, the first to third seed layers 125, 135, and 145 are not limited to the above materials. In an example embodiment, the first to third seed layers 125, 135, and 145 may comprise a Cu / Ti layer where Cu is stacked on Ti or a Cu / TiW layer where Cu is stacked on TiW.

[0027] The first to third conductive line patterns 121, 131, and 141 and the first to third conductive path patterns 123, 133, and 143 may include metals such as Cu, Al, W, Ti, Ta, indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or alloys thereof, but are not limited thereto. In an example embodiment, when Cu is used in the first to third conductive line patterns 121, 131, and 141 and the first to third conductive path patterns 123, 133, and 143, at least a portion of the first to third seed layers 125, 135, and 145 may serve as a diffusion barrier.

[0028] External electrode pads 150 can be disposed on the bottom surface of the redistribution structure 101. External connectors 190 can be disposed on external electrode pads 150. Semiconductor package 10 can be electrically connected to and mounted on the module substrate or system board of an electronic product via external connectors 190. External electrode pads 150 can be used as under-bump metal layers (UBM) on which external connectors 190 are disposed.

[0029] In the example embodiment, the external electrode pad 150 may have a generally uniform thickness. The bottom surface of the external electrode pad 150 on which the external connector 190 is disposed may be flat. For example, the external electrode pad 150 may include metals such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, or Ru, or alloys thereof, but is not limited thereto.

[0030] The configuration of redistribution structure 101 will be described in detail below.

[0031] The redistribution insulating layer 110 may include a first insulating layer 111, a second insulating layer 113, and a third insulating layer 115 stacked sequentially. The first redistribution pattern 120 may include a first conductive line pattern 121, a first conductive path pattern 123, and a first seed layer 125. The second redistribution pattern 130 may include a second conductive line pattern 131, a second conductive path pattern 133, and a second seed layer 135. The third redistribution pattern 140 may include a third conductive line pattern 141, a third conductive path pattern 143, and a third seed layer 145.

[0032] The first insulating layer 111 may include a first passage opening on a portion of the external electrode pad 150 (e.g., exposing a portion of the external electrode pad 150). Figure 9E(VO1 in the diagram). The first seed layer 125 may be disposed on a portion of the top surface of the first insulating layer 111, the inner wall of the first through-path opening VO1, and the portion of the top surface of the external electrode pad 150 exposed through the first through-path opening VO1. A portion of the first seed layer 125 may be disposed between the first conductive line pattern 121 and the top surface of the first insulating layer 111. Another portion of the first seed layer 125 may be disposed between the first conductive path pattern 123 and the external electrode pad 150, and surrounding the sidewall of the first conductive path pattern 123.

[0033] The first conductive line pattern 121 and the first conductive path pattern 123 can be disposed on the first seed layer 125. The first conductive line pattern 121 and the first conductive path pattern 123 can be integrally formed together using a plating process. The first conductive line pattern 121 can be disposed on the first conductive path pattern 123 and on a portion of the first seed layer 125 on the top surface of the first insulating layer 111. The first conductive path pattern 123 can cover and fill the portion of the first seed layer 125 in the first path opening VO1. The first conductive path pattern 123 can extend vertically through the first insulating layer 111 and connect to the first conductive line pattern 121 and the external electrode pad 150.

[0034] In an example implementation, the first conductive path pattern 123 may have a shape in which its width in the horizontal direction decreases in the direction from the first surface 118 of the redistributed insulating layer 110 toward its second surface 119 (or in the direction away from the semiconductor chip 200).

[0035] A second insulating layer 113 may be stacked on top of the first insulating layer 111. The second insulating layer 113 covers a portion of the first conductive wire pattern 121 and has a second passage opening on / exposing a portion of the first conductive wire pattern 121. Figure 9E (VO2 in the middle).

[0036] The second seed layer 135 may be disposed on a portion of the top surface of the second insulating layer 113, the inner wall of the second passage opening VO2, and the portion of the top surface of the first conductive line pattern 121 exposed through the second passage opening VO2. A portion of the second seed layer 135 may be disposed between the second conductive line pattern 131 and the top surface of the second insulating layer 113. Another portion of the second seed layer 135 may be disposed between the second conductive passage pattern 133 and the first conductive line pattern 121 and surrounding the sidewall of the second conductive passage pattern 133.

[0037] The second conductive path pattern 133 and the second conductive line pattern 131 can be disposed on the second seed layer 135. The second conductive path pattern 133 and the second conductive line pattern 131 can be integrally formed together using a plating process. The second conductive line pattern 131 can be disposed on the second conductive path pattern 133 and on a portion of the second seed layer 135 on the top surface of the second insulating layer 113. The second conductive path pattern 133 can cover and fill the portion of the second seed layer 135 in the second path opening VO2. The second conductive path pattern 133 can extend vertically through the second insulating layer 113 and connect to the second conductive line pattern 131 and the first conductive line pattern 121.

[0038] In an example implementation, the second conductive path pattern 133 may have a shape in which its width in the horizontal direction decreases in the direction from the first surface 118 of the redistributed insulating layer 110 toward its second surface 119.

[0039] A third insulating layer 115 may be stacked on top of the second insulating layer 113. The third insulating layer 115 covers a portion of the second conductive wire pattern 131 and has a third passage opening on / exposing another portion of the second conductive wire pattern 131. Figure 9E (VO3 in the middle).

[0040] The third seed layer 145 may be disposed on a portion of the top surface of the third insulating layer 115, the inner wall of the third passage opening VO3, and the portion of the top surface of the second conductive line pattern 131 exposed through the third passage opening VO3. A portion of the third seed layer 145 may be disposed between the third conductive line pattern 141 and the top surface of the third insulating layer 115. Another portion of the third seed layer 145 may be disposed between the third conductive passage pattern 143 and the second conductive line pattern 131 and surround the sidewall of the third conductive passage pattern 143.

[0041] The third conductive path pattern 143 and the third conductive line pattern 141 can be disposed on the third seed layer 145. The third conductive path pattern 143 and the third conductive line pattern 141 can be integrally formed together using a plating process. The third conductive line pattern 141 can be disposed on the third conductive path pattern 143 and on the portion of the third seed layer 145 on the top surface of the third insulating layer 115. The third conductive path pattern 143 can cover and fill the portion of the third seed layer 145 in the third path opening VO3. The third conductive path pattern 143 can extend vertically through the third insulating layer 115 and connect to the third conductive line pattern 141 and the second conductive line pattern 131.

[0042] In an example implementation, the third conductive path pattern 143 may have a shape in which its width in the horizontal direction decreases in the direction from the first surface 118 of the redistributed insulating layer 110 toward its second surface 119.

[0043] A portion of the third conductive line pattern 141 of the third redistribution pattern 140 can be disposed under the semiconductor chip 200 and can be used as a pad for attaching the chip connector 230. In addition, another portion of the third conductive line pattern 141 of the third redistribution pattern 140 can be separated from the side surface of the semiconductor chip 200 in the horizontal direction and can be used as a pad for attaching the conductive post 160.

[0044] Despite Figure 1 The redistribution structure 101 includes three insulating layers (i.e., first to third insulating layers 111, 113, and 115), three conductive line patterns (i.e., first to third conductive line patterns 121, 131, and 141), and three conductive path patterns (i.e., first to third conductive path patterns 123, 133, and 143), but the inventive concept is not limited thereto. The number of insulating layers, conductive line patterns, and conductive path patterns can vary depending on the design of the circuit wiring in the redistribution structure 101.

[0045] Semiconductor chip 200 can be attached to redistribution structure 101. For example, semiconductor chip 200 can be mounted on redistribution structure 101 in a flip-chip manner.

[0046] Semiconductor chip 200 may include a memory chip or a logic chip. The memory chip may include, for example, volatile memory chips such as Dynamic Random Access Memory (DRAM) or Static RAM (SRAM), or non-volatile memory chips such as Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FeRAM), or Resistive RAM (RRAM). In some embodiments, the memory chip may include a High Bandwidth Memory (HBM) DRAM semiconductor chip. The logic chip may include, for example, a microprocessor, an analog device, or a digital signal processor.

[0047] Semiconductor chip 200 may include semiconductor substrate 210 and chip pads 220 on the surface of semiconductor substrate 210.

[0048] Semiconductor substrate 210 may include, for example, silicon (Si). Semiconductor substrate 210 may include semiconductor elements (e.g., germanium (Ge)) or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Semiconductor substrate 210 may have an active side and a passive side opposite to the active side. In an example embodiment, the active side of semiconductor substrate 210 may face redistribution structure 101.

[0049] Semiconductor devices, including various individual components, can be formed in the active side of the semiconductor substrate 210 of the semiconductor chip 200.

[0050] Chip connector 230 may be disposed between chip pad 220 of semiconductor chip 200 and third conductive line pattern 141. Chip connector 230 can electrically connect chip pad 220 of semiconductor chip 200 to third conductive line pattern 141. Chip connector 230 may include at least one selected from, for example, pillar structures, solder bumps, solder balls, and solder layers.

[0051] Through chip connector 230, first to third redistribution patterns 120, 130 and 140, external electrode pads 150 and external connector 190, semiconductor chip 200 can receive from outside semiconductor package 10 at least one selected from control signals, power signals and ground signals for operation of semiconductor chip 200 or data signals to be stored in semiconductor chip 200, or provide data stored in semiconductor chip 200 to outside semiconductor package 10.

[0052] An underfill layer 240 may be disposed between the semiconductor chip 200 and the redistribution structure 101 to surround the chip connector 230. The underfill layer 240 may comprise, for example, an epoxy resin formed using a capillary underfill process. In an example embodiment, the underfill layer 240 may comprise a non-conductive film (NCF).

[0053] The molding layer 250 may be disposed on the upper surface of the redistribution structure 101 (i.e., the first surface 118 of the redistribution insulating layer 110) and may cover at least a portion of the semiconductor chip 200 and the side surfaces of the conductive pillars 160. The molding layer 250 may include, for example, epoxy molding compound (EMC). The molding layer 250 may not be limited to EMC and may include various materials such as epoxy resin materials, thermosetting materials, thermoplastic materials, and ultraviolet (UV) treated materials.

[0054] In an example embodiment, the molding layer 250 may cover a portion of the first surface 118 of the redistribution insulating layer 110 and the side surface of the semiconductor chip 200. The top surface 251 of the molding layer 250 may be coplanar with the top surface of the semiconductor chip 200. In this case, the top surface of the semiconductor chip 200 may be exposed to components outside the semiconductor package 10. In some embodiments, the first and second molding layers 250 may be on opposite first and second side surfaces of the semiconductor chip 200, and may each have first and second conductive pillars 160 therein. Each conductive pillar 160 may have a top surface 161 at a level lower than the adjacent top surface 251 of the molding layer 250.

[0055] The conductive pillar 160 may be horizontally separated from the side surface of the semiconductor chip 200 and may have a pillar or pillar shape extending vertically and penetrating the molding layer 250. The conductive pillar 160 may be arranged on a third redistribution pattern 140 serving as a pad. The conductive pillar 160 may be electrically connected to the semiconductor chip 200 through at least a portion of the first to third redistribution patterns 120, 130 and 140, and may be electrically connected to the external connector 190 through at least a portion of the first to third redistribution patterns 120, 130 and 140 and the external electrode pad 150.

[0056] For example, the conductive post 160 may include Cu, but is not limited to this.

[0057] The molded layer 250 may include a recess 257 exposing a top surface 161 of the conductive post 160 and an inner wall 253 provided by the recess 257. A corner portion 255 where the top surface 251 of the molded layer 250 meets the inner wall 253 of the molded layer 250 may be chamfered or rounded. In some embodiments, the molded layer 250 may include (in a cross-sectional view) a first inner wall 253 and a second inner wall 253 opposite to each other, and the conductive post 160 may extend continuously from the first inner wall 253 to the second inner wall 253.

[0058] In the example embodiment, the top surface 161 of the conductive post 160 may generally have a recessed shape. In other words, the central portion of the top surface 161 of the conductive post 160 may be recessed such that the central portion of the top surface 161 of the conductive post 160 may be lower than the edge portion of the top surface 161 of the conductive post.

[0059] At this time, the top surface 161 of the conductive post 160 can be at a lower level than the top surface 251 of the molding layer 250. In an example embodiment, the vertical distance between the center of the top surface 161 of the conductive post 160 and the top surface 251 of the molding layer 250 can be from about 1 micrometer (μm) to about 100 μm.

[0060] Figure 3 This is a cross-sectional view of a semiconductor package 10a according to an example embodiment.

[0061] In addition to the molding layer 250a Figure 3 The semiconductor package 10a can be compared with the reference Figure 1 and Figure 2 The semiconductor package 10 described is the same as or similar to the reference package 10a. For ease of description, the description will focus on the semiconductor package 10a and the reference package 10a. Figure 1 and Figure 2 The differences between the semiconductor packages 10 are described.

[0062] Reference Figure 3The semiconductor package 10a may include a redistribution structure 101, a semiconductor chip 200, conductive pillars 160, and a molding layer 250a. The molding layer 250a may cover the side and top surfaces of the semiconductor chip 200 and the side surfaces of the conductive pillars 160. The molding layer 250a may include a planarized top surface. The top surface 251a of the molding layer 250a may be at a level higher than the top surface of the semiconductor chip 200. The top surface 251a of the molding layer 250a may also be at a level higher than the top surface 161 of the conductive pillars 160.

[0063] Figure 4 This is a cross-sectional view of the semiconductor package 10b according to an example embodiment. Figure 5 yes Figure 4 An enlarged sectional view of region V in the diagram.

[0064] Figure 4 and Figure 5 The semiconductor package 10b shown can be compared with the reference Figure 1 and Figure 2 The semiconductor package 10b described is the same as or similar to the semiconductor package 10b, except that it also includes an upper redistribution structure 401 and an upper semiconductor chip 500. For ease of description, the description will focus on the semiconductor package 10b and the referenced semiconductor package 10b. Figure 1 and Figure 2 The differences between the semiconductor packages 10 are described.

[0065] Reference Figure 4 and Figure 5 The semiconductor package 10b may include a redistribution structure 101, a semiconductor chip 200, a conductive pillar 160, a molding layer 250, an upper redistribution structure 401, an upper semiconductor chip 500, and an upper molding layer 550.

[0066] The redistribution structure 101 may include a redistribution insulating layer 110, first to third redistribution patterns 120, 130 and 140, and external electrode pads 150. Figure 4 The redistribution structure 101 can be compared with the reference Figure 1 and Figure 2 The redistribution structures described in 101 are essentially the same or similar. Figure 4 and Figure 5 The semiconductor chip 200, conductive pillar 160, and molding layer 250 shown can be compared with the reference. Figure 1 and Figure 2 The semiconductor chip 200, conductive pillar 160 and molding layer 250 described are substantially the same or similar.

[0067] The upper redistribution structure 401 may include an upper redistribution insulating layer 410 and a plurality of upper redistribution patterns (e.g., a first upper redistribution pattern 420 and a second upper redistribution pattern 430). The plurality of upper redistribution patterns may be electrically connected to a third redistribution pattern 140 of the redistribution structure 101 via conductive posts 160.

[0068] The upper redistribution insulating layer 410 may include a plurality of upper insulating layers (e.g., a first upper insulating layer 411 and a second upper insulating layer 413) sequentially stacked on the semiconductor chip 200 and the molding layer 250. For example, the first upper insulating layer 411 and the second upper insulating layer 413 may include a PID material, such as photosensitive polyimide. Alternatively, the first upper insulating layer 411 and the second upper insulating layer 413 may include oxides or nitrides.

[0069] The first upper redistribution pattern 420 and the second upper redistribution pattern 430 may respectively include a first upper conductive line pattern 421 and a second upper conductive line pattern 431, and a first upper conductive path pattern 423 and a second upper conductive path pattern 433. Each of the first upper conductive line pattern 421 and the second upper conductive line pattern 431 may be arranged on at least one of the top and bottom surfaces of a corresponding one of the first upper insulating layer 411 and the second upper insulating layer 413. The first upper conductive path pattern 423 and the second upper conductive path pattern 433 may penetrate at least one of the first upper insulating layer 411 and the second upper insulating layer 413. The first upper conductive path pattern 423 may be connected to the first upper conductive line pattern 421 and the top surface 161 of the conductive post 160, and the second upper conductive path pattern 433 may be connected to the second upper conductive line pattern 431.

[0070] For example, the upper redistribution insulating layer 410 may include a first upper insulating layer 411 and a second upper insulating layer 413 sequentially stacked on the semiconductor chip 200 and the molding layer 250.

[0071] The first upper insulating layer 411 can cover the top surface of the semiconductor chip 200 and the top surface 251 of the molding layer 250. The first upper insulating layer 411 can fill the recesses of the molding layer 250. Figure 2 (257 in the text). The portion of the first upper insulating layer 411 that fills the recess of the molding layer 250 can cover the inner wall 253 of the molding layer 250 and the top surface 161 of the conductive pillar 160. Since the first upper insulating layer 411 fills the recess of the molding layer 250, the contact area between the first upper insulating layer 411 and the molding layer 250 is increased. Therefore, the adhesion strength of the first upper insulating layer 411 to the molding layer 250 can be improved, and delamination of the first upper insulating layer 411 can be suppressed / prevented.

[0072] Furthermore, since the molding layer 250 has a chamfered or rounded corner portion 255, stress concentration on the corner portion 255 can be reduced / prevented and cracks in the vicinity of the corner portion 255 of the molding layer 250 due to stress concentration can be suppressed / prevented.

[0073] The first upper redistribution pattern 420 may include a first upper conductive line pattern 421, a first upper conductive path pattern 423, and a first upper seed layer 425. The second upper redistribution pattern 430 may include a second upper conductive line pattern 431, a second upper conductive path pattern 433, and a second upper seed layer 435.

[0074] The first upper insulating layer 411 may include a passage opening that exposes a portion of the top surface 161 of the conductive post 160. A first upper seed layer 425 may be disposed on a portion of the top surface of the first upper insulating layer 411, the inner wall of the passage opening of the first upper insulating layer 411, and the portion of the top surface 161 of the conductive post 160 exposed through the passage opening of the first upper insulating layer 411. A portion of the first upper seed layer 425 may be disposed between the first upper conductive wire pattern 421 and the top surface of the first upper insulating layer 411, and another portion of the first upper seed layer 425 may be disposed between the first upper conductive passage pattern 423 and the top surface 161 of the conductive post 160 and surrounding the sidewall of the first upper conductive passage pattern 423.

[0075] The first upper conductive line pattern 421 and the first upper conductive path pattern 423 can be disposed on the first upper seed layer 425. The first upper conductive line pattern 421 and the first upper conductive path pattern 423 can be integrally formed together using a plating process. The first upper conductive line pattern 421 can be disposed on a portion of the top surface of the first upper seed layer 425 on the first upper insulating layer 411 and on the first upper conductive path pattern 423. The first upper conductive path pattern 423 can cover a portion of the first upper seed layer 425 in the path opening of the first upper insulating layer 411 and fill the path opening of the first upper insulating layer 411. The first upper conductive path pattern 423 can extend vertically and penetrate the first upper insulating layer 411, electrically connecting the first upper conductive line pattern 421 to the conductive post 160.

[0076] In an example embodiment, the first upper conductive path pattern 423 may have a shape in which its horizontal width increases away from the top surface 161 of the conductive post 160. Therefore, the horizontal width of the first upper conductive path pattern 423 may gradually narrow toward the top surface 161 of the conductive post 160.

[0077] The second upper insulating layer 413 may be stacked on the first upper insulating layer 411, the second upper insulating layer 413 covering a portion of the first upper conductive line pattern 421 and having a passage opening that exposes another portion of the first upper conductive line pattern 421.

[0078] The second upper seed layer 435 may be disposed on a portion of the top surface of the second upper insulating layer 413, the inner wall of the passage opening of the second upper insulating layer 413, and the portion of the top surface of the first upper conductive line pattern 421 exposed through the passage opening of the second upper insulating layer 413. A portion of the second upper seed layer 435 may be disposed between the second upper conductive line pattern 431 and the top surface of the second upper insulating layer 413, and another portion of the second upper seed layer 435 may be disposed between the second upper conductive passage pattern 433 and the first upper conductive line pattern 421 and surround the sidewall of the second upper conductive passage pattern 433.

[0079] The second upper conductive path pattern 433 and the second upper conductive line pattern 431 can be disposed on the second upper seed layer 435. The second upper conductive path pattern 433 and the second upper conductive line pattern 431 can be integrally formed together using a plating process. The second upper conductive line pattern 431 can be disposed on a portion of the second upper seed layer 435 on the top surface of the second upper insulating layer 413 and on the second upper conductive path pattern 433. The second upper conductive path pattern 433 can cover a portion of the second upper seed layer 435 in the path opening of the second upper insulating layer 413 and fill the path opening of the second upper insulating layer 413. The second upper conductive path pattern 433 can extend vertically through the second upper insulating layer 413 and electrically connect the second upper conductive line pattern 431 to the first upper conductive line pattern 421.

[0080] The upper semiconductor chip 500 may be attached to the upper redistribution structure 401. For example, the upper semiconductor chip 500 may be mounted on the upper redistribution structure 401 in a flip-chip manner. The upper semiconductor chip 500 may include a semiconductor substrate 510 and chip pads 520. A chip connector 530 may be disposed between the chip pads 520 of the upper semiconductor chip 500 and a second upper redistribution pattern 430 of the upper redistribution structure 401. The chip connector 530 can electrically connect the chip pads 520 of the upper semiconductor chip 500 to the second upper redistribution pattern 430. An underfill material layer 540 may be disposed between the upper semiconductor chip 500 and the upper redistribution structure 401 to surround the chip connector 530. An upper molding layer 550 covering at least a portion of the upper semiconductor chip 500 may be disposed on the upper redistribution structure 401.

[0081] In the example implementation, semiconductor chip 200 and upper semiconductor chip 500 can be different types. For example, when semiconductor chip 200 is a logic chip, upper semiconductor chip 500 can be a memory chip. In the example implementation, semiconductor package 10b can include a system-in-package (SIP) in which different types of semiconductor chips are electrically connected to each other and operate as a single system. In the example implementation, semiconductor chip 200 and upper semiconductor chip 500 can be the same type.

[0082] Figure 6 Is with Figure 4 An enlarged sectional view of the portion corresponding to region V in the diagram.

[0083] Reference Figure 6 The first upper redistribution pattern 420a may include a plurality of first upper conductive path patterns 423 connected to the first upper conductive line pattern 421. For example, two to five first upper conductive path patterns 423 may be connected to the first upper conductive line pattern 421.

[0084] The first upper conductive path pattern 423 may be separated from each other in the horizontal direction and may extend in the vertical direction to penetrate the first upper insulating layer 411. The first upper conductive path pattern 423 may be connected to the top surface 161 of the conductive post 160, thereby electrically connecting the first upper conductive line pattern 421 to the conductive post 160.

[0085] Figure 7 This is a cross-sectional view of a semiconductor package 10c according to an example embodiment. Figure 8 yes Figure 7 An enlarged sectional view of region VIII. For ease of description, the repeated descriptions already given above will be brief or omitted.

[0086] Reference Figure 7 and Figure 8 Semiconductor package 10c may include a lower package 11L and an upper package 11U on the lower package 11L. Semiconductor package 10c may be a stacked package type, wherein the upper package 11U is attached to the lower package 11L.

[0087] The lower package 11L may include a redistribution structure 101, a semiconductor chip 200, conductive pillars 160, and a molding layer 250. The lower package 11L can be compared with a reference... Figure 1 and Figure 2 The semiconductor package 10 described is substantially the same or similar.

[0088] The upper package 11U may include an upper redistribution structure 401, an upper semiconductor chip 500, a chip connector 530, an underfill material layer 540, and an upper molding layer 550. The upper semiconductor chip 500, chip connector 530, underfill material layer 540, and upper molding layer 550 can be compatible with already referenced... Figure 4 and Figure 5 The upper semiconductor chip 500, chip connector 530, bottom filler layer 540 and upper molding layer 550 described are substantially the same or similar.

[0089] The upper redistribution structure 401 of the upper package 11U may include an upper redistribution insulating layer 410, a plurality of upper redistribution patterns (e.g., a first upper redistribution pattern 420 and a second upper redistribution pattern 430) and electrode pads 450.

[0090] For example, the upper redistribution insulating layer 410 may include a first upper insulating layer 411 and a second upper insulating layer 413 sequentially stacked on the lower package 11L.

[0091] For example, the first upper redistribution pattern 420 may include a first upper conductive line pattern 421, a first upper conductive path pattern 423, and a first upper seed layer 425. The first upper conductive line pattern 421 may extend along the top surface of the first upper insulating layer 411, and the first upper conductive path pattern 423 may partially penetrate the first upper insulating layer 411 and extend in the vertical direction between the first upper conductive line pattern 421 and the electrode pad 450. A portion of the first upper seed layer 425 may be between the first upper conductive line pattern 421 and the first upper insulating layer 411, and another portion of the first upper seed layer 425 may be disposed between the first upper conductive path pattern 423 and the electrode pad 450 and surround the sidewall of the first upper conductive path pattern 423.

[0092] For example, the second upper redistribution pattern 430 may include a second upper conductive line pattern 431, a second upper conductive path pattern 433, and a second upper seed layer 435. The second upper conductive line pattern 431 may extend along the top surface of the second upper insulating layer 413, and the second upper conductive path pattern 433 may penetrate the second upper insulating layer 413 and extend in the vertical direction between the second upper conductive line pattern 431 and the first upper conductive line pattern 421. A portion of the second upper seed layer 435 may be located between the second upper conductive line pattern 431 and the second upper insulating layer 413, and another portion of the second upper seed layer 435 may be disposed between the second upper conductive path pattern 433 and the first upper conductive line pattern 421 and surround the sidewall of the second upper conductive path pattern 433.

[0093] The upper package 11U can be electrically and / or physically connected to the lower package 11L via an inter-package connector 600 between the upper package 11U and the lower package 11L. The inter-package connector 600 can contact the electrode pads 450 and conductive posts 160 of the upper redistribution structure 401 and electrically connect the electrode pads 450 of the upper redistribution structure 401 to the conductive posts 160.

[0094] In an example implementation, the inter-package connector 600 can fill the recesses of the molding layer 250. Figure 2 (257 in the text). The inter-package connector 600 can cover the inner wall 253 of the molding layer 250 and the top surface 161 of the conductive pillar 160. Since the top surface 161 of the conductive pillar 160 has a generally concave shape, the contact area between the top surface 161 of the conductive pillar 160 and the inter-package connector 600 can be increased, and therefore, the contact resistance between the conductive pillar 160 and the inter-package connector 600 can be reduced. As a result, the electrical characteristics of the semiconductor package 10c can be improved.

[0095] Furthermore, since the inter-package connector 600 fills the recess of the molding layer 250, the contact area between the inter-package connector 600 and the molding layer 250 can be increased, thus increasing the adhesion strength between the inter-package connector 600 and the molding layer 250.

[0096] Figures 9A to 9O This is a cross-sectional view of the sequential stages in a method for manufacturing a semiconductor package according to an exemplary embodiment. Referring below... Figures 9A to 9O Description of manufacturing Figure 4 The method of semiconductor packaging 10b.

[0097] Reference Figure 9A A cover layer 320 is formed on a carrier substrate 310 to which a release film 311 is attached. The cover layer 320 may include a redistribution insulating layer 110 (on...). Figure 4 The cover layer 320 may be made of the same insulating material or a different insulating material. For example, the cover layer 320 may include a film of material containing an organic compound. In an example embodiment, the cover layer 320 may include a photosensitive polyimide. Alternatively, the cover layer 320 may include an oxide or a nitride.

[0098] The carrier substrate 310 may comprise a material that is stable relative to the baking and etching processes. When the carrier substrate 310 is subsequently separated and removed by laser ablation, it may comprise a transparent substrate. Alternatively, when the carrier substrate 310 is separated and removed by heating, it may comprise a heat-resistant substrate. In an example embodiment, the carrier substrate 310 may comprise a glass substrate. In an example embodiment, the carrier substrate 310 may comprise a heat-resistant organic polymer material, such as polyimide, polyetheretherketone (PEEK), polyethersulfone (PES), or polyphenylene sulfide (PPS), but is not limited thereto.

[0099] The release film 311 may include, for example, a laser reactive layer that reacts to laser radiation and evaporates, making the carrier substrate 310 separable. The release film 311 may include a carbon material layer. For example, the release film 311 may include an amorphous carbon layer (ACL), a hydrocarbon having a relatively high carbon content of about 85 wt% to about 99 wt% based on its total weight, or a spin-on hard mask (SOH) including derivatives of the hydrocarbon.

[0100] Reference Figure 9B External electrode pads 150 are formed on the capping layer 320. To form the external electrode pads 150, a conductive material film can be formed and patterned on the capping layer 320. The external electrode pads 150 can be formed to have a generally uniform thickness on the top surface of the capping layer 320, and the bottom surface of the external electrode pads 150 that contacts the top surface of the capping layer 320 can be flat.

[0101] In an example embodiment, the external electrode pad 150 may comprise a single metal material. In another example embodiment, the external electrode pad 150 may have a multilayer structure, wherein the multiple layers comprise different metal materials.

[0102] Reference Figure 9C After the external electrode pad 150 is formed, a first insulating layer 111 is formed, which includes a first through-hole opening VO1 that exposes a portion of the external electrode pad 150. For example, to form the first insulating layer 111, an insulating material film covering the external electrode pad 150 and the cover layer 320 can be formed, and a portion of the insulating material film can be removed using exposure and development to form the first through-hole opening VO1. The portion of the external electrode pad 150 can be exposed through the first through-hole opening VO1.

[0103] For example, to form the first access opening VO1, reactive ion etching (RIE) using plasma, laser drilling, etc., can be performed. The first access opening VO1 can have a shape in which its horizontal width decreases downward (towards the external electrode pad 150).

[0104] Reference Figure 9D ,exist Figure 9C The resulting structure forms a first seed crystal layer 125, a first conductive line pattern 121, and a first conductive path pattern 123.

[0105] Specifically, a seed metal film is formed on the top surface of the first insulating layer 111, the inner wall of the first insulating layer 111 provided by the first passage opening VO1, and the outer electrode pad 150 exposed through the first passage opening VO1. For example, physical vapor deposition can be used to form the seed metal film. After forming the seed metal film, a photoresist pattern including the opening is formed, and the seed metal film is used as a seed to perform a plating process, thereby forming a first conductive line pattern 121 and a first conductive passage pattern 123. Thereafter, the photoresist pattern is removed, and the portion of the seed metal film exposed by removing the photoresist pattern is removed. As a result of removing the seed metal film, a first seed layer 125 can be formed between the top surface of the first insulating layer 111 and the first conductive line pattern 121, between the first conductive passage pattern 123 and the inner wall of the first conductive insulating layer 111 (which is provided by the first passage opening VO1), and between the first conductive passage pattern 123 and the outer electrode pad 150. The first seed crystal layer 125, the first conductive line pattern 121, and the first conductive path pattern 123 can form a first redistribution pattern 120.

[0106] Reference Figure 9E The second insulating layer 113 including the second passage opening VO2, the second redistribution pattern 130, the third insulating layer 115 including the third passage opening VO3, and the third redistribution pattern 140 can be used with reference to Figure 9C and Figure 9D The described steps are substantially the same or similar, and are formed sequentially in Figure 9D The resulting structure includes the first to third insulating layers 111, 113 and 115 and the first to third redistribution patterns 120, 130 and 140, which can form the redistribution structure 101.

[0107] Specifically, the second seed layer 135 may be formed to cover the top surface of the second insulating layer 113, the inner wall of the second insulating layer 113 (which is provided by the second via opening VO2), and a portion of the first conductive line pattern 121 (which is exposed through the second via opening VO2). The second conductive line pattern 131 may extend along the top surface of the second insulating layer 113, and the second conductive via pattern 133 may fill the second via opening VO2. The second seed layer 135, the second conductive line pattern 131, and the second conductive via pattern 133 may form a second redistribution pattern 130.

[0108] The third seed layer 145 may be formed to cover the top surface of the third insulating layer 115, the inner wall of the third insulating layer 115 (which is provided by the third passage opening VO3), and a portion of the second conductive line pattern 131 (which is exposed through the third passage opening VO3). The third conductive line pattern 141 may extend along the top surface of the third insulating layer 115, and the third conductive passage pattern 143 may fill the third passage opening VO3. The third seed layer 145, the third conductive line pattern 141, and the third conductive passage pattern 143 may form a third redistribution pattern 140.

[0109] Reference Figure 9F A photoresist pattern 341 is formed on the first surface 118 of the redistribution insulating layer 110. The photoresist pattern 341 may include an opening 342 that exposes a portion of the third conductive line pattern 141 of the third redistribution pattern 140. The opening 342 of the photoresist pattern 341 may define a region in which conductive pillars 160 are formed in a subsequent process. Figure 9G middle).

[0110] Reference Figure 9G and Figure 9F Conductive pillars 160 are formed in the openings 342 of the photoresist pattern 341. The conductive pillars 160 may be formed on the portion of the third conductive line pattern 141 of the third redistribution pattern 140 (which is exposed through the openings 342 of the photoresist pattern 341) to at least partially fill the openings 342 of the photoresist pattern 341. The conductive pillars 160 may include, but are not limited to, Cu.

[0111] Reference Figure 9H and Figure 9G Remove the photoresist pattern 341. For example, a stripping process can be used to remove the photoresist pattern 341.

[0112] Reference Figure 9I The semiconductor chip 200 is attached to the redistribution structure 101. The semiconductor chip 200 can be attached to the redistribution structure 101 such that the chip pad 220 faces the redistribution structure 101. The chip pad 220 of the semiconductor chip 200 can be connected to the third conductive line pattern 141 of the third redistribution pattern 140 via the chip connector 230.

[0113] After attaching the semiconductor chip 200 to the redistribution structure 101, an underfill material layer 240 is formed to fill the space between the semiconductor chip 200 and the redistribution structure 101. The underfill material layer 240 may surround the chip connector 230. For example, after attaching the semiconductor chip 200 to the redistribution structure 101, a capillary underfill process can be used to form the underfill material layer 240. In an example embodiment, the underfill material layer 240 can be formed by attaching a non-conductive film to the chip pads 220 of the semiconductor chip 200 and attaching the semiconductor chip 200 to the redistribution structure 101.

[0114] Reference Figure 9J After forming the bottom filler material layer 240, a molding layer 250 is formed to mold the semiconductor chip 200. The molding layer 250 may cover the semiconductor chip 200 and the conductive pillars 160. The molding layer 250 may cover the side and top surfaces of the semiconductor chip 200 and the side and top surfaces of the conductive pillars 160.

[0115] Reference Figure 9K and Figure 9J A portion of the molding layer 250 can be removed to expose the conductive pillar 160. For example, etch-back or chemical mechanical polishing (CMP) can be performed to remove this portion of the molding layer 250. In this case, the top surface of the conductive pillar 160 can be formed to be at a lower level than the top surface of the molding layer 250 and generally have a recessed shape.

[0116] In an example embodiment, CMP can induce dishing in the conductive pillar 160 by performing CMP on the molding layer 250 and the conductive pillar 160. The molding layer 250 and the conductive pillar 160 comprise different materials and therefore have different removal rates during CMP. Therefore, the materials of the molding layer 250 and the conductive pillar 160 can be appropriately selected to control the amount of dishing in the conductive pillar 160. In an example embodiment, the molding layer 250 may include EMC, and the conductive pillar 160 may include Cu. Furthermore, CMP conditions (e.g., the pressure and rotational speed of the polishing head, and the type of slurry) can be controlled to control the amount of dishing in the conductive pillar 160.

[0117] Furthermore, during CMP, the corner portion where the top surface 251 of the molding layer 250 meets the inner wall 253 is ground away, thus the corner portion 255 of the molding layer 250 (see...) Figure 2 It has a chamfered or rounded shape.

[0118] Reference Figure 9LA first upper insulating layer 411 is formed on the semiconductor chip 200 and the molding layer 250. To form the first upper insulating layer 411, an insulating material film can be formed to cover the top surface of the molding layer 250 and the top surface of the semiconductor chip 200 and fill the recesses 257 of the molding layer 250 (see...). Figure 2 Then, by exposure and development, it is partially removed, thereby forming a passage opening that exposes a portion of the top surface of the conductive pillar 160.

[0119] To form the access opening of the first upper insulating layer 411, for example, RIE or laser drilling can be performed. The access opening of the first upper insulating layer 411 can have a shape in which its horizontal width decreases toward the top surface of the conductive post 160.

[0120] After forming the first upper insulating layer 411, a first upper redistribution pattern 420 is formed. Specifically, a seed metal film is formed on the top surface of the first upper insulating layer 411, the inner wall of the first upper insulating layer 411 provided by the passage openings of the first upper insulating layer 411, and the portion of the top surface of the conductive pillar 160 exposed through the passage openings of the first upper insulating layer 411. For example, physical vapor deposition can be used to form the seed metal film. After forming the seed metal film, a plating process is performed by forming a photoresist pattern including openings and using the seed metal film as a seed to form a first upper conductive line pattern 421 and a first upper conductive passage pattern 423. Thereafter, the photoresist pattern is removed, and the portion of the seed metal film exposed by removing the photoresist pattern is removed. As a result of removing the seed crystal metal film, a first upper seed crystal layer 425 can be formed between the top surface of the first upper insulating layer 411 and the first upper conductive line pattern 421, between the first upper conductive path pattern 423 and the inner wall of the first upper insulating layer 411, and between the first upper conductive path pattern 423 and the conductive pillar 160.

[0121] After the first upper redistribution pattern 420 is formed, the second upper insulating layer 413 can be formed using steps that are substantially the same or similar to those used to form the first upper insulating layer 411, and the second upper redistribution pattern 430 can be formed using steps that are substantially the same or similar to those used to form the first upper redistribution pattern 420. The first upper insulating layer 411, the first upper redistribution pattern 420, the second upper insulating layer 413, and the second upper redistribution pattern 430 can form an upper redistribution structure 401.

[0122] Reference Figure 9MThe upper semiconductor chip 500 is attached to the upper redistribution structure 401. The upper semiconductor chip 500 can be attached to the upper redistribution structure 401 such that the chip pad 520 faces the upper redistribution structure 401. The chip pad 520 of the upper semiconductor chip 500 can be connected to the second upper conductive line pattern 431 of the second upper redistribution pattern 430 via the chip connector 530.

[0123] After attaching the upper semiconductor chip 500 to the upper redistribution structure 401, a bottom filler material layer 540 is formed to fill the space between the upper semiconductor chip 500 and the upper redistribution structure 401 and surround the chip connector 530.

[0124] After forming the bottom filler material layer 540, an upper molding layer 550 is formed to mold the upper semiconductor chip 500. The upper molding layer 550 may cover the side surface of the upper semiconductor chip 500.

[0125] Reference Figure 9N and Figure 9M After the upper molding layer 550 is formed, the carrier substrate 310 is removed. For example, the carrier substrate 310 with the release film 311 attached and Figure 9N The resulting structure is separated. For example, to separate the carrier substrate 310, a laser beam or heat can be radiated onto the release film 311.

[0126] After separating the carrier substrate 310, the cover layer 320 is removed, exposing the external electrode pads 150. For example, the cover layer 320 can be removed using an etching process.

[0127] After removing the cover layer 320, the external connector 190 can be attached. The external connector 190 may include, for example, solder balls or bumps.

[0128] Reference Figure 9O After the external connector 190 is formed, it can be fully formed by performing a singulation process. Figure 4 The semiconductor package 10b is cut along the dicing groove SL in this dicing process. Figure 9N The resulting structure.

[0129] According to the embodiment, since the top surface of the conductive post 160 is at a lower level than the top surface of the molding layer 250, the conductive post 160 can be used as an alignment mark, thus, in forming the first redistribution pattern 420 (in Figure 9L The accuracy of alignment mark recognition can be improved when the conductive post 160 is used as an alignment mark to form the first redistribution pattern 420. Since the accuracy of alignment mark recognition is improved when the conductive post 160 is used as an alignment mark to form the first redistribution pattern 420, the deterioration of the electrical characteristics of the semiconductor package due to misalignment is suppressed / prevented, and the reliability of the semiconductor package can ultimately be improved.

[0130] According to some embodiments, since the molding layer 250 has chamfered or rounded corner portions 255 (in... Figure 5 (in the middle), so it can suppress or prevent cracks from appearing near the corner portion 255 of the molding layer 250 due to stress concentration on the corner portion 255.

[0131] Figure 10 This is a cross-sectional view of a semiconductor package 10d according to an example embodiment. Figure 11 yes Figure 10 An enlarged sectional view of region XI in the diagram.

[0132] Figure 10 and Figure 11 The semiconductor package 10d shown can be compared with the reference Figure 1 and Figure 2 The semiconductor package 10 described is substantially the same as or similar to the reference package 10, except for the structure of the conductive pillars 160a. For ease of description, the description will focus on the semiconductor package 10d and the reference package 10d. Figure 1 and Figure 2 The differences between the semiconductor packages 10 are described.

[0133] Reference Figure 10 and Figure 11 The semiconductor package 10d may include a redistribution structure 101, a semiconductor chip 200, conductive pillars 160a, and a molding layer 250. The top surface 161a of the conductive pillar 160a may have a substantially convex shape. For example, the central portion 160aC of the top surface 161a of the conductive pillar 160a may be at a higher level than the edge portion 160aE of the top surface 161a of the conductive pillar 160a. The edge portion 160aE of the top surface 161a of the conductive pillar 160a may have a slope descending outward from the central portion 160aC of the top surface 161a of the conductive pillar 160a.

[0134] For example, by... Figure 9K The resulting structure is subjected to wet etching to form conductive pillars 160a. Specifically, as referred above... Figure 9K When performing CMP to expose the conductive pillars 160, a gap can be formed between the conductive pillars 160 and the molding layer 250, which have different properties. When... Figure 9K When wet etching is performed on the resulting structure, etchant can flow into the gap between the conductive pillar 160 and the molding layer 250. The edge portion of the conductive pillar 160 is etched by the etchant flowing into the gap between the conductive pillar 160 and the molding layer 250, so that the conductive pillar 160a can have such... Figure 10 and Figure 11 The shape shown is essentially a raised shape.

[0135] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

[0136] This application claims the benefit of Korean Patent Application No. 10-2019-0093355, filed on July 31, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package comprising: a semiconductor chip including chip pads; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pads of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive pillar in the molding layer, the conductive pillar having a bottom surface and a top surface, the bottom surface of the conductive pillar in contact with the lower redistribution pattern of the lower redistribution structure, and the top surface of the conductive pillar having a concave shape, wherein the conductive pillar is on an inner wall of the molding layer, a first portion of the inner wall of the molding layer in contact with the conductive pillar, a second portion of the inner wall of the molding layer exposed from the conductive pillar and extending vertically above the top surface of the conductive pillar, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other, and wherein a corner portion of the molding layer is between a top surface of the molding layer and the second portion of the inner wall of the molding layer and is beveled or rounded.

2. The semiconductor package of claim 1, wherein the top surface of the conductive pillar is at a lower level than the top surface of the molding layer.

3. The semiconductor package of claim 1, further comprising: an upper redistribution insulating layer including a first upper insulating layer and a second upper insulating layer stacked in sequence on the molding layer and the semiconductor chip; and an upper redistribution pattern including an upper conductive line pattern on a top surface of the first upper insulating layer and a first upper conductive via pattern electrically connected to the upper conductive line pattern.

4. The semiconductor package of claim 3, wherein the upper redistribution pattern further includes a plurality of second upper conductive via patterns connected to the upper conductive line pattern, and wherein each of the plurality of second upper conductive via patterns is in contact with the top surface of the conductive pillar.

5. The semiconductor package of claim 3, wherein the first upper insulating layer is on the second portion of the inner wall of the molding layer and the corner portion of the molding layer.

6. The semiconductor package of claim 1, further comprising: a connector on the top surface of the conductive pillar and on the second portion of the inner wall of the molding layer between the top surface of the molding layer and the top surface of the conductive pillar.

7. The semiconductor package of claim 6, wherein the connector is on the corner portion of the molding layer.

8. The semiconductor package of claim 1, wherein the molding layer is on a top surface of the semiconductor chip.

9. The semiconductor package of claim 1, wherein the top surface of the molding layer is coplanar with a top surface of the semiconductor chip.

10. The semiconductor package of claim 1, wherein the molding layer includes an epoxy molding compound, and the conductive pillar includes copper.

11. A semiconductor package comprising: ​ ​ a lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern; a semiconductor chip on a first surface of the lower redistribution insulating layer, the semiconductor chip electrically connected to the lower redistribution pattern; a molding layer on a side surface of the semiconductor chip; and a conductive pillar in the molding layer, the conductive pillar having a bottom surface and a top surface, the bottom surface of the conductive pillar in contact with the lower redistribution pattern of the lower redistribution structure, and the top surface of the conductive pillar at a lower level than a top surface of the molding layer, wherein the conductive pillar is on an inner wall of the molding layer, a first portion of the inner wall of the molding layer in contact with the conductive pillar, a second portion of the inner wall of the molding layer exposed from the conductive pillar and extending vertically above the top surface of the conductive pillar, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar to each other, and wherein a corner portion of the molding layer is between the top surface of the molding layer and the second portion of the inner wall of the molding layer and is chamfered or rounded.

12. The semiconductor package of claim 11, further comprising: an upper redistribution insulating layer on the top surface of the molding layer and the top surface of the conductive pillar, wherein the upper redistribution insulating layer is on the second portion of the inner wall of the molding layer and the corner portion of the molding layer.

13. The semiconductor package of claim 11, further comprising: a connector on the top surface of the conductive pillar, wherein the connector is on the second portion of the inner wall of the molding layer and the corner portion of the molding layer.

14. The semiconductor package of claim 11, wherein the inner wall of the molding layer includes a first inner wall and a second inner wall opposite the first inner wall, and wherein the conductive pillar extends continuously from the first inner wall of the molding layer to the second inner wall of the molding layer.

15. The semiconductor package of claim 11, wherein a central portion of the top surface of the conductive pillar is at a higher level than an edge portion of the top surface of the conductive pillar.

16. The semiconductor package of claim 15, wherein the edge portion of the top surface of the conductive pillar has a slope that descends outwardly from the central portion of the top surface of the conductive pillar.

17. A semiconductor package, comprising: a lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern; a lower semiconductor chip on a first surface of the lower redistribution insulating layer, the lower semiconductor chip electrically connected to the lower redistribution pattern; a conductive pillar on the first surface of the lower redistribution insulating layer, the conductive pillar electrically connected to the lower redistribution pattern and having a top surface, the top surface having a concave shape; a molding layer on a side surface of the lower semiconductor chip and a side surface of the conductive pillar, the molding layer having a top surface at a higher level than the top surface of the conductive pillar; and an upper redistribution structure on the molding layer and the lower semiconductor chip, the upper redistribution structure including an upper redistribution insulating layer on the top surface of the conductive pillar and an upper redistribution pattern penetrating a portion of the upper redistribution insulating layer and contacting the conductive pillar, wherein the conductive pillar is on an inner wall of the molding layer, a first portion of the inner wall of the molding layer contacting the conductive pillar, a second portion of the inner wall of the molding layer being exposed from the conductive pillar and extending vertically above the top surface of the conductive pillar, wherein the first portion and the second portion of the inner wall of the molding layer are vertically coplanar to each other, wherein a corner portion of the molding layer is between the top surface of the molding layer and the second portion of the inner wall of the molding layer and is chamfered or rounded.

18. The semiconductor package of claim 17, wherein the upper redistribution insulating layer is on the second portion of the inner wall of the molding layer and the corner portion of the molding layer.

19. The semiconductor package of claim 17, further comprising: an upper semiconductor chip on the upper redistribution structure, the upper semiconductor chip being electrically connected to the conductive pillar through the upper redistribution pattern.

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