Display device

Abstract

A display device is provided. The display device includes an active area, an inactive area, a plurality of inactive fan-out wirings, a plurality of signal wirings, and a plurality of connection wirings, wherein the active area includes a plurality of pixels that receive a plurality of data signals from a plurality of data lines, the plurality of pixels are arranged in a matrix form, the inactive area is adjacent to the active area in a first direction and includes a pad portion, the plurality of inactive fan-out wirings are located in the inactive area and connected to the pad portion, the plurality of signal wirings extend in the first direction, the plurality of signal wirings intersect the active area and are connected to the plurality of pixels, and the plurality of connection wirings at least partially pass through the active area and connect some of the plurality of inactive fan-out wirings to some of the plurality of signal wirings, respectively. The plurality of inactive fan-out wirings includes a plurality of first inactive fan-out wirings made of a first conductive layer and a plurality of second inactive fan-out wirings made of a second conductive layer different from the first conductive layer.

Description

TECHNICAL FIELD

[0001] Exemplary embodiments relate to a display apparatus in general. BACKGROUND

[0002] With the development of multimedia, display apparatuses are becoming more and more important. Accordingly, various types of display apparatuses, such as organic light emitting displays, liquid crystal displays, and the like, are being used. A display apparatus generally includes an active area that displays an image and a non-active area that is located outside (e.g., arranged around) the active area. Wires for transmitting signals to the active area are arranged in the non-active area. The wires can be fanned out from a pad portion and then extended toward the active area. In addition, it is generally preferred that a display apparatus have a thin bezel. However, if the area of the non-active area is reduced too much in order to achieve a thin bezel, there can be less paths through which the fanned-out wires can pass. In order to secure paths for the fanned-out wires even in a thin bezel structure, some of the fanned-out wires can pass through the active area. However, if the fanned-out wires pass through the active area, the order of a plurality of data signals can change, and thus additional mapping of a driver chip is required. In addition, a plurality of signal wires can include different conductive layers in each area, and in this case, there can be a difference in brightness between the plurality of areas due to process dispersion of each conductive layer.

[0003] The above information disclosed in this Background section is only for the understanding of the background of the present inventive concept, and thus, it can contain information that does not form the prior art. SUMMARY

[0004] Some exemplary embodiments can provide a display apparatus that includes connection wires passing through an active area, but can employ a multi-functional driver chip, and can reduce a difference in brightness between a plurality of areas due to process dispersion of conductive layers.

[0005] Additional aspects will be set forth in the detailed description to follow, and in part will be apparent from the disclosure, or can be learned by practice of the present inventive concept.

[0006] According to an example embodiment, a display device includes an active area, an inactive area, a plurality of inactive fan-out wirings, a plurality of signal wirings, and a plurality of connection wirings. The active area includes a plurality of pixels configured to receive a plurality of data signals from a plurality of data lines. The plurality of pixels are arranged in a matrix form. The inactive area is adjacent to the active area in a first direction. The inactive area includes a pad portion. The plurality of inactive fan-out wirings are located in the inactive area and connected to the pad portion. The plurality of signal wirings extend in the first direction and intersect the active area. The plurality of signal wirings are connected to the plurality of pixels. The plurality of connection wirings at least partially pass through the active area and connect some of the plurality of inactive fan-out wirings to some of the plurality of signal wirings, respectively. The plurality of inactive fan-out wirings include a plurality of first inactive fan-out wirings made of a first conductive layer and a plurality of second inactive fan-out wirings made of a second conductive layer different from the first conductive layer. The plurality of first inactive fan-out wirings and the plurality of second inactive fan-out wirings are alternately arranged along a second direction intersecting the first direction.

[0007] According to an example embodiment, a display device having an active area and an inactive area adjacent to the active area in a first direction includes a plurality of inactive fan-out wirings, a plurality of signal wirings, and a plurality of active fan-out wirings. The plurality of inactive fan-out wirings are located in the inactive area. The plurality of inactive fan-out wirings include a plurality of first inactive fan-out wirings and a plurality of second inactive fan-out wirings alternately arranged along a second direction intersecting the first direction. The plurality of signal wirings are located in the active area. The plurality of signal wirings include a plurality of first signal wirings and a plurality of second signal wirings alternately arranged along the second direction. The plurality of active fan-out wirings pass through the active area. The plurality of first inactive fan-out wirings are made of a first conductive layer. The plurality of second inactive fan-out wirings are made of a second conductive layer. The plurality of signal wirings are made of a third conductive layer. The plurality of active fan-out wirings are made of a fourth conductive layer. The first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are different conductive layers. A first portion of the plurality of first signal wirings is connected to some of the plurality of first inactive fan-out wirings through some of the plurality of active fan-out wirings to form a plurality of first external data lines. A remaining portion of the plurality of first signal wirings is connected to other of the plurality of first inactive fan-out wirings without active fan-out wirings to form a plurality of first internal data lines. A first portion of the plurality of second signal wirings is connected to some of the plurality of second inactive fan-out wirings through other of the plurality of active fan-out wirings to form a plurality of second external data lines. A remaining portion of the plurality of second signal wirings is connected to other of the plurality of second inactive fan-out wirings without active fan-out wirings to form a plurality of second internal data lines.

[0008] The foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are included to provide a further understanding of the concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the concept and together with the description serve to explain the principles of the concept. In the drawings:

[0010] Figure 1 is a plan view of a display device according to an exemplary embodiment;

[0011] Figure 2 is a side view of a display device according to an exemplary embodiment Figure 1

[0012] Figure 3 is a layout diagram showing a pixel arrangement of a display device according to an exemplary embodiment Figure 1

[0013] Figure 4 is a circuit diagram of one pixel of a display device according to an exemplary embodiment Figure 1

[0014] Figure 5 is a sectional view of one pixel of a display device according to an exemplary embodiment Figure 1

[0015] Figure 6 is a layout diagram of some wirings of a display device according to an exemplary embodiment Figure 1

[0016] Figure 7 is a layout diagram showing signal wirings constituting data lines according to an exemplary embodiment

[0017] Figure 8 is a sectional view taken along the sectional line VIII-VIII' of Figure 7

[0018] Figure 9 is a sectional view taken along the sectional line IX-IX' of Figure 7

[0019] Figure 10 is a partial layout diagram showing a pixel arrangement according to an exemplary embodiment

[0020] Figure 11 is a partial layout diagram showing a data line arrangement and a pixel arrangement of a display device according to an exemplary embodiment Figure 10

[0021] Figure 12 is a partial layout diagram showing a pixel arrangement and a data line arrangement according to an exemplary embodiment​​​​​​​​

[0022] Figure 13 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment;

[0023] Figure 14 is a schematic layout diagram illustrating a wiring arrangement of a display device according to an exemplary embodiment;

[0024] Figure 15 is a schematic layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment;

[0025] Figure 16 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment;

[0026] Figure 17 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment;

[0027] Figure 18 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment;

[0028] Figure 19 is a schematic layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment;

[0029] Figure 20 is a perspective view of a display device according to an exemplary embodiment; and

[0030] Figure 21 is a perspective view of a display device according to an exemplary embodiment; Figure 20 is an exploded view of the display device of DETAILED DESCRIPTION

[0031] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments. As used herein, the word "embodiment" and the word "implementation" are used interchangeably and are non-limiting examples of taking one or more of the inventive concepts disclosed herein. It should be apparent, however, that various exemplary embodiments can be practiced in the absence of specific details, or in substitution for one or more equivalent arrangements. In other instances, well known structures and devices are shown in block diagram form in order to avoid obscuring the various exemplary embodiments. Additionally, various exemplary embodiments can be different but not necessarily mutually exclusive. For example, a particular feature, structure, configuration, or characteristic can be used in one exemplary embodiment without being used in another exemplary embodiment.

[0032] Unless otherwise stated, the exemplary embodiments shown will be understood to provide exemplary features of different details of some exemplary embodiments. Accordingly, unless otherwise specified, various described features, components, modules, layers, films, panels, areas, aspects, etc. (hereinafter referred to as “elements”) can be combined, separated, interchanged, and / or rearranged in other manners, without departing from the inventive concept.

[0033] Cross-hatching and / or shading typically are provided in the drawings solely to illustrate the boundaries of elements, unless specified otherwise. The presence of

[0034] When an element such as a layer, region, or substrate is referred to as being “on” another element, or is “connected” or “coupled” to another element, it can be directly on the other element or directly connected or coupled to the other element, or intervening elements can be present. In contrast, when an element is referred to as being “directly on” or “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on,” etc.). In addition, the word “connected” can refer to physical or electrical and / or fluid connection. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one of the group consisting of X, Y, and Z” can be construed as any of X, Y, or Z individually, or X, Y, and Z taken in any logical combination thereof, e.g., XYZ, XYY, YZ, and ZZ.

[0035] Although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0036] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper", "over", "higher", and "side" (e.g., as in "sidewall"), can be used herein for descriptive purposes, for example, relative to the orientation as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Moreover, the device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are to be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the words "comprise", "comprising", "include", "including", and / or "contains", "containing", when used in this specification, specifically imply the existence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Also, note that as used herein, the word "substantially" is used as an intensive adjective to mean that the indicated value, calculation, and / or property is close to, but not necessarily exactly, the stated value, calculation, and / or property.

[0038] Various example embodiments are described herein with reference to cross-sectional illustrations, isometric illustrations, perspective illustrations, plan illustrations, and / or exploded illustrations that are schematic illustrations of idealized example embodiments and / or intermediate structures of example embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the example embodiments disclosed herein are not to be construed as being limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for example, manufacturing. As such, the regions illustrated in the figures can be schematic in nature and the shapes of the regions can not reflect the actual shapes of the regions of the devices, and are merely intended to be illustrative of the regions of the devices.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0040] As is conventional in the art, some of the example embodiments are illustrated in and described with reference to functional block diagrams, units, and / or modules. Those skilled in the art will recognize that the block diagrams, units, and / or modules are illustrative only and that variations in their connection, arrangement, and function can be made that are commensurate with their description herein. For example, one or more blocks, units, and / or modules can be eliminated, and / or two or more blocks, units, and / or modules can be combined. Additionally, the order in which the blocks, units, and / or modules are described is not intended to be limiting.

[0041] In the following, various example embodiments will be explained in detail with reference to the attached drawings.

[0042] Figure 1 is a plan view of a display device 1 according to an example embodiment.

[0043] Figure 1 A planar shape of the display device 1 before being bent is shown. In the drawing, a first direction DR1 indicates a longitudinal direction in a plan view, a second direction DR2 indicates a lateral direction in the plan view, and a third direction DR3 indicates a thickness direction in the plan view. Figure 2 is a display device 1 according to an exemplary embodiment Figure 1 is a side view of the display device 1. Figure 2 A side shape of the display device 1 after being bent in the thickness direction (e.g., the third direction DR3) is shown.

[0044] Referring to Figure 1 and Figure 2 , the display device 1 is a device for displaying moving images and / or still images. The display device 1 can be used as a display screen in any suitable device such as a portable electronic device (e.g., a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, and an ultra-mobile PC (UMPC)) and various other products (e.g., a television, a notebook computer, a display, a billboard, an Internet of Things (IoT) device, etc.), or the display device 1 can be used as a display screen associated with any suitable device.

[0045] The display device 1 can include a display panel 10. The display panel 10 can include a flexible substrate including a flexible polymer material such as polyimide, but exemplary embodiments are not limited thereto. Accordingly, the display panel 10 can be bent, curved, folded, curled, twisted, etc.

[0046] The display panel 10 can include an active area AAR displaying an image and a non-active area NAR not displaying an image. In a plan view, the display panel 10 can be divided into the active area AAR and the non-active area NAR. The non-active area NAR can surround the active area AAR.

[0047] The active area AAR can include a plurality of pixels PX (e.g., Figure 3 in the plurality of pixels PX1 to PX3). The pixels PX can be arranged in a matrix, like a pentile arrangement. Although not shown, each of the plurality of pixels PX can include a light emitting layer and a circuit layer controlling an amount of light emitted from the light emitting layer. The circuit layer can include a wiring, an electrode, and at least one transistor. The light emitting layer can include an organic light emitting material. The light emitting layer can be sealed by an encapsulation layer. An exemplary configuration of each pixel PX will be described later.

[0048] The display panel 10 can include a main area MR and a bending area BR connected to a first side of the main area MR in a first direction DR1. The display panel 10 can further include a sub area SR connected to the bending area BR on the first side in the first direction DR1 and bent in a thickness direction to overlap the main area MR in the thickness direction (e.g., a third direction DR3).

[0049] The main area MR can include an active area AAR. A non-active area NAR can be located in an edge portion surrounding the active area AAR of the main area MR.

[0050] The main area MR can have a shape similar to a planar shape of the display device 1. The main area MR can be a flat area located in one plane. However, the exemplary embodiments are not limited to this case, and at least one of a plurality of edges of the main area MR other than an edge (or side) connected to the bending area BR can also be curved or can be vertically bent.

[0051] If at least one of a plurality of edges of the main area MR other than an edge (or side) connected to the bending area BR is curved or bent, the active area AAR can also be disposed at the curved or bent edge. However, the exemplary embodiments are not limited to this case, and the curved or bent edge can also be a non-active area NAR that does not display an image, or can include a combination of the active area AAR and the non-active area NAR.

[0052] The non-active area NAR of the main area MR can extend from an outer boundary of the active area AAR to an edge of the display panel 10. A signal wiring and / or a driving circuit for transmitting a signal to the active area AAR can be disposed in the non-active area NAR of the main area MR.

[0053] The bending area BR can be connected to a short side of the main area MR. A width of the bending area BR (in the second direction DR2) can be smaller than a width of the main area MR, e.g., a width of the short side of the main area MR. A connection portion of the main area MR and the bending area BR can have an L-shaped notch shape to reduce a width of a bezel.

[0054] In the bending area BR, the display panel 10 can be bent with a certain curvature in a direction opposite to a display surface (e.g., in the third direction DR3). As the display panel 10 is bent in the bending area BR, a surface of the display panel 10 can be reversed. That is, an upward surface of the display panel 10 can be changed to laterally outward, and then downward, by the bending area BR.

[0055] The sub-area SR extends from the bending area BR. After the bending is completed, the sub-area SR can extend in parallel with the main area MR. The sub-area SR can overlap the main area MR in the thickness direction (e.g., the third direction DR3) of the display panel 10. The sub-area SR can overlap the non-active area NAR at the edge of the main area MR, and can also overlap the active area AAR of the main area MR. The width of the sub-area SR can be equal to the width of the bending area BR, but is not necessarily so.

[0056] The pad portion PDR (see Figure 6 ) can be arranged in the sub-area SR of the display panel 10. An external device can be mounted (e.g., attached) on the pad portion PDR. Examples of the external device include the driver chip 20 and a driving board made of a flexible printed circuit board or a rigid printed circuit board. In addition, a wiring connection film, a connector, or the like can be mounted as the external device on the pad portion PDR. Only one external device or a plurality of external devices can be mounted in the sub-area SR. For example, as shown in Figure 1 and Figure 2 , the driver chip 20 can be arranged in the sub-area SR of the display panel 10, and the driving board 30 can be attached to the end portion of the sub-area SR. In this case, the display panel 10 can include both a pad portion connected to the driver chip 20 and a pad portion connected to the driving board 30. In an exemplary embodiment, the driver chip 20 can be mounted on a film, and the film can be attached to the sub-area SR of the display panel 10.

[0057] The driver chip 20 can be mounted on the surface of the display panel 10, which is the same surface as the display surface (or the same side of the display panel 10 as the display surface). As described above, when the surface of the display panel 10 is reversed by the bending of the bending area BR, the upper surface of the driver chip 20 mounted on the surface of the display panel 10 can face downward, while the surface of the display panel 10 faces downward in the thickness direction.

[0058] The driver chip 20 can be attached to the display panel 10 by an anisotropic conductive film, or can be attached to the display panel 10 by ultrasonic bonding. The lateral width of the driver chip 20 can be smaller than the lateral width of the display panel 10. The driver chip 20 can be arranged in the center portion of the sub-area SR in the lateral direction (e.g., the second direction DR2), and the left and right edges of the driver chip 20 can be spaced apart from the left and right edges of the sub-area SR, respectively.

[0059] The driver chip 20 can include an integrated circuit for driving the display panel 10. In an exemplary embodiment, the integrated circuit can be a data driver integrated circuit that generates and provides a data signal. The driver chip 20 is connected to a wiring pad WR_PD (see Figure 6), and provides a data signal to a wiring pad WR_PD. A wiring WR (see Figure 6 ) extends toward the pixel PX, and transmits the data signal to the pixel PX.

[0060] Figure 3 is a layout view illustrating a pixel arrangement of the display device 1 according to an exemplary embodiment. Figure 1

[0061] Referring to Figure 3 , the plurality of pixels PX includes first color pixels PX1, second color pixels PX2, and third color pixels PX3. In an exemplary embodiment, the first color pixels PX1 can be red pixels, the second color pixels PX2 can be blue pixels, and the third color pixels PX3 can be green pixels. The plurality of pixels PX can be alternately arranged in a matrix form, for example, a pentile form.

[0062] Each of the plurality of pixels PX can include a light emitting area EMA and a non-light emitting area NEA surrounding the light emitting area EMA. The light emitting area EMA can have different sizes in at least one of the first color pixels PX1, the second color pixels PX2, and the third color pixels PX3, such as in each of the first color pixels PX1, the second color pixels PX2, and the third color pixels PX3. For example, the light emitting area EMA of each second color pixel PX2 can be larger than the light emitting area EMA of each first color pixel PX1, and the light emitting area EMA of each third color pixel PX3 can be smaller than the light emitting area EMA of each first color pixel PX1. The light emitting area EMA of each pixel PX can have a substantially octagonal shape; however, the light emitting area EMA of each pixel PX is not limited to the octagonal shape, and can have various shapes, such as a hexagonal shape, a circular shape, a diamond shape, or other polygonal shapes or polygonal shapes with rounded corners.

[0063] In some pixel columns (hereinafter referred to as first pixel columns PXC1), a plurality of first color pixels PX1 and a plurality of second color pixels PX2 are alternately arranged along a first direction DR1 (e.g., a column direction). In other pixel columns (hereinafter referred to as second pixel columns PXC2), a plurality of third color pixels PX3 are repeatedly arranged. The plurality of first pixel columns PXC1 and the plurality of second pixel columns PXC2 are alternately arranged along a second direction DR2 (e.g., a row direction). For example, odd pixel columns can be the first pixel columns PXC1, and even pixel columns can be the second pixel columns PXC2.

[0064] ​The plurality of light emitting areas EMA belonging to one pixel column can be substantially aligned along the first direction DR1. The light emitting areas EMA in one pixel column can be staggered with respect to the light emitting areas EMA in an adjacent pixel column. For example, the first color pixels PX1 and the second color pixels PX2 in each first pixel column PXC1 can be aligned along the second direction DR2 with a space between adjacent third color pixels PX3 in an adjacent second pixel column PXC2, and the third color pixels PX3 in each second pixel column PXC2 can be aligned along the second direction DR2 with a space between adjacent first color pixels PX1 and second color pixels PX2 in an adjacent first pixel column PXC1.

[0065] In the pixel rows, the first color pixels PX1 and the second color pixels PX2 are alternately arranged with the third color pixels PX3 intervening therebetween. In each first pixel row PXR1, the first color pixels PX1, the third color pixels PX3, the second color pixels PX2, and the third color pixels PX3 can be repeatedly arranged in this order. In each second pixel row PXR2, the second color pixels PX2, the third color pixels PX3, the first color pixels PX1, and the third color pixels PX3 can be repeatedly arranged in this order. The first pixel rows PXR1 and the second pixel rows PXR2 are alternately arranged along the first direction DR1. For example, the odd pixel rows can be the first pixel rows PXR1, and the even pixel rows can be the second pixel rows PXR2. In one pixel row, the light emitting areas EMA of the first color pixels PX1 and the second color pixels PX2 can be relatively positioned at the second side in the first direction DR1 compared to the light emitting areas EMA of the third color pixels PX3. That is, the respective light emitting areas EMA of the plurality of pixels PX in each pixel row can be arranged in a zigzag shape along the second direction DR2.

[0066] The pixels PX belonging to the same column can receive a data signal from the same data line, and the pixels PX belonging to the same row can receive a gate signal from the same gate line. Each pixel PX can be driven by a pixel circuit. The pixel circuit can include a plurality of transistors and at least one capacitor. In Figure 4 A circuit diagram of an exemplary pixel circuit is shown in

[0067] Figure 4 A circuit diagram of one pixel PX of a display apparatus according to an exemplary embodiment.

[0068] Referring to Figure 4 , the pixel circuit can include a first transistor TR1, a second transistor TR2, a capacitor Cst, and an organic light emitting diode OLED. Each pixel circuit is connected to a scan (or gate) line SL, a data line DL, and a first power voltage line ELVDDL.

[0069] The first transistor TR1 can be a driving transistor, and the second transistor TR2 can be a switching transistor. Although both the first transistor TR1 and the second transistor TR2 are p-channel metal-oxide-semiconductor (PMOS) transistors in the accompanying drawings, either or both of the first transistor TR1 and the second transistor TR2 can also be n-channel metal-oxide-semiconductor (NMOS) transistors.

[0070] The first electrode (e.g., source electrode) of the first transistor TR1 is connected to the first power supply voltage line ELVDDL, and the second electrode (e.g., drain electrode) of the first transistor TR1 is connected to the pixel electrode (e.g., anode) of the organic light-emitting diode (OLED). The first electrode (e.g., source electrode) of the second transistor TR2 is connected to the data line DL, and the second electrode (e.g., drain electrode) of the second transistor TR2 is connected to the gate electrode of the first transistor TR1. A capacitor Cst is connected between the gate electrode and the first electrode of the first transistor TR1. The common electrode (e.g., cathode) of the organic light-emitting diode (OLED) receives a second power supply voltage ELVSS. The second power supply voltage ELVSS may be lower than the first power supply voltage ELVDD provided by the first power supply voltage line ELVDDL.

[0071] The second transistor TR2 can output a data signal transmitted to the data line DL in response to a scan signal transmitted to the scan line SL. The capacitor Cst can be charged with a voltage corresponding to the data signal received from the second transistor TR2. The first transistor TR1 can control the driving current flowing through the organic light-emitting diode (OLED) according to the amount of charge stored in the capacitor Cst.

[0072] Figure 4 The equivalent circuit is only one example, and the pixel circuit may also include a greater number (e.g., seven) of transistors and capacitors.

[0073] Figure 5 According to an exemplary implementation Figure 1 A cross-sectional view of a pixel PX of the display device 1. Figure 5 In the example, it is shown in the form of a thin-film transistor. Figure 4 The first transistor is TR1, and the second transistor is TR2, which is not shown. Reference will now be made to... Figure 5 The cross-sectional structure of pixel PX is described in detail.

[0074] The display panel 10 can include a substrate 100, a buffer layer 105, a semiconductor layer 110, a first insulating layer 121, a first gate conductive layer 130, a second insulating layer 122, a second gate conductive layer 140, a third insulating layer 123, a first data conductive layer 150, a fourth insulating layer 124, a second data conductive layer 160, a fifth insulating layer 125, a pixel electrode 170, a pixel defining layer 126 including an opening exposing the pixel electrode 170, an organic layer 190 disposed in the opening of the pixel defining layer 126, and a common electrode 180 disposed on the organic layer 190 and the pixel defining layer 126. Each of the above-described multiple layers can be individually a single layer or a stacked multiple layer. At least one other layer can also be disposed between any two of the above-described multiple layers.

[0075] The substrate 100 supports each layer disposed on the substrate 100. The substrate 100 can be made of an insulating material such as a polymer resin. The polymer material can be, for example, at least one of polyether sulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), and cellulose acetate propionate (CAP), or a combination of these materials. The substrate 100 can be a flexible substrate that can be bent, folded, stretched, curled, twisted, etc. The material forming the flexible substrate can be polyimide (PI), but is not limited thereto.

[0076] The buffer layer 105 is disposed on the substrate 100. The buffer layer 105 can prevent (or mitigate) diffusion of impurity ions, prevent penetration of moisture or external air, and perform a function of surface planarization. The buffer layer 105 can include at least one of silicon nitride, silicon oxide, and silicon oxynitride. The buffer layer 105 can be omitted depending on the type of the substrate 100 or process conditions.

[0077] The semiconductor layer 110 is disposed on the buffer layer 105. The semiconductor layer 110 forms a channel of a thin film transistor of the pixel PX. The semiconductor layer 110 can include polysilicon. However, the material of the semiconductor layer 110 is not limited to polysilicon, and the semiconductor layer 110 can include single crystalline silicon, low-temperature polysilicon, amorphous silicon, or an oxide semiconductor. Examples of the oxide semiconductor can include binary compounds (AB x ), ternary compounds (AB x C y ), and quaternary compounds (AB x C y D z ) including at least one of, for example, indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), and magnesium (Mg).

[0078] The first insulating layer 121 can be a gate insulating layer having a gate insulating function. The first insulating layer 121 can include a silicon compound or a metal oxide, etc. For example, the first insulating layer 121 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide, or the like. These materials can be used alone or in combination with each other. The first insulating layer 121 can be a single layer or a multi-layer structure composed of a stack of different materials.

[0079] The first insulating layer 121 is disposed on the semiconductor layer 110. The first insulating layer 121 can be disposed substantially over the entire surface of the substrate 100.

[0080] The first gate conductive layer 130 is disposed on the first insulating layer 121. The first gate conductive layer 130 can include a gate electrode 131 of a thin film transistor of the pixel PX, a scan line SL connected to the gate electrode 131, and a first storage capacitor electrode 132. A second non-active fan-out wiring NFW_2 (see FIG. 2) of the non-active area NAR can also be made of the first gate conductive layer 130. Figure 8 ) also can be made of the first gate conductive layer 130.

[0081] The first gate conductive layer 130 can include one or more metals, such as at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first gate conductive layer 130 can be a single layer or a multi-layer structure.

[0082] The second insulating layer 122 can be disposed on the first gate conductive layer 130. The second insulating layer 122 can be an interlayer insulating layer or a second gate insulating layer. The second insulating layer 122 can include an inorganic insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide.

[0083] The second gate conductive layer 140 is disposed on the second insulating layer 122. The second gate conductive layer 140 can include a second storage capacitor electrode. A first non-active fan-out wiring NFW_1 (see FIG. 2) of the non-active area NAR can also be made of the second gate conductive layer 140. Figure 8) can also be made of the second gate conductive layer 140. The second gate conductive layer 140 can include one or more metals such as at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second gate conductive layer 140 can be made of the same material as the first gate conductive layer 130, but is not limited thereto. The second gate conductive layer 140 can be a single layer or a multi-layer structure.

[0084] The third insulating layer 123 is disposed on the second gate conductive layer 140. The third insulating layer 123 can be an interlayer insulating layer. The third insulating layer 123 can include an inorganic insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide or an organic insulating material such as at least one of polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB). The third insulating layer 123 can be a single layer or a multi-layer structure composed of a stack of different materials.

[0085] The first data conductive layer 150 is disposed on the third insulating layer 123. The first data conductive layer 150 can be a first source / drain conductive layer. The first data conductive layer 150 can include a first electrode 151 and a second electrode 152 of a thin film transistor of the pixel PX. A plurality of signal wirings SW1 and SW2 (see FIG. 1) can also be made of the first data conductive layer 150. Figure 8 The first data conductive layer 150 can include one or more metals such as at least one of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first data conductive layer 150 can be a single layer or a multi-layer structure. For example, the first data conductive layer 150 can have a stack structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0086] The first data conductive layer 150 can include one or more metals such as at least one of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first data conductive layer 150 can be a single layer or a multi-layer structure. For example, the first data conductive layer 150 can have a stack structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0087] A fourth insulating layer 124 is disposed on the first data conductive layer 150. The fourth insulating layer 124 covers the first data conductive layer 150. The fourth insulating layer 124 can be an interlayer insulating layer or a via layer. The fourth insulating layer 124 can include an organic insulating material such as at least one of polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0088] A second data conductive layer 160 is disposed on the fourth insulating layer 124. The second data conductive layer 160 can be a second source / drain conductive layer. The second data conductive layer 160 can include a connection electrode 161 of the pixel PX. A connection wiring CNW (see Figure 8 ) can also be made of the second data conductive layer 160. The connection electrode 161 can be electrically connected to the second electrode 152 of the thin film transistor of the pixel PX through a contact hole penetrating the fourth insulating layer 124.

[0089] The second data conductive layer 160 can include one or more metals such as at least one of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second data conductive layer 160 can be a single layer or a multi-layer structure. The second data conductive layer 160 can be made of the same material as the first data conductive layer 150, but is not limited thereto.

[0090] A fifth insulating layer 125 is disposed on the second data conductive layer 160. The fifth insulating layer 125 covers the second data conductive layer 160. The fifth insulating layer 125 can be a via layer. The fifth insulating layer 125 can include the same material as the fourth insulating layer 124 described above, or can include one or more materials selected from a plurality of materials exemplified as the material of the fourth insulating layer 124.

[0091] A pixel electrode 170 is disposed on the fifth insulating layer 125. The pixel electrode 170 can be an anode of a light emitting element (for example, an organic light emitting diode OLED (see Figure 4 )). The pixel electrode 170 can be electrically connected to the connection electrode 161 made of the second data conductive layer 160 through a contact hole penetrating the fifth insulating layer 125, and can be connected to the second electrode 152 of the thin film transistor through the connection electrode 161. The pixel electrode 170 can at least partially overlap with the emission area EMA of the pixel PX.

[0092] The pixel electrode 170 can have a stacked structure in which a material layer having a high work function such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture of at least two of them are stacked, but is not limited thereto. The material layer having a high work function can be disposed on the reflective material layer so as to be closer to the organic layer 190 than the reflective material. The pixel electrode 170 can have a multilayer structure of ITO / Mg, ITO / MgF2, ITO / Ag, or ITO / Ag / ITO, but is not limited thereto.

[0093] The pixel-defining layer 126 can be disposed on the pixel electrode 170. The pixel-defining layer 126 can at least partially overlap the non-emitting area NEA of the pixel PX. The pixel-defining layer 126 can include an opening exposing at least a portion of the pixel electrode 170. The pixel-defining layer 126 can include an inorganic insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide or an organic insulating material such as at least one of polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB). The pixel-defining layer 126 can be a single layer or a multilayer structure composed of a stack of different materials.

[0094] The light-emitting layer is disposed in the opening of the pixel-defining layer 126. The light-emitting layer can be made of an inorganic material or an organic material. In an exemplary embodiment, the light-emitting layer can include the organic layer 190. The organic layer 190 can include an organic light-emitting layer, a hole injection / transport layer, and an electron injection / transport layer. The organic layer 190 can overlap the emitting area EMA.

[0095] The common electrode 180 is disposed on the organic layer 190 and the pixel-defining layer 126. The common electrode 180 can be a light-emitting element (e.g., an organic light-emitting diode OLED (see FIG. 1B)) such as an anode electrode or a cathode electrode, but is not limited thereto. The common electrode 180 can be disposed on the pixel-defining layer 126 to be in contact with the organic layer 190. Figure 4The common electrode 180 can be disposed not only in the light-emitting region EMA of the pixel PX but also in the non-light-emitting region NEA of the pixel PX. For example, the common electrode 180 can be disposed on the entire surface of each pixel PX. The common electrode 180 can include a layer of a material having a small (or low) work function, such as at least one of Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, and Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). The common electrode 180 can further include a layer of a transparent metal oxide disposed on the layer of the material having a small work function.

[0096] Although not shown, an encapsulation layer can be disposed on the common electrode 180. The encapsulation layer can include an inorganic layer. In an exemplary embodiment, the encapsulation layer can include a first inorganic layer, an organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the organic layer.

[0097] Figure 6 is a layout diagram of some wirings of the display device 1 according to an exemplary embodiment. Figure 1

[0098] Referring to FIG. 1, Figure 6 A width of a row of the plurality of wiring pads WR_PD of the pad portion PDR in the second direction DR2 can be less than a width of the active region AAR in the second direction DR2. To cover more of the active region AAR, the plurality of wirings WR can fan out from the plurality of wiring pads WR_PD toward the active region AAR. It can be desirable to arrange the plurality of wirings WR in the non-active region NAR adjacent to the active region AAR so that the plurality of wirings WR cover the entire active region AAR. However, if the bezel of the display device 1 is reduced, there can be insufficient space for the plurality of wirings WR to fan out. The space for the plurality of wirings WR can be further reduced if the display device 1 has an L-shaped cutout shape or if other wirings are disposed at the corners and thus the plurality of wirings WR cannot pass through the corners. As a result, the width of the plurality of wirings WR extending from the pad portion PDR arranged in the non-active region NAR adjacent to the active region AAR in the second direction DR2 can be less than the width of the active region AAR.

[0099] ​The active area AAR can be divided into an inner active area AAR_I and outer active areas AAR_L (AAR_L1 and AAR_L2) according to the relative relationship of the area in which the plurality of wirings WR are arranged in the non-active area NAR adjacent to the active area AAR from the pad portion PDR. The inner active area AAR_I can be defined as an active area which overlaps the plurality of wirings WR when the plurality of wirings WR extend in the first direction DR1 toward the second side, while the plurality of wirings WR extend from the pad portion PDR of the non-active area NAR adjacent to the active area AAR. The outer active area AAR_L can be defined as an active area which does not overlap the plurality of wirings WR when the plurality of wirings WR extend in the first direction DR1 toward the second side, while the plurality of wirings WR extend from the pad portion PDR of the non-active area NAR adjacent to the active area AAR. In the drawing, the inner active area AAR_I is located in a central portion of the active area AAR, the first outer active area AAR_L1 is located at a first side of the inner active area AAR_I in the second direction DR2, and the second outer active area AAR_L2 is located at a second side of the inner active area AAR_I in the second direction DR2. However, the exemplary embodiments are not limited to this case, and the number, position, etc. of the inner active area AAR_I and the outer active area AAR_L can be variously changed according to the position of the row of the plurality of wiring pads WR_PD of the pad portion PDR.

[0100] In the inner active area AAR_I, each wiring WR can extend in the first direction DR1 from the non-active area NAR (e.g., inner non-active area NAR) adjacent to the inner active area AAR_I. Thus, each wiring WR can be arranged adjacent to the pixel PX in the corresponding area, and can transmit a signal to the pixel PX. On the other hand, each wiring WR can extend from the inner non-active area NAR outward (e.g., toward the first side or the second side in the second direction DR2) to a position in the outer active area AAR_L through a bypass wiring WR_CN, and then extend in the first direction DR1 from the position. Thus, each wiring WR can be arranged adjacent to the pixel PX in the corresponding area, and can transmit a signal to the pixel PX. The bypass wiring WR_CN can extend through the inner active area AAR_I to the non-active area NAR (e.g., outer non-active area NAR) adjacent to the outer active area AAR_L. Since other wirings WR are arranged in the active area AAR through which the bypass wiring WR_CN extends, the bypass wiring WR_CN can be made of a conductive layer located in a different layer from the wirings WR of the active area AAR to avoid short-circuiting with the wirings WR.

[0101] Figure 7 FIG. 1 is a layout diagram illustrating a signal wiring constituting a data line according to an exemplary embodiment. Figure 8 FIG. 2 is a layout diagram according to an exemplary embodiment along Figure 7a cross-sectional view taken along the cross-sectional line VIII-VIII' of FIG. 8. Figure 9 is along Figure 7 a cross-sectional view taken along the cross-sectional line IX-IX' of FIG. 9.

[0102] Referring to Figures 7 to 9 , the plurality of data lines DL include a plurality of first data lines DL1 providing a plurality of first data signals to a plurality of pixels PX belonging to a plurality of first pixel columns PXC1 and a plurality of second data lines DL2 providing a plurality of second data signals to a plurality of pixels PX belonging to a plurality of second pixel columns PXC2. The plurality of first data lines DL1 and the plurality of second data lines DL2 can connect the pad portion PDR and the plurality of pixels PX of the active area AAR by using a number of conductive layers. The plurality of first data lines DL1 and the plurality of second data lines DL2 can be arranged in alternation one by one over the entire active area AAR along the second direction DR2.

[0103] The first data lines DL1 and the second data lines DL2 can be divided into internal data lines and external data lines. The internal data lines can be data lines for providing data signals to pixels PX located in the internal active area AAR_I, and the external data lines can be data lines for providing data signals to pixels PX located in the external active area AAR_L.

[0104] The data lines can include first and second non-active fan-out wirings NFW_1 and NFW_2 and first and second signal wirings SW1 and SW2. The first and second non-active fan-out wirings NFW_1 and NFW_2 can be disposed in the internal non-active area NAR, and the first and second signal wirings SW1 and SW2 can extend from the internal non-active area NAR to intersect the active area AAR.

[0105] The first data lines DL1 corresponding to the internal data lines can include the first and second non-active fan-out wirings NFW_1 and NFW_2 and the first and second signal wirings SW1 and SW2. The second data lines DL2 corresponding to the internal data lines can include the first and second non-active fan-out wirings NFW_1 and NFW_2 and the first and second signal wirings SW1 and SW2.

[0106] The first and second non-active fan-out wirings NFW_1 and NFW_2 and the first and second signal wirings SW1 and SW2 of the internal data lines can be connected to each other in an internal wiring contact CNI located in the non-active area NAR adjacent to the internal active area AAR_I. The first and second non-active fan-out wirings NFW_1 and NFW_2 and the first and second signal wirings SW1 and SW2 of the internal data lines can be directly contacted to each other in the internal wiring contact CNI.

[0107] The external data line can include, in addition to the first and second non-active fanout wires NFW_1 and NFW_2 and the first and second signal wires SW1 and SW2, a connection wire CNW (see, for example, WR_CN in FIG. 1). Figure 6 The first and second non-active fanout wires NFW_1 and NFW_2 can be disposed in the internal non-active region NAR, and the first and second signal wires SW1 and SW2 and the connection wire CNW can extend from the internal non-active region NAR to intersect the active region AAR.

[0108] The first data line DL1 corresponding to the external data line can include the first non-active fanout wire NFW_1, the connection wire CNW, and the first signal wire SW1. The second data line DL2 corresponding to the external data line can include the second non-active fanout wire NFW_2, the connection wire CNW, and the second signal wire SW2. The connection wire CNW can be an active fanout wire passing through the active region AAR.

[0109] The connection wire CNW of the external data line and the first and second non-active fanout wires NFW_1 and NFW_2 can be connected to each other in an internal wire contact CNI located in the internal non-active region NAR. The first and second non-active fanout wires NFW_1 and NFW_2 and the connection wire CNW can be in direct contact with each other in the internal wire contact CNI. The connection wire CNW and the first and second signal wires SW1 and SW2 can be connected to each other in a plurality of external wire contacts located in the non-active region NAR adjacent to the external active region AAR_L. In the plurality of external wire contacts, the connection wire CNW and the first and second signal wires SW1 and SW2 can be connected by a contact electrode CNE. However, exemplary embodiments are not limited to this case, and the connection wire CNW and the first and second signal wires SW1 and SW2 can also be in direct contact with each other without the contact electrode CNE. In this case, in each external wire contact, at least one of the connection wire CNW, the first and second signal wires SW1 and SW2 can further include a structure corresponding to the shape of the contact electrode CNE (for example, a portion in which the wire extends in the second direction DR2).

[0110] The above-mentioned internal data lines are data lines in which the first non-active fanout wiring NFW_1 and the second non-active fanout wiring NFW_2 and the first signal wiring SW1 and the second signal wiring SW2 are directly connected to each other without the connection wiring CNW intersecting the active region AAR. Thus, the internal data lines can be referred to as directly connected data lines, straight data lines, or direct data lines. On the other hand, the external data lines are data lines in which the first non-active fanout wiring NFW_1 and the second non-active fanout wiring NFW_2 and the first signal wiring SW1 and the second signal wiring SW2 are connected by the connection wiring CNW. Thus, the external data lines can be referred to as indirectly connected data lines, roundabout data lines, or indirect data lines.

[0111] The first non-active fanout wiring NFW_1 and the second non-active fanout wiring NFW_2, the first signal wiring SW1 and the second signal wiring SW2, and the connection wiring CNW can be made of a plurality of conductive layers located in different layers. In an exemplary embodiment, the first non-active fanout wiring NFW_1 and the second non-active fanout wiring NFW_2 can be made of the first gate conductive layer 130 and the second gate conductive layer 140, and the first signal wiring SW1 and the second signal wiring SW2 and the connection wiring CNW can be made of different first data conductive layer 150 and second data conductive layer 160.

[0112] For example, the first non-active fanout wiring NFW_1 belonging to the first data line DL1 can be made of the second gate conductive layer 140, regardless of whether they are internal data lines or external data lines, and the second non-active fanout wiring NFW_2 belonging to the second data line DL2 can be made of the first gate conductive layer 130, regardless of whether they are internal data lines or external data lines. However, exemplary embodiments are not limited to this case, and the first non-active fanout wiring NFW_1 can also be made of the first gate conductive layer 130, and the second non-active fanout wiring NFW_2 can also be made of the second gate conductive layer 140.

[0113] The first signal wiring SW1 and the second signal wiring SW2 can all be made of the first data conductive layer 150, regardless of whether they are internal data lines or external data lines, and the connection wiring CNW can be made of the second data conductive layer 160, or vice versa.

[0114] The contact electrode CNE can be made of a conductive layer arranged in a layer different from the connection wiring CNW and the first signal wiring SW1 and the second signal wiring SW2. For example, as shown in the figure, the contact electrode CNE can be made of the second gate conductive layer 140, but can also be made of the first gate conductive layer 130.

[0115] The first non-active fan-out wire NFW_1 and the second non-active fan-out wire NFW_2 can be connected to the wire pad WR_PD, and can extend to different conductive layers in the middle to the wire pad WR_PD. For example, the first non-active fan-out wire NFW_1 and the second non-active fan-out wire NFW_2 can pass through the bend region BR by using the first data conductive layer 150 or the second data conductive layer 160, and then extend in the sub-region SR by using the first gate conductive layer 130 or the second gate conductive layer 140. The wire pad WR_PD can include the first gate conductive layer 130 and the second gate conductive layer 140, and the first data conductive layer 150 and the second data conductive layer 160 connected to the first gate conductive layer 130 and the second gate conductive layer 140 by contacts. When different conductive layers are connected to each other, a contact hole for connecting different conductive layers can be formed in the part where different conductive layers are connected.

[0116] Figure 10 is a partial layout diagram illustrating a pixel arrangement according to an exemplary embodiment. Figure 11 is a partial layout diagram illustrating a pixel arrangement according to an exemplary embodiment. Figure 10 is a partial layout diagram illustrating a data line arrangement and a pixel arrangement according to an exemplary embodiment. In Figure 10 and Figure 11 , each pixel PX is illustrated in a rectangle for convenience of description. Figure 10 and Figure 11 conceptually illustrates a space covered by each pixel PX, regardless of the shape of the light emitting area EMA of the pixel PX. The same description can be applied not only to the case where the light emitting area EMA of the pixel PX is actually a rectangle, but also to the case where the light emitting area EMA of the pixel PX is staggered as illustrated in Figure 3 .

[0117] Referring to Figure 10 and Figure 11 , the first signal wire SW1 and the second signal wire SW2 can extend along a plurality of boundaries (or intervals between pixels PX) of a plurality of pixels PX. Here, the boundary of each pixel PX is an edge portion of a space occupied by the pixel PX, and can indicate a space outside the light emitting area EMA of the pixel PX. In the following exemplary embodiments, a case where the first signal wire SW1 and the second signal wire SW2 are arranged at a plurality of boundaries of a plurality of pixels PX will be described. However, the first signal wire SW1 and the second signal wire SW2 can also be arranged to partially overlap a plurality of light emitting areas EMA of a plurality of pixels PX. When the display device 1 is a top emission display device, even if the first signal wire SW1 and the second signal wire SW2 overlap the plurality of light emitting areas EMA across the plurality of pixels PX, they can not affect the brightness of the emitted light.

[0118] The first signal wirings SW1 providing the first data signal to the first pixel columns PXC1 in the active area AAR can be arranged adjacent to the first side of the first pixel columns PXC1 in the second direction DR2, and the second signal wirings SW2 providing the second data signal to the second pixel columns PXC2 can be arranged adjacent to the second side of the second pixel columns PXC2 in the second direction DR2. The first signal wirings SW1 and the second signal wirings SW2 can form a pair, and the pair of the first signal wirings SW1 and the second signal wirings SW2 can be arranged every other pixel column PX.

[0119] The plurality of pixel column spaces can include a plurality of first pixel column spaces PXT_C#12, PXT_C#34, PXT_C#56, and PXT_C#78 in which the first signal wirings SW1 and the second signal wirings SW2 extend in parallel to each other and a plurality of second pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67 in which the first signal wirings SW1 and the second signal wirings SW2 are not arranged. The plurality of first pixel column spaces PXT_C#12, PXT_C#34, PXT_C#56, and PXT_C#78 and the plurality of second pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67 can be alternately arranged along the second direction DR2. For example, the first signal wirings SW1 and the second signal wirings SW2 are arranged in parallel to each other in spaces (e.g., the plurality of first pixel column spaces PXT_C#12, PXT_C#34, PXT_C#56, and PXT_C#78) between the first pixel columns PXC1 and the second pixel columns PXC2 arranged at the first side of the first pixel columns PXC1 in the second direction DR2. The first signal wirings SW1 and the second signal wirings SW2 are not arranged in spaces (e.g., the plurality of second pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67) between the second pixel columns PXC2 and the first pixel columns PXC1 arranged at the first side of the second pixel columns PXC2 in the second direction DR2. A portion of each connection wiring CNW can be arranged in at least a portion of the second pixel column spaces PXT_C#23, PXT_C#45, or PXT_C#67.

[0120] The connection wirings CNW can be arranged in the active area AAR along the boundaries of the pixels PX. The connection wirings CNW can include a meander structure. Each of the plurality of connection wirings CNW can include a first extension CNW_1 and a third extension CNW_3 extending in the first direction DR1 and a second extension CNW_2 extending in the second direction DR2.

[0121] The first extension CNW_1 can extend from the inner non-active region NAR toward the inner active region AAR_I (e.g., toward the second side in the first direction DR1). A first end of the first extension CNW_1 can be located in the inner non-active region NAR, and a second end of the first extension CNW_1 can be located in the inner active region AAR_I. The first end of the first extension CNW_1 can be connected to the non-active fan-out wiring in the inner wiring contact CNI.

[0122] The second extension CNW_2 can be connected to the first extension CNW_1, and can extend toward the second side (or the first side) in the second direction DR2. The second extension CNW_2 can extend from the inner active region AAR_I toward the outer active region AAR_L. A first end of the second extension CNW_2 can be located in the inner active region AAR_I, and a second end of the second extension CNW_2 can be located in the outer active region AAR_L.

[0123] The first end of the second extension CNW_2 can be connected to the second end of the first extension CNW_1. The first bend of each connection wiring CNW can be located at the first end of the second extension CNW_2 and / or the second end of the first extension CNW_1. The entirety of the second extension CNW_2 can be arranged in the active region AAR.

[0124] The third extension CNW_3 can be connected to the second extension CNW_2, and can extend from the outer active region AAR_L toward the outer non-active region NAR (e.g., the first side in the first direction DR1). A first end of the third extension CNW_3 can be located in the outer active region AAR_L, and a second end of the third extension CNW_3 can be located in the outer non-active region NAR. The first end of the third extension CNW_3 can be connected to the second end of the second extension CNW_2. The second bend of each connection wiring CNW can be arranged at the first end of the third extension CNW_3 and / or the second end of the second extension CNW_2. The second end of the third extension CNW_3 can be connected to the contact electrode CNE and / or the first signal wiring SW1 or the second signal wiring SW2 connected with the contact electrode CNE in the outer wiring contact.

[0125] The first extension CNW_1 and the third extension CNW_3 of the connection wiring CNW can be arranged in the plurality of second pixel column space PXT_C#23, PXT_C#45, and PXT_C#67 in the active region AAR. The second extension CNW_2 of the connection wiring CNW can be arranged in the plurality of pixel row space in the active region AAR.

[0126] The first extension CNW_1 and the third extension CNW_3 of the connection wire CNW passing through the plurality of pixel column spaces do not overlap the first signal wire SW1 and the second signal wire SW2, but the second extension CNW_2 of the connection wire CNW passing through the plurality of pixel row spaces can intersect and partially overlap the first signal wire SW1 and the second signal wire SW2 at the intersection.

[0127] The plurality of connection wires CNW connected to different first signal wires SW1 and second signal wires SW2 are arranged at different positions and spaced apart from each other to avoid short circuit therebetween. In an exemplary embodiment, the second extension CNW_2 of one connection wire CNW can be arranged in one pixel row space. One or both of the first extension CNW_1 or the third extension CNW_3 can be arranged in one pixel column space. However, the number of connection wires CNW arranged in the pixel space can vary depending on the width of the pixel space.

[0128] The first signal wires SW1 and the second signal wires SW2 of the external data lines can be connected to the non-effective fan-out wires located farther away from them as they are farther away from the internal active area AAR_I. That is, the first signal wires SW1 and the second signal wires SW2 of the external data lines adjacent to the internal active area AAR_I can be connected to the non-effective fan-out wires relatively close to them. As the first signal wires SW1 and the second signal wires SW2 of the external data lines are farther away from the first side in the second direction DR2, the non-effective fan-out wires closer to the second side in the second direction DR2 can be connected to the first signal wires SW1 and the second signal wires SW2. In a plan view, the connection wires CNW of the external data lines located at the relatively outer side can surround the connection wires CNW of the external data lines located inside the above-mentioned external data lines. Each connection wire CNW can be arranged to have the shortest path in the plurality of second pixel column spaces PXT_C#23, PXT_C#45 and PXT_C#67 and the pixel row space. Accordingly, the plurality of second pixel column spaces PXT_C#23, PXT_C#45 and PXT_C#67 and the pixel row space can sequentially serve as the path for each connection wire CNW without missing in the middle.

[0129] The routing of the plurality of data lines DL1 and DL2 will be described in more detail based on the pixel arrangement shown in FIG. 4A. Figure 10 Figure 10 ​In the present embodiment, the plurality of pixels PX are arranged in a 4x8 structure in the second outer active area AAR_L2 and the inner active area AAR_I adjacent to the second outer active area AAR_L2. The wiring arrangement of the first outer active area AAR_L1 and the inner active area AAR_I adjacent to the first outer active area AAR_L1 can be symmetrical to the wiring arrangement of the second outer active area AAR_L2 and the inner active area AAR_I adjacent to the second outer active area AAR_L2. Figure 11

[0130] The leftmost column in the drawing is referred to as the first column, and the column number increases toward the right side. In addition, the lowermost row is referred to as the first row, and the row number increases toward the upper side. The inter-pixel spaces are named by providing the numbers of the adjacent pixels, for example, "1 / 2 inter-pixel space". The plurality of connection wirings CNW are numbered in the order of the shortest path to the longest path.

[0131] The first pixel column PXC#1, the third pixel column PXC#3, the fifth pixel column PXC#5, and the seventh pixel column PXC#7 correspond to the first pixel column PXC1, and the second pixel column PXC#2, the fourth pixel column PXC#4, the sixth pixel column PXC#6, and the eighth pixel column PXC#8 correspond to the second pixel column PXC2. In addition, the first pixel column PXC#1 to the fourth pixel column PXC#4 are pixel columns arranged in the outer active area AAR_L, and the fifth pixel column PXC#5 to the eighth pixel column PXC#8 are pixel columns arranged in the inner active area AAR_I.

[0132] The eight non-active fan-out wirings are arranged in the inner non-active area NAR. The first non-active fan-out wiring NFW#1, the third non-active fan-out wiring NFW#3, the fifth non-active fan-out wiring NFW#5, and the seventh non-active fan-out wiring NFW#7 from the left side in the drawing are the second non-active fan-out wirings NFW_2 belonging to the second data line DL2 connected to the second pixel column PXC2. The second non-active fan-out wiring NFW#2, the fourth non-active fan-out wiring NFW#4, the sixth non-active fan-out wiring NFW#6, and the eighth non-active fan-out wiring NFW#8 from the left side in the drawing are the first non-active fan-out wirings NFW_1 belonging to the first data line DL1 connected to the first pixel column PXC1.

[0133] ​The first non-active fan-out wiring NFW#1 is connected to the second signal wiring SW2 connected to the fourth pixel column PXC#4 through a first connection wiring CNW#1. A first extension CNW_1 of the first connection wiring CNW#1 is arranged in the 4 / 5 pixel column space PXT_C#45 in the first pixel row PXR#1. A second extension CNW_2 of the first connection wiring CNW#1 extends from the 1 / 2 pixel row space PXT_R#12 of the 4 / 5 pixel column space PXT_C#45. A third extension CNW_3 of the first connection wiring CNW#1 is arranged in the 4 / 5 pixel column space PXT_C#45 in the first pixel row PXR#1 and is arranged at a second side on the second direction DR2 of the first extension CNW_1. The third extension CNW_3 of the first connection wiring CNW#1 is connected to the second signal wiring SW2 arranged in the 3 / 4 pixel column space PXT_C#34 through a contact electrode CNE.

[0134] The second non-active fan-out wiring NFW#2 is arranged in the 5 / 6 pixel column space PXT_C#56 and is connected to the first signal wiring SW1 connected to the fifth pixel column PXC#5.

[0135] The third non-active fan-out wiring NFW#3 is arranged in the 5 / 6 pixel column space PXT_C#56 and is connected to the second signal wiring SW2 connected to the sixth pixel column PXC#6. The second signal wiring SW2 connected to the third non-active fan-out wiring NFW#3 in the 5 / 6 pixel column space PXT_C#56 is arranged at a first side on the second direction DR2 of the first signal wiring SW1 connected to the second non-active fan-out wiring NFW#2.

[0136] The fourth non-active fan-out wiring NFW#4 is connected to the first signal wiring SW1 connected to the third pixel column PXC#3 through a second connection wiring CNW#2. A first extension CNW_1 of the second connection wiring CNW#2 is arranged in the 6 / 7 pixel column space PXT_C#67 in the first pixel row PXR#1 and the second pixel row PXR#2. A second extension CNW_2 of the second connection wiring CNW#2 extends from the 6 / 7 pixel column space PXT_C#67 to the 2 / 3 pixel column space PXT_C#23 in the 2 / 3 pixel row space PXT_R#23. A third extension CNW_3 of the second connection wiring CNW#2 is arranged in the 2 / 3 pixel column space PXT_C#23 in the second pixel row PXR#2 and the first pixel row PXR#1.

[0137] The fifth non-effective fan-out wiring NFW#5 is connected to the second signal wiring SW2 connected to the second pixel column PXC#2 through the third connection wiring CNW#3. The first extension CNW_1 of the third connection wiring CNW#3 is arranged in the 6 / 7 inter-pixel column space PXT_C#67 in the first pixel row PXR#1, the second pixel row PXR#2, and the third pixel row PXR#3. The first extension CNW_1 of the third connection wiring CNW#3 in the first pixel row PXR#1 and the second pixel row PXR#2 is arranged at a first side on the second direction DR2 of the first extension CNW_1 of the second connection wiring CNW#2. The second extension CNW_2 of the third connection wiring CNW#3 extends from the 6 / 7 inter-pixel column space PXT_C#67 to the 2 / 3 inter-pixel column space PXT_C#23 in the 3 / 4 inter-pixel row space PXT_R#34. The third extension CNW_3 of the third connection wiring CNW#3 is arranged in the 2 / 3 inter-pixel column space PXT_C#23 in the third pixel row PXR#3, the second pixel row PXR#2, and the first pixel row PXR#1. The third extension CNW_3 of the third connection wiring CNW#3 in the first pixel row PXR#1 and the second pixel row PXR#2 is arranged at a second side on the second direction DR2 of the third extension CNW_3 of the second connection wiring CNW#2.

[0138] The sixth non-effective fan-out wiring NFW#6 is arranged in the 7 / 8 inter-pixel column space PXT_C#78 and connected to the first signal wiring SW1 connected to the seventh pixel column PXC#7.

[0139] The seventh non-effective fan-out wiring NFW#7 is arranged in the 7 / 8 inter-pixel column space PXT_C#78 and connected to the second signal wiring SW2 connected to the eighth pixel column PXC#8. The second signal wiring SW2 connected to the seventh non-effective fan-out wiring NFW#7 in the 7 / 8 inter-pixel column space PXT_C#78 is arranged at a first side on the second direction DR2 of the first signal wiring SW1 connected to the sixth non-effective fan-out wiring NFW#6.

[0140] The eighth non-effective fan-out wiring NFW#8 is connected to the first signal wiring SW1 connected to the first pixel column PXC#1 through the fourth connection wiring CNW#4. A first extension CNW_1 of the fourth connection wiring CNW#4 is arranged in a space (e.g., 8 / 9-pixel-column-inter-space) at the right side of the eighth pixel column PXC#8 in the first pixel row PXR#1, the second pixel row PXR#2, the third pixel row PXR#3, and the fourth pixel row PXR#4. A second extension CNW_2 of the fourth connection wiring CNW#4 extends from the space (e.g., 8 / 9-pixel-column-inter-space) at the right side of the eighth pixel column PXC#8 to a space (e.g., 0 / 1-pixel-column-inter-space) at the left side of the first pixel column PXC#1 in the fourth pixel row PXR#4 from the space (e.g., 8 / 9-pixel-column-inter-space) at the right side of the eighth pixel column PXC#8. A third extension CNW_3 of the fourth connection wiring CNW#4 is arranged in a space at the left side of the first pixel column PXC#1 in the fourth pixel row PXR#4, the third pixel row PXR#3, the second pixel row PXR#2, and the first pixel row PXR#1.

[0141] As described above, the two first signal wirings SW1 and the second signal wirings SW2 are arranged in one first pixel column-inter-space PXT_C#12, PXT_C#34, PXT_C#56, or PXT_C#78. For example, one first signal wiring SW1 providing a first data signal to the first pixel column PXC1 and one second signal wiring SW2 providing a second data signal to the second pixel column PXC2 are arranged in one first pixel column-inter-space PXT_C#12, PXT_C#34, PXT_C#56, or PXT_C#78. In one first pixel column-inter-space PXT_C#12, PXT_C#34, PXT_C#56, or PXT_C#78, the first signal wiring SW1 is arranged closer to the second side in the second direction DR2 than the second signal wiring SW2.

[0142] In addition, the first signal wiring SW1 and the second signal wiring SW2 are not arranged in the plurality of second pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67, and the connection wiring CNW is arranged in a portion of at least one of the plurality of second pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67. Each of the plurality of second pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67 can be divided into a region in which the connection wiring CNW is arranged and a region in which the connection wiring CNW is not arranged. In the region in which the connection wiring CNW is arranged, one or two first direction extension portions of the connection wiring CNW are arranged in one second pixel column space PXT_C#23, PXT_C#45, or PXT_C#67. The first extension portion CNW_1 and the third extension portion CNW_3 of one connection wiring CNW can be arranged as in the 4 / 5 pixel column space PXT_C#45, and the first extension portion CNW_1 or the third extension portion CNW_3 of two different connection wirings CNW can be arranged as in the 6 / 7 pixel column space PXT_C#67.

[0143] Referring to Figure 10 and Figure 11 the arrangement of the non-effective fanout wirings, the non-effective fanout wirings belonging to the internal data lines and the non-effective fanout wirings belonging to the external data lines coexist. For example, after arranging the non-effective fanout wiring NFW#1 of one external data line, a pair of non-effective fanout wirings NFW#2 / NFW#3, NFW#6 / NFW#7, and the like of two internal data lines and a pair of non-effective fanout wirings NFW#4 / NFW#5, and the like of two external data lines are alternately arranged along the row direction of the array (for example, toward the first side in the second direction DR2). As described above, although the non-effective fanout wirings of the internal data lines and the non-effective fanout wirings of the external data lines coexist, the first non-effective fanout wiring NFW_1 belonging to the first data line DL1 and the second non-effective fanout wiring NFW_2 belonging to the second data line DL2 are alternately and repeatedly arranged along the second direction DR2 based on the data signals. Accordingly, in the pad portion PDR connected to the non-effective fanout wirings, the wiring pads WR_PD receiving the first data signals and the wiring pads WR_PD receiving the second data signals can be alternately and repeatedly arranged one by one along the row direction of the wiring pads WR_PD.

[0144] In the driver chip connected to the pad portion PDR, which output terminals (or a plurality of bumps connected to the output terminals) can be used to output the first data signals and the second data signals is mapped in advance. The driver chip has Figure 3A display device of a pixel arrangement in which only straight data lines are included without a detour data line generally uses a driver chip mapped so that a first data signal output terminal and a second data signal output terminal are sequentially and alternately arranged. In an exemplary embodiment, although the display device 1 includes not only straight data lines but also detour data lines using effective fan-out wiring, since the wiring pads WR_PD receiving a first data signal and the wiring pads WR_PD receiving a second data signal are alternately arranged one by one along a row direction of the wiring pads WR_PD, the above multifunction driver chip can be utilized without additionally mapping data signal components to the output terminals.

[0145] Further, the internal data lines of the exemplary embodiment described in association with Figure 10 and Figure 11 all of the first signal wirings SW1 connected to the first non-effective fan-out wirings NFW_1 and the second signal wirings SW2 connected to the second non-effective fan-out wirings NFW_2. In the internal active area AAR_I, the first signal wirings SW1 connected to the first non-effective fan-out wirings NFW_1 and the second signal wirings SW2 connected to the second non-effective fan-out wirings NFW_2 are alternately arranged one by one. In addition, the external data lines include all of the first signal wirings SW1 connected to the first non-effective fan-out wirings NFW_1 and the second signal wirings SW2 connected to the second non-effective fan-out wirings NFW_2. In the external active area AAR_L, the first signal wirings SW1 connected to the first non-effective fan-out wirings NFW_1 through the connection wirings CNW and the second signal wirings SW2 connected to the second non-effective fan-out wirings NFW_2 through the connection wirings CNW are alternately arranged one by one.

[0146] As described above, the first non-active fan-out wiring NFW_1 and the second non-active fan-out wiring NFW_2 are made of different conductive layers. For example, the first non-active fan-out wiring NFW_1 can be made of the first gate conductive layer 130, and the second non-active fan-out wiring NFW_2 can be made of the second gate conductive layer 140. Different conductive layers can show different process dispersions in a manufacturing process. Different process dispersions can cause different resistances of the conductive layers and different data signals provided through the data lines connected with the conductive layers. If a plurality of pixels PX connected with a plurality of data lines DL including a specific conductive layer form a block, there can be a luminance difference between zones because the luminance of the block is affected by the process dispersion of the specific conductive layer. In an exemplary embodiment, first signal wirings SW1 connected with the first non-active fan-out wiring NFW_1 made of the first gate conductive layer 130 and second signal wirings SW2 connected with the second non-active fan-out wiring NFW_2 made of the second gate conductive layer 140 are all alternately arranged over the inner active zone AAR_I and the outer active zone AAR_L. For example, data lines DL including a specific conductive layer are not placed together in a block, but are uniformly distributed over the entire zone. Accordingly, it is possible to prevent (or mitigate) a luminance difference between zones caused by the process dispersion of the specific conductive layer. A resistance difference between the first data line DL1 and the second data line DL2 alternately arranged due to the process dispersion of the specific conductive layer is not related to the luminance difference between zones, and such a problem can be solved by compensating for the value of a data signal provided through a driver chip.

[0147] Hereinafter, various other exemplary embodiments will be described.

[0148] Figure 12 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment. In the following embodiments, elements of a pixel array will be named as described in Figure 10 .

[0149] Referring to Figure 12 , the display device and the display device 1 described in association with Figure 11 differ in that a plurality of first pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67 in which the first signal wirings SW1 and the second signal wirings SW2 are arranged are located in a space between the second pixel column PXC2 and the first pixel column PXC1 arranged at a first side in a second direction DR2 of the second pixel column PXC2, and a plurality of second pixel column spaces PXT_C#12, PXT_C#34, PXT_C#56, and PXT_C#78 in which the connection wirings CNW are arranged are located in a space between the first pixel column PXC1 and the second pixel column PXC2 arranged at a first side in the second direction DR2 of the first pixel column PXC1.

[0150] In Figure 12 the 4x8 pixel arrangement, the first, third, fifth and seventh pixel columns PXC#1, PXC#3, PXC#5 and PXC#7 correspond to the first pixel column PXC1, and the second, fourth, sixth and eighth pixel columns PXC#2, PXC#4, PXC#6 and PXC#8 correspond to the second pixel column PXC2. In addition, the first to fourth pixel columns PXC#1 to PXC#4 are pixel columns arranged in the outer active area AAR_L, and the fifth to eighth pixel columns PXC#5 to PXC#8 are pixel columns arranged in the inner active area AAR_I.

[0151] The eight non-active fan-out wirings are arranged in the inner non-active area NAR. The arrangement of the plurality of non-active fan-out wirings is opposite to the arrangement described in relation to Figure 11 For example, the first, third, fifth and seventh non-active fan-out wirings NFW#1, NFW#3, NFW#5 and NFW#7 from the left side in the figure are first non-active fan-out wirings NFW_1 belonging to the first data line DL1 connected to the first pixel column PXC1, and the second, fourth, sixth and eighth non-active fan-out wirings NFW#2, NFW#4, NFW#6 and NFW#8 are second non-active fan-out wirings NFW_2 belonging to the second data line DL2 connected to the second pixel column PXC2.

[0152] The first non-active fan-out wiring NFW#1 is arranged in the 4 / 5 pixel column space PXT_C#45 and connected to the first signal wiring SW1 connected to the fifth pixel column PXC#5.

[0153] The second non-active fan-out wiring NFW#2 is connected to the second signal wiring SW2 connected to the fourth pixel column PXC#4 by the first connection wiring CNW#1. A first extension CNW_1 of the first connection wiring CNW#1 is arranged in the 5 / 6 pixel column space PXT_C#56 in the first pixel row PXR#1. A second extension CNW_2 of the first connection wiring CNW#1 extends from the 5 / 6 pixel column space PXT_C#56 to the 3 / 4 pixel column space PXT_C#34 in the 1 / 2 pixel row space PXT_R#12. A third extension CNW_3 of the first connection wiring CNW#1 is arranged in the 3 / 4 pixel column space PXT_C#34 in the first pixel row PXR#1. The third extension CNW_3 of the first connection wiring CNW#1 is connected to the second signal wiring SW2 arranged in the 4 / 5 pixel column space PXT_C#45 by a contact electrode CNE.

[0154] The third non-effective fan-out wiring NFW#3 is connected to the first signal wiring SW1 connected to the third pixel column PXC#3 through the second connection wiring CNW#2. The first extension CNW_1 of the second connection wiring CNW#2 is arranged in the 5 / 6 inter-pixel column space PXT_C#56 in the first pixel row PXR#1 and the second pixel row PXR#2. The first extension CNW_1 of the second connection wiring CNW#2 in the first pixel row PXR#1 is arranged at a first side on the second direction DR2 of the first extension CNW_1 of the first connection wiring CNW#1. The second extension CNW_2 of the second connection wiring CNW#2 extends from the 5 / 6 inter-pixel column space PXT_C#56 to the 3 / 4 inter-pixel column space PXT_C#34 in the 2 / 3 inter-pixel row space PXT_R#23. The third extension CNW_3 of the second connection wiring CNW#2 is arranged in the 3 / 4 inter-pixel column space PXT_C#34 in the second pixel row PXR#2 and the first pixel row PXR#1. The third extension CNW_3 of the second connection wiring CNW#2 is connected to the first signal wiring SW1 arranged in the 2 / 3 inter-pixel column space PXT_C#23 through a contact electrode CNE. The third extension CNW_3 of the second connection wiring CNW#2 in the first pixel row PXR#1 is arranged at a second side on the second direction DR2 of the third extension CNW_3 of the first connection wiring CNW#1.

[0155] The fourth non-effective fan-out wiring NFW#4 is arranged in the 6 / 7 inter-pixel column space PXT_C#67 and connected to the second signal wiring SW2 connected to the sixth pixel column PXC#6.

[0156] The fifth non-effective fan-out wiring NFW#5 is arranged in the 6 / 7 inter-pixel column space PXT_C#67 and connected to the first signal wiring SW1 connected to the seventh pixel column PXC#7. The first signal wiring SW1 connected to the seventh pixel column PXC#7 in the 6 / 7 inter-pixel column space PXT_C#67 is arranged at a first side on the second direction DR2 of the second signal wiring SW2 connected to the sixth pixel column PXC#6.

[0157] A sixth non-effective fan-out wiring NFW#6 is connected to the second signal wiring SW2 connected to the second pixel column PXC#2 through a third connection wiring CNW#3. A first extension CNW_1 of the third connection wiring CNW#3 is arranged in the 7 / 8 pixel column space PXT_C#78 in the first pixel row PXR#1, the second pixel row PXR#2, and the third pixel row PXR#3. A second extension CNW_2 of the third connection wiring CNW#3 extends from the 7 / 8 pixel column space PXT_C#78 to the 1 / 2 pixel column space PXT_C#12 in the 3 / 4 pixel row space PXT_R#34. A third extension CNW_3 of the third connection wiring CNW#3 is arranged in the 1 / 2 pixel column space PXT_C#12 in the third pixel row PXR#3, the second pixel row PXR#2, and the first pixel row PXR#1. The third extension CNW_3 of the third connection wiring CNW#3 is connected to the second signal wiring SW2 arranged in the 2 / 3 pixel column space PXT_C#23 through a contact electrode CNE.

[0158] A seventh non-effective fan-out wiring NFW#7 is connected to the first signal wiring SW1 connected to the first pixel column PXC#1 through a fourth connection wiring CNW#4. A first extension CNW_1 of the fourth connection wiring CNW#4 is arranged in the 7 / 8 pixel column space PXT_C#78 in the first pixel row PXR#1, the second pixel row PXR#2, the third pixel row PXR#3, and the fourth pixel row PXR#4. The first extension CNW_1 of the fourth connection wiring CNW#4 in the first pixel row PXR#1, the second pixel row PXR#2, and the third pixel row PXR#3 is arranged at a first side on a second direction DR2 of the first extension CNW_1 of the third connection wiring CNW#3. A second extension CNW_2 of the fourth connection wiring CNW#4 extends from the 7 / 8 pixel column space PXT_C#78 to the 1 / 2 pixel column space PXT_C#12 in a space (e.g., 4 / 5 pixel row space) above the fourth pixel row PXR#4. A third extension CNW_3 of the fourth connection wiring CNW#4 is arranged in the 1 / 2 pixel column space PXT_C#12 in the fourth pixel row PXR#4, the third pixel row PXR#3, the second pixel row PXR#2, and the first pixel row PXR#1. The third extension CNW_3 of the fourth connection wiring CNW#4 is connected to the first signal wiring SW1 arranged in a space (e.g., 0 / 1 pixel column space) at a left side of the first pixel column PXC#1 through a contact electrode CNE. In the third pixel row PXR#3, the second pixel row PXR#2, and the first pixel row PXR#1, the third extension CNW_3 of the fourth connection wiring CNW#4 is arranged at a second side on the second direction DR2 of the third extension CNW_3 of the third connection wiring CNW#3.

[0159] An eighth non-active fan-out wire NFW#8 is arranged in a space (e.g., 8 / 9 pixel column space) at the right side of the eighth pixel column PXC#8, and is connected to the second signal wire SW2 connected to the eighth pixel column PXC#8.

[0160] The exemplary embodiment described in association with Figure 12 differs from the exemplary embodiment described in association with Figure 11 in the arrangement of the plurality of first pixel column spaces PXT_C#23, PXT_C#45, and PXT_C#67 and the plurality of second pixel column spaces PXT_C#12, PXT_C#34, PXT_C#56, and PXT_C#78 and the arrangement of the plurality of connection wires CNW. However, the first non-active fan-out wires NFW_1 belonging to the first data line DL1 and the second non-active fan-out wires NFW_2 belonging to the second data line DL2 are alternately and repeatedly arranged one by one along the row direction (e.g., the second direction DR2). Thus, although the exemplary embodiment described in association with Figure 12 not only includes straight data lines but also includes detour data lines using active fan-out wires, since the wire pad WR_PD receiving the first data signal and the wire pad WR_PD receiving the second data signal are alternately arranged along the row direction of the wire pad WR_PD, a multi-functional driver chip can be used without additional mapping of the data signal components to the output terminals.

[0161] Further, the first signal wire SW1 connected to the first non-active fan-out wire NFW_1 made of the first gate conductive layer 130 and the second signal wire SW2 connected to the second non-active fan-out wire NFW_2 made of the second gate conductive layer 140 are alternately arranged one by one above the inner active area AAR_I and the outer active area AAR_L. Thus, it is possible to prevent or mitigate the luminance difference between the areas due to process dispersion of a certain conductive layer.

[0162] Figure 13 is a partial layout diagram showing the arrangement of pixels and data lines according to an exemplary embodiment.

[0163] Referring to Figure 13 , the display device and the display device 1 described in association with Figure 11 differs in that the dummy wire pattern DMP is arranged in the same layer as the connection wire CNW.

[0164] For example, as with Figure 11As described in relation to the above, the first signal wiring SW1 and the second signal wiring SW2 or the connection wiring CNW are arranged in some of the pixel-to-pixel spaces but not in other pixel-to-pixel spaces. As described above, when the plurality of pixel-to-pixel spaces are divided into spaces in which the wirings are arranged and spaces in which the wirings are not arranged, a visual defect (or difference) can occur in viewing the spaces from the outside due to the difference in reflectivity. If the dummy wiring pattern DMP is arranged in the spaces in which the first signal wiring SW1 and the second signal wiring SW2 or the connection wiring CNW are not arranged among the plurality of pixel-to-pixel spaces, the difference between the spaces can be reduced, thereby preventing (or reducing) the spaces from being viewed from the outside. That is, visibility (or display quality) can be improved.

[0165] The dummy wiring pattern DMP can be made of the same conductive layer as the connection wiring CNW. When the connection wiring CNW is made of the second data conductive layer 160, the dummy wiring pattern DMP is also made of the second data conductive layer 160. The dummy wiring pattern DMP can be formed together (simultaneously) with the connection wiring CNW.

[0166] The dummy wiring pattern DMP can be separate from the connection wiring CNW. That is, the dummy wiring pattern DMP is formed in the same layer as the connection wiring CNW but can be spaced apart from the connection wiring CNW in a plan view. The dummy wiring pattern DMP can be a floating wiring pattern that does not directly transmit an electrical signal.

[0167] The dummy wiring pattern DMP can have substantially the same shape and arrangement as the connection wiring CNW in the pixel-to-pixel spaces. However, since the dummy wiring pattern DMP arranged in the pixel-to-pixel spaces is spaced apart from the adjacent connection wiring CNW, they can have a shorter length than the adjacent connection wiring CNW.

[0168] In an exemplary embodiment, one connection wiring CNW can pass through the pixel row-to-pixel row spaces and extend in the second direction DR2. Similarly, one dummy wiring pattern DMP can also pass through the pixel row-to-pixel row spaces and extend in the second direction DR2.

[0169] The connection wiring CNW passing through the pixel column-to-pixel column spaces can include one or two portions extending in the first direction DR1. When two portions extend, they can belong to different connection wirings CNW or one connection wiring CNW. In either case, the connection wiring CNW passing through the pixel column-to-pixel column spaces can generally include two portions extending in the first direction DR1. Two dummy wiring patterns DMP can be arranged in the pixel column-to-pixel column spaces in which the connection wiring CNW is not arranged, and one dummy wiring pattern DMP can be arranged in the pixel column-to-pixel column space in which one extension of the connection wiring CNW is arranged.

[0170] Figure 14is a schematic layout diagram showing the wiring arrangement of the display device 2 according to an exemplary embodiment. In order to improve visibility, Figure 14 It is shown that the display device 2 can include a plurality of dummy wiring patterns DMP not only in the plurality of areas surrounding the connection wiring CNW but also in the plurality of areas spaced apart from the connection wiring CNW.

[0171] Referring to Figure 14 , the connection wiring CNW can be mainly arranged in a lower area AAR_B of the active area AAR adjacent to the non-active area NAR in a plan view, and can not be arranged in an upper area AAR_U. In this case, the lower area AAR_B and the upper area AAR_U of the active area AAR can be distinguished from each other by the naked eye according to the presence or absence of the connection wiring CNW. Even in the lower area AAR_B of the active area AAR, the pixel-to-pixel space in which the connection wiring CNW is arranged can be distinguished from the pixel-to-pixel space in which the connection wiring CNW is not arranged. As shown in Figure 14 , in the lower area AAR_B of the active area AAR, the dummy wiring pattern DMP can be arranged in the pixel-to-pixel space in which the connection wiring CNW is not arranged. As described above, if the dummy wiring pattern DMP is arranged in the lower area AAR_B of the active area AAR, it is possible to prevent or alleviate the visual defect (or difference) due to the presence of the connection wiring CNW in the lower area AAR_B. However, it is still difficult to prevent the lower area AAR_B from being distinguished from the upper area AAR_U of the active area AAR in which the connection wiring CNW is not arranged at all.

[0172] In order to prevent or alleviate the lower area AAR_B and the upper area AAR_U of the active area AAR from being visually distinguished and observed due to the presence of the connection wiring CNW, the dummy wiring pattern DMP can also be arranged in the upper area AAR_U of the active area AAR. The dummy wiring pattern DMP can be arranged in all the pixel-to-pixel spaces in which the connection wiring CNW is not arranged. Two dummy wiring patterns DMP extending in the first direction DR1 can be arranged in the pixel-column-to-pixel-column space, and one dummy wiring pattern DMP extending in the second direction DR2 can be arranged in the pixel-row-to-pixel-row space. In the upper area AAR_U of the active area AAR, the dummy wiring pattern DMP can pass through a plurality of pixels PX. For example, the dummy wiring pattern DMP arranged in the pixel-row-to-pixel-row space can extend from the outermost pixel PX at a first side in the second direction DR2 to the outermost pixel PX at a second side in the second direction DR2. In addition, the dummy wiring pattern DMP arranged in the pixel-column-to-pixel-column space can extend from the outermost pixel PX at a second side in the first direction DR1 to the pixel PX adjacent to the lower area AAR_B of the active area AAR in which the connection wiring CNW is arranged.

[0173] Figure 15is a schematic layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment.

[0174] Referring to Figure 15 , the display device 3 differs from the display device 2 described in association with Figure 14 in that each dummy wiring pattern DMP arranged in the upper area AAR_U of the active area AAR is divided into a plurality of segments along the first direction DR1 or the second direction DR2 and is generally arranged in the shape of a stitch, e.g., a plurality of line segments. The dummy wiring pattern DMP arranged in the pixel column space in the lower area AAR_B of the active area AAR extends to a length generally corresponding to one pixel row. In addition, the dummy wiring pattern DMP arranged in the pixel row space in the lower area AAR_B of the active area AAR extends to a length generally corresponding to two pixel columns. As shown in Figure 15 , the dummy wiring pattern DMP arranged in the upper area AAR_U of the active area AAR also extends to a similar length to the dummy wiring pattern DMP arranged in the lower area AAR_B. That is, the dummy wiring pattern DMP arranged in the pixel column space in the upper area AAR_U of the active area AAR can extend to a length generally corresponding to one pixel row, and the dummy wiring pattern DMP arranged in the pixel row space can extend to a length generally corresponding to two pixel columns.

[0175] As described above, if the plurality of dummy wiring patterns DMP arranged in the upper area AAR_U of the active area AAR where no connection wiring CNW is arranged extend to the same length and are arranged in the same manner as the dummy wiring pattern DMP arranged in the lower area AAR_B, it is possible to further prevent or alleviate the visual defect of distinguishing the upper area AAR_U and the lower area AAR_B of the active area AAR with the naked eye.

[0176] Figure 16 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment. Figure 16 It is shown that Figure 13 the dummy wiring pattern DMP can be applied to the exemplary embodiments described in association with Figure 12 .

[0177] Referring to Figure 16 , the display device differs from the display device described in association with Figure 13 in the arrangement of the pixels PX, the connection wiring CNW, and the data line DL. In the display device described in association with Figure 13In the exemplary embodiments described in association with, the first signal wiring SW1 and the second signal wiring SW2 or the connection wiring CNW are arranged in some of the inter-pixel spaces, but not in other inter-pixel spaces. Thus, the dummy wiring pattern DMP can be arranged in the inter-pixel spaces in which the first signal wiring SW1 and the second signal wiring SW2 and the connection wiring CNW are not arranged. This can reduce the difference between the spaces, thereby preventing (or mitigating) the spaces from being observed from the outside. The number and arrangement of the dummy wiring patterns DMP and the connection wirings CNW are the same as described in association with Figure 13 The same applies to the exemplary embodiments described in association with, and thus the redundant descriptions thereof are omitted.

[0178] Figure 17 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment.

[0179] Referring to Figure 17 , the display device and the exemplary embodiments described in association with Figure 13 differ in that the dummy wiring pattern DMP is omitted, and instead, each connection wiring CNW includes a dummy portion CNW_D.

[0180] For example, each connection wiring CNW can include an effective wiring portion CNW_E and a dummy portion CNW_D, where the effective wiring portion CNW_E extends from the non-effective fan-out wiring at a shortest distance in order to connect to the first signal wiring SW1 or the second signal wiring SW2, and the dummy portion CNW_D branches from the effective wiring portion CNW_E and extends to the inter-pixel spaces. The effective wiring portion CNW_E of each connection wiring CNW can have substantially the same shape as each connection wiring CNW of Figure 13 . The dummy portion CNW_D of each connection wiring CNW can have substantially the same shape as the dummy wiring pattern DMP of Figure 13 , except that they are connected to the adjacent effective wiring portion CNW_E.

[0181] Some of the plurality of dummy portions CNW_D of each connection wiring CNW can be arranged in the inter-pixel column spaces and can extend in the first direction DR1. The other dummy portions CNW_D of each connection wiring CNW can be arranged in the inter-pixel row spaces and can extend in the second direction DR2. Each dummy portion CNW_D of one connection wiring CNW can extend to the vicinity of the adjacent connection wiring CNW, but can be spaced apart from the adjacent connection wiring CNW without contacting the adjacent connection wiring CNW.

[0182] Each dummy portion CNW_D of each connection wiring CNW is shaped as the dummy wiring pattern DMP of Figure 13 with the end portion connected to the adjacent connection wiring CNW. As Figure 17As shown in FIG. 10, each dummy portion CNW_D of each connection wiring CNW can also be modified to be shaped like the dummy wiring pattern DMP having the other end portion connected to the adjacent connection wiring CNW.

[0183] In the exemplary embodiment, two dummy portions CNW_D arranged in one pixel inter-column space can belong to different connection wirings CNW. That is, two dummy portions CNW_D arranged in one pixel inter-column space can be connected to respective portions of different connection wirings CNW. Here, the respective portions of different connection wirings CNW to which two dummy portions CNW_D are connected can be effective wiring portions CNW_E. However, if all branches of a plurality of dummy portions CNW_D depart from or extend beyond a plurality of pixel inter-column spaces, an end portion of one dummy portion CNW_D can be connected to another dummy portion CNW_D.

[0184] As Figure 17 As shown in FIG. 10, a dummy portion CNW_D arranged at a first side of a certain pixel inter-column space can belong to a connection wiring CNW located at the first side in the first direction DR1, and a dummy portion CNW_D arranged at a second side of the certain pixel inter-column space can belong to a connection wiring CNW located at the second side in the first direction DR1. Such a connection structure between the dummy portion CNW_D and the effective wiring portion CNW_E can be repeated along the row direction. That is, a dummy portion CNW_D arranged at a first side of an effective wiring portion CNW_E in the first direction DR1 and a dummy portion CNW_D arranged at a second side of the effective wiring portion CNW_E in the first direction DR1 can be repeatedly arranged along one row.

[0185] In addition, each dummy portion CNW_D arranged in each pixel inter-row space can belong to a connection wiring CNW arranged at a first side or a second side in the second direction DR2. In the same column, a dummy portion CNW_D belonging to a connection wiring CNW arranged at a first side in the second direction DR2 and a dummy portion CNW_D belonging to a connection wiring CNW arranged at a second side in the second direction DR2 can be alternately arranged along the first direction DR1.

[0186] As described above, a dummy portion CNW_D having a connection structure at one side and a dummy portion CNW_D having a connection structure at the other side are alternately arranged along the first direction DR1 and the second direction DR2. Accordingly, a plurality of connection wirings CNW can generally be arranged in a pinwheel shape or a cyclone shape. This wiring arrangement pattern can further prevent or alleviate visual defects, thereby further improving visibility or display quality.

[0187] Figure 18 FIG. 11 is a partial layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment.

[0188] Referring toFigure 18 Display devices and Figure 17 The exemplary embodiments described in connection differ in that each connection trace CNW also includes a protruding pattern PTP. The protruding pattern PTP may protrude from a first-direction extension of each connection trace CNW arranged in each pixel inter-row space (e.g., a first extension CNW_1, a third extension CNW_3, or a dummy extension CNW_D extending in the first direction DR1) in the second direction DR2. In a pixel inter-row space, the first-direction extensions of two connection traces CNWs extend parallel to each other as described above. Here, the protruding pattern PTP of one of the plurality of connection traces CNWs may protrude toward another connection trace CNW. The protruding length of each of the plurality of protruding patterns PTP may be less than the width of each pixel PX in the first direction DR1, the width of each pixel PX in the second direction DR2, and the width of each inter-pixel space.

[0189] Multiple protruding patterns (PTPs) of each connection trace CNW can protrude to points that are spaced apart from adjacent connection trace CNWs without contacting them. The protrusion length of each protruding pattern PTP can be less than the distance between the first-direction extensions of two connection trace CNWs in a pixel inter-column space. The protrusion distance of each protruding pattern PTP of a connection trace CNW can be greater than or equal to the distance between that connection trace CNW and another connection trace CNW facing that connection trace CNW, but is not limited thereto.

[0190] Each protruding pattern PTP can be arranged at the intersection of the pixel column space and the pixel row space, but the exemplary embodiment is not limited to this. Each protruding pattern PTP can be arranged on the extension of the connecting wiring CNW that passes through the same pixel row space as the protruding pattern PTP, for example, on the extension of the second extension CNW_2 or the dummy part CNW_D extending in the second direction DR2. Protruding pattern PTPs belonging to the connecting wiring CNW located on one side of a pixel column space and protruding pattern PTPs belonging to the connecting wiring CNW located on the other side can be alternately arranged in multiple pixel row spaces.

[0191] Each inter-pixel row space includes a region through which the second extension CNW_2 of the connection wiring CNW or the dummy CNW_D extending in the second direction DR2 passes. However, each inter-pixel row space also includes a region through which the above wiring does not pass. For example, the second extension CNW_2 of the connection wiring CNW or the dummy CNW_D extending in the second direction DR2 is not arranged in each inter-pixel row space through which a pair of the first direction extensions of the connection wiring CNW passes. In this case, since there is no second direction extension in the space between the first direction extensions of the connection wiring CNW facing each other, a visual defect (or difference) can occur in which the space is observed from the outside. If the protruding pattern PTP protruding in the second direction DR2 is arranged in the space between the first direction extensions of the connection wiring CNW facing each other, the visual defect can be minimized or reduced. Further, since the connection structures of the protruding pattern PTP are alternately and respectively arranged in rows, the visibility or display quality can be further improved.

[0192] Figure 19 is a schematic layout diagram illustrating a pixel arrangement and a data line arrangement according to an exemplary embodiment. Figure 19 is shown Figure 18 The wiring structure of

[0193] Referring to Figure 19 , the connection wiring CNW is arranged in the lower region AAR_B of the active region AAR of the display device 4, but not in the upper region AAR_U. In the lower region AAR_B, the dummy CNW_D is arranged in each inter-pixel space in which the active wiring portion CNW_E of the connection wiring CNW is not arranged. In addition, in the upper region AAR_U in which the connection wiring CNW is not arranged, a plurality of dummy wiring patterns DMP are arranged, the dummy wiring patterns DMP have substantially the same shape, and the dummy wiring patterns DMP are arranged in substantially the same manner as the connection wiring CNW arranged in the lower region AAR_B. Like the connection wiring CNW of the lower region AAR_B, the dummy wiring pattern DMP can include the protruding pattern PTP. Although the dummy wiring pattern DMP of the upper region AAR_U is separated from the connection wiring CNW of the lower region AAR_B in the drawing, the dummy wiring pattern DMP can also be connected to the connection wiring CNW of the lower region AAR_B to form the dummy CNW_D.

[0194] As shown in Figure 19 , the connection wiring CNW including the dummy CNW_D arranged in the lower region AAR_B of the active region AAR and the dummy wiring pattern DMP arranged in the upper region AAR_U of the active region AAR can be generally arranged in the shape of a plurality of windmill patterns. This wiring arrangement pattern can further prevent or alleviate visual defects or differences, thereby further improving the visibility or display quality.

[0195] Figure 20 is a perspective view of a display device 5 according to an exemplary embodiment. Figure 21 is a perspective view of a display device 5 according to an exemplary embodiment. Figure 20 is an expanded view of the display device 5 of Figure 20 and Figure 21 It is shown that the display device 5 can be applied as a multi-faceted display device.

[0196] Referring to Figure 20 and Figure 21 The display device 5 according to an exemplary embodiment includes a front active area AAR0, a plurality of side active areas AAR1 to AAR4, and a plurality of corner areas C1 to C4.

[0197] The front active area AAR0 and the plurality of side active areas AAR1 to AAR4 can constitute an active area AAR in which an image is displayed. The plurality of side active areas AAR1 to AAR4 can be bent at an angle in a range of 30 to 120 degrees with respect to the front active area AAR0.

[0198] The plurality of corner areas C1 to C4 can be located between the plurality of side active areas AAR1 to AAR4. The plurality of corner areas C1 to C4 can include first to fourth corner areas C1 to C4 located between the first to fourth side active areas AAR1 to AAR4, respectively. The first to fourth corner areas C1 to C4 can be positioned adjacent to four corners where long and short sides of the front active area AAR0 meet. Except for their positions, the first to fourth corner areas C1 to C4 can be substantially the same in function or configuration. The plurality of corner areas C1 to C4 can constitute a non-active area NAR in which an image is not displayed, and can provide a space through which wiring passes.

[0199] In an exemplary embodiment, a width of the pad portion PDR is less than a width of the entire active area AAR as described above with reference to Figure 6 Thus, straight wiring can be used to transmit a signal to the first side active area AAR1, the front active area AAR0, and the third side active area AAR3 overlapping the area in which the wiring WR extending from the pad portion PDR is arranged in the first direction DR1. However, it is difficult to secure a space for straight wiring to transmit a signal to the second side active area AAR2 or the fourth side active area AAR4 in the non-active area NAR. In the case of the second side active area AAR2 or the fourth side active area AAR4, a signal can be transmitted by using detour wiring through a bypass wiring WR CN passing through the active area AAR as described above. Since this has been described in detail above, a redundant description thereof is omitted.

[0200] While certain example embodiments and implementations have been described herein, other embodiments and variations thereon will be apparent to those of ordinary skill in the art from the descriptions herein. Accordingly, the inventive concept is not limited to these embodiments and implementations, but rather the scope of the inventive concept is to be accorded the broadest scope possible under the principles of patent law consistent with the teachings and disclosures herein, and various obvious modifications and equivalent arrangements are intended to be encompassed.

Claims

1. A display device comprising: an effective region including a plurality of pixels configured to receive a plurality of data signals from a plurality of data lines, the plurality of pixels being arranged in a matrix form; a non-effective region adjacent to the effective region in a first direction, the non-effective region including a pad portion; a plurality of non-effective fan-out wirings located in the non-effective region and connected to the pad portion; a plurality of signal wirings extending in the first direction and intersecting the effective region, the plurality of signal wirings being connected to the plurality of pixels; and a plurality of connection wirings at least partially passing through the effective region and connecting some of the non-effective fan-out wirings to some of the plurality of signal wirings, respectively, wherein the plurality of non-effective fan-out wirings include: a plurality of first non-effective fan-out wirings made of a first conductive layer; and a plurality of second non-effective fan-out wirings made of a second conductive layer different from the first conductive layer, wherein the plurality of first non-effective fan-out wirings and the plurality of second non-effective fan-out wirings are alternately arranged along a second direction intersecting the first direction and extend in the first direction, wherein each of the plurality of connection wirings includes: a first extension located in a pixel-column space between adjacent pixels of the plurality of pixels; a second extension connected to the first extension and located in a pixel-row space between adjacent pixels of the plurality of pixels; and a third extension connected to the second extension and disposed in a pixel-column space between adjacent pixels of the plurality of pixels, and wherein the third extension of each of the plurality of connection wirings does not overlap the signal wiring connected thereto. the matrix form includes a plurality of first pixel columns and a plurality of second pixel columns alternately arranged; 2. The display device of claim 1, wherein, the plurality of first pixel columns are a plurality of pixel columns in which first color pixels and second color pixels are alternately arranged; and the plurality of second pixel columns are a plurality of pixel columns in which third color pixels are repeatedly arranged. a plurality of signal wirings connected to the plurality of first non-effective fan-out wirings among the plurality of signal wirings are connected to the plurality of first pixel columns; and 3. The display device of claim 2, wherein, a plurality of signal wirings connected to the plurality of second non-effective fan-out wirings among the plurality of signal wirings are connected to the plurality of second pixel columns. the plurality of signal wirings are made of a third conductive layer; the plurality of connection wirings are made of a fourth conductive layer; 4. The display device of claim 1, wherein, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are different conductive layers. the plurality of signal wirings are disposed in a plurality of pixel-column spaces between adjacent pixels of the plurality of pixels. the plurality of pixel-column spaces in which the plurality of signal wirings are disposed are different from the pixel-column spaces in which the first extensions or the third extensions are disposed.

5. The display device of claim 4, wherein, ​ 6. The display device of claim 5, wherein, ​ 7. The display device of claim 6, wherein, The plurality of pixel column spaces in which the plurality of signal wirings are arranged and the pixel column space in which the first extension or the third extension is arranged are alternately arranged along a row direction.

8. The display device of claim 5, wherein, The first extension contacts a corresponding non-active fan-out wiring of the plurality of non-active fan-out wirings in the non-active area.

9. The display device of claim 5, wherein, The third extension is connected to a corresponding signal wiring of the plurality of signal wirings in the non-active area.

10. The display device according to claim 9, further comprising: a contact electrode in the non-active area, wherein the contact electrode is made of the first conductive layer or the second conductive layer; and the contact electrode is connected to each of the third extension and the corresponding signal wiring.

11. The display device of claim 5, wherein, Each of the plurality of connection wirings includes: an active wiring portion including the first extension, the second extension, and the third extension; and a dummy portion branched from the active wiring portion, the dummy portion being in a pixel space between adjacent pixels of the plurality of pixels.

12. The display device of claim 11, wherein, Each of the plurality of connection wirings further includes a protruding pattern protruding toward an adjacent connection wiring of the plurality of connection wirings; and a protruding length of the protruding pattern is smaller than a width of each of the plurality of pixels and a width of the pixel space.

13. The display device according to claim 4, further comprising: a dummy wiring pattern made of the fourth conductive layer, arranged in a pixel space in which the plurality of signal wirings and the plurality of connection wirings are not arranged, and separated from the plurality of connection wirings.

14. The display device of claim 2, wherein, The plurality of data signals includes a first data signal and a second data signal; and The plurality of data lines includes: a plurality of first data lines including the plurality of first non-active fan-out wirings and configured to supply the first data signal to the plurality of first pixel columns; and a plurality of second data lines including the plurality of second non-active fan-out wirings and configured to supply the second data signal to the plurality of second pixel columns. The active area is divided into:

15. The display device of claim 1, wherein, an inner active area overlapping a plurality of extension lines of the plurality of non-active fan-out wirings in the first direction; and an outer active area not overlapping the plurality of extension lines. The plurality of signal wirings arranged in the inner active area are a plurality of direct signal wirings directly connected to some of the plurality of non-active fan-out wirings; and 16. The display device of claim 15, wherein, The plurality of signal wirings arranged in the outer active area are a plurality of indirect signal wirings connected to others of the plurality of non-active fan-out wirings through the plurality of connection wirings. A pair of the plurality of non-active fan-out wirings connected to the plurality of direct signal wirings and a pair of the plurality of non-active fan-out wirings connected to the plurality of indirect signal wirings are alternately arranged along the second direction.

18. A display device having an active area and a non-active area adjacent to the active area in a first direction, the display device comprising:

17. The display device of claim 16, wherein, ​ ​ a plurality of non-active fan-out wirings located in the non-active region, the plurality of non-active fan-out wirings including a plurality of first non-active fan-out wirings and a plurality of second non-active fan-out wirings alternately arranged along a second direction intersecting the first direction; a plurality of signal wirings located in the active region, the plurality of signal wirings including a plurality of first signal wirings and a plurality of second signal wirings alternately arranged along the second direction, wherein the plurality of first signal wirings and the plurality of second signal wirings extend in the first direction and do not overlap with each other; and a plurality of active fan-out wirings passing through the active region, wherein the plurality of first non-active fan-out wirings are made of a first conductive layer; the plurality of second non-active fan-out wirings are made of a second conductive layer; the plurality of signal wirings are made of a third conductive layer; the plurality of active fan-out wirings are made of a fourth conductive layer; the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer are different conductive layers; a first portion of the plurality of first signal wirings is connected to some of the plurality of first non-active fan-out wirings through some of the plurality of active fan-out wirings to form a plurality of first external data lines; a remaining portion of the plurality of first signal wirings is connected to another of the plurality of first non-active fan-out wirings without the active fan-out wirings to form a plurality of first internal data lines; a first portion of the plurality of second signal wirings is connected to some of the plurality of second non-active fan-out wirings through another of the plurality of active fan-out wirings to form a plurality of second external data lines; and a remaining portion of the plurality of second signal wirings is connected to another of the plurality of second non-active fan-out wirings without the active fan-out wirings to form a plurality of second internal data lines.

19. The display device of claim 18, wherein, the active region includes an internal active region and an external active region adjacent to the internal active region in the second direction.

20. The display device of claim 19, wherein, the plurality of first signal wirings of the plurality of first internal data lines and the plurality of second signal wirings of the plurality of second internal data lines are alternately arranged in the internal active region along the second direction; and the plurality of first signal wirings of the plurality of first external data lines and the plurality of second signal wirings of the plurality of second external data lines are alternately arranged in the external active region along the second direction. each of the internal active region and the external active region includes a plurality of first pixel columns and a plurality of second pixel columns alternately arranged along the second direction; 21. The display device of claim 20, wherein, the plurality of first pixel columns are a plurality of pixel columns in which first color pixels and second color pixels are alternately arranged along the first direction; and the plurality of second pixel columns are a plurality of pixel columns in which third color pixels are repeatedly arranged in the first direction. the plurality of first pixel columns of the internal active region are connected to the plurality of first signal wirings of the plurality of first internal data lines; and 22. The display device of claim 21, wherein, the plurality of second pixel columns of the external active region are connected to the plurality of second signal wirings of the plurality of second external data lines. the plurality of second pixel columns of the inner active area are connected to the plurality of second signal wirings of the plurality of second inner data lines; the plurality of first pixel columns of the outer active area are connected to the plurality of first signal wirings of the plurality of first outer data lines; and the plurality of second pixel columns of the outer active area are connected to the plurality of second signal wirings of the plurality of second outer data lines.

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