Synchronization method and control device

Abstract

The present invention provides a synchronization method and a control device, which maintain the synchronization accuracy between a communication control circuit and an external device even when a basic timing signal generating circuit and a communication control circuit operate with different clocks. In the synchronization method, a basic timing signal generating circuit generates a basic timing signal, a communication control circuit generates a first communication cycle timing signal, an input difference between the basic timing signal and a specified first communication cycle timing signal is measured, a correction amount of the input difference is divided by the number of first communication cycle timing signals, the division operation value is added in a communication cycle, the timing generated by the first communication cycle timing signal is corrected at a timing above a specified value, a data packet of timing correction data is sent to an external device, the external device generates a second communication cycle timing signal, and the timing generated by the second communication cycle timing signal is corrected according to the reception timing of the timing correction data so as to be synchronized with the first communication cycle timing signal.

Description

Technical Field

[0001] The invention relates to a synchronization method and a control device. Background Art

[0002] The numerical control device controls the position or speed of each of the multiple motors such as the servo motor included in the machine tool or robot by real-time communication, thereby performing the processing of complex shapes. Therefore, the communication cycle timing signal generated by the communication control circuit included in the numerical control device according to the communication cycle and the communication cycle timing signal generated by the amplifier of each motor need to be synchronized with high precision. In addition, the communication cycle timing signal of the communication control circuit needs to be synchronized with the basic timing signal, which represents the basic unit time of the action of the numerical control device generated by the basic timing signal generation circuit included in the numerical control device.

[0003] Furthermore, when the numerical controller of the master unit is connected to the numerical controller of the slave unit, it is also necessary to synchronize the basic timing signal of the master unit with the basic timing signal of the slave unit.

[0004] In this regard, a technology is known in which, even if a deviation occurs in the basic timing signals of the master unit and the slave unit due to communication abnormality between the master unit's numerical controller and the slave unit's numerical controller, the deviation is corrected to achieve synchronization.

[0005] Prior art literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2006-244264

[0007] However, in the numerical control device, there is a situation where the clock sources of the basic timing signal generated by the basic timing signal generating circuit and the communication cycle timing signal generated by the communication control circuit are different. In this case, whenever the communication control circuit performs real-time communication, it is necessary to make the communication cycle timing signal of the communication control circuit follow the basic timing signal. However, for example, during the basic timing signal with a 4ms interval, when the communication control circuit performs 256 communications, the interval of the communication cycle timing signal (1 communication cycle) is 15.625us, but because the clocks that serve as the reference are different, the accuracy error of the clock may cause a deviation between the basic timing signal and the communication cycle timing signal.

[0008] Fig. 9 It is a diagram showing an example of the control device 1 .

[0009] like Fig. 9As shown, the control device 1 includes a basic timing signal generating circuit 2 and a communication control circuit 3. The communication control circuit 3 of the control device 1 is connected to n amplifiers 10(1) to 10(n) (n is an integer greater than or equal to 1).

[0010] The control device 1 is a numerical control device known to those skilled in the art, and controls the operation of a machine tool not shown. When the machine tool not shown is a robot, the control device 1 may include a robot control device or the like.

[0011] The amplifiers 10(1)-10(n) may also be included in a machine tool or robot (not shown) that is controlled by the control device 1. Hereinafter, when it is not necessary to distinguish the amplifiers 10(1)-10(n) individually, they are collectively referred to as "amplifiers 10".

[0012] The basic timing signal generating circuit 2 generates a basic timing signal indicating a basic unit time of the operation of the control device 1 .

[0013] like Fig. 10A As shown, the communication control circuit 3 generates a communication cycle timing signal (hereinafter also referred to as "timing signal EXSYN") according to the communication cycle (15.625us). In addition, the communication control circuit 3 transmits a data packet PK including timing correction data stored in a header portion together with control data for the motor of each amplifier 10 according to the timing signal EXSYN generated according to one communication cycle.

[0014] For example, Fig. 10B As shown, the amplifier 10(1) measures in advance the time T from the communication cycle timing signal (hereinafter also referred to as "timing signal EXSYN1") of the amplifier 10(1) generated in 1 communication cycle until the timing correction data of the data packet PK is received. The amplifier 10(1) compares the timing of the pre-measured time T until the timing correction data is received with the timing of the timing correction data of the data packet PK actually received, based on the clock signal of the clock (not shown) included in the amplifier 10(1). The amplifier 10(1) can determine whether to shift the next timing signal EXSYN1 based on the comparison result to correct the deviation between the control device 1 and the amplifier 10(1).

[0015] In addition, the synchronization process of the amplifiers 10(2)-10(n) is the same as the synchronization process of the amplifier 10(1).

[0016] The communication control circuit 3 of the control device 1 and each amplifier 10 need to be synchronized with high precision. On the other hand, the communication control circuit 3 needs to synchronize the timing signal EXSYN with the basic timing signal generated by the basic timing signal generating circuit 2. However, when the basic timing signal generating circuit 2 and the communication control circuit 3 operate with different clocks, a synchronization circuit is required to synchronize the basic timing signal generating circuit 2 and the communication control circuit 3. Summary of the invention

[0017] However, there is a problem that the deviation between the control device 1 and the amplifier 10 ( 1 ) cannot be substantially corrected in the correction process for synchronizing the basic timing signal generation circuit 2 and the communication control circuit 3 , resulting in a decrease in synchronization accuracy.

[0018] (1) One aspect of the synchronization method disclosed in the present invention is a synchronization method for real-time communication between a control device including a basic timing signal generating circuit and a communication control circuit operating with clocks different from each other and at least one external device, comprising the following steps: a basic timing signal generating step, wherein the basic timing signal generating circuit generates a basic timing signal representing a basic unit time of the operation of the control device; a first communication cycle timing signal generating step, wherein the communication control circuit generates a first communication cycle timing signal representing a communication cycle with the external device; an input difference step, wherein the communication control circuit measures an input difference of a specified first communication cycle timing signal relative to the basic timing signal; and a correction timing averaging step, wherein the communication control circuit divides a correction amount corresponding to the input difference measured in the input difference step by the correction amount corresponding to the basic timing signal. The number of the first communication cycle timing signals generated within the interval of the basic timing signal, the values ​​obtained by division operation are added according to the communication cycle, and the timing of generating the first communication cycle timing signal is corrected when the added value is greater than the specified value; a sending step, the communication control circuit sends a data packet containing timing correction data representing the correction of the timing for generating the first communication cycle timing signal to the external device according to the communication cycle; a second communication cycle timing signal generating step, the external device generates a second communication cycle timing signal representing the communication cycle with the control device; and a synchronization step, the external device corrects the timing of generating the second communication cycle timing signal according to the timing of the timing correction data received from the data packet to synchronize it with the first communication cycle timing signal.

[0019] (2) One mode of the control device disclosed in the present invention is a control device comprising a basic timing signal generating circuit and a communication control circuit which operate at different clocks from each other, and which communicates with at least one external device in real time, wherein the basic timing signal generating circuit generates a basic timing signal representing a basic unit time of the operation of the control device, and the communication control circuit comprises: a communication cycle timing signal generating circuit which generates a communication cycle timing signal representing a communication cycle with the external device; an input difference counter which measures an input difference of a specified communication cycle timing signal relative to the basic timing signal; and a correction timing averaging circuit which divides a correction amount corresponding to the input difference measured by the input difference counter by the number of communication cycle timing signals generated within the interval of the basic timing signal, and adds the values ​​obtained by the division operation according to the communication cycle, thereby correcting the timing of the communication cycle timing signal generated by the communication cycle timing signal generating circuit when the added value is greater than a specified value, and the communication control circuit sends a data packet including timing correction data representing the correction of the timing for generating the communication cycle timing signal to the external device according to the communication cycle.

[0020] Effects of the Invention

[0021] According to one aspect, even when the basic timing signal generating circuit and the communication control circuit operate with different clocks, the synchronization accuracy between the communication control circuit and the external device can be maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a diagram schematically illustrating a synchronization circuit for synchronizing a basic timing signal generation circuit and a communication control circuit.

[0023] Figure 2 This is a diagram showing an example of the relationship between the basic timing signal and the communication cycle timing signal.

[0024] Figure 3 is an example Figure 1 FIG. 1 is a diagram of a circuit diagram of the details of the synchronization circuit.

[0025] Figure 4 This is a diagram for explaining an example of a frequency deviation between a communication control circuit and an amplifier.

[0026] Figure 5 This is a diagram showing an example of a synchronization circuit included in the communication control circuit of the control device according to the first embodiment.

[0027] Figure 6 This is a diagram showing an example of the relationship between a basic timing signal, a communication cycle timing signal of a communication control circuit, and a communication cycle timing signal of an amplifier.

[0028] Figure 7 This is a diagram showing an example of a case where the control device according to the second embodiment performs Ethernet synchronization of a basic timing signal with other control devices.

[0029] Figure 8 This is a diagram showing an example of a synchronization circuit included in a communication control circuit of a control device according to the second embodiment.

[0030] Fig. 9 This is a diagram showing an example of a control device.

[0031] Fig. 10A This is a diagram showing an example of a communication cycle timing signal and a data packet generated by a communication control circuit.

[0032] Fig. 10B This is a diagram for explaining an example of synchronization processing in an amplifier.

[0033] Description of Reference Numerals

[0034] 1. 1A control device;

[0035] 2 Basic timing signal generation circuit;

[0036] 3. Communication control circuit;

[0037] 10(1)-10(n) amplifiers;

[0038] 30 Input difference counter;

[0039] 100, 100A synchronous circuit;

[0040] 110 communication cycle timing signal generating circuit;

[0041] 200 division circuit;

[0042] 210 Adding circuits;

[0043] 300 upper limit setting register;

[0044] 310 comparison circuit. DETAILED DESCRIPTION

[0045] Before describing the first embodiment, a basic configuration of a synchronization circuit for synchronizing the basic timing signal generation circuit 2 and the communication control circuit 3 when the basic timing signal generation circuit 2 and the communication control circuit 3 have different clocks will be described.

[0046] Unless otherwise specified, Fig. 9 Elements having the same functions as those shown are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0047] Figure 1 1 is a diagram schematically illustrating a synchronization circuit 50 for synchronizing the basic timing signal generation circuit 2 and the communication control circuit 3. The synchronization circuit 50 is included in the communication control circuit 3.

[0048] In the following description, for example, it is assumed that the basic timing signal 2 is generated every 4 ms. In addition, the timing signal EXSYN of the communication control circuit 3 is generated every 15.625 us so that 256 communications are performed during the 4 ms period between the basic timing signals. In addition, for example, the basic timing signal may be generated at a time interval other than 4 ms, and the timing signal EXSYN may be generated at a time interval other than 15.625 us.

[0049] Figure 1 The synchronous circuit 50 shown includes an input difference counter 30 , an adder 31 , an LPF (Low-Pass Filter) 32 , and a correction counter 33 .

[0050] like Figure 2 As shown, the input difference counter 30 measures the input difference between the basic timing signal and the 256th timing signal EXSYN based on a clock signal from a clock (not shown), and counts the difference as the number of clocks.

[0051] The adder 31 outputs a value obtained by adding the clock count Δt from the input difference counter 30 and the feedback value from the LPF 32 to the correction counter 33 .

[0052] The correction counter 33 shifts the timing signal EXSYN of the number represented by the value received from the adder 31 forward by one clock or backward by one clock so that it follows the basic timing signal.

[0053] Here, the reason why the adder 31 adds the feedback value from the LPF 32 to the number of clocks Δt from the input difference counter 30 is as follows. As described above, the communication control circuit 3 shifts each of the timing signals EXSYN, which are the same number of clocks as the counted number, forward by one clock or backward by one clock to follow the basic timing signal. However, when there is only the number of clocks Δt from the input difference counter 30, the deviation between the basic timing signal and the 256th timing signal EXSYN continues to appear forever. Therefore, the adder 31 adds the feedback value from the LPF 32 to the number of clocks Δt from the input difference counter 30, so that the basic timing signal and the 256th timing signal EXSYN are synchronized.

[0054] Figure 2 It is to make Figure 1 A diagram illustrating an example of a process in which a basic timing signal involved in synchronization processing is synchronized with a timing signal EXSYN.

[0055] like Figure 2 As shown in FIG. 1 , the input difference counter 30 counts the input difference between the basic timing signal from the basic timing signal generating circuit 2 and the 256th timing signal EXSYN as the clock number Δt based on the clock signal from the clock (not shown) included in the communication control circuit 3. When the added value from the adder 31 is -3 clocks, the correction counter 33 counts Figure 2 The first, second, and third consecutive timing signals EXSYN after the 256th timing signal EXSYN are shifted forward by one clock and follow the basic timing signal. Thus, the communication control circuit 3 can be synchronized with the basic timing signal generation circuit 2.

[0056] Figure 3 is an example Figure 1 FIG. 5 is a diagram of a detailed circuit diagram of the synchronization circuit 50 .

[0057] Figure 3 The illustrated synchronization circuit 50 includes, for example, an input difference counter 30 , an adder 31 , an LPF 32 , a correction counter 33 , a communication cycle timing signal generating circuit 110 , a 256 counter 120 , an operation timing circuit 130 , and a correction direction determining circuit 140 .

[0058] In addition, known elements can be used for each element of a latch, an absolute value, and a sign, and detailed description thereof will be omitted.

[0059] The communication cycle timing signal generating circuit 110 generates the timing signal EXSYN according to 1 communication cycle (for example, 1296 clocks) based on the clock signal from the clock (not shown) included in the communication control circuit 3, for example, when the signal of "1" is not input to the "+" and "-" terminals from the correction direction determining circuit 140 described later. On the other hand, when the signal of "1" is input to the "+" terminal from the correction direction determining circuit 140 described later, the communication cycle timing signal generating circuit 110 generates the timing signal EXSYN with 1297 clocks as 1 communication cycle. That is, the communication cycle timing signal generating circuit 110 generates the timing signal EXSYN at a timing that is shifted backward by 1 clock. In addition, when the signal of "1" is input to the "-" terminal from the correction direction determining circuit 140 described later, the communication cycle timing signal generating circuit 110 generates the timing signal EXSYN with 1295 clocks as 1 communication cycle. That is, the communication cycle timing signal generating circuit 110 generates the timing signal EXSYN at a timing that is shifted forward by 1 clock.

[0060] In addition, although one communication cycle is set to 1296 clocks, it may be set to another number of clocks.

[0061] The 256 counter 120 counts the number of timing signals EXSYN generated by the communication cycle timing signal generating circuit 110, and outputs one signal every 256 (ie, every 4 ms) to the input difference counter 30 and the operation timing circuit 130 described later.

[0062] As described above, the input difference counter 30 measures the input difference between the basic timing signal and the 256th timing signal EXSYN which is the prescribed timing signal EXSYN.

[0063] More specifically, the input difference counter 30 counts the input difference between the basic timing signal and the 256th timing signal EXSYN as the number of clocks based on the clock signal of the clock (not shown) from the communication control circuit 3. When the input of the terminal B (basic timing signal) is earlier than the input of the terminal A (256th timing signal EXSYN), the input difference counter 30 outputs a count value of the negative number of clocks to the adder 31. On the other hand, when the input of the terminal B (basic timing signal) is later than the input of the terminal A (256th timing signal EXSYN), the input difference counter 30 outputs a count value of the positive number of clocks to the adder 31.

[0064] The correction counter 33 sets the absolute value of the value obtained by adding the clock count Δt input to the difference counter 30 and the feedback value of the LPF 32 by the adder 31 at the timing when the signal from the action timing circuit 130 described later is input to the "Load" terminal. The correction counter 33 decrements the set value by one each time the timing signal EXSYN from the communication cycle timing signal generating circuit 110 is input to the "-1" terminal. When the set value is 1 or more, the correction counter 33 outputs a signal of "1" to the correction direction determining circuit 140 described later at the timing when the set value is decremented by one.

[0065] The action timing circuit 130 outputs a signal to each element of the LPF 32, the latch, and the correction counter 33 at the timing of the input of the signal later than the 256th timing signal EXSYN and the basic timing signal. Thus, each element of the LPF 32, the latch, and the correction counter 33 operates at the timing of receiving the signal from the action timing circuit 130.

[0066] The correction direction determination circuit 140 outputs a signal of "1" from the terminal "+" when a signal of "1" is input from the correction counter 33 to the terminal A and a signal of "0" is input to the terminal "Sign" (i.e., the count value of the adder 31 is positive). In this case, the communication cycle timing signal generation circuit 110 generates a timing signal EXSYN that is shifted backward by 1 clock with 1297 clocks as 1 communication cycle. On the other hand, the correction direction determination circuit 140 outputs a signal of "1" from the terminal "-" when a signal of "1" is input from the correction counter 33 to the terminal A and a signal of "1" is input to the terminal "Sign" (i.e., the count value of the adder 31 is negative). Thus, the communication cycle timing signal generation circuit 110 generates a timing signal EXSYN that is shifted forward by 1 clock with 1295 clocks as 1 communication cycle.

[0067] But, for example, in Figure 3 When the value obtained by adding the clock number Δt of the input difference counter 30 and the feedback value of the LPF 32 is "-32" clocks, as shown in FIG. Figure 4 As shown, in order to catch up with the basic timing signal, the communication control circuit 3 generates 32 timing signals EXSYN that are shifted forward by 1 clock (corrected by -1 clock) from the first one. Figure 4 As shown, in order to synchronize the amplifier 10 with the timing signal EXSYN of the communication control circuit 3, 32 timing signals EXSYN1 corrected by -1 clock are continuously generated from the second one.

[0068] The timing signal EXSYN of the communication control circuit 3 is corrected in the direction of the basic timing signal, so the timing signal EXSYN1 of the amplifier 10 also follows. Figure 4 As shown, for example, when the timing signal EXSYN of the communication control circuit 3 is corrected in the negative direction, the clock frequency of the timing signal EXSYN1 of the amplifier 10 is lower than the clock frequency of the timing signal EXSYN due to the accuracy error, the timing signal EXSYN and the timing signal EXSYN1 of the amplifier 10 are always corrected during the period of generating 32 timing signals EXSYN that are shifted forward by 1 clock. As a result, the control device 1 and the amplifier 10 cannot be corrected, and the synchronization error caused by the frequency deviation may accumulate.

[0069] Similarly, when the timing signal EXSYN of the communication control circuit 3 is corrected in the positive direction, if the clock frequency of the timing signal EXSYN1 generated by the amplifier 10 is higher than the clock frequency of the timing signal EXSYN generated by the communication control circuit 3 due to the accuracy error, the synchronization error caused by the frequency deviation may accumulate while the communication control circuit 3 corrects the timing signal EXSYN in the positive direction.

[0070] In the synchronization circuit for synchronizing the basic timing signal generating circuit 2 and the communication control circuit 3 as described above, there is a risk that synchronization errors due to frequency deviations may accumulate.

[0071] <First embodiment>

[0072] Therefore, in the first embodiment, the synchronization circuit 100 of the communication control circuit 3 has, for example, a correction timing averaging circuit that eliminates the deviation between the basic timing signal and the 256th timing signal EXSYN when the deviation is smaller than 256 clocks. Thus, the timing signal EXSYN can be corrected on an average basis at the interval (4 ms) of the basic timing signal.

[0073] First, the outline of this embodiment is described. In this embodiment, the synchronization circuit 100 of the communication control circuit 3 has: a correction timing averaging circuit, which divides the correction amount corresponding to the input difference measured by the input difference counter by the number of timing signals EXSYN generated in the interval of the basic timing signal, adds the values ​​obtained by the division operation according to the communication cycle, and corrects the timing of the communication cycle timing signal generation circuit 110 generating the timing signal EXSYN when the added value is greater than the specified value. The synchronization circuit 100 generates the timing signal EXSYN that is greater than the specified value in the timing signal EXSYN, that is, the timing signal EXSYN generated at the separated intervals, by shifting forward by 1 clock or backward by 1 clock one by one through the correction timing averaging circuit. Then, the amplifier 10 corrects the synchronization error caused by the frequency deviation between the timing signal EXSYN of the communication control circuit 3 and the timing signal EXSYN1 of the amplifier 10 at the timing when the communication control circuit 3 does not correct the timing signal EXSYN.

[0074] Thus, according to the present embodiment, even when the basic timing signal generating circuit 2 and the communication control circuit 3 operate with different clocks, the synchronization accuracy between the communication control circuit 3 and the amplifier 10 can be maintained.

[0075] Next, the configuration of the first embodiment will be described in detail using the drawings.

[0076] <Synchronous circuit 100>

[0077] Figure 5 1 is a diagram showing an example of a synchronization circuit 100 included in the communication control circuit 3 of the control device 1 according to the present embodiment. Figure 3 Elements having the same functions as the elements of the synchronization circuit 50 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0078] Figure 5The synchronization circuit 100 shown in the figure includes, for example, a communication cycle timing signal generating circuit 110, a 256 counter 120, an input difference counter 30, an adder 31, an LPF 32, a dividing circuit 200, an adding circuit 210, an action timing circuit 130, and a correction direction determining circuit 140. That is, the synchronization circuit 100 replaces Figure 3 The correction counter 33 includes a division circuit 200 and an addition circuit 210. The division circuit 200 and the addition circuit 210 cooperate with each other to function as a correction timing averaging circuit.

[0079] The division circuit 200 divides the correction amount corresponding to the input difference measured by the input difference counter 30 by the number of timing signals EXSYN generated during the interval of the basic timing signal.

[0080] As an example, when the value obtained by adding the clock count Δt of the input difference counter 30 and the feedback value of the LPF 32 by the adder 31 is a correction value of "-64" clock, the division circuit 200 divides the value of "64" by the value of "256". The division circuit 200 outputs the value "0.25" obtained by the division operation to the addition circuit 210.

[0081] In addition, when the number of timing signals EXSYN generated in the interval of the basic timing signal is a power of 2 such as "256", the division circuit 200 may be a shift circuit.

[0082] The adding circuit 210 adds the divided values ​​for each communication cycle, and corrects the timing at which the communication cycle timing signal generating circuit 110 generates the timing signal EXSYN when the added value reaches a predetermined value.

[0083] More specifically, the adding circuit 210 adds the value "0.25" obtained by the division operation to obtain the values ​​of "0.25", "0.5", "0.75", and "1.0" each time the timing signal EXSYN is received from the communication cycle timing signal generating circuit 110. For example, when the predetermined value is preset to "1" and the value obtained by the addition is equal to or greater than "1.0", the adding circuit 210 outputs a signal of "1" from the "one bit" terminal to the correction direction determining circuit 140, and sets one bit of the value obtained by the addition to "0". Thereafter, the adding circuit 210 adds the value "0.25" obtained by the division operation each time the timing signal EXSYN is received from the communication cycle timing signal generating circuit 110.

[0084] Figure 6 1 is a diagram showing an example of the relationship between the basic timing signal, the timing signal EXSYN of the communication control circuit 3, and the timing signal EXSYN1 of the amplifier 10(1).

[0085] As described above, the adding circuit 210 receives the four timing signals EXSYN and outputs a signal of "1" from the "one bit" terminal to the correction direction determining circuit 140. Figure 6 As shown, the communication cycle timing signal generating circuit 110 corrects the timing of the 64 timing signals EXSYN after thinning out, such as the 4th and 8th timing signals once out of four times among the generated 256 timing signals EXSYN, thereby achieving synchronization with the basic timing signal.

[0086] In addition, amplifier 10 (1) corrects the timing of the 64 timing signals EXSYN1 after thinning out once in four times, such as the 5th and 9th, based on the data packet PK received from the communication control circuit 3 in one communication cycle, thereby being synchronized with the timing signal EXSYN of the communication control circuit 3.

[0087] On the other hand, the communication control circuit 3 does not correct the timing signal EXSYN three times out of four. Therefore, during the period when the communication control circuit 3 does not correct the timing signal EXSYN, the amplifier 10(1) can correct the timing of generating the timing signal EXSYN1 based on the data packet PK received from the communication control circuit 3 in one communication cycle. As a result, the amplifier 10(1) can suppress the accumulation of synchronization errors caused by frequency deviations and maintain the synchronization accuracy with the control device 1.

[0088] As described above, the synchronization circuit 100 of the communication control circuit 3 of the first embodiment divides the correction amount corresponding to the input difference measured by the input difference counter 30 by the number of timing signals EXSYN generated in the interval of the basic timing signal, and adds the values ​​obtained by the division operation for each communication cycle. The synchronization circuit 100 corrects the timing of generating the timing signal EXSYN by the communication cycle timing signal generating circuit 110 when the added value is equal to or greater than a predetermined value. Thus, the synchronization circuit 100 can synchronize the basic timing signal generating circuit 2 with the communication control circuit 3 even when the basic timing signal generating circuit 2 and the communication control circuit 3 operate with different clocks.

[0089] Furthermore, the amplifier 10 corrects the synchronization error caused by the frequency deviation between the timing signal EXSYN of the communication control circuit 3 and the timing signal EXSYN1 of the amplifier 10 at the timing when the communication control circuit 3 does not correct the timing signal EXSYN. Thus, the accumulation of synchronization errors caused by the frequency deviation between the timing signal EXSYN of the communication control circuit 3 and the timing signal EXSYN1 of the amplifier 10 can be suppressed.

[0090] That is, the synchronization circuit 100 has, for example, a correction timing averaging circuit that eliminates the deviation between the basic timing signal and the 256th timing signal EXSYN when the deviation is smaller than 256 clocks. Thus, the timing signal EXSYN can be corrected at an average interval (4 ms) of the basic timing signal.

[0091] The first embodiment has been described above.

[0092] <Second embodiment>

[0093] On the other hand, for example, when the control device 1A performs Ethernet (registered trademark) synchronization of the basic timing signal with the other control device 1B, the basic timing signal input to the communication control circuit 3 is compared with the basic timing signal of the other control device 1B, and as a result, the basic timing signal input to the communication control circuit 3 is sometimes input with a large deviation with respect to the 256th timing signal EXSYN. In this case, the synchronization circuit 100 of the communication control circuit 3 requires a time longer than the interval (4ms) of the basic timing signal in order to eliminate the deviation. Therefore, even if the synchronization circuit 100 has the corrected timing averaging circuit (division circuit 200 and addition circuit 210) of the first embodiment, since the synchronization circuit 100 always follows the basic timing signal, the synchronization error caused by the accuracy error of the clocks of the communication control circuit 3 and the amplifier 10 is accumulated.

[0094] Therefore, in the second embodiment, the synchronization circuit 100A of the communication control circuit 3 has, in addition to the functions of the first embodiment, an upper limit value setting register 300, which sets the upper limit value for the correction amount; and a comparison circuit 310, which compares the correction amount with the upper limit value, outputs the correction amount to the correction timing averaging circuit when the correction amount is below the upper limit value, and outputs the upper limit value as the correction amount to the correction timing averaging circuit when the correction amount is larger than the upper limit value.

[0095] Therefore, when the basic timing signal is input to the communication control circuit 3 with a large deviation relative to the 256th timing signal EXSYN, the synchronization circuit 100A can maintain the synchronization accuracy between the communication control circuit 3 and the amplifier 10 even if the basic timing signal generating circuit 2 and the communication control circuit 3 operate with different clocks.

[0096] Hereinafter, a second embodiment will be described.

[0097] Figure 7 1A according to the second embodiment is a diagram showing an example of Ethernet synchronization of a basic timing signal between a control device 1A and another control device 1B. Fig. 9 Elements having the same functions as those of the control device 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0098] like Figure 7 As shown, the basic timing signal generating circuit 2 of the control device 1A and the basic timing signal generating circuit 2 of the control device 1B are connected to each other to perform Ethernet synchronization of the basic timing signal. In this case, as a result of the control device 1A matching the basic timing signal with the basic timing signal of the control device 1B, the basic timing signal input to the communication control circuit 3 may be input with a large deviation relative to the 256th timing signal EXSYN. In order to eliminate the deviation, the communication control circuit 3 of the control device 1A needs a time longer than the interval (for example, 4ms) of the basic timing signal.

[0099] In this case, even if the communication control circuit 3 of the control device 1A has Figure 5 The correction timing averaging circuit also always follows the basic timing signal. In addition, the synchronization error caused by the accuracy error of the clock (not shown) of the communication control circuit 3 and the amplifier 10 is accumulated.

[0100] <Synchronous circuit 100A>

[0101] Figure 8 FIG. 1 is a diagram showing an example of a synchronization circuit 100A included in the communication control circuit 3 of the control device 1A according to the second embodiment. Figure 5 Elements having the same functions as the elements of the synchronization circuit 100 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0102] like Figure 8 As shown, the synchronization circuit 100A includes a communication cycle timing signal generating circuit 110, a 256-bit counter 120, an input difference counter 30, an adder 31, an LPF 32, a dividing circuit 200, an adding circuit 210, an operation timing circuit 130, a correction direction determining circuit 140, an upper limit value setting register 300, and a comparison circuit 310. The upper limit value setting register 300 and the comparison circuit 310 cooperate to function as an upper limit value setting circuit.

[0103] The upper limit value setting register 300 sets an upper limit value for a correction amount obtained by adding the clock count Δt input to the difference counter 30 and the feedback value of the LPF 32 by the adder 31 .

[0104] For example, the upper limit value setting register 300 may set “128” as the upper limit value.

[0105] In addition, the upper limit value may be a value other than "128" as long as it is a value smaller than the number of timing signals EXSYN generated during the interval of the basic timing signal.

[0106] Comparison circuit 310 compares the correction amount with the upper limit value, and outputs the correction amount to the correction timing averaging circuit when the correction amount is less than the upper limit value, and outputs the upper limit value as the correction amount to the correction timing averaging circuit when the correction amount is greater than the upper limit value.

[0107] For example, the comparison circuit 310 compares the correction amount of the value obtained by adding the clock count Δt of the input difference counter 30 and the feedback value of the LPF 32 input to the terminal A by the adder 31 with the upper limit value "128" of the upper limit value setting register 300 input to the terminal B. When the correction amount of the value obtained by adding the clock count Δt of the input difference counter 30 and the feedback value of the LPF 32 by the adder 31 is "-64" clocks, the comparison circuit 310 outputs the value "64" to the division circuit 200.

[0108] On the other hand, when the correction amount of the value obtained by adding the clock count Δt of the input difference counter 30 and the feedback value of the LPF 32 by the adder 31 is "-300" clocks, the comparison circuit 310 outputs the value of the upper limit value "128" to the division circuit 200. In this case, since the value obtained by the division operation performed by the division circuit 200 is "0.5" (=128 / 256) for the addition circuit 210, the timing of generating the timing signal EXSYN once out of the two times by the communication cycle timing signal generation circuit 110 can be corrected.

[0109] In this case, the communication control circuit 3 does not correct the timing signal EXSYN once out of the two times. Therefore, the amplifier 10(1) can correct the timing of generating the timing signal EXSYN1 based on the data packet PK received from the communication control circuit 3 in one communication cycle during the period when the communication control circuit 3 does not correct the timing signal EXSYN. As a result, the amplifier 10(1) can suppress the accumulation of synchronization errors caused by frequency deviations and maintain the synchronization accuracy with the control device 1A.

[0110] As described above, when the synchronization circuit 100A of the communication control circuit 3 of the second embodiment performs Ethernet synchronization of the basic timing signal with the other control device 1B, for example, the correction amount corresponding to the input difference measured by the input difference counter 30 is compared with the upper limit value set in the upper limit value setting register 300. When the correction amount is less than the upper limit value, the synchronization circuit 100A outputs the correction amount to the division circuit 200, and when the correction amount is greater than the upper limit value, the upper limit value is output as the correction amount to the division circuit 200.

[0111] Therefore, when the basic timing signal is input to the communication control circuit 3 with a large deviation relative to the 256th timing signal EXSYN, the synchronization circuit 100A can synchronize the basic timing signal generating circuit 2 and the communication control circuit 3 even when the basic timing signal generating circuit 2 and the communication control circuit 3 operate with different clocks.

[0112] Furthermore, the amplifier 10 corrects the synchronization error caused by the frequency deviation between the timing signal EXSYN of the communication control circuit 3 and the timing signal EXSYN1 of the amplifier 10 at the timing when the communication control circuit 3 does not correct the timing signal EXSYN. Thus, the accumulation of the synchronization error caused by the frequency deviation between the timing signal EXSYN of the communication control circuit 3 and the timing signal EXSYN1 of the amplifier 10 can be suppressed.

[0113] The second embodiment has been described above.

[0114] As mentioned above, although the 1st embodiment and the 2nd embodiment were demonstrated, the control apparatus 1, 1A is not limited to the said embodiment, and includes the deformation|transformation, improvement, etc. within the range which can achieve an objective.

[0115] <Variation 1>

[0116] In the first and second embodiments described above, the basic timing signal is generated at 4 ms, and the timing signal EXSYN is generated at 15.625 us so that 256 timing signals EXSYN are generated in the interval of 4 ms of the basic timing signal, but the present invention is not limited thereto. For example, the basic timing signal may be generated at a time interval other than 4 ms, and the timing signal EXSYN may be generated in a manner such that a number other than 256 is generated in the interval of the basic timing signal.

[0117] Furthermore, when the number of timing signals EXSYN generated in the interval of the basic timing signal is a power of 2 such as "128" or "512", the division circuit 200 may be a shift circuit.

[0118] <Variation 2>

[0119] Furthermore, for example, in the second embodiment, the control device 1A performs Ethernet synchronization of the basic timing signal with the other control device 1B. However, the control device 1A may perform synchronization of the basic timing signal other than Ethernet synchronization with the other control device 1B.

[0120] Furthermore, the control device 1A may perform Ethernet synchronization of basic timing signals with a plurality of other control devices 1B.

[0121] In addition, each function included in the control device 1 and 1A according to the first embodiment and the second embodiment can be realized by hardware, software, or a combination thereof. Here, the term "realized by software" means that the computer reads the program and executes it.

[0122] Each structural unit included in the control device 1, 1A can be implemented by hardware including electronic circuits, software, or a combination thereof. When implemented by software, the program constituting the software is installed in a computer. In addition, these programs can be recorded in a removable medium and distributed to users, or downloaded to the user's computer via a network for distribution. In addition, when constituted by hardware, for example, a part or all of the functions of each structural unit included in the above-mentioned device can be constituted by an integrated circuit (IC) such as ASIC (Application Specific Integrated Circuit), gate array, FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device).

[0123] Various types of non-transitory computer readable media (Non-transitory computer readable medium) can be used to store the program and provide it to the computer. Non-transitory computer readable media include various types of tangible storage media (Tangible storage medium). Examples of non-transitory computer readable media include: magnetic storage media (e.g., floppy disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., optical magnetic disks), CD-ROM (Read Only Memory), CD-R, CD-R / W, semiconductor memory (e.g., mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM). In addition, the program can be supplied to the computer via various types of transient computer readable media (Transitory computer readable medium). Examples of transient computer readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer readable media can supply the program to the computer via wired communication paths such as wires and optical fibers or wireless communication paths.

[0124] Furthermore, regarding the steps describing the program recorded in the recording medium, it goes without saying that the processing is performed in time series according to the order, and also includes processing that is not necessarily performed in time series and processing that is executed in parallel or individually.

[0125] In other words, the synchronization method and control device of the present disclosure can take various embodiments having the following structures.

[0126] (1) The synchronization method disclosed in the present invention is a synchronization method for real-time communication between a control device 1 and at least one external device (amplifier 10) comprising a basic timing signal generating circuit 2 and a communication control circuit 3 operating with clocks different from each other, and comprises the following steps: a basic timing signal generating step, in which the basic timing signal generating circuit 2 generates a basic timing signal representing a basic unit time of the operation of the control device; a first communication cycle timing signal generating step, in which the communication control circuit 3 generates a first communication cycle timing signal representing a communication cycle with the external device; an input difference step, in which the communication control circuit 3 measures an input difference of a prescribed first communication cycle timing signal with respect to the basic timing signal; and a corrected timing averaging step, in which the communication control circuit 3 averages the input difference corresponding to the input difference measured by the input difference step. The correction amount is divided by the number of the first communication cycle timing signals generated within the interval of the basic timing signal, the values ​​obtained by the division are added according to the communication cycle, and the timing for generating the first communication cycle timing signal is corrected when the added value is greater than the specified value; a sending step, the communication control circuit 3 sends a data packet PK containing timing correction data indicating the correction of the timing for generating the first communication cycle timing signal to the external device according to the communication cycle; a second communication cycle timing signal generating step, the external device generates a second communication cycle timing signal indicating the communication cycle with the control device; and a synchronization step, the external device corrects the timing for generating the second communication cycle timing signal according to the timing of the timing correction data of the received data packet PK, and synchronizes it with the first communication cycle timing signal.

[0127] According to this synchronization method, even when the basic timing signal generating circuit 2 and the communication control circuit 3 operate with different clocks, the synchronization accuracy between the communication control circuit 3 and the amplifier 10 ( 1 ) can be ensured.

[0128] (2) The synchronization method described in (1) may further include the following steps: an upper limit value setting step for setting an upper limit value for the correction amount; and a comparison step for comparing the correction amount with the upper limit value, outputting the correction amount when the correction amount is below the upper limit value, and outputting the upper limit value as the correction amount when the correction amount is greater than the upper limit value.

[0129] In this way, even when the control device performs Ethernet synchronization with other control devices, the synchronization accuracy between the communication control circuit 3 and the amplifier 10 ( 1 ) can be guaranteed.

[0130] (3) In the synchronization method described in (1) or (2), the number of first communication cycle timing signals generated during the interval of the basic timing signal is a power of 2.

[0131] This can reduce the amount of computation required to perform division operations.

[0132] (4) The control device 1 disclosed in the present invention is a control device that includes a basic timing signal generating circuit 2 and a communication control circuit 3 that operate at different clocks from each other, and that communicates with at least one external device (amplifier 10) in real time. The basic timing signal generating circuit 2 generates a basic timing signal that represents a basic unit time of the operation of the control device. The communication control circuit 3 includes: a communication cycle timing signal generating circuit 110 that generates a communication cycle timing signal that represents a communication cycle with the external device; an input difference counter 30 that measures an input difference of a specified communication cycle timing signal relative to the basic timing signal; and a correction timing averaging circuit that divides a correction amount corresponding to the input difference measured by the input difference counter 30 by the number of communication cycle timing signals generated in an interval of the basic timing signal, and adds the values ​​obtained by the division operation according to the communication cycle, thereby correcting the timing of the communication cycle timing signal generated by the communication cycle timing signal generating circuit 110 when the added value is greater than a specified value, and the communication control circuit 3 sends a data packet PK including timing correction data representing the correction of the timing for generating the communication cycle timing signal to the external device according to the communication cycle.

[0133] According to this control device, the same effect as (1) can be obtained.

[0134] (5) The control device 1 described in (4) may further include: an upper limit value setting register 300, which sets an upper limit value for the correction amount; and a comparison circuit 310, which compares the correction amount with the upper limit value, and outputs the correction amount to a correction timing averaging circuit when the correction amount is below the upper limit value, and outputs the upper limit value as the correction amount to the correction timing averaging circuit when the correction amount is greater than the upper limit value.

[0135] In this way, the same effect as (2) can be obtained.

[0136] (6) In the control device 1 described in (4) or (5), the number of communication cycle timing signals generated during the interval of the basic timing signal may be a power of 2.

[0137] In this way, the same effect as (3) can be obtained.

Claims

1. A synchronization method for real-time communication between a control device including a basic timing signal generating circuit and a communication control circuit operating with clocks different from each other and at least one external device, It is characterized in that The synchronization method has the following steps: a basic timing signal generating step, wherein the basic timing signal generating circuit generates a basic timing signal representing a basic unit time of an operation of the control device; a first communication cycle timing signal generating step, wherein the communication control circuit generates a first communication cycle timing signal indicating a communication cycle with the external device; An input difference step, wherein the communication control circuit measures an input difference of the first communication cycle timing signal relative to the basic timing signal; a correction timing averaging step, wherein the communication control circuit divides a correction amount corresponding to the input difference measured in the input difference step by the number of the first communication cycle timing signals generated within the interval of the basic timing signal, adds the values ​​obtained by the division according to the communication cycle, and corrects the timing of generating the first communication cycle timing signal when the added value is greater than a specified value; a sending step in which the communication control circuit sends a data packet including timing correction data indicating a correction of the timing of generating the first communication cycle timing signal to the external device according to the communication cycle; a second communication cycle timing signal generating step, wherein the external device generates a second communication cycle timing signal indicating a communication cycle with the control device; as well as In a synchronization step, the external device corrects the timing of generating the second communication cycle timing signal based on the timing of receiving the timing correction data of the data packet so as to synchronize the timing with the first communication cycle timing signal.

2. The synchronization method according to claim 1, It is characterized in that The synchronization method further comprises the following steps: an upper limit value setting step of setting an upper limit value for the correction amount; and The comparison step compares the correction amount with the upper limit value, outputs the correction amount when the correction amount is equal to or less than the upper limit value, and outputs the upper limit value as the correction amount when the correction amount is greater than the upper limit value.

3. The synchronization method according to claim 1 or 2, It is characterized in that The number of the first communication cycle timing signals generated within the interval of the basic timing signal is a power of 2.

4. A control device comprising a basic timing signal generating circuit and a communication control circuit operating at different clocks, and communicating with at least one external device in real time, It is characterized in that The basic timing signal generating circuit generates a basic timing signal indicating a basic unit time of the operation of the control device. The communication control circuit has: a communication cycle timing signal generating circuit, which generates a communication cycle timing signal indicating a communication cycle with the external device; an input difference counter for measuring an input difference of a prescribed communication cycle timing signal relative to the basic timing signal; as well as a correction timing averaging circuit that divides a correction amount corresponding to the input difference measured by the input difference counter by the number of the communication cycle timing signals generated within the interval of the basic timing signal, adds the values ​​obtained by the division operation according to the communication cycle, thereby correcting the timing of the communication cycle timing signal generated by the communication cycle timing signal generating circuit when the added value is greater than a specified value, The communication control circuit transmits a data packet including timing correction data indicating correction of timing of generating the communication cycle timing signal to an external device in accordance with the communication cycle.

5. The control device according to claim 4, It is characterized in that The control device has: an upper limit value setting register for setting an upper limit value for the correction amount; and A comparison circuit compares the correction amount with the upper limit value, outputs the correction amount to the correction timing averaging circuit when the correction amount is below the upper limit value, and outputs the upper limit value as the correction amount to the correction timing averaging circuit when the correction amount is greater than the upper limit value.

6. The control device according to claim 4 or 5, It is characterized in that The number of the communication cycle timing signals generated within the interval of the basic timing signal is a power of 2.

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