Semiconductor packaging

Abstract

The present invention discloses a semiconductor package, comprising: a bottom package, including a substrate, a radio frequency die and a system single die arranged in a side-by-side manner on the substrate, a molding compound covering the radio frequency die and the system single die, and an interposer located on the molding compound; a connecting element, arranged on the upper surface of the substrate, wherein the connecting element surrounds the system single die; a signal interference shielding element, arranged between the radio frequency die and the system single die; and a top package, mounted on the interposer. In this way, the signal interference shielding element can block potential digital high-frequency digital signal interference from the circuit, so as to reduce the noise to meet the sensitivity attenuation requirement, so as to protect the signal stability of the package, especially the bottom package.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor package. Background Art

[0002] Semiconductor integrated circuit dies or chips are usually packaged to protect them from external environmental contamination or damage. The package can provide physical protection, stability, and external connections to the die inside the package. In some cases, a dynamic random access memory (DRAM) package can be stacked on a bottom package to form a package-on-package (PoP) package.

[0003] However, the interposer substrate disposed between the top package (i.e., DRAM package) and the bottom package, as well as the high-frequency interconnect traces and / or vias used to communicate with the DRAM chip, can adversely affect the performance of the PoP package, especially when the bottom package includes a vulnerable radio-frequency (RF) chip. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor package, which can reduce noise to meet the requirement of de-sense, so as to protect the signal stability of the package, especially the bottom package.

[0005] According to a first aspect of the present invention, a semiconductor package is disclosed, comprising:

[0006] A bottom package including a substrate, an RF die and a system single die arranged in a side-by-side manner on the substrate, a molding compound covering the RF die and the system single die, and an interposer located on the molding compound;

[0007] a connection element disposed on the upper surface of the substrate, wherein the connection element surrounds the system single die;

[0008] a signal interference shielding element, disposed between the radio frequency die and the system single die; and

[0009] A top package is mounted on the interposer.

[0010] The semiconductor package provided by the present invention includes a signal interference shielding element arranged between the RF die and the system single die, which can prevent potential digital high-frequency digital signal interference from the circuit, thereby reducing noise to meet the sensitivity attenuation requirements and protecting the signal stability of the package, especially the bottom package. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic cross-sectional view showing an exemplary PoP package according to one embodiment of the present invention;

[0012] Figure 2 yes Figure 1 , showing a perspective top view of an exemplary PoP package in FIG. 1 , showing a side-by-side arrangement of an RF die and a SoC (system-on-a-chip) die and an arrangement of connection elements around the RF die and the SoC die in a bottom package of the PoP package;

[0013] Figure 3 is a perspective top view of a PoP package according to another embodiment of the present invention, showing the arrangement of connection elements around the RF die and the SoC die;

[0014] Figure 4 It is shown Figure 1 Schematic partial top view of a separated ground plane configuration of an exemplary PoP package in;

[0015] Figure 5 It is shown Figure 1 A graph of noise versus frequency for a PoP package with and without a separate ground plane;

[0016] Figure 6 is a schematic cross-sectional view of a PoP package according to another embodiment of the present invention;

[0017] Figure 7 is a schematic cross-sectional view of a PoP package according to yet another embodiment of the present invention;

[0018] Figure 8 is a schematic cross-sectional view of a PoP package according to yet another embodiment of the present invention;

[0019] Fig. 9 yes Figure 8 00140 1000 0 ... DETAILED DESCRIPTION

[0020] In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings which are a part of the present invention, and in which specific preferred embodiments in which the present invention can be practiced are shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. Therefore, the following detailed description should not be regarded as having a limiting meaning, and the scope of the embodiments of the present invention is limited only by the appended claims.

[0021] It should be understood that although the present embodiment may use the terms first, second, third, primary, secondary, etc. to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present inventive concept, the first or primary element, component, region, layer or part discussed below may be referred to as a second or secondary element, component, region, layer or part.

[0022] This embodiment may use spatial relative terms, such as "under...", "below...", "below...", "below...", "above...", "above...", etc., to facilitate description of the relationship between one element or feature in the figure and another element or feature. It should be understood that in addition to the directional orientation shown in the figure, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the elements described as "under..." or "under..." or "below" other elements or features will be oriented "above..." or "above" other elements or features. Therefore, the exemplary terms "under..." and "below" can include directions above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article are interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intermediate layers.

[0023] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the", "said" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items and may be abbreviated as " / ".

[0024] It should be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly above, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or intervening elements or layers may be present between the element or layer and the other element or layer. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “directly adjacent to” another element or layer, there are no intervening elements or layers present.

[0025] Note that: (i) like features throughout the figures will be indicated by like reference numerals, and they will not necessarily appear in the detailed description of each figure, and (ii) a series of figures may show different aspects of a single item, with each aspect associated with various reference labels that may appear throughout the sequence, or may appear only in selected figures of the sequence.

[0026] The present invention relates to a semiconductor chip package with reduced noise (less than a noise threshold level) to meet the sensitivity attenuation (de-sense) requirements, which is suitable for 5G (fifth generation mobile communication) or automotive applications. According to some embodiments, the semiconductor chip package can be a package-on-package (PoP) package, which includes a DRAM package (top package) stacked on an RF-SiP (Radio-Frequency System In Package) package (bottom package), but is not limited thereto. Electromagnetic interference to the RF chip or die in the bottom RF-SiP package can be mitigated, and in-package noise originating from high-frequency digital transmission can be reduced.

[0027] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic cross-sectional view of an exemplary PoP package according to one embodiment of the present invention. Figure 2 yes Figure 10014 is a perspective top view of an exemplary PoP package in FIG. 10 , showing the side-by-side arrangement of an RF (radio frequency) die and a SoC (system on chip) die in a bottom package and the arrangement of connecting elements disposed around the RF die and the SoC die.

[0028] like Figure 1 As shown, according to an exemplary embodiment, the PoP package 1 includes a bottom package 10 and a top package 20 stacked on the bottom package 10. According to an exemplary embodiment, the top package 20 may be a memory package, such as a dynamic random access memory (DRAM) package, having at least one packaged DRAM die, such as double data rate 4 (DDR4), low-power DDR4 (LPDDR4), double data rate 5 (DDR5), low-power DDR5 (LPDDR5), etc. According to an exemplary embodiment, the bottom package 10 may include a package substrate 100 having an upper surface 100a and a bottom surface 100b. According to an exemplary embodiment, the RF die D1 and the SoC die D2 are mounted on the upper surface 100a of the package substrate 100 in a side-by-side manner.

[0029] According to an exemplary embodiment, the package substrate 100 may be a multi-layer circuit board or a multi-layer wiring board. For example, the package substrate 100 may be a two-layer, three-layer or four-layer circuit board, but is not limited thereto. According to an exemplary embodiment, the RF die D1 and the SoC die D2 may be flip chips and are bonded to the package substrate 100 in a flip chip manner.

[0030] For example, the bump B1 on the active surface of the RF die D1 is electrically connected to the corresponding pad 101 on the upper surface 100a of the package substrate 100. For example, an antenna (not shown) or a system board (not shown) provided in a printed circuit board can be electrically coupled to the RF die D1 through the interconnection traces 103 and the through-holes 104 in the package substrate 100 and the terminal balls TB provided on the bottom surface 100b of the package substrate 100. For example, the bump B2 on the active surface of the SoC die D2 is electrically connected to the corresponding pad 102 on the upper surface 100a of the package substrate 100. For example, a signal from or to the SoC die D2 can be transmitted through the interconnection traces 103 and the through-holes 104 in the package substrate 100 and the terminal balls TB provided on the bottom surface 100b of the package substrate 100.

[0031] According to an exemplary embodiment, the RF die D1, the SoC die D2 and the upper surface 100a of the package substrate 100 are packaged by the molding compound 110. According to an exemplary embodiment, Figure 1and Figure 2 As shown, a plurality of connection elements C1-C5 are disposed on the upper surface 100a of the package substrate 100. For example, the connection elements C1-C5 may include Cu (copper) / tin (Sn) balls (Cu core solder balls), Cu pillars, Cu bumps, Cu through holes, through-molding material through holes, etc. According to an exemplary embodiment, the connection elements C1-C5 are surrounded by the molding material 110. It should be understood that Figure 2 The number of rows / columns of the connection elements C1-C5 is for illustration purposes only. The connection elements C1-C5 may all be disposed on the upper surface 100a of the package substrate 100. For example, the connection elements C1-C5 may be formed in the same process, so they are coplanar (on the upper surface 100a together). In other embodiments described below, for example, the through holes V1-V3 or PTH1-PTH3 may also be coplanar and may be formed in the same process.

[0032] According to an exemplary embodiment, Figure 2 As shown, when viewed from above, the SoC die D2 may have a rectangular shape and may have four edges E1 to E4. Connecting elements C1, C2, a portion of the connecting element C4 and a portion of the connecting element C5 are arranged around the RF die D1. Connecting elements C2 and C3, the remaining connecting elements C4 and the remaining connecting elements C5 are arranged around the SoC die D2. According to an exemplary embodiment, at least the connecting element C2 directly disposed between the edge E1 of the SoC die D2 and the RF die D1 is grounded, the connecting element C2 may be used as a shielding ball, and the connecting element C2 may be referred to as a signal interference shielding element. In this embodiment, for convenience of description, C1 to C5 are all referred to as connecting elements, however, it can be understood that in the case of having both connecting elements and signal interference shielding elements, the connecting elements should refer to C1, C3, C4 and C5, and the signal interference shielding element refers to C2. According to an exemplary embodiment, the connecting elements C1, C2 and some connecting elements C3 may be electrically coupled to the ground. According to an exemplary embodiment, some connecting elements C3 may be electrically coupled to a power supply. It should be understood that the function of each connecting element C1-C5 can be specified according to design requirements and layout design. In some embodiments, the connecting element near the center of each row or column can be grounded. According to another embodiment, Figure 3 As shown, one or more rows (rows or columns) of connecting elements C1 may be omitted. Figure 3 In the embodiment, the PoP package 1a may only include the connection elements C2 to C5. In addition, the connection element C1 may also be grounded.

[0033] According to an exemplary embodiment, the connecting elements C4 and C5 can be electrically coupled to the top package 20 through the interposer 120. The interposer 120 has a rewiring trace 121 and / or a fan-out / fan-in pad 122 that matches the ball map of the top package 20. Matching can mean that the elements can be connected to each other, and does not necessarily mean that the layout is completely consistent. The interposer 120 may include two or more metal layers, such as a copper layer. The interposer 120 may include a laminated material. For example, the interposer 120 may include a BT (Bismaleimide / Triazine) laminated material. In another embodiment, the interposer 120 may be a Si (silicon) interposer and may include a through-silicon via. It should be understood that the structure of the interposer 120 shown in the figure is for illustration purposes only. In another embodiment, the interposer 120 may be a re-distributed layer (RDL) interposer, which can make the package structure thinner, thereby making the package volume smaller and suitable for different needs.

[0034] According to an exemplary embodiment, the RF die D1 may be a millimeter wave (mmw) intermediate frequency (IF) RF die, but is not limited thereto. According to an exemplary embodiment, the SoC die D2 may be a 5G processor die, but is not limited thereto. For example, the SoC die D2 may include interfaces such as a camera serial interface (CSI) 301 and / or a display serial interface (DSI) 302. These interfaces 301 and 302 are designed for high-bandwidth video input (such as CSI) and output (such as DSI). They may be arranged on edges E3 and E4, respectively. The SoC die D2 may also include a universal flash storage (Universal Flash Storage, UFS) interface 303, which is a JEDEC standard for high-performance mobile storage devices suitable for next-generation data storage. According to a non-limiting exemplary embodiment, the UFS interface 303 may be arranged on edge E2. The SoC die D2 may further include an ABB (analog baseband) / SerDes (Serializer and Deserializer) interface 304 and a universal serial bus (USB) 2.0 / 3.0 interface 305, which may be arranged on the edge E1. The SoC die D2 may further include DDR interfaces 311-314, which are arranged on the edges E3 and E4, respectively.

[0035] It is worth noting that the RF die D1 is disposed near the edge E1. Therefore, the DDR interfaces 311-314 are arranged on the edges E3 and E4, which are different from the edge E1 adjacent to the RF die D1 and directly facing the RF die D1, so that the wiring (such as the high-frequency digital signal traces 311a-314a) can be convenient, and the possibility of noise or interference due to proximity can be reduced. Preferably, when viewed from above, the high-frequency digital signal traces 311a-314a in the package substrate 100 are electrically connected to the DDR interfaces 311-314 on the edges E3 and E4, respectively, do not cross the edge E1 and do not overlap with the RF die D1 (of course, they do not overlap with the edge E1 either), so that the possibility of coupling between the high-frequency digital signal traces 311a-314a and, for example, the RF die D1 can be reduced, thereby reducing noise or interference. The high-frequency digital signal traces 311a to 314a can be connected to the connecting elements C4 and C5, and then connected to the interposer 120 via the connecting elements C4 and C5, and then connected to the top package 20. In addition, potential digital signal interference from the high-frequency digital signal traces 311a to 314a can be blocked by the grounded connecting element C2 set between the edge E1 of the SoC die D2 and the RF die D1. A row (row or column) of grounded connecting elements C2 (signal interference shielding elements) inserted between the RF die D1 and the SoC die D2 can effectively reduce noise. The connecting elements C2 can also be two rows or three rows or more. The connecting elements C2 can be as follows Figure 2As shown, there are multiple arrangements, or it can be a continuous (or integrated) long strip or rod or other continuous object. Of course, at this time, the connecting element C2 should be divided into two continuous objects, and the two are electrically insulated. Of course, considering the convenience of the process, the shape, size, etc. of the connecting element can be freely selected according to the needs. In this embodiment, the SoC chip D2 and the top package 20 can be electrically connected through high-frequency digital signal traces 311a~314a, connecting elements C4 and C5 (of course, there are also interposers 120 (wiring therein, fan-out / fan-in pads 122, etc.), solder balls on the interposer 120, etc.), so the connecting elements C4 and C5 may interfere with the RF chip D1 when transmitting signals. In the present invention, the connecting element C2 is added, and the connecting element C2 is grounded, so that the connecting element C2 can be used to shield these interferences (and release the interference), thereby preventing potential digital high-frequency digital signal interference from the circuit (especially interference to the RF chip D1) and ensuring the normal operation of the package. In addition, in this embodiment, the connecting element C2 is arranged on the packaging substrate 100 (on the upper surface 100a) and in the molding material 110, so that the interference from the high-frequency digital signal traces 311a~314a, the connecting elements C4 and C5 can be shielded. If the connecting element C2 is arranged in other positions, such as in the packaging substrate 100 or in the interposer 120, the interference from the high-frequency digital signal traces 311a~314a, the connecting elements C4 and C5 cannot be shielded. In addition, in this embodiment, the connecting element C2 can also shield the interference caused by the connecting element C3, which is also located on the packaging substrate 100 and in the molding material 110. Therefore, the connecting element C2 has the function of shielding different interferences to protect the stability of the packaging operation.

[0036] Please refer to Figure 4 and Figure 5 , Figure 4 Yes Display Figure 1 Schematic partial top view of the configuration of a separate ground plane of an exemplary PoP package. Figure 5 Yes Display Figure 1 Figure 2 shows the noise vs. frequency curve for a PoP package with and without a separate ground plane. Figure 4As shown, the ground plane G1 that can be set in the interposer 120 is electrically connected to the connecting element C1a and electrically connected to the RF die D1 (part of the connecting element C1 may not be connected to the ground plane G1, but may be grounded or connected to the ground plane G2, etc.), so the ground plane G1 may be the ground plane of the RF die D1. The SoC die D2 may be connected to the ground plane G2 through wiring, such as DRAM wiring (such as 311a-314a, etc.), so the ground plane G2 may be the ground plane of the DRAM and / or SoC die D2. The ground plane G1 in the interposer 120 is separated from the ground plane G2 (for example, the ground planes G1 and G2 are parallel to each other in the vertical direction and are not electrically connected to each other; or the ground planes G1 and G2 are on the same layer but are electrically insulated from each other), for example, physically separated, that is, electrically insulated from each other (no electrical connection). As shown Figure 5 As shown, by providing such a configuration, the ground planes G1 and G2 are physically separated, so that the ground of the RF die D1 and the ground of the SoC die D2 are not directly connected, thereby avoiding the transmission of noise between each other, further increasing the shielding effect, reducing noise, and the noise can be reduced to -170dBm / Hz or even lower, especially reducing the negative impact of the SoC die D2 on the RF die D1. At this time, since the RF die D1 and the SoC die D2 are not electrically connected, the interference between them is only the interference that is emitted into the space (such as air or molding material, etc.), and this part of the interference will be shielded by the grounded connection element C2 (signal interference shielding element). Therefore, the solution in this embodiment (a connection element C2 is provided between the RF die D1 and the SoC die D2 and the ground planes G1 and G2 are physically separated) can further shield the interference, greatly reduce noise and interference, and protect the stability of the packaging operation. In addition, the connecting element C2 may include a first signal interference shielding element C2a and a second signal interference shielding element C2b, wherein the first signal interference shielding element C2a is connected to the ground plane G1, and the second signal interference shielding element C2b is connected to the ground plane G2. The first signal interference shielding element C2a and the second signal interference shielding element C2b are electrically insulated from each other and have no electrical connection. Therefore, the ground planes G1 and G2 can be grounded independently of each other, thereby avoiding the mutual influence between the RF die D1 and the SoC die D2 (due to the ground connection), reducing noise and interference.

[0037] In some embodiments, the ground planes G1 and G2 may also be disposed in the package substrate 100. . This is similar to the above-mentioned ground planes G1 and G2 being disposed in the interposer 120. The ground plane G1 of the package substrate 100 is physically separated from the ground plane G2, and the same effect as the ground planes G1 and G2 being disposed in the interposer 120 can be achieved, which greatly reduces noise and interference. That is, in this embodiment, the ground planes G1 and G2 may be disposed only in the interposer 120, or only in the package substrate 100, or the ground planes G1 and G2 may be disposed in both the interposer 120 and the package substrate 100. When the ground planes G1 and G2 are disposed in both the interposer 120 and the package substrate 100, the first signal interference shielding element C2a may also connect the ground plane G1 in the interposer 120 with the ground plane G1 in the package substrate 100, and the second signal interference shielding element C2b may also connect the ground plane G2 in the interposer 120 with the ground plane G2 in the package substrate 100. In this way, the ground planes G1 (in the interposer 120 and in the packaging substrate 100) and G2 (in the interposer 120 and in the packaging substrate 100) can be grounded independently of each other, thereby avoiding the mutual influence between the RF die D1 and the SoC die D2 (due to the ground connection), and reducing noise and interference. Of course, the ground plane G1 in the interposer 120 and the ground plane G1 in the packaging substrate 100 may not be connected, but grounded separately; the ground plane G2 in the interposer 120 and the ground plane G2 in the packaging substrate 100 may not be connected, but grounded separately, and the above can be set according to needs. When the ground planes G1 and G2 are set in both the interposer 120 and the packaging substrate 100 (of course, the ground planes G1 and G2 in the interposer 120 and the packaging substrate 100 are separated at this time), the effect of reducing noise and anti-interference is the best, so that interference can be shielded from both the upper and lower directions, greatly reducing noise (this effect can be referred to as Figure 5 Of course, the ground planes G1 and G2 can be disposed only in the interposer 120 or only in the package substrate 100, which can also achieve a better effect of reducing noise and resisting interference.

[0038] In addition, in this embodiment, other methods can also be used, for example, when the ground planes G1 and G2 are both provided in the interposer 120 and in the package substrate 100; the ground planes G1 and G2 in the interposer 120 are separated, while the ground planes G1 and G2 in the package substrate 100 are electrically connected (or integrated, or coupled to each other, that is, sharing a ground plane); or the ground planes G1 and G2 in the interposer 120 are electrically connected (or integrated, or coupled to each other, that is, sharing a ground plane), while the ground planes G1 and G2 in the package substrate 100 are separated. In this case, since at least one of the interposer 120 and the package substrate 100 has separated ground planes G1 and G2, the effect of reducing noise and interference can also be achieved. Of course, the best effect is achieved when the ground planes G1 and G2 in the interposer 120 and the package substrate 100 are both separated (for example, physically separated, that is, electrically insulated). For ease of understanding, the ground plane G1 located in the interposer 120 may be referred to as the first ground plane, and the ground plane G2 located in the interposer 120 may be referred to as the second ground plane; the ground plane G1 located in the package substrate 100 may be referred to as the third ground plane, and the ground plane G2 located in the package substrate 100 may be referred to as the fourth ground plane. Of course, this is not a limitation, and the ground plane G1 located in the package substrate 100 may be referred to as the first ground plane, and the ground plane G2 located in the package substrate 100 may be referred to as the second ground plane; the ground plane G1 located in the interposer 120 may be referred to as the third ground plane, and the ground plane G2 located in the interposer 120 may be referred to as the fourth ground plane. Alternatively, both ground planes G1 become the first ground plane, and both ground planes G2 become the second ground plane. For the sake of clarity, the ground plane G1 in the interposer 120 may be referred to as the first ground plane in the interposer 120, and the ground plane G2 in the interposer 120 may be referred to as the second ground plane in the interposer 120; the ground plane G1 in the package substrate 100 may be referred to as the first ground plane in the package substrate 100, and the ground plane G2 in the package substrate 100 may be referred to as the second ground plane in the package substrate 100. Or other naming methods are used, which are only for the convenience of understanding. As an example, the implementation of this paragraph can be described as follows: the first ground plane in the interposer 120 is physically separated from the second ground plane, and the first ground plane in the package substrate 100 is electrically connected or integrally connected to the second ground plane; or the first ground plane in the package substrate 100 is physically separated from the second ground plane, and the first ground plane in the interposer 120 is electrically connected or integrally connected to the second ground plane. Therefore, that is to say, in this embodiment, as long as at least one of the package substrate 100 and the interposer 120 has mutually separated ground planes G1 and G2, noise and interference can be reduced.Specifically, mutually separated ground planes G1 and G2 may be provided in both the package substrate 100 and the interposer 120; or mutually separated ground planes G1 and G2 may be provided only in the interposer 120 (or mutually separated ground planes G1 and G2 may be provided only in the package substrate 100); or mutually separated ground planes G1 and G2 may be provided in the package substrate 100, while the ground planes G1 and G2 in the interposer 120 are electrically connected (or integrated); or mutually separated ground planes G1 and G2 may be provided in the interposer 120, while the ground planes G1 and G2 in the package substrate 100 are electrically connected (or integrated). All of the above methods can reduce noise and interference.

[0039] Figure 6 1 is a schematic cross-sectional view showing a PoP package according to another embodiment of the present invention, wherein the same reference numerals represent the same elements, regions or layers. Figure 6 As shown, the PoP package 2 includes a bottom package 10a and a top package 20 stacked on the bottom package 10a. The bottom package 10a may include a redistribution layer (RDL) 400, and the input / output pads on the RF die D1 and the SoC die D2 may be redistributed through the RDL 400 to form pads BP on the bottom surface 400b, and terminal balls TB such as ball grid array (BGA) balls are mounted on the corresponding pads BP. Similarly, the RF die D1 and the SoC die D2 are encapsulated by the molding compound 110, and copper vias V1-V3 may be formed in the molding compound 110, and the copper vias V1-V3 are electrically connected to the molded RDL 420. The pads 422 for (connecting) the top package 20 are formed in the molded RDL 420. The top package 20 such as LPDDR4 or LPDDR5 DRAM package can be electrically connected to the DDR interface of the SoC die D2 through the molded RDL 420, copper vias V1-V3 and RDL 400. Figure 2 or Figure 3 As shown, the layout of the copper via V2 is similar to the connection element C2. The grounded copper via V2 can be used as a shielding element to block potential digital high-frequency digital signal interference from the circuit. The use of RDL 400 can make the package structure thinner, thereby making the package smaller and suitable for different needs.

[0040] Figure 7 1 is a schematic cross-sectional view showing a PoP package according to another embodiment of the present invention, wherein the same reference numerals represent the same elements, regions or layers. Figure 7As shown, similarly, the PoP package 3 includes a bottom package 10b and a top package 20 stacked on the bottom package 10b. The bottom package 10b can be an embedded die package. The RF die D1 and the SoC die D2 are embedded in the substrate and interconnected through the substrate process to form a system-in-board package. For example, the RF die D1 and the SoC die D2 can be embedded in the core substrate 500. The core substrate 500 may include a copper clad laminate (CCL) substrate or an organic laminate substrate known in the art. A build-up layer BL (Build-up layer) and an interconnect structure Tr (interconnect structure) such as a high-density interconnect (HDI) trace and laser drilling can be formed on the core substrate 500. Through holes PTH1~PTH3 can be formed in the core substrate 500 of the bottom package 10b, and the through holes PTH1~PTH3 can be electrically coupled to the circuit layer 520. A pad 522 for (connecting) the top package 20 may be formed in the circuit layer 520. The top package 20 such as the LPDDR4 or LPDDR5 DRAM package may be electrically connected to the DDR interface of the SoC die D2 through the circuit layer 520, the through holes PTH1-PTH3 and the interconnect structure Tr of the substrate 500. The layout of the through hole PTH2 is similar to Figure 2 or Figure 3 The connecting element C2 is shown. The ground through hole PTH2 can be used as a shielding element to block potential digital signal interference from high-frequency digital signals.

[0041] Please refer to Figure 8 and Fig. 9 , Figure 8 FIG. 4 is a cross-sectional schematic diagram of a PoP package according to another embodiment of the present invention. Fig. 9 is a perspective top view of the PoP package, showing the Figure 8 The side-by-side arrangement of the RF die and the SoC die in the bottom package of the exemplary PoP and the arrangement of the connecting elements around the RF die and the SoC die disposed in the bottom package of the exemplary PoP.

[0042] like Figure 8As shown, the PoP package 4 includes a bottom package 10c and a top package 20 stacked on the bottom package 10c. According to an exemplary embodiment, the top package 20 may be a memory package, such as a DRAM package having at least one packaged DRAM die, such as DDR4, LPDDR4, DDR5, LPDDR5, etc. According to an exemplary embodiment, the bottom package 10c may include a package substrate 100 having an upper surface 100a and a bottom surface 100b. According to an exemplary embodiment, the RF die D1 and the SoC die D2 are mounted on the upper surface 100a of the package substrate 100 in a side-by-side manner.

[0043] According to an exemplary embodiment, similarly, the package substrate 100 may be a multi-layer circuit board or a multi-layer wiring board. For example, the package substrate 100 may be a two-layer, three-layer or four-layer circuit board, but is not limited thereto. According to an exemplary embodiment, the RF die D1 and the SoC die D2 may be flip chips and may be bonded to the package substrate 100 in a flip chip manner.

[0044] According to an exemplary embodiment, the RF die D1, the SoC die D2 and the upper surface 100a of the package substrate 100 are packaged by the molding compound 110. According to an exemplary embodiment, Figure 8 and Fig. 9 As shown, a plurality of connection elements C2 to C5 are disposed on the upper surface 100a of the package substrate 100. For example, the connection elements C2 to C5 may include Cu / Sn balls (Cu core solder balls), Cu columns, Cu bumps, Cu through holes, through-molding through holes, etc. According to an exemplary embodiment, the connection elements C2 to C5 are surrounded by a molding compound 110. According to an exemplary embodiment, the connection elements C2 to C5 may be electrically coupled to the top package 20 through an interposer 120. The interposer 120 has rewiring traces and / or fan-out / fan-out pads that match the solder ball layout of the top package 20. The interposer 120 may include two or more metal layers, such as a copper layer. The interposer 120 may include a laminate. For example, the interposer 120 may include a BT (bismaleimide / triazine) laminate. In another embodiment, the interposer 120 may be a Si interposer and may include a through-silicon via. It should be understood that the structure of the interposer 120 shown in the figure is for illustrative purposes only.

[0045] The size of the package substrate 100 is larger than the upper interposer 120. Therefore, only the SoC die D2 is completely surrounded by the connection elements C2-C5. In addition, only the SoC die D2 overlaps with the interposer 120. The high-frequency digital signal traces in the package substrate 100 that are electrically connected to the DDR interfaces on the edges E3 and E4, respectively, do not intersect with the edge E1 and do not overlap with the RF die D1. By using a smaller-sized interposer 120, the cost of the interposer 120 can be saved. The grounded connection element C2 can be used as a shielding element to block potential digital signal interference from high-frequency digital signals.

[0046] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor package, characterized in that: include: A bottom package including a substrate, an RF die and a system single die arranged in a side-by-side manner on the substrate, a molding compound covering the RF die and the system single die, and an interposer located on the molding compound; a connection element disposed on the upper surface of the substrate, wherein the connection element surrounds the system single die; a signal interference shielding element, disposed between the radio frequency die and the system single die, and grounded; and A top package mounted on the interposer; The system single die includes a first edge, a second edge and a third edge, the first edge is adjacent to the RF die and directly faces the RF die, the second edge and the third edge are connected to the first edge and the second edge and the third edge are located on opposite sides of the system single die, the signal interference shielding element corresponds to the first edge, the connecting element includes a second connecting element corresponding to the second edge and a third connecting element corresponding to the third edge, and the second connecting element and the third connecting element are used to transmit signals.

2. The semiconductor package according to claim 1, wherein: The top package is a memory package, wherein the memory package is a dynamic random access memory package having at least one packaged dynamic random access memory die, wherein the RF die is a millimeter wave intermediate frequency RF die.

3. The semiconductor package according to claim 1, wherein: The connecting elements include copper / tin balls, copper pillars, copper bumps, copper through-holes or through-mold vias.

4. The semiconductor package according to claim 1, wherein: The connecting element and the signal interference shielding element are surrounded by the molding compound.

5. The semiconductor package according to claim 4, wherein: The connecting element is coplanar with the signal interference shielding element.

6. The semiconductor package according to claim 1, wherein: The interposer includes rerouting traces and / or fan-out / fan-in pads that match the solder ball layout of the top package.

7. The semiconductor package according to claim 1, wherein: The interposer includes a silicon interposer or a redistribution layer interposer.

8. The semiconductor package according to claim 1, wherein: The second edge is arranged with a double data rate interface, and the first edge is different from the second edge.

9. The semiconductor package according to claim 1, wherein: Also comprising a first ground plane and a second ground plane; the first ground plane is physically separated from the second ground plane; The RF die is electrically coupled to the first ground plane, and the system single die is electrically coupled to the second ground plane.

10. The semiconductor package according to claim 9, wherein: The first ground plane and the second ground plane are disposed in both the interposer and the packaging substrate.

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