Pixel array substrate

Abstract

The present invention discloses a pixel array substrate, comprising a plurality of scan line pads, a plurality of data line pads, a plurality of scan lines, a plurality of data lines, a plurality of gate transmission lines, a plurality of pixels, a data line signal chip and a scan line signal chip. The scan line extends along a first direction. The data line and the gate transmission line extend along a second direction. The data line is electrically connected to the data line pad. The scan line is electrically connected to the scan line pad through the gate transmission line. The ratio of the number of rows of pixels arranged along the first direction to the number of rows of pixels arranged along the second direction is X:Y. Each pixel includes m sub-pixels.

Description

Technical Field

[0001] The invention relates to a pixel array substrate, and in particular to a pixel array substrate in which scan line pads and data line pads are arranged along an arrangement direction. Background Art

[0002] Display panels have been widely used in a variety of electronic products due to their small size and low radiation. In existing display panels, a large area of ​​driving circuit area is usually reserved outside the display area to set up the driving circuit, and the sub-pixels are controlled by the driving circuit. However, the driving circuit area outside the display area makes the display panel have a very wide border and limits the screen-to-body ratio of the product. With the advancement of technology, consumers have higher and higher requirements for the appearance of display panels. In order to improve consumers' willingness to buy, how to increase the screen-to-body ratio of display panels has become one of the problems that manufacturers currently want to solve. Summary of the invention

[0003] The invention provides a pixel array substrate, which can improve the problem of signal interference between scan line pads and data line pads.

[0004] At least one embodiment of the present invention provides a pixel array substrate, comprising a plurality of scan line pads, a plurality of data line pads, a plurality of scan lines, a plurality of data lines, a plurality of gate transmission lines, a plurality of pixels, a data line signal chip and a scan line signal chip. The scan line pads and the data line pads are located on the substrate. The scan line extends along a first direction. The data line and the gate transmission line extend along a second direction. The data line is electrically connected to the data line pad. The scan line is electrically connected to the scan line pad through the gate transmission line. The pixel is located on the substrate. The ratio of the number of rows of pixels arranged along the first direction to the number of rows of pixels arranged along the second direction is X:Y. Each pixel includes m sub-pixels, and the sub-pixels are electrically connected to the scan line and the data line. The data line signal chip is electrically connected to the data line pad, and the scan line signal chip is electrically connected to the scan line pad. The scan line pad and the data line pad are arranged into a plurality of repeating units in an arrangement direction, and the total number of the scan line pads and the data line pads in each repeating unit is U. U=a×(k×m×X+h×n×Y), where n is the number of scan line signal chips, and a, k and h are positive integers.

[0005] At least one embodiment of the present invention provides a pixel array substrate including a plurality of scan line pads, a plurality of first data line pads, a plurality of second data line pads, a plurality of third data line pads, a plurality of scan lines, a plurality of data lines, a plurality of gate transmission lines, a plurality of red sub-pixels, a plurality of green sub-pixels, a plurality of blue sub-pixels and at least one thin film flip chip packaging circuit. The scan line pad, the first data line pad, the second data line pad and the third data line pad are located on the substrate. The scan line pad, the first data line pad, the second data line pad and the third data line pad are arranged in an arrangement direction. The scan line extends along the first direction. The data line and the gate transmission line extend along the second direction. The scan line is electrically connected to the scan line pad through the gate transmission line. The data line is electrically connected to the first data line pad, the second data line pad and the third data line pad. The red sub-pixel, the green sub-pixel and the blue sub-pixel are electrically connected to the scan line and the data line. The red sub-pixel is electrically connected to the first data line pad. The green sub-pixel is electrically connected to the second data line pad. The blue sub-pixel is electrically connected to the third data line pad. The number of scan line pads located between the first data line pad and the second data line pad or between the third data line pad and the second data line pad in the arrangement direction is less than the number of scan line pads located between the first data line pad and the third data line pad. The chip-on-film packaging circuit includes a data line signal chip and a scan line signal chip. The data line signal chip is electrically connected to the first data line pad, the second data line pad and the third data line pad. The scan line signal chip is electrically connected to the scan line pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a top view schematically showing a pixel array substrate according to an embodiment of the present invention.

[0007] Figure 2A The figure is a top view of a display area of ​​a pixel array substrate according to an embodiment of the present invention.

[0008] Figure 2B is a top view schematically showing a sub-pixel according to an embodiment of the present invention.

[0009] Figure 3A The figure is a top view of a chip-on-film packaging circuit according to an embodiment of the present invention.

[0010] Figure 3B The figure is a top view of a chip-on-film packaging circuit according to an embodiment of the present invention.

[0011] Figure 4 It is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to embodiment 1 of the present invention.

[0012] Figure 5It is a top view schematically showing a pixel array substrate according to an embodiment of the present invention.

[0013] Figure 6 It is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to embodiment 2 of the present invention.

[0014] Figure 7 It is a top view schematically showing a pixel array substrate according to an embodiment of the present invention.

[0015] Figure 8 It is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to embodiment 3 of the present invention.

[0016] Fig. 9 It is a top view schematically showing a pixel array substrate according to an embodiment of the present invention.

[0017] Fig. 10A yes Fig. 9 Schematic cross-sectional view of line aa'.

[0018] Fig. 10B yes Fig. 9 Schematic cross-section of line bb'.

[0019] Wherein, the reference numerals are:

[0020] 10, 20, 30: Pixel array substrate

[0021] 110: Scan line

[0022] 120: Gate transmission line

[0023] 130: First fan-out line

[0024] 210: Data line

[0025] 220: Second fan-out line

[0026] AA: Display area

[0027] BA: Surrounding area

[0028] CC1: First conductor layer

[0029] CC2: Second conductor layer

[0030] CH: Channel Layer

[0031] CH1: First connection structure

[0032] CH2: Second connection structure

[0033] CH3: Third connection structure

[0034] CH4: Fourth connection structure

[0035] CS: Switching structure

[0036] COF: Chip on Film

[0037] D1: First data line pad

[0038] D2: Second data line pad

[0039] D3: The third data line pad

[0040] DC: Data line signal chip

[0041] DE: Drain

[0042] E1: First Direction

[0043] E2: Second Direction

[0044] G: Scan line pad

[0045] GC: Scan line signal chip

[0046] GE: Gate

[0047] GI: Gate Insulation Layer

[0048] I1: First insulation layer

[0049] I2: Second insulation layer

[0050] I3: The third insulation layer

[0051] L1: First row

[0052] L2: Second row

[0053] M1: First metal layer

[0054] M2: Second metal layer

[0055] P1: Red sub-pixel

[0056] P2: Green sub-pixel

[0057] P3: Blue sub-pixel

[0058] O: Open

[0059] PE: Pixel electrode

[0060] PL: Flat layer

[0061] PU: Repeating unit

[0062] PX: Pixel

[0063] RD: Arrangement direction

[0064] SB:Substrate

[0065] SE: Source

[0066] T: Switching element

[0067] TH1, TH2: Through hole DETAILED DESCRIPTION

[0068] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

[0069] Throughout the specification, the same reference numerals represent the same or similar elements. In the accompanying drawings, for clarity, the thickness of layers, films, panels, regions, etc. is magnified. It should be understood that when an element such as a layer, film, region or substrate is referred to as "on another element" or "connected to another element", it can be directly on another element or connected to another element, or other elements may also exist between the element and the other element. On the contrary, when an element is referred to as "directly on another element" or "directly connected to another element", there are no other elements between the element and the other element. As used herein, "connection" may refer to physical and / or electrical connection. Furthermore, two elements being "electrically connected" or "coupled" to each other may be other elements between the two elements.

[0070] It should be understood that although the terms "first" and "second", etc., may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part.

[0071] Figure 1 It is a top view schematically showing a pixel array substrate according to an embodiment of the present invention. Figure 2A The figure is a top view of a display area of ​​a pixel array substrate according to an embodiment of the present invention. Figure 2B yes Figure 2A A top view schematic diagram of a sub-pixel. Figure 3A is a top view schematic diagram of a chip-on-film packaging circuit according to an embodiment of the present invention, wherein Figure 3A For example Figure 1 An enlarged schematic diagram of a chip-on-film packaging circuit COF. Figure 3B The figure is a top view of a chip-on-film packaging circuit according to an embodiment of the present invention.

[0072] Please refer to Figure 1The pixel array substrate 10 includes a plurality of scan line pads G, a plurality of data line pads (such as a first data line pad D1, a second data line pad D2 and a third data line pad D3), a plurality of scan lines 110, a plurality of data lines 210, a plurality of gate transmission lines 120, a plurality of pixels ( Figure 1 In this embodiment, the pixel array substrate 10 further includes a plurality of first fan-out lines 130 and a plurality of second fan-out lines 220 .

[0073] The substrate SB has a display area AA and a peripheral area BA outside the display area AA. The substrate SB may be made of glass, quartz, organic polymer, or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable material. If a conductive material or metal is used, an insulating layer (not shown) is applied to the substrate SB to prevent short circuit problems.

[0074] The scan line pad G is located on the substrate SB. In the present embodiment, the scan line pad G is located on the peripheral area BA. The first fan-out line 130 electrically connects the scan line pad G to the gate transmission line 120. The scan line 110 and the gate transmission line 120 are located on the display area AA. The scan line 110 extends along the first direction E1, and the gate transmission line 120 extends along the second direction E2. In the present embodiment, the gate transmission line 120 is electrically connected to the scan line 110 through the switching structure CS, and the scan line 110 is electrically connected to the scan line pad G through the gate transmission line 120 and the first fan-out line 130.

[0075] In this embodiment, each scan line pad G is electrically connected to two corresponding scan lines 110 , thereby reducing the number of scan line pads G, but the present invention is not limited thereto. In other embodiments, different scan lines 110 do not share the same scan line pad G.

[0076] The data line pads (eg, the first data line pad D1, the second data line pad D2, and the third data line pad D3) are located on the substrate SB. In this embodiment, the data line pads are located on the peripheral area BA. The second fan-out line 220 electrically connects the data line pads to the data line 210. The data line 210 extends along the second direction E2.

[0077] Please refer to Figure 1 and Figure 2A , the pixel PX is located on the substrate SB. In this embodiment, each pixel 300 includes a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, but the present invention is not limited thereto. In other embodiments, each pixel PX also includes sub-pixels of other colors.

[0078] Please refer to Figure 1 , Figure 2B and Figure 2A In the present embodiment, the pixel array substrate 10 is driven in a HG2D (half-gatetwo-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel P2, and blue sub-pixel P3) overlaps two corresponding data lines 210 and one corresponding scan line 110.

[0079] The sub-pixels are electrically connected to the scan line 110 and the data line 210. In the present embodiment, the red sub-pixel P1, the green sub-pixel P2, and the blue sub-pixel P3 are electrically connected to the scan line 110 and the data line 210. The red sub-pixel P1 is electrically connected to the first data line pad D1. The green sub-pixel P2 is electrically connected to the second data line pad D2. The blue sub-pixel P3 is electrically connected to the third data line pad D3.

[0080] Each sub-pixel includes a switch element T and a pixel electrode PE. The switch element T includes a gate electrode GE, a channel layer CH, a source electrode SE and a drain electrode DE.

[0081] The gate GE is located on the substrate SB and is electrically connected to the corresponding scan line 110. The channel layer CH overlaps the gate GE, and a gate insulating layer (not shown in the figure) is sandwiched between the channel layer CH and the gate GE.

[0082] The source electrode SE and the drain electrode DE are electrically connected to the channel layer CH. The source electrode SE is electrically connected to the data line 210. A planar layer (not shown) is located on the source electrode SE and the drain electrode DE. The pixel electrode PE is located on the planar layer and is electrically connected to the drain electrode DE through an opening O penetrating the planar layer.

[0083] In some embodiments, the pixel array substrate 10 further includes a common signal line CL1, a common signal line CL2, and a common signal line CL3. The common signal line CL1, the common signal line CL2, and the scan line 110 all extend along the first direction E1, and the common signal line CL1, the common signal line CL2, and the scan line 110 belong to the same conductive layer (e.g., the first metal layer). The common signal line CL3, the data line 210, and the gate transmission line 120 all extend along the second direction E2, and the common signal line CL3, the data line 210, and the gate transmission line 120 belong to the same conductive layer (e.g., the second metal layer).

[0084] The scan line pads G and the data line pads (for example, the first data line pad D1, the second data line pad D2 and the third data line pad D3) are arranged in the arrangement direction RD. In the present embodiment, the scan line pads G and the data line pads are arranged in a first row L1 and a second row L2 in the arrangement direction RD. The pads in the first row L1 are aligned with each other, and the pads in the second row L2 are aligned with each other. By arranging the scan line pads G and the data line pads in two rows in the arrangement direction RD, the wiring space can be more effectively utilized. In some embodiments, the pads located in the first row L1 and the pads located in the second row L2 belong to different metal layers, for example, the pads located in the first row L1 belong to the first metal layer, and the pads located in the second row L2 belong to the second metal layer. There is an insulating layer between the first metal layer and the second metal layer, thereby avoiding short circuits between adjacent pads.

[0085] In some embodiments, the number of scan line pads G located between the first data line pad D1 and the second data line pad D2 or between the third data line pad D3 and the second data line pad D2 in the arrangement direction RD is less than the number of scan line pads G located between the first data line pad D1 and the third data line pad D3, thereby improving the impact of signal interference between the scan line pads G and the data line pads on the display image.

[0086] The chip-on-film packaging circuit COF is electrically connected to the scan line pads G and the data line pads D (eg, the first data line pad D1 , the second data line pad D2 , and the third data line pad D3 ).

[0087] Please refer to Figure 3A and Figure 3B The chip-on-film packaging circuit COF includes a data line signal chip DC, a scan line signal chip GC, a first insulating layer I1, a second insulating layer I2, a third insulating layer I3, a first wire layer CC1, a second wire layer CC2, multiple first connection structures CH1, multiple second connection structures CH2, multiple third connection structures CH3 and multiple fourth connection structures CH4.

[0088] The first insulating layer I1, the second insulating layer I2 and the third insulating layer I3 are overlapped in sequence. The data line signal chip DC and the scan line signal chip GC are located on the first insulating layer I1.

[0089] The first conductive line layer CC1 is located between the second insulating layer I2 and the first insulating layer I1. A plurality of first connection structures CH1 penetrate the first insulating layer I1 and are electrically connected to the first conductive line layer CC1.

[0090] The second wire layer CC2 is located between the second insulating layer I2 and the third insulating layer I3. A plurality of second connection structures CH2 penetrate the first insulating layer I1 and the second insulating layer I2 and are electrically connected to the second wire layer CC2. In this embodiment, since the first wire layer CC1 and the second wire layer CC2 belong to different film layers, the wiring space of the first wire layer CC1 and the second wire layer CC2 can be effectively increased.

[0091] The third connection structure CH3 penetrates the second insulating layer I2 and the third insulating layer I3 and is electrically connected to the first conductive line layer CC1. A plurality of fourth connection structures CH4 penetrates the third insulating layer I3 and is electrically connected to the second conductive line layer CC2.

[0092] The data line signal chip DC is electrically connected to one of the first wire layer CC1 and the second wire layer CC2, and the scan line signal chip GC is electrically connected to the other of the first wire layer CC1 and the second wire layer CC2. In this embodiment, the data line signal chip DC is electrically connected to the first wire layer CC1, and the scan line signal chip GC is electrically connected to the second wire layer CC2.

[0093] The data line signal chip is DC electrically connected to the data line pad (eg Figure 1 The first data line pad D1, the second data line pad D2 and the third data line pad D3), and the scan line signal chip GC is electrically connected to the scan line pad G.

[0094] In this embodiment, the data line signal chip DC and the scan line signal chip GC are both located on the same side of the display area AA, so the frame of the display panel can be reduced, thereby increasing the screen-to-body ratio of the display device. In some embodiments, the width between the side of the display area AA where the chip-on-film packaging circuit COF is not provided and the edge of the pixel array substrate 10 is less than 2 mm.

[0095] In this embodiment, a chip-on-film packaging circuit COF includes a data line signal chip DC and a scan line signal chip GC. Therefore, the first fan-out line 130 and the second fan-out line 220 may not overlap each other, thereby improving the impact of signal interference between the first fan-out line 130 and the second fan-out line 220 on the display image.

[0096] Please refer to Figure 1 In this embodiment, the pixel array substrate 10 includes n scan line signal chips GC. For example, the pixel array substrate 10 includes 2 film chip packaging circuits COF, and each film chip packaging circuit COF has 1 scan line signal chip GC. Therefore, the pixel array substrate 10 includes 2 scan line signal chips GC in total, that is, n is 2. In other embodiments, n is greater than 2.

[0097] In this embodiment, each scan line 110 is electrically connected to a plurality of scan line signal chips GC, so that the signal on the scan line 110 can be distributed more evenly. For example, the pixel array substrate 10 includes a total of n scan line signal chips GC, and each scan line 110 is electrically connected to n scan line signal chips GC.

[0098] Figure 4 It is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to embodiment 1 of the present invention.

[0099] The scan line pads G and the data line pads D (eg, the first data line pad, the second data line pad, and the third data line pad) are arranged into a plurality of repeating units PU in the arrangement direction RD, and the total number of the scan line pads G and the data line pads D in each repeating unit PU is U.

[0100] Figure 4 It is used to illustrate the arrangement order of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned. For example, the scan line pads G and the data line pads D in the repeating unit PU can be as follows Figure 1 The diagram is divided into a first row L1 and a second row L2. Figure 1 The first pad in the first row L1 is Figure 4 The first pad is in the middle. Figure 1 The first pad in the second row L2 is Figure 4 The middle is the second pad. Figure 1 The second pad in the first row L1 is Figure 4 The middle one is the third pad, and the arrangement order of other pads is similar.

[0101] In this embodiment, if Figure 2A As shown, the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y. For example, in a display panel with a resolution of 1920×1080, X:Y is 16:9. In this embodiment, each pixel PX includes m sub-pixels, where m is a positive integer. In this embodiment, in order to improve the signal interference problem between the scan line pad G and the data line pad D, the scan line pad G and the data line pad D meet the rule of formula 1.

[0102] Formula 1:

[0103] U = a × (k × m × X + h × n × Y)

[0104] In Formula 1, n is the number of scan line signal chips, and a, k, and h are positive integers.

[0105] Example 1

[0106] In Embodiment 1, the pixel array substrate is driven in a HG2D manner, and each sub-pixel overlaps two data lines and one scan line. In Embodiment 1, each scan line pad G is electrically connected to the corresponding two scan lines. In Embodiment 1, some scan line pads G are located in the first row L1, and another part of the scan line pads G are located in the second row L2 (e.g. Figure 1 As shown in FIG. 1 ), part of the scan line pads G belongs to the first metal layer, and another part of the scan line pads G belongs to the second metal layer. In Embodiment 1, a is 1, k is 4, and h is 1.

[0107] X:Y is 16:9. Each pixel PX includes 3 sub-pixels, that is, m is 3. The pixel array substrate has 3 scan line signal chips, that is, n is 3.

[0108] In Example 1, the total number U of scan line pads G and data line pads D in each repeating unit PU is calculated using Formula 1, U =1×(4×3×16+1×3×9) = 219, which means that the total number U of scan line pads G and data line pads D in each repeating unit PU is 219.

[0109] In the first embodiment, in order to make the scan line pads G and the data line pads D more evenly distributed, the number R of the data line pads D between two adjacent scan line pads G in the arrangement direction RD complies with the rule of formula 2.

[0110] Formula 2:

[0111] R = 2×m×N

[0112] In Formula 2, N is an integer between 1 and k+1.

[0113] In the first embodiment, R=2×3×1 to 2×3×5, which means that the number of the data line pads D between two adjacent scan line pads G is between 6 and 30.

[0114] Figure 5 is a top view schematic diagram of a pixel array substrate according to an embodiment of the present invention. It must be noted here that Figure 5 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0115] Figure 5 The pixel array substrate 20 and Figure 1The difference between the pixel array substrate 10 and the pixel array substrate 20 is that: in the pixel array substrate 20, different scan lines 110 do not share the same scan line pad G.

[0116] Please refer to Figure 5 In the present embodiment, each gate transmission line 120 is electrically connected to a corresponding scan line pad G and to a corresponding scan line 110 .

[0117] Figure 6 It is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to embodiment 2 of the present invention.

[0118] The scan line pads G and the data line pads D (eg, the first data line pad, the second data line pad, and the third data line pad) are arranged into a plurality of repeating units PU in the arrangement direction RD, and the total number of the scan line pads G and the data line pads D in each repeating unit PU is U.

[0119] Figure 6 It is used to illustrate the arrangement order of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned. For example, the scan line pads G and the data line pads D in the repeating unit PU can be as follows Figure 5 The diagram is divided into a first row L1 and a second row L2. Figure 5 The first pad in the first row L1 is Figure 6 The first pad is in the middle. Figure 5 The first pad in the second row L2 is Figure 6 The middle is the second pad. Figure 5 The second pad in the first row L1 is Figure 6 The middle one is the third pad, and the arrangement order of other pads is similar.

[0120] In this embodiment, if Figure 2A As shown, the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y. In this embodiment, each pixel PX includes m sub-pixels, where m is a positive integer. In this embodiment, in order to improve the signal interference problem between the scan line pad G and the data line pad D, the scan line pad G and the data line pad D meet the rule of formula 1.

[0121] Example 2

[0122] In Embodiment 2, the pixel array substrate is driven in a HG2D manner, and each sub-pixel overlaps two data lines and one scan line. In Embodiment 2, each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line. In Embodiment 2, some scan line pads G are located in the first row L1, and another part of the scan line pads G are located in the second row L2 (e.g. Figure 5 As shown in FIG. 1 ), part of the scan line pads G belongs to the first metal layer, and another part of the scan line pads G belongs to the second metal layer. In Embodiment 2, a is 1, k is 2, and h is 1.

[0123] X:Y is 16:9. Each pixel PX includes 3 sub-pixels, that is, m is 3. The pixel array substrate has 3 scan line signal chips, that is, n is 3.

[0124] In Example 2, the total number U of scan line pads G and data line pads D in each repeating unit PU is calculated using Formula 1, U=1×(2×3×16+1×3×9)=123, which means that the total number U of scan line pads G and data line pads D in each repeating unit PU is 123.

[0125] In the second embodiment, in order to make the scan line pads G and the data line pads D more evenly distributed, the number R of the data line pads D between two adjacent scan line pads G in the arrangement direction RD complies with the rule of formula 2.

[0126] In the second embodiment, R=2×3×1 to 2×3×3, which means that the number of the data line pads D between two adjacent scan line pads G is between 6 and 18.

[0127] Figure 7 is a top view schematic diagram of a pixel array substrate according to an embodiment of the present invention. It must be noted here that Figure 7 The implementation examples are used Figure 2A The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0128] Figure 7 The pixel array substrate 30 and Figure 2A The difference between the pixel array substrate 10 and the pixel array substrate 10 is that the pixel array substrate 30 is driven in a 1G1D (one-gate one-data line) manner, and each sub-pixel (red sub-pixel P1, green sub-pixel P2 and blue sub-pixel P3) overlaps a corresponding one of the data lines 210 and a corresponding one of the scan lines 110.

[0129] Figure 8 It is a schematic diagram of an arrangement sequence of scan line pads and data line pads according to embodiment 3 of the present invention.

[0130] The scan line pads G and the data line pads D (eg, the first data line pad, the second data line pad, and the third data line pad) are arranged into a plurality of repeating units PU in the arrangement direction RD, and the total number of the scan line pads G and the data line pads D in each repeating unit PU is U.

[0131] Figure 8 It is used to illustrate the arrangement order of the scan line pads G and the data line pads D in the repeating unit PU, and the scan line pads G and the data line pads D in the repeating unit PU are not completely aligned. For example, the scan line pads G and the data line pads D in the repeating unit PU can be as follows Figure 5 The diagram is divided into a first row L1 and a second row L2. Figure 1 The first pad in the first row L1 is Figure 8 The first pad is in the middle. Figure 5 The first pad in the second row L2 is Figure 8 The middle is the second pad. Figure 5 The second pad in the first row L1 is Figure 8 The middle one is the third pad, and the arrangement order of other pads is similar.

[0132] In this embodiment, if Figure 7 As shown, the ratio of the number of rows of pixels PX arranged along the first direction E1 to the number of rows of pixels PX arranged along the second direction E2 is X:Y. In this embodiment, each pixel PX includes m sub-pixels, where m is a positive integer. In this embodiment, in order to improve the signal interference problem between the scan line pad G and the data line pad D, the scan line pad G and the data line pad D meet the rule of formula 1.

[0133] Example 3

[0134] In Embodiment 3, the pixel array substrate is driven in a 1G1D manner, and each sub-pixel overlaps a data line and a scan line. In Embodiment 3, each scan line pad G is electrically connected to a corresponding scan line, and different scan lines are not directly electrically connected through the scan line pad or the gate transmission line. In Embodiment 3, some scan line pads G are located in the first row L1, and another part of the scan line pads G are located in the second row L2 (such as Figure 5 As shown in FIG. 1 ), part of the scan line pads G belongs to the first metal layer, and another part of the scan line pads G belongs to the second metal layer. In Embodiment 3, a is 1, k is 1, and h is 1.

[0135] X:Y is 16:9. Each pixel PX includes 3 sub-pixels, that is, m is 3. The pixel array substrate has 3 scan line signal chips, that is, n is 3.

[0136] In Example 3, the total number U of scan line pads G and data line pads D in each repeating unit PU is calculated using Formula 1, U=1×(1×3×16+1×3×9)=75, which means that the total number U of scan line pads G and data line pads D in each repeating unit PU is 75.

[0137] In the third embodiment, in order to make the scan line pads G and the data line pads D more evenly distributed, the number R of the data line pads D between two adjacent scan line pads G in the arrangement direction RD complies with the rule of formula 2.

[0138] In the third embodiment, R=2×3×1 to 2×3×2, which means that the number of the data line pads D between two adjacent scan line pads G is between 6 and 12.

[0139] Fig. 9 It is a top view schematically showing a pixel array substrate according to an embodiment of the present invention. Fig. 10A yes Fig. 9 Schematic cross-sectional view of line aa'. Fig. 10B yes Fig. 9 The cross-sectional diagram of line bb'. It must be noted here that Fig. 9 The implementation examples are used Figure 5 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0140] Please refer to Fig. 9 In the pixel array substrate 30, the scan line pads G are all located in the same row. For example, the scan line pads G are all located in the first row L1 or the scan line pads G are all located in the second row. In this embodiment, the pads located in the first row L1 (including the scan line pads G and the data line pads D) belong to the first metal layer M1, and the pads located in the second row L2 (including the data line pads D) belong to the second metal layer M2. In other embodiments, the pads located in the second row L2 belong to the first metal layer M1, and the pads in the first row L1 belong to the second metal layer M2. In this embodiment, all the scan line pads G are aligned with each other in the arrangement direction RD.

[0141] In this embodiment, the scan line pads G all belong to the first metal layer M1 , thus reducing the problem of signal deviation caused by the switching structure (eg, the switching structure from the first metal layer M1 to the second metal layer M2 ) of different scan lines 110 .

[0142] The first metal layer M1 is located on the substrate SB. The gate insulating layer GI covers the first metal layer M1. The gate insulating layer GI on the pads belonging to the first metal layer M1 (e.g., the scan line pad G) has a through hole TH1. The planar layer PL is located on the gate insulating layer GI and has a through hole TH2 on the pads belonging to the first metal layer M1 (e.g., the scan line pad G) and on the pads belonging to the second metal layer M2 (e.g., the third data line pad D3).

[0143] In some embodiments, a plurality of conductive structures CP are filled in the through hole TH1 and the through hole TH2 to be electrically connected to the corresponding scan line pad G and the third data line pad D3 , respectively. The material of the conductive structure CP includes, for example, metal oxide.

[0144] Example 4

[0145] In Embodiment 4, the pixel array substrate is driven in a HG2D manner, and each sub-pixel overlaps two data lines and one scan line. In Embodiment 4, each scan line pad G is electrically connected to the corresponding two scan lines. In Embodiment 4, all scan line pads G belong to the same metal layer (e.g., the first metal layer or the second metal layer). In Embodiment 4, a is 2, k is 4, and h is 1.

[0146] X:Y is 16:9. Each pixel PX includes 3 sub-pixels, that is, m is 3. The pixel array substrate has 3 scan line signal chips, that is, n is 3.

[0147] In Example 4, the total number U of scan line pads G and data line pads D in each repeating unit PU is calculated using Formula 1, U=2×(4×3×16+1×3×9)=438, which means that the total number U of scan line pads G and data line pads D in each repeating unit PU is 438.

[0148] In the fourth embodiment, in order to make the scan line pads G and the data line pads D more evenly distributed, the number R of the data line pads D between two adjacent scan line pads G in the arrangement direction RD complies with the rule of formula 3.

[0149] Formula 3:

[0150] R = 2×m×N+1

[0151] In Formula 3, N is an integer between 1 and k+1.

[0152] In the fourth embodiment, R=2×3×1+1 to 2×3×5+1, which means that the number of the data line pads D between two adjacent scan line pads G is between 7 and 31.

[0153] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A pixel array substrate, characterized in that: include: A plurality of scan line pads, a plurality of first data line pads, a plurality of second data line pads and a plurality of third data line pads are located on a substrate, wherein the scan line pads, the first data line pads, the second data line pads and the third data line pads are arranged in an arrangement direction; A plurality of scanning lines extending along a first direction; A plurality of data lines and a plurality of gate transmission lines extending along a second direction, wherein the scan lines are electrically connected to the scan line pads through the gate transmission lines, and the data lines are electrically connected to the first data line pads, the second data line pads, and the third data line pads; a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels, electrically connected to the scan lines and the data lines, wherein the red sub-pixels are electrically connected to the first data line pads, the green sub-pixels are electrically connected to the second data line pads, and the blue sub-pixels are electrically connected to the third data line pads, wherein the number of the scan line pads located between the first data line pads and the second data line pads or between the third data line pads and the second data line pads in the arrangement direction is less than the number of the scan line pads located between the first data line pads and the third data line pads; At least one thin film chip-on-chip packaging circuit includes at least one data line signal chip and at least one scan line signal chip, the at least one data line signal chip is electrically connected to the first data line pads, the second data line pads and the third data line pads, and the at least one scan line signal chip is electrically connected to the scan line pads.

2. The pixel array substrate according to claim 1, wherein: The at least one chip-on-film package circuit comprises: A first insulating layer, a second insulating layer and a third insulating layer are overlapped in sequence, and the at least one data line signal chip and the at least one scan line signal chip are located on the first insulating layer; A first conductive line layer is located between the second insulating layer and the first insulating layer; a second conductive line layer, located between the second insulating layer and the third insulating layer; A plurality of first connection structures, penetrating the first insulating layer and electrically connected to the first conductive line layer; A plurality of second connection structures, penetrating the first insulating layer and the second insulating layer, and electrically connected to the second conductive wire layer; a plurality of third connection structures, penetrating the second insulating layer and the third insulating layer, and electrically connected to the first conductive line layer; and A plurality of fourth connection structures penetrate the third insulating layer and are electrically connected to the second conductor layer, wherein the at least one data line signal chip is electrically connected to one of the first conductor layer and the second conductor layer, and the at least one scan line signal chip is electrically connected to the other of the first conductor layer and the second conductor layer.

3. The pixel array substrate according to claim 1, wherein: The red sub-pixels, the green sub-pixels and the blue sub-pixels form a plurality of pixels, wherein the ratio of the number of rows of the pixels arranged along the first direction to the number of rows of the pixels arranged along the second direction is X:Y, wherein each pixel includes m sub-pixels; The scan line pads and the data line pads are arranged into a plurality of repeating units in the arrangement direction, and the total number of the scan line pads and the data line pads in each of the repeating units is U, wherein U=a×(k×m×X+h×n×Y), wherein n is the number of the at least one scan line signal chip, and a, k, and h are positive integers.

4. The pixel array substrate according to claim 3, wherein: Each of the sub-pixels overlaps with corresponding two of the data lines and a corresponding one of the scan lines, and each of the scan line pads is electrically connected to the corresponding two scan lines.

5. The pixel array substrate according to claim 4, wherein: Some of the scan line pads and some of the data line pads belong to the first metal layer, and another part of the scan line pads and another part of the data line pads belong to the second metal layer, wherein a is 1, k is 4, and h is 1.

6. The pixel array substrate according to claim 5, characterized in that: There are R data line pads between two adjacent scan line pads in the arrangement direction, where R=2×m×N, and N is an integer between 1 and k+1.

7. The pixel array substrate according to claim 4, wherein: The scan line pads all belong to the same metal layer, where a is 2, k is 4, and h is 1.

8. The pixel array substrate according to claim 7, wherein: There are R data line pads between two adjacent scan line pads in the arrangement direction, where R=2×m×N+1, and N is an integer between 1 and k+1.

9. The pixel array substrate according to claim 7, wherein: The scan line pads are aligned with each other in the arrangement direction.

10. The pixel array substrate according to claim 3, wherein: Each of the sub-pixels overlaps two corresponding data lines and one corresponding scan line, and different scan lines are not directly electrically connected through the scan line pads or the gate transmission lines, where a is 1, k is 2, and h is 1.

11. The pixel array substrate according to claim 10, wherein: There are R data line pads between two adjacent scan line pads in the arrangement direction, where R=2×m×N, and N is an integer between 1 and k+1.

12. The pixel array substrate according to claim 3, wherein: Each of the sub-pixels overlaps a corresponding one of the data lines and a corresponding one of the scan lines, wherein a is 1, k is 1, and h is 1.

13. The pixel array substrate according to claim 12, wherein: There are R data line pads between two adjacent scan line pads in the arrangement direction, where R=2×m×N, and N is an integer between 1 and k+1.

14. The pixel array substrate according to claim 3, wherein: Also includes: A plurality of first fan-out lines electrically connecting the scan line pads to the gate transmission lines; and A plurality of second fan-out lines electrically connect the data line pads to the data lines, wherein the first fan-out lines and the second fan-out lines do not overlap each other.

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