Power supply circuit and display device

Abstract

The present application provides a power supply circuit and a display device, the power supply circuit comprising: a reference current generating circuit for generating a reference current; a driving circuit connected to the reference current generating circuit for generating a mirror current with an adjustable mirror ratio according to the reference current, and outputting a bias voltage and a gate driving voltage; a channel current output circuit connected to the driving circuit for receiving the bias voltage and the gate driving voltage, and generating a channel current with an adjustable mirror ratio according to the mirror current. Since the mirror ratio is adjustable, the current accuracy can be improved, and when the output current needs to be larger, the mirror current can still be smaller, thereby reducing power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a power supply circuit and a display device. Background Art

[0002] In LED (Light Emitting Diode) display driver chips, most of them use Figure 1 The structure shown is used as a constant current source generating circuit, which is divided into three parts. First, the reference current generating circuit 101 uses the built-in reference voltage Vref and the external resistor Rext to generate the reference current I0. The second part uses the current mirror circuit 102 (the number ratio of MOS metal oxide semiconductor devices is M:N) to obtain the current I1 by mirroring the current. The third part, the current output circuit 103 (the number ratio of MOS devices is J:K) generates and drives the output constant current source Iout. Among them, the second and third parts are to adapt to the LED common anode structure and meet the multi-channel driving capability requirements.

[0003] When the output constant current source current Iout needs to be larger, since the ratio of K:J is fixed, the current I1 needs to be very large, thereby increasing the power consumption of the chip. Summary of the invention

[0004] An embodiment of the present application provides a power supply circuit for reducing power consumption.

[0005] An embodiment of the present application provides a power supply circuit, including:

[0006] A reference current generating circuit, used for generating a reference current;

[0007] A driving circuit, connected to the reference current generating circuit, for generating a mirror current with an adjustable mirror ratio according to the reference current, and outputting a bias voltage and a gate driving voltage;

[0008] The channel current output circuit is connected to the driving circuit, and is used for receiving the bias voltage and the gate driving voltage, and generating a channel current with an adjustable mirror ratio according to the mirror current.

[0009] In one embodiment, the reference current generating circuit includes:

[0010] The first amplifier has an inverting input terminal for inputting a reference voltage;

[0011] a resistor, a first end of which is grounded, and a second end of which is connected to a positive input terminal of the first amplifier;

[0012] A plurality of groups of first P-type field effect transistors, with sources connected to a power supply, gates respectively connected to the output ends of the first amplifiers, drains connected to the second ends of the resistors, and outputting the reference current to the resistors;

[0013] The first switch is connected to the plurality of groups of first P-type field effect transistors and is used to independently control whether the first P-type field effect transistors of each group are turned on or off.

[0014] In one embodiment, the driving circuit comprises:

[0015] A second P-type field effect transistor, having a source connected to a power supply, a gate connected to the gates of the plurality of groups of first P-type field effect transistors, and a drain used to output the mirror current;

[0016] A second amplifier, whose inverting input terminal is used to input a reference voltage, and whose output terminal is used to provide the gate drive voltage;

[0017] A first N-type field effect transistor, having a gate connected to the output end of the second amplifier, a source grounded, and a drain connected to the drain of the second P-type field effect transistor and the positive input end of the second amplifier, is used to provide the bias voltage that is the same as the reference voltage.

[0018] In one embodiment, the channel current output circuit includes:

[0019] A third amplifier, a positive input terminal of which is connected to the drain of the first N-type field effect transistor;

[0020] a third N-type field effect transistor, having a gate connected to the output end of the third amplifier; a source connected to the inverting input end of the third amplifier, and a drain used to output the channel current;

[0021] A plurality of groups of second N-type field effect transistors, wherein the drains are respectively connected to the reverse input terminals of the third amplifier; the gates are respectively connected to the output terminals of the second amplifier; and the sources are grounded;

[0022] The second switch is connected to a plurality of groups of the second N-type field effect transistors and is used to independently control whether the second N-type field effect transistors of each group are turned on or off.

[0023] In one embodiment, the driving circuit further includes:

[0024] A driving buffer is connected to the output end of the second amplifier and the gates of the plurality of groups of second N-type field effect transistors, and is used to increase the gate driving voltage.

[0025] In one embodiment, the first switch includes a plurality of first sub-switches, which independently control the conduction of a plurality of groups of the first P-type field effect transistors;

[0026] The second switch includes a plurality of second sub-switches, which independently control whether a plurality of groups of the second N-type field effect transistors are turned on or off.

[0027] In one embodiment, the number ratio between the plurality of first P-type field effect transistors is the same as the number ratio between the plurality of second N-type field effect transistors.

[0028] In one embodiment, an adjustment ratio of the number of on-state transistors of the plurality of first P-type field effect transistors is the same as an adjustment ratio of the number of on-state transistors of the plurality of second N-type field effect transistors.

[0029] In one embodiment, the switch control signals of the first switch and the second switch are the same.

[0030] The present application also provides a display device, including:

[0031] LED display panel, the LED display panel is a common cathode or common anode structure;

[0032] A driving chip connected to the LED display panel, the driving chip includes the above-mentioned power supply circuit, wherein there are multiple channel current output circuits; if the LED display panel is a common cathode structure, the multiple channel current output circuits are respectively connected to the anodes of multiple light-emitting diodes of the LED display panel;

[0033] If the LED display panel is a common anode structure, the multiple channel current output circuits are respectively connected to cathodes of multiple light emitting diodes of the LED display panel.

[0034] The technical solution provided by the embodiment of the present application generates a reference current through a reference current generating circuit; the reference current generating circuit is connected through a driving circuit, and based on the reference current, a mirror current with an adjustable mirror ratio is generated, and a bias voltage and a gate drive voltage are output; a channel current output circuit is connected to the driving circuit, and is used to receive the bias voltage and the gate drive voltage, and generate a channel current with an adjustable mirror ratio according to the mirror current. Since the mirror ratio is adjustable, the current accuracy can be improved, and when the channel current needs to be larger, the mirror current can still be smaller, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings required for use in the embodiments of the present application are briefly introduced below.

[0036] Figure 1 It is a structural schematic diagram of the power supply circuit provided in the background technology;

[0037] Figure 2 A schematic diagram of the principle of current mirroring provided in one embodiment of the present application;

[0038] Figure 3 It is a schematic diagram of a power supply circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0040] Similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0041] Figure 2 The schematic diagram of the principle of current mirroring provided in the embodiment of the present application. Figure 2 As shown, N-type field effect transistor (NFET) NM0 and N-type field effect transistor NM1 have the same gate voltage Vg1. Assuming that the gate voltage of N-type field effect transistor NM2 is Vg2, the drain voltages of N-type field effect transistor NM0, N-type field effect transistor NM1 and N-type field effect transistor NM2 are Vd0, Vd1 and Vd2 respectively. Then, if the gate voltage Vg1 of N-type field effect transistor NM1 is equal to the gate voltage Vg2 of N-type field effect transistor NM2, and the drain voltage Vd1 of N-type field effect transistor NM1 is equal to the drain voltage Vd2 of N-type field effect transistor NM2, then the two devices N-type field effect transistor NM1 and N-type field effect transistor NM2 are under the same bias condition, so the current I1 of the branch where N-type field effect transistor NM1 is located is equal to the current I2 of the branch where N-type field effect transistor NM2 is located, that is, it can be said that current I2 mirrors current I1.

[0042] Figure 3 A schematic diagram of a power supply circuit provided in an embodiment of the present application. Figure 3 As shown, the power supply circuit includes: a reference current generating circuit 301 , a driving circuit 302 and a channel current output circuit 303 .

[0043] The reference current generating circuit 301 is used to generate the reference current I0. In one embodiment, the reference current generating circuit 301 includes: a first amplifier OP0, a resistor REXT, a plurality of first P-type field effect transistors PM0, and a first switch K0;

[0044] Among them, the first and the second are mainly used for distinction. The reverse input terminal of the first amplifier OP0 is used to input the reference voltage VREF, the output terminal is connected to the gates of multiple groups of first P-type field effect transistors PM0, and is used to provide the gate voltage VGATEP, and the positive input terminal is connected to the second end of the resistor REXT. The first end of the resistor REXT is grounded, and the second end is connected to the positive input terminal of the first amplifier OP0 and the drain of multiple groups of first P-type field effect transistors PM0. The source of multiple groups of first P-type field effect transistors PM0 is connected to the power supply, the gate is respectively connected to the output terminal of the first amplifier OP0, and the drain is connected to the second end of the resistor REXT, and the reference current I0 is output to the resistor REXT.

[0045] The reference voltage VREF can be generated by a bandgap reference voltage source inside the chip, and a negative feedback structure is formed by using the first amplifier OP0, multiple groups of first P-type field effect transistors PM0 and an external resistor REXT to obtain a reference current I0.

[0046]

[0047] Wherein, I0 represents the reference current, Vref represents the reference voltage, and Rext represents the resistance.

[0048] The first switch K0 is connected to a plurality of groups of first P-type field effect transistors PM0 and is used to independently control whether the first P-type field effect transistors PM0 of each group are turned on or off.

[0049] like Figure 3 As shown, the multiple groups of first P-type field effect transistors PM0 can be 4 groups (PM0:1, PM0:2, PM0:3, PM0:4), for example, the number ratio of the 4 groups of first P-type field effect transistors PM0 can be M:M:2M:4M; the gate of each group of first P-type field effect transistors PM0 is connected to the output end of the first amplifier OP0, the source is connected to the power supply, and the drain is connected to the first end of the resistor REXT connected to the first amplifier OP0.

[0050] The first switch K0 may include a plurality of first sub-switches (K0:1, K0:2, K0:3, K0:4), which are connected to a plurality of groups of first P-type field effect transistors PM0 in a one-to-one correspondence, and are used to individually control the conduction of the first P-type field effect transistors PM0 of each group. Each first sub-switch may have two states, being turned on when connected to a high level and being turned off when connected to a low level.

[0051] like Figure 3As shown, K0:1 is used to control the conduction of the first group of first P-type field effect transistors PM0:1, K0:2 is used to control the conduction of the second group of first P-type field effect transistors PM0:2, K0:3 is used to control the conduction of the third group of first P-type field effect transistors PM0:3, and K0:4 is used to control the conduction of the fourth group of first P-type field effect transistors PM0:4. As needed, the conduction of K0:1, K0:2, K0:3, and K0:4 can be independently controlled to control the number of first P-type field effect transistors PM0 that are turned on.

[0052] The driving circuit 302 is connected to the reference current generating circuit 301, and is used to generate a mirror current I1 with an adjustable mirror ratio according to the reference current I0, and output a bias voltage and a gate driving voltage;

[0053] In one embodiment, if Figure 3 As shown, the driving circuit 302 includes: a second P-type field effect transistor PM1, a second amplifier OP1 and a first N-type field effect transistor NM1.

[0054] The gate of the second P-type field effect transistor PM1 is connected to the gates of the plurality of groups of first P-type field effect transistors PM0, the source is connected to the power supply, and the drain is used to output the mirror current I1. The second P-type field effect transistor PM1 and the plurality of groups of first P-type field effect transistors PM0 form a current mirror. Under the same voltage bias, the current of the MOS device is proportional to the device size. When the MOS devices of the same size are used, the current ratio is determined by the number of MOS devices. By adjusting the number of MOS devices, the required current ratio can be obtained. Therefore, by controlling the first switch K0, the number of the first P-type field effect transistors PM0 that are turned on can be adjusted, thereby controlling the size of the mirror current I1.

[0055] like Figure 3 As shown, the ratio of the number of the four groups of first P-type field effect transistors PM0 can be M:M:2M:4M, which are controlled by switches K0:1, K0:2, K0:3, and K0:4 respectively. Assuming that the number of the first P-type field effect transistors PM0 turned on is R1×M (R1 may be 1, 2, 3, 4, 5, 6, 7, 8) by controlling the above switches. Then, in the current branch of the second P-type field effect transistor PM1 and the first N-type field effect transistor NM0, according to the current mirror, the branch current I1=N / (R1×M)×I0. I1 represents the output mirror current. N represents the number of the second P-type field effect transistors PM1. Through the current mirroring of the first P-type field effect transistor PM0 and the second P-type field effect transistor PM1, a precisely matched mirror current I1 can be obtained.

[0056] The inverting input terminal of the second amplifier OP1 is used to input a reference voltage VCRES, the output terminal is used to provide a gate driving voltage VGATE, and the forward input terminal is connected to the drain of the first N-type field effect transistor NM0.

[0057] The first N-type field effect transistor NM0 has a gate connected to the output end of the second amplifier OP1, a source grounded, and a drain connected to the drain of the second P-type field effect transistor PM1 and the positive input end of the second amplifier OP1, for providing a bias voltage the same as the reference voltage VCRES.

[0058] like Figure 3 As shown, the negative feedback loop formed by the second P-type field effect transistor PM1, the first N-type field effect transistor NM0 and the second amplifier OP1 can set the drain voltage (i.e., bias voltage) of the first N-type field effect transistor NM0. Because the negative feedback system is in a steady state, the voltages of the two input terminals of the second amplifier OP1 are the same (only a slight difference, depending on the loop open-loop gain), so the drain voltage of the first N-type field effect transistor NM0 is equal to the inverting input voltage VCRES of the second amplifier OP1. That is, the bias voltage can be equal to the input reference voltage.

[0059] The channel current output circuit 303 is connected to the driving circuit 302 , and is used for receiving the bias voltage and the gate driving voltage, and generating a channel current Iout with an adjustable mirror ratio according to the mirror current I0 .

[0060] like Figure 3 As shown, the channel current output circuit includes: a third amplifier DRIVER_OP, a third N-type field effect transistor NM2, a plurality of groups of second N-type field effect transistors NM1 and a second switch K1.

[0061] The positive input terminal of the third amplifier DRIVER_OP is connected to the drain of the first N-type field effect transistor NM0, so the voltage input to the positive input terminal of the third amplifier DRIVER_OP is equal to the reference voltage VCRES. The gate of the third N-type field effect transistor NM2 is connected to the output terminal of the third amplifier DRIVER_OP; the source is connected to the drain of multiple groups of second N-type field effect transistors NM1 and the reverse input terminal of the third amplifier DRIVER_OP, and the drain is used to output the channel current.

[0062] Because the voltages of the two input terminals of the amplifier are the same when the negative feedback system is in steady state, the voltage input to the inverting input terminal of the third amplifier DRIVER_OP is also equal to the reference voltage VCRES, thereby providing a bias voltage for the plurality of second N-type field effect transistors NM1, and the bias voltage is also equal to the reference voltage VCRES.

[0063] The drains of the plurality of second N-type field effect transistors NM1 are respectively connected to the inverting input terminal of the third amplifier DRIVER_OP; the gates are respectively connected to the output terminals of the second amplifier OP1; and the sources are grounded.

[0064] The second switch K1 is connected to a plurality of groups of the second N-type field effect transistors NM1 , and is used to independently control whether the second N-type field effect transistors NM1 of each group are turned on or off.

[0065] In one embodiment, if Figure 3 As shown, the second N-type field effect transistor NM1 can have 4 groups (NM1:1, NM1:2, NM1:3, NM1:4), and the number ratio of each group of MOS tubes is K:K:2K:4K. Each group of second N-type field effect transistors NM1 is connected to the reverse input terminal of the third amplifier DRIVER_OP and the source of the third N-type field effect transistor NM2, so as to provide the same bias voltage for each group of N-type field effect transistors NM1.

[0066] The second switch K1 may include a plurality of second sub-switches (K1:1, K1:2, K1:3, K1:4), which are connected to a plurality of groups of the second N-type field effect transistors NM1 in a one-to-one correspondence, and are used to individually control the conduction of the second N-type field effect transistors NM1 of each group. Each second sub-switch may have two states, being turned on when connected to a high level and being turned off when connected to a low level.

[0067] like Figure 3 As shown, K1:1 controls the conduction of the first group of second N-type field effect transistors NM1:1, K1:2 controls the conduction of the second group of second N-type field effect transistors NM1:2, K1:3 controls the conduction of the third group of second N-type field effect transistors NM1:3, and K1:4 controls the conduction of the fourth group of second N-type field effect transistors NM1:4.

[0068] The number ratio of the plurality of groups of second N-type field effect transistors NM1 may be K:K:2K:4K. Assuming that the second switch K1 is controlled to make the number of the second N-type field effect transistors NM1 turned on R2×K (R2 may be 1, 2, 3, 4, 5, 6, 7, 8), the number of the first N-type field effect transistors NM0 is assumed to be J. Since the gate voltage of the second N-type field effect transistor NM1 is equal to VGATE and the drain voltage is equal to VCRES, in the current branch of the second N-type field effect transistor NM1 and the third N-type field effect transistor NM2, according to the current mirror, the accurate output current can be obtained, and the branch current Iout=R2×K / J×I1, and Iout represents the channel current. Therefore, by controlling the second switch K1, the number of the second N-type field effect transistors NM1 turned on R2×K can be adjusted, thereby controlling the magnitude of the output current Iout.

[0069] In one embodiment, if Figure 3As shown, the driving circuit 302 also includes a driving buffer, which is connected to the output end of the second amplifier OP1 and the gates of the multiple groups of second N-type field effect transistors NM1, and is used to increase the gate driving voltage and increase the subsequent driving capability. The buffer can be an inverter with several stages of gradually increasing device sizes or a circuit with a similar structure, such as two inverters connected in series.

[0070] In one embodiment, the number ratio between the multiple groups of first P-type field effect transistors and the number ratio between the multiple groups of second N-type field effect transistors may be the same. For example, the number ratio of the multiple groups of first P-type field effect transistors PM0 is M:M:2M:4M; the number ratio of the multiple groups of second N-type field effect transistors NN1 is K:K:2K:4K, then the number ratios may be considered to be the same.

[0071] In one embodiment, the adjustment ratio of the number of on-state transistors of the plurality of first P-type field effect transistors is the same as the adjustment ratio of the number of on-state transistors of the plurality of second N-type field effect transistors.

[0072] That is, R1 and R2 are equal in the above text. Among them, the number of the first P-type field effect tube PM0 that is turned on can be controlled by the first switch K0. The number of the first P-type field effect tube PM0 that is turned on can be M, 2M, 3M, 4M, 5M, 6M, 7M, 8M. The number of the second N-type field effect tube NN1 that is turned on can be controlled by the second switch K1. The number of the second N-type field effect tube NN1 that is turned on is K, 2K, 3K, 4K, 5K, 6K, 7K, 8K. Therefore, when the number of the first P-type field effect tube PM0 that is turned on is M. When the number of the second N-type field effect tube NN1 that is turned on is K, when the number of the first P-type field effect tube PM0 that is turned on is 2M, the number of the second N-type field effect tube NN1 that is turned on is 2K, and so on. It can be considered that the adjustment ratio of the number of turns on is the same.

[0073] In one embodiment, the switch control signals of the first switch and the second switch can be the same, so that the adjustment ratio of the number of conduction of the multiple groups of first P-type field effect transistors is the same as the adjustment ratio of the number of conduction of the multiple groups of second N-type field effect transistors, that is, the values ​​of R1 and R2 are controlled to be equal. The switch control signal can be used to control the first switch K0 and the second switch K1. When the switch control signals are the same, that is, the control signals of K0:1 and K1:1 are the same, the control signals of K0:2 and K1:2 are the same, the control signals of K0:3 and K1:3 are the same, and the control signals of K0:4 and K1:4 are the same, so that when the number ratio of the multiple groups of first P-type field effect transistors PM0 is the same as the number ratio of the multiple groups of second N-type field effect transistors NN1, the adjustment ratio of the number of conduction can be the same, that is, R1=R2, and thus after two current mirroring, it can be obtained:

[0074]

[0075]

[0076]

[0077]

[0078] That is to say, both R1 and R2 can be represented by R, and they can be offset by each other. By adjusting the ratio of the two mirror images of the resistor REXT, the accurate output current Iout can be obtained.

[0079] In one embodiment, when the output current is small, only K0:1 and K1:1 can be turned on. At this time, the accuracy of the constant current source is the best. When the output current Iout increases and exceeds the capacity of NM1:1, K0:2 and K1:2 are turned on. In this way, as the set output current Iout increases, switches K0:1~4 and K1:1~4 are turned on one by one, that is, when the current is small, a smaller number of NMOS devices are used to turn on, which will improve the current accuracy of the chip. In order to make the NMOS device in the linear region, it can be judged by monitoring the VGATE voltage. Once VGATE is too high or too low, we turn on the next level switch or turn off the current switch. In one embodiment, a comparator and a logic circuit can be set to automatically judge whether the VGATE voltage is too high or too low, so as to output the corresponding switch control signal to control the first switch K0 and the second switch K1. Ensure the accuracy of the current mirror in a larger current range, while reducing the power consumption of the chip. The following table shows the R value of the switch in different conduction states.

[0080]

[0081] At this time, use the following formula to calculate the static current of the chip:

[0082] Idis=Idis_ana+I0+I1+L*ICH

[0083] Among them, Idis represents the static current of the entire chip; Idis_ana represents the static current of other analog modules; I0 and I1 represent the two branch currents in the power supply circuit respectively; L represents the number of output constant current channels; ICH represents the static current of the analog circuit in the constant current source channel. In general, N / M>1, and K / J>1. Therefore, I1 is the one that changes the most in the static current of the chip.

[0084] Based on the circuit provided in the embodiment of the present application, As the output constant current source current Iout increases, R increases accordingly and I1 decreases. Therefore, it can be concluded that the circuit architecture provided in the embodiment of the present application can effectively reduce chip power consumption.

[0085] The power supply circuit provided in the embodiment of the present application can be applied to a driver chip, which can be a driver chip of an LED (Light Emitting Diode) display panel. The embodiment of the present application also provides a display device, which may include an LED display panel and a driver chip, and the LED display panel may be a common cathode or common anode structure. The driver chip is connected to the LED display panel, and the driver chip may include the power supply circuit provided in the embodiment of the present application, wherein there are multiple channel current output circuits; taking row drive as an example, a common anode refers to the anodes of multiple light-emitting diodes in the same row being connected together (for example, connected to +5V), and the output terminals IOUT of multiple channel current output circuits are respectively connected to the cathodes of multiple light-emitting diodes, and different cathode levels control different brightness. A common cathode refers to the cathodes of multiple light-emitting diodes in the same row being connected together (for example, grounded), and the output terminals IOUT of multiple channel current output circuits are respectively connected to the anodes of multiple light-emitting diodes, and different anode levels control different brightness.

[0086] The functional modules in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part. The connection mentioned in the text can be a direct connection or an indirect connection.

Claims

1. A power supply circuit, characterized in that: include: A reference current generating circuit is used to generate a reference current, and the reference current generating circuit includes: a first amplifier, whose reverse input terminal is used to input a reference voltage; a resistor, whose first terminal is grounded and whose second terminal is connected to the positive input terminal of the first amplifier; a plurality of groups of first P-type field effect transistors, whose sources are connected to a power supply, whose gates are respectively connected to the output terminals of the first amplifiers, whose drains are connected to the second terminals of the resistors, and which output the reference current to the resistors; a first switch, which is connected to the plurality of groups of first P-type field effect transistors and is used to independently control whether the first P-type field effect transistors of each group are turned on or off; A driving circuit connected to the reference current generating circuit, the driving circuit comprising: a second P-type field effect transistor, the source of which is connected to a power supply, the gate of which is connected to the gates of the plurality of groups of first P-type field effect transistors, and the drain of which is used to output a mirror current; a second amplifier, the reverse input of which is used to input a reference voltage, and the output of which is used to provide a gate driving voltage; a first N-type field effect transistor, the gate of which is connected to the output of the second amplifier, the source of which is grounded, the drain of which is connected to the drain of the second P-type field effect transistor and the positive input of the second amplifier, and is used to provide a bias voltage that is the same as the reference voltage; the driving circuit is used to generate a mirror current with an adjustable mirror ratio according to the reference current, and output the bias voltage and the gate driving voltage; A channel current output circuit, connected to the driving circuit, for receiving the bias voltage and the gate driving voltage, and generating a channel current with an adjustable mirror ratio according to the mirror current; Wherein, the plurality of groups of first P-type field effect transistors are four groups.

2. The power supply circuit according to claim 1, characterized in that: The channel current output circuit comprises: A third amplifier, a positive input terminal of which is connected to the drain of the first N-type field effect transistor; a third N-type field effect transistor, having a gate connected to the output end of the third amplifier; a source connected to the inverting input end of the third amplifier, and a drain used to output the channel current; A plurality of groups of second N-type field effect transistors, wherein the drains are respectively connected to the reverse input terminals of the third amplifier; the gates are respectively connected to the output terminals of the second amplifier; and the sources are grounded; The second switch is connected to a plurality of groups of the second N-type field effect transistors and is used to independently control whether the second N-type field effect transistors of each group are turned on or off.

3. The power supply circuit according to claim 2, characterized in that: The driving circuit further includes: A driving buffer is connected to the output end of the second amplifier and the gates of the plurality of groups of second N-type field effect transistors, and is used to increase the gate driving voltage.

4. The power supply circuit according to claim 2, characterized in that: The first switch includes a plurality of first sub-switches, which independently control the conduction of a plurality of groups of the first P-type field effect transistors; The second switch includes a plurality of second sub-switches, which independently control whether a plurality of groups of the second N-type field effect transistors are turned on or off.

5. The power supply circuit according to claim 2, characterized in that: The number ratio between the plurality of groups of first P-type field effect transistors is the same as the number ratio between the plurality of groups of second N-type field effect transistors.

6. The power supply circuit according to claim 5, characterized in that: The adjustment ratio of the number of turned-on transistors of the plurality of first P-type field effect transistors is the same as the adjustment ratio of the number of turned-on transistors of the plurality of second N-type field effect transistors.

7. The power supply circuit according to claim 6, characterized in that: The switch control signals of the first switch and the second switch are the same.

8. A display device, characterized in that: include: LED display panel, the LED display panel is a common cathode or common anode structure; A driving chip connected to the LED display panel, the driving chip comprising the power supply circuit according to claim 1, wherein there are multiple channel current output circuits; If the LED display panel is a common cathode structure, the plurality of channel current output circuits are respectively connected to anodes of a plurality of light emitting diodes of the LED display panel; If the LED display panel is a common anode structure, the plurality of channel current output circuits are respectively connected to cathodes of a plurality of light emitting diodes of the LED display panel.

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