Read refresh via signal calibration for non-volatile memory

Abstract

The present application relates to read refresh via signal calibration for non-volatile memory. A processing device in a memory subsystem initiates a read operation on each of a plurality of sectors in a first region of a memory device during a first time interval, wherein at least a subset of the plurality of sectors in the first region of the memory device stores host data. As a result of at least one read operation, the processing device further receives at least one data signal from a corresponding one of the plurality of sectors in the first region of the memory device, and uses the at least one data signal to perform a signal calibration operation to synchronize one or more related signals with a reference clock signal used by the processing device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to read refresh via signal calibration for non-volatile memory. Background Art

[0002] The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] One embodiment of the present application provides a system comprising: a memory device; a processing device operatively coupled to the memory device to perform operations including: initiating a read operation on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device stores host data; receiving at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device as a result of at least one read operation; and performing a signal calibration operation using the at least one data signal to synchronize one or more related signals with a reference clock signal used by the processing device.

[0004] Another embodiment of the present application provides a method, comprising: initiating a read operation on each of a plurality of segments in a first area of ​​a memory device during a first time interval, wherein at least a subset of the plurality of segments in the first area of ​​the memory device stores host data; receiving at least one data signal from a corresponding one of the plurality of segments in the first area of ​​the memory device as a result of at least one read operation; and performing a signal calibration operation using the at least one data signal to synchronize one or more related signals with a reference clock signal used by a processing device.

[0005] Yet another embodiment of the present application provides a non-transitory computer-readable storage medium comprising instructions which, when executed by a processing device, cause the processing device to perform the following operations: initiate a first read operation on a first segment of a plurality of segments in a first area of ​​a memory device, wherein at least a subset of the plurality of segments in the first area of ​​the memory device stores host data; receive a first data signal from the first segment in the first area of ​​the memory device as a result of the first read operation; use at least the first data signal to perform a signal calibration operation to synchronize one or more related signals with a reference clock signal used by the processing device; determine whether there are additional segments of the plurality of segments in the first area of ​​the memory device to be read during a first time interval; and systematically read the additional segments during the first time interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 is a block diagram illustrating the operation of a memory subsystem controller to perform a read refresh via signal calibration for a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart of an example method for performing read refresh via signal calibration for a non-volatile memory device according to some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method for performing read refresh via signal calibration for a non-volatile memory device according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram illustrating the operation of a signal calibration component that performs a read refresh for a memory device via signal calibration according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to read refresh via signal calibration for non-volatile memory in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (e.g., a memory device that stores data). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0014] The memory subsystem may include a plurality of memory devices that can store data from the host system. The memory device may be a non-volatile memory device, such as a three-dimensional cross-point ("3D cross-point") memory device that is a cross-point array of non-volatile memory that can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. Another example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The memory subsystem includes a memory subsystem controller that can communicate with the memory devices to perform operations such as reading data, writing data, or erasing data at the memory devices and other such operations. Figure 1 The memory subsystem controller is described in more detail.

[0015] The host system may send an access request (e.g., a write command, a read command) to the memory subsystem so as to store data on the memory device at the memory subsystem and read data from the memory device on the memory subsystem. As specified by the host request, the data to be read or written is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), name space) of the host data, which is the location that the host system associates with the host data. The logical address information (e.g., LBA, name space) may be part of the metadata of the host data. The metadata, together with the host data, is referred to as "payload" hereinafter. Metadata, host data, and parity data for error correction may collectively form an error correction code (ECC) codeword. Metadata may also include a data version (e.g., to distinguish the life of the written data), a valid bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0016] Each of the memory devices may include one or more memory cell arrays. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logic states associated with the number of bits stored. The logic states may be represented by binary values ​​such as "0" and "1" or combinations of these values. For example, a single level cell (SLC) may store one bit of information and have two logic states.

[0017] The memory subsystem may initiate a media management operation, which may include performing, for example, a write operation or a read operation, a refresh or fold operation, or other operation on host data stored on the memory device. For example, the memory subsystem may rewrite previously written host data from a location on the memory device to the same location or a new location as part of a write refresh operation. In another example, the media management operation may include rereading host data stored on the memory device as part of a read refresh operation. "User data" hereinafter generally refers to host data and data rewritten as part of media management. "System data" hereinafter refers to data generated and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical to physical address mapping tables), data from records, scratch pad data, etc.

[0018] The storage of data at the memory device may increase the wear of the memory device. After a threshold amount of write operations, the wear may render the memory device unreliable, such that data can no longer be reliably stored and retrieved from the memory device. As the number of write operations and / or erase operations performed on the memory cell increases, the probability that the data stored at the memory cell contains errors increases due to the increasing damage to the memory cell. The additional read and write operations may also result in a higher error rate for the data stored at the memory cell. This may increase the use of error recovery operations, including but not limited to read retries (i.e., sensing the memory component again) and RAID (Redundant Array of Independent Disks) for subsequent data operations (e.g., reads and / or writes) performed on the memory cell. The increased use of error recovery operations may result in reduced performance of conventional memory subsystems. In addition, as the error rate continues to increase, it may even exceed the error recovery capabilities of the memory subsystem, thereby causing irreparable loss of data. In addition, because more resources of the memory subsystem are used to perform error recovery operations, fewer resources are available to perform other read operations or write operations.

[0019] For certain memory types (i.e., for memory subsystems that employ certain types of storage media), error rates may vary over time. Specifically, some non-volatile memories have a threshold voltage (Vt) distribution that moves over time (hereinafter referred to as 'intrinsic movement'). At a given read level (i.e., the voltage applied to the memory cell as part of a read operation), if the Vt distribution moves, then certain reliability statistics may also be affected. An example of a reliability statistic is the raw bit error rate (RBER). The RBER may be defined as the ratio of the number of erroneous bits to the number of all data bits stored in the cells of the memory subsystem, where the cell may be the entire memory subsystem, a die of a memory component, a series of codewords, or any other meaningful portion of the memory subsystem. Since the Vt distribution may be constantly affected by intrinsic movement, interference from itself or neighboring cells, circuit system noise, temperature, etc., various refresh operations may be performed to restore the Vt distribution to a desired state. For example, a write refresh operation includes rewriting the data of a memory cell to the same or different physical memory location in order to give the cell a clean slate without the severe inherent shifts of the Vt distribution, interference effects, and noise. The cell may be rewritten one or more times according to its current state (i.e., a logic '0' is rewritten to a logic '0' and a logic '1' is rewritten to a logic '1') or rewritten a certain even number of times in an alternating state (i.e., a logic state that is inverted for the first rewrite and restored for the second rewrite). However, a write refresh operation is expensive in terms of subsystem performance and memory component endurance, so in conventional memory subsystems, a read refresh operation may be preferred in certain situations. A read refresh operation involves reading the contents of a memory cell to take advantage of the partial write effect that occurs with a read operation. For certain types of memory components, a read operation may change the Vt distribution of a memory cell, which is also referred to as a partial write effect. For example, in a read operation, any unit voltage that is lower than and / or close to an applied read voltage may be physically pushed further away from the point of the read voltage. The result of a read refresh performed at the optimal read voltage is recovery of the Vt distribution and additional separation between Vt distributions, a larger read window budget (RWB) and improved RBER and noise robustness.

[0020] In addition, many high-speed electronic systems including memory subsystems operate with critical timing requirements that dictate the need to use a periodic clock waveform with a precise timing relationship relative to a reference signal. The accuracy of signals transmitted between components, such as between a memory subsystem controller and a memory device, relies on synchronization between the corresponding signals of each component. While some signals should be perfectly aligned (e.g., have zero offset so that signal transitions occur simultaneously), other signals may have a specific non-zero offset so that signal transitions occur after a known amount of time delay. Even for integrated circuits implemented on the same board or package, various factors may cause the timing signals of different components to drift and / or fluctuate over time. For example, different manufacturing parameters, process variations, ambient temperature, applied voltage, clock jitter, noise, and interference may all cause large phase differences in the corresponding signals. Therefore, the memory subsystem may continuously perform signal calibration operations during the start-up of the memory device contained therein. These signal calibration operations detect whether the corresponding clock signals or other signals of the memory subsystem controller and the memory device remain synchronized to ensure the integrity of the data transmitted between the two components. For example, the memory subsystem controller may periodically collect output data read from the memory device and execute a signal processing routine to optimize the signal offset internally. This period may be as short as one or several microseconds, which results in a large number of signal calibration read operations being performed over time.

[0021] Aspects of the present disclosure address the above and other deficiencies by performing read refresh via signal calibration for non-volatile memory. In one embodiment, a memory subsystem controller allocates a dual-purpose area of ​​one or more memory devices in a memory subsystem for both servicing host-initiated memory operations and performing signal calibration operations. Thus, the memory segments of this area can store host data and can be read by the memory subsystem controller for signal calibration. In one embodiment, the memory subsystem controller systematically initiates a read operation on each of the segments in the area during a first time interval. As a result of each read operation, the memory subsystem controller receives a data signal from a corresponding one of the segments in the area and uses the data signal to perform a signal calibration operation to synchronize the related signals with a reference clock signal used by the memory subsystem controller. Depending on the embodiment, the memory subsystem may include any number of related signals with corresponding synchronization requirements, which may be optimized (for synchronization purposes) based on the received data signals. These related signals may include, for example, a data signal (DQ), a data strobe signal (DQS), a data mask signal (DM), a command / address signal (CA), or some other signal. The memory subsystem controller may read each sector sequentially or in some other systematic manner to ensure that each sector in the region of the memory device will be read at least once during the first time interval for purposes of signal calibration. In another embodiment, the signal calibration operation is based on a batch of reads (e.g., a set number of recent read operations) rather than on a single signal from one read operation. For example, the memory subsystem controller may receive a number of data signals from a set number of read operations that each correspond to a different sector, and may group the read operations together and perform signal calibration based on the combination.

[0022] Advantages of the present disclosure include, but are not limited to, improved performance in a memory subsystem. By reading each segment in a designated area, where at least a portion of these segments store host data, the memory subsystem controller performs sufficient signal calibration read operations to ensure that relevant clock signals used by the memory device and the memory subsystem controller remain synchronized. In addition, the capacity of the memory device available for storing host data is increased because a portion of the memory device does not need to be separately reserved for signal calibration read operations, and repeated read operations do not damage such dedicated areas. In addition, the system signal calibration read performed during the first time interval provides the additional benefit of read refresh to the segments in the area of ​​the memory device. Therefore, the memory subsystem controller can reduce or even eliminate the number and frequency of management read refresh operations performed on the area of ​​the memory device. This allows system resources to be used for operations, including servicing host memory access operations, thereby improving performance and reducing latency.

[0023] Figure 1An example computing environment 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0024] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0025] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0026] The host system 120 may be a computing device such as a desktop computer, a notebook computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transportation), an Internet of Things (IoT) device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such computing devices including a memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 .

[0027] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memories and write-in-place memories, such as three-dimensional cross-point ("3D cross-point") memory. A 3D cross-point memory device is a cross-point array of non-volatile memory cells that can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells.

[0029] Although non-volatile memory components such as 3D cross-point type and NAND type memory are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), or non-volatile (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] One type of memory cell, such as a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a three-level cell (TLC), and a four-level cell (QLC), may store multiple bits per cell. In some embodiments, a particular memory component may include an SLC portion of a memory cell, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages or codewords that may refer to cells of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D crosspoint) may group pages across dies and channels to form management units (MUs).

[0031] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0034] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. In some embodiments, memory device 130 may be a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 includes a signal calibration component 113. In one embodiment, the signal calibration component 113 may perform signal calibration operations during the start-up of the memory device 130. These signal calibration operations detect whether the corresponding clock signals of the memory subsystem controller 115 and the memory device 130 remain synchronized to ensure the integrity of the data transmitted between the two components. In one embodiment, for example, the signal calibration component 113 may periodically collect output data read from the memory device 130 and perform a signal processing routine to internally optimize the signal offset. In one embodiment, the signal calibration component 113 systematically initiates a read operation on each of the sectors in a given zone of the memory device 130 during a first time interval. As a result of each read operation or a batch of read operations, the signal calibration component 113 receives one or more data signals from a corresponding one or more of the sectors in the zone and uses the data signals to perform signal calibration operations to synchronize the relevant signals (e.g., DQ, DQS, DM, CA) with the reference clock signal used by the memory subsystem controller 115. The signal calibration component 113 can read each segment sequentially or in some other systematic manner to ensure that each segment in a region of the memory device will be read at least once during the first time interval for purposes of signal calibration.

[0038] Compared to conventional systems, the signal calibration component 113 performs these signal calibration read operations on the segments of the memory device 130 storing host data. These conventional systems typically include a fixed redundant area of ​​the memory device that is repeatedly read for signal calibration throughout the life of the memory device. This fixed redundant area is transparent to the media management operations of the memory subsystem controller 115 and is treated as non-existent. Therefore, this area reduces the space available on the memory device for storing host data. In addition, since the signal calibration read operations can be performed at a very high rate, the number of read operations performed on this dedicated area can be very high, causing physical damage to the segments in the area and early failure of the memory device. Other conventional systems perform register read operations on the memory device 130 for signal calibration purposes. Some memory devices have strict constraints on when the memory subsystem controller can perform register read operations, which may prevent register reads from being performed at a frequency sufficient to meet signal calibration requirements. In addition, conventional techniques do not take advantage of the read refresh characteristics of the segments of the memory device storing host data, thereby requiring the memory subsystem controller to issue a sufficient number of management read refresh operations on the segments of the memory device respectively.

[0039] However, when a dual-purpose region of the memory device 130 is identified (i.e., a region that includes segments that store host data and can be read by the signal calibration component 113 for performing signal calibration operations), the above-identified disadvantages are eliminated. In one embodiment, when the signal calibration component 113 spreads the signal calibration read operations across the entire region of the memory device 130 (i.e., where this region can include all or substantially all available segments on the memory device 130), both signal calibration and read refresh objectives can be achieved simultaneously. Additional details regarding the operation of the signal calibration component 113 are described below.

[0040] Figure 2 1 is a block diagram illustrating the operation 200 of the memory subsystem controller 115 to perform a read refresh for the memory device 130 via signal calibration according to some embodiments of the present disclosure. In one embodiment, the memory subsystem controller 115 is operatively coupled to the memory device 130 via one or more electrical connections (e.g., one or more buses). Depending on the embodiment, the one or more buses may include a number of separate communication channels 210, 212, 214. Each of the separate communication channels 210, 212, 214 may separately transmit data and / or command signals between the memory subsystem controller 115 and the corresponding portion of the memory device 130. The memory subsystem controller 115 may transmit and receive these signals using one or more internal clock signals (also referred to herein as "reference clock signals" or "reference clock signals"). In one embodiment, the memory subsystem controller 115 may transmit and receive signals on each of the communication channels 210, 212, 214 using a single common reference clock signal. In another embodiment, the memory subsystem controller 115 may transmit and receive signals for each of the communication channels 210 , 212 , 214 using a separate reference clock signal.

[0041] In one embodiment, the signal calibration component 113 may identify one or more zones in the memory device 130, such as the zone 232 and the zone 234. The zones in the memory device 130 may be physically or logically separated, and each zone may include any number of memory segments. Depending on the underlying media type used for the memory device 130, each zone may be defined, for example, as one or more basic units (e.g., pages), one or more managed units (e.g., groups of pages or ECC codewords), or any other applicable slices or partitions of the memory device 130. Depending on the embodiment, the size and arrangement of the zones 232 and 234 may be flexible and may change during the useful life of the memory device 130. For example, either or both of the zones 232 and 234 may include one or more of a mapped area, an unmapped area, a reserved area, and / or a deregistered area. The mapped area may include one or more segments that currently store host data (i.e., data stored on behalf of the host system 120). Segments from a mapped area may become unmapped over time, such as when data stored at a mapped segment is moved to a different segment as part of a wear leveling operation. An unmapped area may include one or more segments that are not currently storing host data but are eligible to store host data. Segments from an unmapped area may become mapped over time, such as when data stored at an unmapped segment is moved to a mapped segment as part of a wear leveling operation. A reserved area may include one or more segments that may be used to replace a defective segment on the memory device 130, and a cancelled area may include one or more defective segments that previously stored host data.

[0042] In one implementation, the signal calibration component 113 may perform a signal calibration operation during the power-up of the memory device 130. To do so, the signal calibration component 113 may identify a certain region of the memory device 130, such as the region 232, and initiate a read operation of each of the individual sectors in the region 232. As described above, the region 232 may include a portion of the memory device 130, or may include all sectors of the memory device 130. Regardless of size or arrangement, the region 232 may include at least some sectors that store or may be used to store host data on behalf of the host system 120. For example, at least some of the sectors in the region 232 may store data written to the memory subsystem 110 by the host system 120 or data to be read from the memory subsystem by the host system 120.

[0043] In one embodiment, each of the communication channels 210, 212, 214 is used to send and receive signals from multiple memory dies of the memory device 130. In one embodiment, the region 232 may include multiple memory dies and may be accessed using multiple communication channels 210, 212, 214. Depending on the reference clock signal involved, the signal calibration component 113 may perform a single signal calibration for all communication channels 210, 212, 214, a single signal calibration for a subset of the communication channels, or a separate signal calibration for each of the communication channels. In one embodiment, the signal calibration component 113 may periodically collect output data read from certain sections of the region 232 of the memory device 130 and received via one or more of the communication channels 210, 212, 214. The signal calibration component 113 may use the data signal from each section of the region 232 to perform a signal calibration operation to synchronize the relevant signals with the reference clock signal used by the memory subsystem controller 115. In one embodiment, the signal calibration operation includes a signal processing routine to internally optimize the signal offset to ensure that the signals are fully aligned. The signal calibration component 113 can repeat this process periodically for each segment in the region 232 to ensure that the synchronization of the clock signal is verified at regular intervals and that each segment of the region 232 is read within a certain time interval to take advantage of the read refresh properties of the underlying storage medium. Thus, compared to embodiments where the signal calibration reads do not involve the region 232 of the memory device 130, the signal calibration component 113 can schedule management of read refresh operations on the segments of the region 232 at a reduced or even eliminated frequency.

[0044] Figure 3 300 is a flowchart of an example method for performing read refresh via signal calibration for a non-volatile memory device according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The signal calibration component 113 of the embodiment is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0045] At operation 310, processing logic turns on (or detects turning on) a memory subsystem 110 that includes one or more memory devices (e.g., memory device 130). At operation 320, processing logic identifies a region of the memory device 130 that is designated for signal calibration, such as region 232. In one embodiment, region 232 may be a physical or logical partition of the memory device 130. Region 232 may include, for example, one or more of a mapped area, an unmapped area, a reserved area, and / or a cancelled area. In one embodiment, at least a subset of the sectors in region 232 stores host data from the host system 120. This subset may include, for example, a portion of region 232 or all of region 232. Depending on the embodiment, region 232 may include all sectors of the memory device 130, or a portion of the sectors of the memory device 130.

[0046] At operation 330, processing logic systematically performs signal calibration read operations on segments of zone 232 at a specified rate during a first time interval. Figure 4 Described in more detail, the signal calibration component 113 may periodically collect output data read from each segment of the region 232, and use each data signal or a series of recent data signals read from the region 232 to perform a signal calibration operation to internally optimize the signal offset. The signal calibration component 113 may read each segment of the region 232 sequentially or in some other systematic manner to ensure that each segment in the region 232 of the memory device will be read at least once during the first time interval for the purpose of signal calibration. The first time interval may be set according to the frequency at which each segment in the region 232 should be read in order to utilize the read refresh capability and ensure constant operation of the memory device 130.

[0047] At operation 340, processing logic optionally schedules read refresh operations on the segments of the region 232 storing host data at a first frequency. In one embodiment, the first frequency is based on the length of the first time interval. Compared to embodiments where the signal calibration read does not involve the region 232 of the memory device 130, the signal calibration component 113 may schedule the management read refresh operations on the segments of the region 232 at a reduced or even eliminated frequency. For example, if the physical characteristics of the memory device 130 indicate a frequency at which read refresh operations are performed, the frequency may be reduced to the first frequency given that the signal calibration component 113 performs a signal calibration read on each segment of the region 232 (which provides the same benefits as the management read refresh operations).

[0048] At operation 350, processing logic determines whether a change to zone 232 is detected. Over the useful life of memory device 130, numerous factors may affect zone 232. For example, the size of zone 232 may increase or decrease, such as when a canceled area or a reserved area is used to perform signal calibration reads. The size of zone 232 may change when a segment is added to a canceled area or removed from a reserved area. In addition, although the actual size of zone 232 may not change, the actual coverage of zone 232 may change, such as when a mapped area or an unmapped area is used to perform signal calibration reads. Furthermore, both the size and actual coverage of zone 232 may change. If no change to zone 232 is detected, processing logic returns to operation 330 and continues to systematically perform read operations on segments of zone 232.

[0049] If a change to the zone 232 is detected, then at operation 360, the processing logic identifies the updated zone designated for signal calibration and returns to operation 330 and systematically performs read operations on segments of the updated zone. For example, the updated zone may include the zone 234, a portion of the zone 232 and all of the zone 234, a portion of the zone 232 and a portion of the zone 234, all of the zone 232 and all of the zone 234, all of the zone 232 and a portion of the zone 234, or any other combination.

[0050] Figure 4 400 is a flowchart of an example method for performing read refresh via signal calibration for a non-volatile memory device according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The signal calibration component 113 of the embodiment is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0051] At operation 410, processing logic determines whether a threshold time period has expired. In one embodiment, the threshold time period is based on a system requirement for signal calibration (i.e., how often a signal calibration needs to be performed in order to ensure accurate operation of the memory subsystem). Thus, for a given number of sectors in a region 232 of a memory device 130, the first time interval represents a time period during which all sectors of a region 232 of the memory device 130 may be read using a signal calibration read operation, where each read is separated by a threshold time period. Thus, given a particular signal calibration requirement, the threshold time period represents how often the sectors in the region 232 must be read in order to ensure that a signal calibration can be successfully performed.

[0052] If the threshold time period has expired, then at operation 420, processing logic initiates a read operation on the segment in region 232 of memory device 130. In one embodiment, to initiate a read operation, signal calibration component 113 identifies the current / next segment to be read according to the algorithm being used (see Figure 5 ) and applies a corresponding read voltage signal to the identified segment. At operation 430, as a result of the read operation, processing logic receives a data signal from a corresponding segment in region 232 of memory device 130. In one embodiment, signal calibration component 113 receives one or more data signals, which may include a voltage waveform or a waveform representing one or more values ​​stored in a corresponding memory segment.

[0053] At operation 440, the processing logic uses the data signal (or a batch of data signals) to perform a signal calibration operation to synchronize the related signals with the reference clock signal used by the memory subsystem controller 115. In one embodiment, the signal calibration component 113 compares one or more data signals read from one or more sections of the area 232 with the reference clock signal. The signal calibration component 113 can use a signal processing routine to optimize the offset of the related signals (e.g., DQ, DQS, DM, CA). For example, in one embodiment, the signal calibration component 113 can compare the offset between the transitions of each signal to ensure that the offset is within the allowable deviation from the expected value. Depending on the embodiment, the expected offset may be zero or some other non-zero value. In one embodiment, the signal calibration component 113 compares the received data signal with a separate clock signal used by the memory subsystem controller 115 to determine the offset and optimizes the offset of the related signal according to the determined offset. In another embodiment, the signal calibration component 113 directly compares the related signal with the received data signal to determine the signal transition offset. In other embodiments, some other signal processing routine may be used.

[0054] At operation 450, processing logic determines whether there are additional segments in the first zone 232. If there are additional segments in the first zone 232, processing logic returns to operation 410 and performs operations 420-440 for each remaining segment in the first zone 232. If there are no additional segments in the first zone 232, at operation 460, processing logic restarts signal calibration for the first zone 232.

[0055] Figure 5 is a block diagram illustrating the operation 500 of the signal calibration component 113 performing a read refresh for the memory device 130 via signal calibration according to some embodiments of the present disclosure. In one embodiment, the memory device 130 may include multiple memory dies, such as memory dies 510, 520, 530, each of which includes a number of memory segments. Depending on the embodiment, the identified region 232 of the memory device 130 may also span multiple memory dies. In different embodiments, the signal calibration component 113 may use different algorithms to ensure that each of the memory components across the multiple memory dies 510, 520, 530 is read by the signal calibration read operation during the first time interval.

[0056] In one embodiment, the signal calibration component 113 reads each segment of a given memory die 510 in sequence until all segments in the memory die 510 have been read. For example, the signal calibration component 113 may sequentially read segments 512, 514, and so on, ending with segment 516. Then, the signal calibration component 113 may switch to the next memory die, such as memory die 520, sequentially reading segments 522, 524, and so on, ending with segment 526. The signal calibration component 113 may repeat this process in the same manner for all memory dies, ending with memory die 530, and sequentially reading segments 532, 534, and so on, until segment 536. Once all segments on all memory dies of the memory device 130 (or in the region 232) have been read, the signal calibration component 113 may return to the first memory die 510 and continue the process.

[0057] In another embodiment, the signal calibration component 113 reads the first segment of each memory die, then reads the second segment of each memory die, then reads the third segment of each memory die, etc. For example, the signal calibration component 113 may read segment 512 of memory die 510, then reads segment 522 of memory die 520, and then reads segment 532 of memory die 530. After reading the first segment on each of the memory dies 510, 520, 530, the signal calibration component 113 may return to the first memory die 510 and begin reading the second segment of each memory die. For example, the signal calibration component 113 may read segment 514 of memory die 510, then read segment 524 of memory die 520, and then read segment 534 of memory die 530. Signal calibration component 113 can repeat this process in the same manner, concluding by reading segment 516 of memory die 510, segment 526 of memory die 520, and segment 536 of memory die 530. Once all segments on all memory dies of memory device 130 (or in region 232) have been read, signal calibration component 113 can return to first memory die 510 and continue the process.

[0058] Other algorithms are possible depending on the embodiment, and depending on the specific media type used for memory device 130. For example, each memory die 510, 520, 530 may have other meaningful intermediate hierarchies (e.g., layers, planes, etc.) between individual memory cells and memory dies. Thus, other multiple-fold loops may be formed to ensure that each sector is read. Furthermore, the order in which these nested loops are followed may be arbitrary, depending on hardware implementation details.

[0059] Figure 6 An example machine of a computer system 600 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0060] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0061] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0062] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, and the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

[0063] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside completely or at least partially within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0064] In one embodiment, the instructions 626 include instructions for implementing the Figure 1The signal calibration component 113 of the present invention is provided with instructions for the functionality of the signal calibration component 113. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0065] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0066] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0067] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0068] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0069] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0070] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A system for memory operation, comprising: Memory device; a processing device operatively coupled to the memory device to perform operations including: initiating a series of consecutive read operations on a plurality of sectors in a first region of the memory device to read data from each of the plurality of sectors at least once during a first time interval, wherein at least a subset of the plurality of sectors in the first region of the memory device stores host data; receiving, as a result of the series of consecutive read operations, a plurality of data signals corresponding to the plurality of sectors in the first region of the memory device read at least once during the first time interval; as well as One or more signal calibration operations associated with a signal calibration requirement are performed using the multiple data signals read from the multiple segments by the series of continuous read operations during the first time interval to synchronize the multiple data signals with a reference clock signal used by the processing device, wherein performing the one or more signal calibration operations includes comparing offsets between transitions of the multiple data signals and the reference clock signal, and if the offsets are not within an allowable deviation from an expected value, adjusting the offsets to synchronize the multiple data signals.

2. The system of claim 1, wherein the first zone comprises one or more of: a mapped area having one or more sectors currently storing host data; an unmapped area having one or more sectors that do not currently store host data but are eligible to store host data; a reserved area having one or more sectors that can be used to replace defective sectors on the memory device; or A cancelled area has one or more defective sectors that previously stored host data.

3. The system of claim 1, wherein the first region includes all of the segments of the memory device.

4. The system of claim 1 , wherein the series of consecutive read operations is initiated in response to detecting expiration of a first threshold time period associated with the signal calibration requirement, and wherein the first time interval is based on the first threshold time period and the number of the plurality of sectors in the first region of the memory device, and wherein the processing device is configured to further perform operations comprising: Initiating a subsequent threshold time period in response to expiration of at least one read operation in the series of consecutive read operations; and A subsequent read operation is initiated in response to the expiration of the subsequent threshold time period.

5. The system of claim 1, wherein the memory device comprises a plurality of memory dies, and wherein the first region of the memory device spans the plurality of memory dies.

6. The system of claim 5, wherein initiating the read operation on each of the plurality of sectors in the first region of the memory device comprises: sequentially reading each sector on a first memory die of the plurality of memory dies; as well as After sequentially reading each sector on the first memory die, sequentially reading each sector on a second memory die of the plurality of memory die.

7. The system of claim 6, wherein initiating the read operation on each of the plurality of sectors in the first region of the memory device comprises: reading a first sector on each of the plurality of memory dies; as well as After reading the first sector on each of the plurality of memory dies, a second sector on each of the plurality of memory dies is read.

8. The system of claim 1, wherein the processing device is configured to further perform operations comprising: determining a change to the first region of the memory device, the change forming a second region of the memory device; initiating a second read operation on each of a plurality of sectors in the second region of the memory device; receiving at least one second data signal from a corresponding second segment of the plurality of segments in the second region of the memory device as a result of at least one second read operation; as well as A second signal calibration operation is performed using the at least one second data signal to synchronize the at least one second data signal with the reference clock signal used by the processing device.

9. The system of claim 1, wherein the processing device is configured to further perform operations comprising: Read refresh operations are scheduled on the subset of the plurality of sectors in the first region of the memory device storing host data at a first frequency, wherein the first frequency is based on a length of the first time interval.

10. A method for memory operation, comprising: initiating a series of consecutive read operations on a plurality of sectors in a first region of a memory device to read data from each of the plurality of sectors at least once during a first time interval, wherein at least a subset of the plurality of sectors in the first region of the memory device stores host data; receiving, as a result of the series of consecutive read operations, a plurality of data signals corresponding to the plurality of sectors in the first region of the memory device read at least once during the first time interval; as well as One or more signal calibration operations associated with a signal calibration requirement are performed using the multiple data signals read from the multiple segments by the series of continuous read operations during the first time interval to synchronize the multiple data signals with a reference clock signal used by a processing device, wherein performing the one or more signal calibration operations includes comparing offsets between transitions of the multiple data signals and the reference clock signal, and if the offsets are not within an allowable deviation from an expected value, adjusting the offsets to synchronize the multiple data signals.

11. The method of claim 10, wherein the first region comprises one or more of: a mapped area having one or more sectors currently storing host data; an unmapped area having one or more sectors that do not currently store host data but are eligible to store host data; a reserved area having one or more sectors that can be used to replace defective sectors on the memory device; or A cancelled area has one or more defective sectors that previously stored host data.

12. The method of claim 10, wherein the first region includes all of the sectors of the memory device.

13. The method of claim 10, wherein the series of consecutive read operations is initiated in response to detecting expiration of a first threshold time period associated with the signal calibration requirement, and wherein the first time interval is based on the first threshold time period and the number of the plurality of sectors in the first region of the memory device, and the method further comprises: starting a subsequent threshold time period in response to expiration of at least one read operation in the series of consecutive read operations; as well as A subsequent read operation is initiated in response to the expiration of the subsequent threshold time period.

14. The method of claim 10, wherein the memory device comprises a plurality of memory dies, and wherein the first region of the memory device spans the plurality of memory dies.

15. The method of claim 14, wherein initiating the read operation on each of the plurality of sectors in the first region of the memory device comprises: sequentially reading each sector on a first memory die of the plurality of memory dies; as well as After sequentially reading each sector on the first memory die, sequentially reading each sector on a second memory die of the plurality of memory die.

16. The method of claim 14, wherein initiating the read operation on each of the plurality of sectors in the first region of the memory device comprises: reading a first sector on each of the plurality of memory dies; as well as After reading the first sector on each of the plurality of memory dies, a second sector on each of the plurality of memory dies is read.

17. The method according to claim 10, further comprising: determining a change to the first region of the memory device, the change forming a second region of the memory device; initiating a second read operation on each of a plurality of sectors in the second region of the memory device; receiving at least one second data signal from a corresponding second segment of the plurality of segments in the second region of the memory device as a result of at least one second read operation; as well as A second signal calibration operation is performed using the at least one second data signal to synchronize the at least one second data signal with the reference clock signal used by the processing device.

18. The method according to claim 10, further comprising: Read refresh operations are scheduled on the subset of the plurality of sectors in the first region of the memory device storing host data at a first frequency, wherein the first frequency is based on a length of the first time interval.

19. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: initiating a first read operation on a first segment of a plurality of sectors in a first region of a memory device, wherein at least a subset of the plurality of sectors in the first region of the memory device stores host data; receiving a first data signal from the first segment in the first region of the memory device as a result of the first read operation; performing a signal calibration operation using at least the first data signal to synchronize at least the first data signal with a reference clock signal used by the processing device; determining that there are additional segments of the plurality of segments to be read during a first time interval in the first region of the memory device; operating the additional sectors in a series of consecutive additional read operations to read data from each of the additional sectors at least once during the first time interval; receiving, as a result of the series of consecutive read operations, a plurality of data signals corresponding to the plurality of sectors in the first region of the memory device read at least once during the first time interval; as well as One or more signal calibration operations associated with a signal calibration requirement are performed using the multiple data signals read from the multiple segments by the series of continuous read operations during the first time interval to synchronize the multiple data signals with the reference clock signal used by the processing device, wherein to perform the one or more signal calibration operations, the processing device compares offsets between transitions of the multiple data signals and the reference clock signal, and if the offsets are not within an allowable deviation from an expected value, adjusts the offsets to synchronize the multiple data signals.

20. The non-transitory computer-readable storage medium of claim 19, wherein the instructions further cause the processing device to: and scheduling read refresh operations on the subset of the plurality of sectors storing host data in the first region of the memory device at a first frequency, wherein the first frequency is based on a length of the first time interval, wherein the first read operation is initiated in response to detecting an expiration of a first threshold time period associated with the signal calibration requirement, and wherein the length of the first time interval is based on the first threshold time period and a number of the plurality of sectors in the first region of the memory device.

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