Storage and calculation integrated calculation module based on OAM form

Abstract

The invention provides a storage and calculation integrated calculation module based on an OAM (Operation Administration and Maintenance) form, which is used for integrating a plurality of storage and calculation integrated chips of different types and realizing communication between a CPU (Central Processing Unit) and the storage and calculation integrated chips, and is characterized in that an external interface of the calculation module is connected with an external UBB (Universal Business Business) bottom plate by adopting an interface designed by an OAM protocol; the calculation module comprises a power supply interlayer card, a controller card and a memory operator card which are sequentially connected in a stacked mode, and the power supply interlayer card is configured in the mode that a power supply interface designed through an OAM protocol is used for conducting power supply conversion, supplying power to the controller card and the memory operator card and providing a path for data signal transmission between the controller card and a CPU on an external UBB bottom plate; the controller card is configured to perform conversion among different protocols, and communication and data signal transmission between the operator card and a CPU (Central Processing Unit) on the external UBB bottom plate; the storage operator card is configured to store a data signal and provide a chip connection interface for one or more storage and calculation integrated chips; and a data signal is transmitted to the storage and calculation integrated chip connected with the chip connecting interface through the chip connecting interface.

Description

Technical Field

[0001] The present invention relates to the field of computer hardware structure and design, specifically, to the hardware field of storage-computing integrated computing, and more specifically, to a storage-computing integrated computing module based on the OAM form. Background Art

[0002] In the past two decades, processor performance has increased at a rate of about 55% per year, while memory performance has only increased at a rate of about 10% per year. As a result, the uneven performance improvement rate has caused the current storage speed to lag seriously behind the processor's computing speed in the long run. In the setting of traditional computers, the storage module serves computing, so the design will consider the separation and priority of storage and computing. But now, storage and computing have to be considered as a whole to serve data collection, transmission and processing in the best possible way. Here, the redistribution process of storage and computing will face various problems, which are mainly reflected in the problems of storage wall, bandwidth wall and power consumption wall.

[0003] With the continuous development of artificial intelligence technology, computing models are constantly developing and breaking through on a large scale, which requires the support of large-scale computing. However, due to the inherent disadvantages of analog computing, there are few cases of integration of more than 100Mb in the current storage-computing technology single-chip array, which makes it difficult for the current storage-computing technology to provide support for large-scale computing problems.

[0004] The storage-computing integrated computing module is an innovative computing architecture, which is mainly based on integrating computing functions directly into the storage unit, thereby reducing the need to move data between the processor and the memory, effectively reducing energy consumption and improving computing efficiency. It is divided into in-memory computing and near-memory computing. However, its defect is that it will cause the storage-computing integrated module to be unable to be systematically integrated: since the research on storage-computing integration is still at the forefront, everyone's research focus is still on the realization of the storage-computing integrated architecture inside the chip. The form of the storage-computing integrated computing card generally refers to the form of the storage medium. For example, the near-memory computing card is generally designed as an HBM interface or a DIMM interface. The in-memory computing card currently has various forms, and there is no industry-standard interface form. The difference in physical form interfaces causes the storage-computing integrated module to be unable to be well integrated into the system. The existing implementation of the storage-computing integrated computing module is mainly concentrated in the research of storage-computing integrated chips. For example, the application number is: CN20110498977, and the invention name is: energy storage and computing integrated unit and state control method, integrated module, processor and device, which mainly focuses on the research of storage-computing integrated chips. From the perspective of chip research, the existing integrated storage and computing modules cannot meet the needs of system integration of integrated storage and computing modules.

[0005] Therefore, when faced with storage and computing chips with different architectures, the existing storage and computing integrated computing modules are unable to achieve the problem of highly integrating and scheduling the storage and computing chips with different architectures.

[0006] It should be noted that this background technology is only used to introduce the relevant information of the present invention to help understand the technical solution of the present invention, but it does not mean that the relevant information is necessarily the prior art. The relevant information is submitted and disclosed together with the present invention solution. If there is no evidence that the relevant information has been disclosed before the application date of the present invention, the relevant information shall not be regarded as the prior art. Summary of the invention

[0007] Therefore, the purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a storage and computing integrated computing module based on the OAM form.

[0008] The objective of the present invention is achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, there is provided an integrated storage and computing module based on an OAM form, which is used to integrate multiple integrated storage and computing chips of different types and realize communication between the CPU and the integrated storage and computing chip. The external interface of the computing module adopts an interface designed by the OAM protocol to be connected to an external UBB baseboard. The computing module comprises: a power mezzanine card, a controller card and a storage and computing sub-card which are arranged on the UBB baseboard and are stacked in sequence, wherein the power mezzanine card is configured to: use a power interface designed by the OAM protocol to perform power conversion, supply power to the controller card, the storage and computing sub-card and the integrated storage and computing chip, and provide a path for data signal transmission between the controller card and the CPU on the external UBB baseboard; the controller card is configured to: perform conversion between different protocols, and communicate and transmit data signals between the storage and computing sub-card and the CPU on the external UBB baseboard; the storage and computing sub-card is configured to: store data signals and provide a chip connection interface for one or more integrated storage and computing chips, wherein data signals are transmitted to the integrated storage and computing chip connected to the interface through the chip connection interface.

[0010] In some embodiments of the present invention, the controller card includes an FPGA chip, and the FPGA chip is configured to: convert the private protocol on the storage and computing sub-card into a PCIE protocol, convert the PCIE protocol into a GPIO protocol, and control the data signal transmission between the CPU on the external UBB baseboard and the storage and computing integrated chip.

[0011] In some embodiments of the present invention, the controller card includes multiple interfaces connected to the FPGA chip, the multiple interfaces include a logic interface, a high-speed GPIO interface and a PCIE interface connected to the external UBB baseboard, the logic interface is designed using the OAM protocol, and the high-speed GPIO interface is designed using the private protocol supported by each storage and computing integrated chip, wherein the logic interface is used to receive the private protocol transmitted from the storage and computing sub-card, and to transmit the PCIE protocol to the CPU on the external UBB baseboard or receive the PCIE protocol from the CPU on the external UBB baseboard; the high-speed GPIO interface is used to transmit data signals between the controller card and the storage and computing sub-card; the PCIE interface is used to communicate with the CPU on the external UBB baseboard based on the PCIE protocol.

[0012] In some embodiments of the present invention, the computing module includes one or more layers of storage and computing sub-cards. When the computing module includes one layer of storage and computing sub-cards, the storage and computing sub-cards are connected to the high-speed IO physical interface of the controller card through their high-speed IO physical interface and transmit data signals; when the computing module includes multiple layers of storage and computing sub-cards, the multiple layers of storage and computing sub-cards are stacked and connected in sequence, and two adjacent layers of storage and computing sub-cards are connected through their respective high-speed IO physical interfaces, wherein a layer of storage and computing sub-cards adjacent to the controller card is connected to the high-speed IO physical interface of the controller card through its high-speed IO physical interface and transmit data signals, and a storage and computing sub-card not adjacent to the controller card is connected to the high-speed IO physical interface of the storage and computing sub-card stacked between it and the controller card through its high-speed IO physical interface, so as to achieve connection with the controller card and transmit data signals; wherein the high-speed IO physical interfaces of the storage and computing sub-cards and the controller card both adopt high-speed GPIO interfaces designed with private protocols supported by each storage and computing integrated chip.

[0013] In some embodiments of the present invention, when the computing module includes a layer of storage and computing sub-cards, a booster of a preset height is set between the storage and computing sub-cards and the controller card; when the computing module includes multiple layers of storage and computing sub-cards, a booster of a preset height is set between a layer of storage and computing sub-cards adjacent to the controller card and the controller card, and a booster of a preset height is set between any two adjacent layers of storage and computing sub-cards in the multiple layers of storage and computing sub-cards; wherein the booster rigidly connects the high-speed IO physical interfaces of the two adjacent layers of cards, the booster is used to realize the electrical connection between the two adjacent layers of cards and the data signal transmission between the two adjacent layers of cards, and after the booster rigidly connects the two adjacent layers of cards, the fixing holes of the two adjacent layers of cards are aligned.

[0014] In some embodiments of the present invention, the computing module also includes a heat dissipation system, which includes: a first heat sink arranged between the controller card and a layer of storage and computing sub-cards adjacent thereto, and a second heat sink arranged on each layer of storage and computing integrated chip; wherein the first heat sink and the second heat sink both adopt air cooling and / or liquid cooling.

[0015] In some embodiments of the present invention, the power mezzanine card includes a power conversion sub-board and a power baseboard with a hollow middle connected in sequence, and the power conversion sub-board is connected to the power baseboard through a power line passing through the hollow middle part of the power baseboard: the power baseboard is used for direct transmission of data signals between the controller card and the CPU on the external UBB baseboard; the power conversion sub-board is used to convert the power transmitted from the UBB baseboard into a lower voltage power supply, and provide the converted power to the controller card.

[0016] In some embodiments of the present invention, the controller card includes a multi-layer printed circuit board, which includes a power layer, a signal layer and a ground layer, wherein the power layer is used to convert and distribute power using a power chip; the signal layer is used to transmit high-speed differential signals using a serpentine routing method and / or a differential pair wiring method for high-speed differential signals; and the ground layer is used to provide a reference potential for each component in the controller card.

[0017] In some embodiments of the present invention, the multiple storage and computing integrated chips integrated in the computing module include an SRAM storage and computing integrated chip, a DRAM storage and computing integrated chip, and an RRAM storage and computing integrated chip or a combination thereof.

[0018] According to a second aspect of the present invention, there is provided a storage-computing integrated computing system based on an OAM form, the system comprising a plurality of storage-computing integrated chips of different types, one or more computing modules based on the first aspect of the present invention, a UBB baseboard and a CPU, wherein the plurality of storage-computing integrated chips are integrated on the computing module, the computing module and the CPU are connected via a UBB baseboard, the UBB baseboard comprises a plurality of groups of interfaces, each group of interfaces is used to connect a computing module, and the plurality of groups of interfaces are connected to a plurality of computing modules, and the plurality of groups of interfaces communicate with each other using a high-speed network protocol to realize the interconnection of the plurality of computing modules connected to the UBB baseboard; wherein the CPU transmits a data signal related to the computing task to one or more computing modules connected thereto through the UBB baseboard according to the current computing task, and transmits the data signal to the storage-computing integrated chip thereon through the computing module; the storage-computing integrated chip performs calculations according to the transmitted data signal to obtain calculation results, and transmits the calculation results to the computing module, and the calculation results are transmitted to the CPU through the UBB baseboard through the computing module.

[0019] Compared with the prior art, the advantages of the present invention are:

[0020] The computing module of the present invention uniformly adopts the standard specification of the OAM protocol for the external interface, which ensures the high compatibility of the module and simplifies the integrated connection between the various cards in the module. In addition, the present invention separates the controller card and the storage and operation sub-card into two layers and overlaps and connects them to form a three-dimensional module, and separately sets a chip connection interface on the storage and operation sub-card, so that the storage and operation sub-card can be connected to multiple storage and computing integrated chips, combined with the unified OAM protocol definition of the external interface and the layered three-dimensional structure of the computing module, it is more conducive to the system integration of storage and computing integrated chips of different architecture types. The present invention can integrate multiple chips of different architecture types, thereby providing large-scale computing support, such as providing computing power support capabilities for large neural network models, and providing a better foundation for the development of artificial intelligence technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The embodiments of the present invention are further described below with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram of the architecture of an integrated storage and computing module based on the OAM form according to an embodiment of the present invention;

[0023] Figure 2 A schematic diagram showing the principle of the conversion process between different protocols performed by a controller card according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the front layout of a controller card according to an embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of the back layout of a controller card according to an embodiment of the present invention;

[0026] Figure 5 A complete wiring diagram of a controller card according to an embodiment of the present invention;

[0027] Figure 6 A schematic diagram of a power supply design principle of a controller card according to an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of routing of high-speed differential signals according to an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of the structural design of a storage and computing sub-card according to an embodiment of the present invention;

[0030] Fig. 9 This is a schematic diagram of the connection structure between a layer-1 storage computing sub-card and a controller card according to an embodiment of the present invention;

[0031] Fig.10 This is a schematic diagram of the physical connection between a layer 1 storage computing sub-card and a controller card according to an embodiment of the present invention;

[0032] Fig.11 Schematic diagram of the connection structure of a two-layer storage and computing sub-card and a controller card according to an embodiment of the present invention;

[0033] Fig.12 A schematic diagram of a design example of a heat dissipation system in a connection structure of two-layer storage and computing sub-cards and a controller card according to an embodiment of the present invention;

[0034] Fig.13 A schematic diagram of a design example of a heat dissipation system under a connection structure of a layer of storage and computing sub-cards and a controller card according to an embodiment of the present invention;

[0035] Fig.14 A schematic diagram of a physical design of a heat dissipation system under a connection structure of a layer of storage and computing sub-cards and a controller card according to an embodiment of the present invention;

[0036] Fig.15 It is a schematic diagram of the structure of a storage-computing integrated computing system based on the OAM form according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0038] As mentioned in the background technology section, when faced with storage and computing chips with different architectures, existing storage and computing integrated computing modules are unable to achieve high system integration and scheduling of storage and computing chips with different architectures.

[0039] To solve the above problems, according to one embodiment of the present invention, the inventor proposes a storage-computing integrated computing module based on the OAM form. The external interface of the module adopts an interface designed with the OAM protocol to connect to the external UBB baseboard. The module is used to integrate multiple storage-computing integrated chips of different types and realize the communication between the external CPU and the storage-computing integrated chip through the external UBB baseboard. The module includes a power mezzanine card, a controller card and a storage-computing sub-card which are stacked in sequence. The power mezzanine card is configured to: use the power interface designed with the OAM protocol to perform power conversion to provide power and provide a path for data signal transmission between the controller card and the external CPU; the controller card is configured to: communicate and transmit data signals between the storage-computing sub-card and the external CPU; the storage-computing sub-card is configured to: provide a chip connection interface for one or more storage-computing integrated chips. Among them, the data signal is transmitted to the storage-computing integrated chip connected to the interface through the chip connection interface. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the existing module only realizes the integration of a single chip, and the existing module integrates all components such as the controller and chip interface into a circuit board, making it difficult for the module to integrate multiple chips of the same type, and the storage-computing integrated chip does not have a standard interface form. Therefore, it is extremely challenging to integrate multiple different types of chips using existing modules. The external interface of the computing module of the present invention uniformly adopts the standard specification of the OAM protocol to ensure the high compatibility of the module and simplify the integrated connection inside the module. In addition, the present invention separates the controller card and the storage-computing sub-card into two layers and overlaps them to form a three-dimensional module, and separately sets a chip connection interface on the storage-computing sub-card, so that the storage-computing sub-card can be connected to multiple storage-computing integrated chips. Combined with the external interface defined by the unified OAM protocol and the layered three-dimensional structure of the module, it is more conducive to the system integration of storage-computing integrated chips of different architecture types.

[0040] Before specifically introducing the embodiments of the present invention, some of the terms used therein are explained as follows:

[0041] OAM (OCP Accelerator Module): is an accelerator module technical specification defined by the OCP (Open Compute Project) organization, which is used to define the mezzanine shape and general specifications of computing accelerator modules.

[0042] OAM form: It is the physical form of the accelerator card that complies with the OAM protocol specifications.

[0043] UBB (Universal Baseboard) is a standardized hardware platform defined by the OCP organization to support OAM modules.

[0044] OAM protocol: is the OCP Accelerator Module protocol specification specified by the OCP organization.

[0045] OAM module: It is an Open Compute Project Accelerator Module (OCP Accelerator Module), a hardware acceleration module designed for AI, machine learning, deep learning, and high-performance computing devices. It generally follows standardized design rules and has unified specifications and protocols in terms of form factor, power input, high-speed connectors, interconnection capabilities, heat dissipation design, system management, and interconnection topology.

[0046] OAM interface: It is the interface between the UBB backplane and the OAM module designed according to the OAM protocol.

[0047] High-speed IO physical interface: physical interface technology used to achieve high-speed data transmission in electronic devices.

[0048] According to one embodiment of the present invention, the computing module includes a power mezzanine card, a controller card, and a memory-computing sub-card, which are arranged on a UBB baseboard and are stacked in sequence. The memory-computing sub-card is connected to multiple memory-computing integrated chips. The CPU and the memory-computing integrated chip communicate with the computing module through the UBB baseboard and transmit data signals. The data signals include computing tasks and data. The memory-computing integrated chip will perform calculations based on the computing tasks and data received by the device. Among them, a layer of memory-computing sub-cards or multiple layers of memory-computing sub-cards can be set in the computing module according to actual computing needs. See Figure 1 , which is a schematic diagram of the architecture of a storage-computing integrated computing module based on the OAM form. The storage-computing integrated computing module in the figure includes a power mezzanine card, a controller card and two layers of storage-computing sub-cards arranged on a UBB baseboard and stacked in sequence, and the two layers of storage-computing sub-cards are storage-computing sub-card 1 and storage-computing sub-card 2. In order to better understand the present invention, the following is a detailed description of each part of the computing module in combination with specific embodiments.

[0049] 1. Power Mezzanine Card

[0050] According to one embodiment of the present invention, the power mezzanine card is configured to: use a power interface designed with an OAM protocol to perform power conversion, provide power for the controller card, storage and computing sub-card, and storage and computing integrated chip, and provide a path for data signal transmission between the controller card and the CPU on the external UBB baseboard.

[0051] According to one embodiment of the present invention, the power mezzanine card includes a power conversion sub-board and a power baseboard with a hollow middle connected in sequence, and the power conversion sub-board is connected to the power baseboard through a power line passing through the hollow middle part of the power baseboard. Schematically, the power conversion sub-board is flexibly connected to the power baseboard through multiple power lines (for example, four power lines) passing through the hollow middle part of the power baseboard.

[0052] According to one embodiment of the present invention, the power baseboard is used for direct transmission of data signals between the controller card and the CPU on the external UBB baseboard. The power interface is arranged on the power baseboard, and the power interface includes connectors arranged on the front and back sides of the power baseboard, wherein the connector is a high-speed connector defined by the OAM protocol, which realizes the direct connection between the controller card and the UBB baseboard, and ensures the direct transmission of high-speed signals between the controller card and the UBB baseboard to transmit data signals. The material of the power baseboard adopts a material with good electrical insulation performance and mechanical strength, such as FR-4 or Rogers PCB material. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the hollow design in the middle of the power baseboard can reduce weight and provide space for the installation of the power conversion sub-board. In addition, the power mezzanine card utilizes the longitudinal space of the high-speed connectors on the front and back sides of the power baseboard through the hollow design, and connects the power line from the middle, saving the horizontal space. At the same time, the hollowing out in the middle of the power baseboard allows the middle part of the power conversion sub-board below to place higher components, thereby improving space utilization. Indicatively, the middle part of the power conversion sub-board under the power base before hollowing out has only 5mm of height space, and components with a height greater than 5mm cannot be integrated. After hollowing out, the power conversion sub-board can use a total of 10mm of height space, doubling the height space that can be used in the middle part of the actual power conversion sub-board.

[0053] According to one embodiment of the present invention, the power conversion sub-board is used to convert the power transmitted from the UBB baseboard into a lower voltage power supply, and provide the converted power supply to the controller card. Schematically, the power conversion sub-board can convert the transmitted 54V power supply into a lower voltage 12V power supply. On the power interface, the adaptability of the computing module to different input voltages is increased by the power conversion sub-board. Among them, when designing the power conversion sub-board, a DC-DC converter (Direct Current to Direct Current Converter) can be used as the power conversion sub-board. The DC-DC converter is a DC-to-DC power converter. There are high-voltage to low-voltage DC-DC converters and low-voltage to high-voltage DC-DC converters. The present invention uses a low-voltage to high-voltage DC-DC converter, which can convert a DC voltage into another lower voltage DC voltage, for example, the DC-DC converter is configured to be able to handle a 54V input and provide a stable 12V output.

[0054] According to one embodiment of the present invention, the power mezzanine card obtains power from the UBB baseboard through the high-speed connector on the back side of its power baseboard, and converts it into the voltage required by the controller card through the power conversion subboard of the power mezzanine card, and transmits the power of suitable voltage to the controller card through the high-speed connector on the front side of the power baseboard of the power mezzanine card, and simultaneously transmits the signal when the controller card and the UBB baseboard communicate. Among them, the layout design of the power mezzanine card: the DC-DC converter and the capacitors, inductors and other components related to the converter are compactly arranged on the power mezzanine power baseboard. It is also necessary to design a heat dissipation method for the power conversion subboard, such as using thermal conductive glue and / or heat sink to transfer heat to the upper board card for heat dissipation, such as transferring it to the controller card for heat dissipation. The size design of the power mezzanine card: it is necessary to ensure that the size of the power mezzanine card is compatible with the controller card and the UBB baseboard, and design a mechanical locking and snap-on mechanism that is easy to install and disassemble.

[0055] 2. Controller Card

[0056] According to an embodiment of the present invention, the controller card is configured to: perform conversion between different protocols, and perform communication and data signal transmission between the storage and computing daughter card and the CPU on the external UBB backplane.

[0057] According to one embodiment of the present invention, the controller card includes an FPGA chip, and the FPGA chip is configured to: convert the private protocol on the storage-computing subcard into the PCIE protocol, convert the PCIE protocol into the GPIO protocol, and control the data signal transmission between the CPU on the external UBB backplane and the storage-computing integrated chip. The private protocol on the storage-computing subcard is that the storage-computing integrated chip transmits its own private protocol to the storage-computing subcard, and the storage-computing subcard then transmits the private protocol to the controller card, and the controller card converts the private protocol into the PCIE protocol to transmit the data signal to the CPU. See Figure 2 , which is a schematic diagram of the controller card's conversion process between different protocols. The figure shows the process of CPU and storage computing sub-card communicating and transmitting data signals through the controller card. The following is an explanation of the process:

[0058] 1) When the controller card receives the PCIE protocol from the CPU, the controller card converts the PCIE protocol into the GPIO protocol through the FPGA chip, and the process of converting the PCIE protocol into the GPIO protocol includes: first converting the PCIE protocol into the AXI (Advanced eXtensible Interface) protocol, and then converting the AXI protocol into the GPIO protocol.

[0059] 2) When the controller card receives the private protocol from the storage and computing subcard, the controller card converts the private protocol on the storage and computing subcard into the standard PCIE protocol. The process of converting the private protocol into the standard PCIE protocol includes: converting the private protocol into the GPIO protocol through the FPGA chip, and then converting the GPIO protocol into the PCIE protocol. When converting the GPIO protocol into the PCIE protocol, the GPIO protocol is first converted into the AXI protocol, and then the AXI protocol is converted into the PCIE protocol. The controller card communicates with the CPU connected to the external UBB baseboard based on the PCIE protocol, and the controller card communicates with the storage and computing subcard based on the GPIO protocol.

[0060] 3) During the data signal transmission process, the CPU transmits the data signal to the storage and calculation sub-card through the controller card. After the storage and calculation sub-card performs calculations through the storage and calculation integrated chip connected thereto, the calculation results are transmitted to the controller card through the storage and calculation sub-card, and then transmitted to the CPU through the controller card. The controller card of the present invention realizes communication and data exchange between each card and the CPU.

[0061] According to an embodiment of the present invention, the controller card is divided into a front side and a back side, the front side includes an FPGA chip, a logic interface connected to the FPGA chip, and a high-speed GPIO interface, and the back side includes an OAM connector connected to the UBB backplane. Figure 3, which is a schematic diagram of the front layout of the controller card. The figure includes components such as an FPGA chip, multiple power chips connected to the FPGA chip, a memory stick, multiple logic interfaces, two high-speed GPIO interfaces, and a clock chip. Among them, the two high-speed GPIO interfaces are interfaces set on the high-speed IO physical interface of the controller card, and the two high-speed GPIO interfaces are high-speed GPIO interface 0 and high-speed GPIO interface 1, respectively, and correspond to high-speed IO physical interface 0 and high-speed IO physical interface 1, respectively. The logical interface is designed using the OAM protocol, and when designing the high-speed GPIO interface, it is necessary to consider performance indicators such as data signal transmission rate, delay and bandwidth, while ensuring the integrity and reliability of the data signal. The design method of the FMC physical interface is referenced when designing the high-speed IO physical interface of the present invention, and since the high-speed IO physical interface is the external data interface of the storage-computing integrated chip, the protocol used by the designed high-speed GPIO interface is used to support the private protocol of each storage-computing integrated chip, that is, the high-speed GPIO interface is designed using the private protocol supported by each storage-computing integrated chip. The protocol used by the high-speed GPIO interface is implemented at the software layer, that is, the protocol used can be redeveloped according to actual needs. For example, for an SRAM storage-computing integrated chip, the protocol used by the high-speed GPIO interface corresponding to the chip can be independently defined. The power chip is used for power conversion and power management; the memory stick is used to store data; the logic interface is used to receive the private protocol transmitted from the storage-computing subcard, and to transmit the PCIE protocol to the CPU on the external UBB baseboard or receive the PCIE protocol from the CPU on the external UBB baseboard; the clock chip is used to provide a clock output signal; both high-speed GPIO interfaces are used to transmit data signals between the controller card and the storage-computing subcard.

[0062] According to one embodiment of the present invention, see Figure 4 , which is a schematic diagram of the back layout of the controller card. The figure includes an OAM connector connected to the FPGA chip and the UBB baseboard. The OAM connector enables the computing module to realize the functions of the standard OAM module in accordance with the OAM protocol. The OAM connector is provided with a PCIE interface connected to the external UBB baseboard, wherein the PCIE interface is used to communicate with the CPU on the external UBB baseboard based on the PCIE protocol. The present invention defines the Host link as a PCIE interface, Host link: the communication link that the OAM module connects to the host through the UBB baseboard and the CPU SerDes, generally one or two x16 high-speed interfaces, and the x16 high-speed interface is the PCI Express (PCIE) x16 slot.

[0063] According to one embodiment of the present invention, the controller card is a printed circuit board (i.e., a PCB board), and the controller card includes a multi-layer printed circuit board. The multi-layer printed circuit board includes a power layer, a signal layer, and a ground layer, wherein the power layer is used to use a power chip to perform power conversion and distribute power; the signal layer is used to transmit high-speed differential signals using a serpentine routing method and / or a differential pair wiring method for high-speed differential signals, to ensure the integrity of high-speed signal transmission and reduce signal loss and interference during transmission; the ground layer is used to provide a reference potential for each component in the controller card. The ground layer can provide a stable ground reference, help reduce noise, and improve signal stability.

[0064] Indicative, based on Figure 3 and Figure 4 Taking the layout design of each component in as an example, the wiring of the controller card can be seen in Figure 5 , Figure 5 This is a complete wiring diagram of the controller card. To ensure data signal integrity: the present invention designs the signal integrity of the board from four aspects: power integrity (PI), electromagnetic interference, single network signal integrity, and crosstalk:

[0065] 1) Design with power integrity in mind: Mainly consider how to provide a stable, low-noise power supply for stable chip operation, as well as the wiring of power and ground wires. Stable and low-noise power supply is mainly provided by hierarchical design of power supply and classification design of secondary power supply according to power ladder.

[0066] According to one embodiment of the present invention, see Figure 6, which is a schematic diagram of the power supply design principle of the controller card. In the figure, the power supply is divided into two-stage design. The first-stage power supply is the total power supply input from the outside. After the power supply signal of this part is mainly processed by anti-reverse connection, anti-surge, anti-overvoltage and anti-overcurrent, the first-stage power supply is output. The secondary power supply is a power conversion design based on the voltage and power requirements of the load chip from the total power supply. Different power conversion design schemes are selected according to the different power requirements of the responsible chip. The output of the first-stage power supply is used as the input of the second-stage power supply, and the input is converted into a secondary power output through the secondary power conversion circuit. Schematically, the secondary power conversion circuit includes multiple DCDC power conversion circuits and multiple LDO power conversion circuits. The multiple DCDC power conversion circuits are respectively DCDC power conversion circuit 1, DCDC power conversion circuit 2, etc., and the multiple LDO power conversion circuits are respectively LDO power conversion circuit N-1, LDO power conversion circuit N. The secondary circuit output 1, secondary circuit output 2, ..., secondary circuit output N-1 and secondary circuit output N are obtained through DCDC power conversion circuit 1, DCDC power conversion circuit 2, ..., LDO power conversion circuit N-1 and LDO power conversion circuit N respectively. Among them, the high-power end adopts a DCDC power conversion circuit, which is designed based on a low-noise DCDC power chip plus a filter capacitor group for filtering. The low-power end selects an LDO power conversion circuit, which is designed based on an LDO power chip with a smaller ripple factor plus a filter capacitor.

[0067] 2) Design with electromagnetic interference in mind: This problem is divided into noise sources and radiation propagation paths. Power supply noise is the main noise source in high-frequency circuits, so in order to reduce power supply noise interference, low-noise power supply chips are selected, and the controller card is designed with a dedicated power supply layer and bottom layer to reduce capacitive reactance, and decoupling capacitors are added between the power supply and the ground. The optimization of the radiation propagation path mainly uses back drilling technology to reduce stub routing, to weaken the antenna effect of the controller card routing, and ultimately reduce external radiation.

[0068] 3) Consider the signal integrity of a single network when designing: consider maintaining impedance continuity and avoiding impedance mutations. Specifically, the key signal termination terminal matching resistors and the differential pair routing design of key signals. Figure 3 and Figure 4 Taking the layout design of each component in as an example, the differential signal routing of the controller card can be seen in Figure 7 , which is a schematic diagram for high-speed differential signal routing. For high-speed differential signals such as PCIE, the yellow circuit in the figure is the differential signal routing, which uses a serpentine routing method and / or a differential pair wiring method to transmit high-speed differential signals to reduce crosstalk.

[0069] 4) Design with crosstalk in mind: Since crosstalk is mainly electromagnetic, capacitive and inductive coupling interference between signal lines, the interference of high-frequency signals on low-frequency signals is particularly obvious. Therefore, when dealing with interference problems, we should first select components with the lowest possible speed, and separate high and low speed rates as much as possible in component layout. In addition, the parallel distance between high-speed signals and low-speed signals on the routing should be minimized.

[0070] 3. Storage of Operator Cards

[0071] According to one embodiment of the present invention, the storage and computing daughter card is configured to: store data signals and provide a chip connection interface for one or more storage and computing integrated chips, wherein the data signal is transmitted to the storage and computing integrated chip connected to the interface through the chip connection interface.

[0072] According to one embodiment of the present invention, the chip connection interface of the storage-computing daughter card can be customized according to different types of storage-computing integrated chips. Schematically, the storage-computing daughter card can provide a chip connection interface for an SRAM storage-computing integrated chip, a DRAM storage-computing integrated chip, and / or an RRAM storage-computing integrated chip. The external dimensions of the storage-computing daughter card comply with the unified OAM (Open AirModule) protocol. The external dimensions of the storage-computing daughter card are the same as the OAM module dimensions specified in the OAM protocol to ensure compatibility and consistency. Schematically, see Figure 8 , which is a schematic diagram of the structural design of the storage and computing sub-card. The four circles are the fixing holes used to fix with different layers. The two rectangular frames divided in the middle are used to integrate the storage and computing integrated chip or other components. The fixing holes are distributed on the upper and lower sides of the middle rectangular frame with a distance of 12mm, and the distance to the left and right edges of the middle rectangular frame is 24mm, and a rectangular area corresponding to the upper and lower sides is a divided high-speed IO physical interface. The chip connection interface of the storage and computing sub-card of the present invention is customized according to the chip, which is conducive to the system integration of storage and computing integrated chips of different architecture types.

[0073] According to one embodiment of the present invention, the computing module includes one or more layers of storage and computing sub-cards, and the number of storage and computing sub-cards can be scalably designed according to the physical space, the number of GPIO signals and the storage and computing chip requirements, that is, the number of storage and computing sub-cards can be adjusted according to the system requirements and the GPIO (general input and output) interface provided by the controller card. This scalability design allows the computing module to increase or decrease the number of storage and computing sub-cards as needed to adapt to different computing and storage requirements. Schematically, the computing module can be provided with 1 layer, 2 layers, 3 layers or 4 layers of storage and computing sub-cards, which is not limited by the present invention. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the scalability design method of the storage and computing sub-card provides a high degree of flexibility and scalability, so that the present invention can quickly adjust the computing module and upgrade the computing power according to different application requirements.

[0074] According to one embodiment of the present invention, the high-speed IO physical interface of the storage-calculation sub-card is similar to the high-speed IO physical interface of the controller card, and the high-speed IO physical interface of the storage-calculation sub-card is also provided with a high-speed GPIO interface, which is the external data interface of the storage-calculation integrated chip, and the adopted protocol is used to support the private protocol of each storage-calculation integrated chip, that is, the high-speed GPIO interface is designed with the private protocol supported by each storage-calculation integrated chip. Schematically, the high-speed GPIO interface of the storage-calculation sub-card can adopt a 400pin high-speed connector interface. Among them, the present invention customizes a high-speed GPIO interface, so that the controller card and the storage-calculation sub-card, and the multi-layer storage-calculation sub-card can be connected through the high-speed GPIO interface, and the unified OAM protocol and interface design also simplify the integration and compatibility issues between cards and computing modules.

[0075] According to one embodiment of the present invention, when the computing module includes a layer of storage and operator subcards, the storage and operator subcards are connected to the high-speed IO physical interface of the controller card through its high-speed IO physical interface and transmit data signals; when the computing module includes a layer of storage and operator subcards, a booster of a preset height is set between the storage and operator subcards and the controller card; wherein the booster is used to realize the electrical connection between the two adjacent layers of cards and the data signal transmission between the two adjacent layers of cards by rigidly connecting the high-speed IO physical interfaces of the two adjacent layers of cards, and after the booster is rigidly connected to the two adjacent layers of cards, the fixing holes of the two adjacent layers of cards are aligned. At the same time, the power supply of the controller card is supplied to the upper storage and operator subcard through the booster. The technical solution of this embodiment can at least achieve the following beneficial technical effects: the booster is set to separate the two adjacent layers of cards at a preset height, so that there is space between the two circuit boards, which can increase the placement space of components and can also achieve better heat dissipation. In addition, the rigid connection of the booster and the alignment of the fixing holes of the two layers of boards are completed at one time, which is convenient for installation and integration.

[0076] Indicatively, see Fig. 9 , which is a schematic diagram of the connection structure of a layer of storage and computing sub-cards and a controller card. The figure includes a storage and computing integrated chip 1, a storage and computing sub-card 2, a support column 3, a controller card 4, a booster 5, an FPGA chip 6 on the controller card, a memory bar 7 on the controller card, and a fixing hole 8. The high-speed IO physical interface of the storage and computing sub-card is connected to the high-speed IO physical interface of the controller card through the booster 5 and transmits data signals. The booster rigidly connects the high-speed IO physical interfaces of the two adjacent layers of cards, aligns the fixing holes of the two layers of cards, and connects and fixes the two ends of the support column through fasteners and the aligned fixing holes of the upper and lower layers of cards to achieve the connection and fixation of the storage and computing sub-card and the controller card. Schematically, the fasteners can be buckles or bolts. Fig. 9 The corresponding physical picture can be found in Fig.10, which is a physical connection diagram of a layer of storage and computing sub-cards and controller cards, including, from bottom to top, a power mezzanine card stacked on the UBB baseboard, a controller card, a storage and computing sub-card rigidly connected to the controller card through a booster, and a storage and computing integrated chip (socket) integrated on the storage and computing sub-card.

[0077] According to one embodiment of the present invention, when the computing module includes multiple layers of storage and computing sub-cards, the multiple layers of storage and computing sub-cards are stacked and connected in sequence, and two adjacent layers of storage and computing sub-cards are connected through their respective high-speed IO physical interfaces, wherein a layer of storage and computing sub-cards adjacent to the controller card is connected to the high-speed IO physical interface of the controller card through its high-speed IO physical interface and performs data signal transmission, and a storage and computing sub-card not adjacent to the controller card is connected to the high-speed IO physical interface of the storage and computing sub-card stacked between it and the controller card through its high-speed IO physical interface, so as to achieve connection with the controller card and data signal transmission. Among them, a booster of a preset height is set between a layer of storage and computing sub-cards adjacent to the controller card and the controller card, and a booster of a preset height is set between any two adjacent layers of storage and computing sub-cards in the multiple layers of storage and computing sub-cards. Similarly, the booster can also realize electrical connection between two adjacent layers of cards and data signal transmission between two adjacent layers of cards by rigidly connecting the respective high-speed IO physical interfaces of the two adjacent layers of cards.

[0078] Indicatively, see Fig.11 , which is a schematic diagram of the connection structure of two layers of storage and computing sub-cards and controller cards. The two layers of storage and computing sub-cards are respectively recorded as storage and computing sub-card 1 and storage and computing sub-card 2. The three layers from bottom to top in the figure are controller card, storage and computing sub-card 1 and storage and computing sub-card 2. The controller card and storage and computing sub-card 1 are connected to their respective high-speed IO physical interfaces through a booster and perform data signal transmission and power supply. The storage and computing sub-card 1 and storage and computing sub-card 2 are connected to their respective high-speed IO physical interfaces through a booster and perform data signal transmission and power supply.

[0079] 4. Cooling system

[0080] According to one embodiment of the present invention, the computing module also includes a heat dissipation system, which includes: a first heat sink arranged between the controller card and a layer of storage and computing sub-cards adjacent thereto, and a second heat sink arranged on each layer of storage and computing integrated chip; wherein the first heat sink and the second heat sink both adopt air cooling and / or liquid cooling. Alternatively, the first heat sink and the second heat sink both adopt heat sinks, air cooling and liquid cooling or a combination thereof, and the present invention does not limit the heat dissipation method. Schematically, such as adopting a combination of air cooling and liquid cooling, adopting air cooling alone, or adopting a combination of heat sinks and air cooling. The technical solution of this embodiment can at least achieve the following beneficial technical effects: Since integrating multiple chips for calculation may require higher power, the power supply and thermal management solutions should be considered during the design to ensure the stable operation of the module. Therefore, the present invention combines the height increaser arranged between the two layers of cards so that there is space between the two circuit boards for heat dissipation, which helps the integrated circuit board to better dissipate heat and provide stable power supply.

[0081] According to one embodiment of the present invention, when designing a heat dissipation system, a thermal simulation analysis can be performed first to evaluate the thermal effect during the power conversion process. Heat dissipation solution: Based on the thermal simulation results, a heat dissipation solution is designed, such as a heat sink, air duct or liquid cooling system. That is, the thermal performance of the computing module is evaluated to ensure that the heat dissipation design meets the requirements. For example, see Fig.12 , which is a schematic diagram of a heat dissipation system design example under a connection structure of two layers of storage and computing sub-cards and controller cards. Fig.11 , the cooling system simulates the design under the structure of controller card, storage and computing sub-card 1 and storage and computing sub-card 2 from bottom to top. The thermal performance of the computing module is evaluated by setting the heat-generating devices on each layer of the card. In the figure, the storage and computing sub-card 1 is provided with a high-speed IO physical interface 1, and the storage and computing sub-card 2 is provided with a high-speed IO physical interface 2. In addition, the storage and computing sub-card 2 is also provided with a high device H30 connected to the high-speed IO physical interface 2, which is used to simulate the height restriction of the components that can be installed on the storage and computing sub-card 2, that is, the height of the components that can be installed on the storage and computing sub-card 2 does not exceed the height of the high device H30 connected to the high-speed IO physical interface 2. The thermal simulation structure constructed under the interface setting condition includes:

[0082] A 20W heating device H5 connected to the back of the high-speed IO physical interface 1, a 100W heating device H5 connected to the front of the high-speed IO physical interface 1, a 20W heating device H5 connected to the back of the high-speed IO physical interface 2, and a 100W heating device H5 connected to the front of the high-speed IO physical interface 2;

[0083] The cooling system under the built-in thermal simulation structure includes:

[0084] The air cooling 1 provided between the controller card and the storage computing sub-card 1 is used to dissipate heat from the 20W heat generating device H5 connected to the back of the controller card and the high-speed IO physical interface 1;

[0085] Water cooling 1 and air cooling 2 are provided between storage and computing sub-card 1 and storage and computing sub-card 2, and are used to dissipate heat for the 100W heating device H5 connected to the front of the high-speed IO physical interface 1 and the 20W heating device H5 connected to the back of the high-speed IO physical interface 2, respectively;

[0086] The water cooling 2 provided on the storage computing daughter card 2 is used to dissipate the heat of the 100W heat generating device H5 connected to the back side of the high-speed IO physical interface 2.

[0087] According to one embodiment of the present invention, see Fig.13 , which is a schematic diagram of a heat dissipation system design example under a connection structure of a storage computing sub-card and a controller card. Fig. 9 , the cooling system simulates the design under the structure of controller card and storage and computing sub-card from bottom to top. The figure shows water cooling, storage and computing integrated chip (socket), storage and computing sub-card, support column, FPGA chip of controller card and controller card from top to bottom. Among them, water cooling or air cooling is set on the orange part of the FPGA chip of the controller card to dissipate the heat of the chip. Fig.13 The corresponding physical picture can be found in Fig.14 It is a schematic diagram of the physical design of the heat dissipation system under the connection structure of a storage and computing daughter card and a controller card. From bottom to top, it includes a power mezzanine card stacked on the UBB baseboard, a controller card, a storage and computing daughter card connected to the controller card, a storage and computing integrated chip (socket) integrated on the storage and computing daughter card, and a heat sink.

[0088] According to one embodiment of the present invention, the multiple storage-computing integrated chips integrated in the computing module of the above embodiment include an SRAM storage-computing integrated chip, a DRAM storage-computing integrated chip and an RRAM storage-computing integrated chip or a combination thereof. For example, an SRAM storage-computing integrated chip and a DRAM storage-computing integrated chip are integrated, or an SRAM storage-computing integrated chip, a DRAM storage-computing integrated chip and an RRAM storage-computing integrated chip are integrated, or two SRAM storage-computing integrated chips and one RRAM storage-computing integrated chip are integrated, etc., and various types of chips can be selected for integration according to actual needs.

[0089] According to one embodiment of the present invention, there is provided a storage-computing integrated computing system based on an OAM form, the system comprising a plurality of storage-computing integrated chips of different types, one or more computing modules based on the above-mentioned embodiments, a UBB baseboard and a CPU, wherein the plurality of storage-computing integrated chips are integrated on the computing module, the computing module and the CPU are connected via a UBB baseboard, the UBB baseboard comprises a plurality of groups of interfaces, each group of interfaces is used to connect a computing module, and the plurality of groups of interfaces are connected to a plurality of computing modules, and the plurality of groups of interfaces communicate with each other using a high-speed network protocol to realize the interconnection of the plurality of computing modules connected to the UBB baseboard; wherein the CPU transmits a data signal related to the computing task to one or more computing modules connected thereto through the UBB baseboard according to the current computing task, and transmits the data signal to the storage-computing integrated chip thereon through the computing module; the storage-computing integrated chip performs calculations according to the transmitted data signal to obtain calculation results, and transmits the calculation results to the computing module, and the calculation results are transmitted to the CPU through the UBB baseboard through the computing module. The technical solution of this embodiment can at least achieve the following beneficial technical effects: by interconnecting multiple computing modules and integrating several storage-computing integrated chips of different types, a storage-computing integrated computing system with large-scale interconnection capabilities is provided, thereby providing computing power support capabilities for large-scale neural network models faced in artificial intelligence fields such as computer vision.

[0090] According to one embodiment of the present invention, the interconnection between the storage and computing modules adopts high-speed network protocols including but not limited to Ethernet, InfiniBand or other network protocols specified by OAM protocols. During the design, the chip interface, interconnection topology, interconnection protocol, memory access mode and algorithm adaptation of the multi-storage and computing integrated chip system are designed to support the storage and computing integrated computing system with 100TOPS computing power integration, and provide computing power support for large neural network models in the field of computer vision. For illustration, see Fig.15 , which is a schematic diagram of the structure of a storage-computing integrated computing system based on the OAM form. The system includes four interconnected computing modules, a UBB baseboard and a CPU. Each computing module integrates multiple storage-computing integrated chips. Each computing module is provided with a heat sink for dissipating the heat of the storage-computing integrated chip on it.

[0091] It should be noted that although the above describes the various steps in a specific order, it does not mean that the various steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently or even in a different order as long as the required functions can be achieved.

[0092] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0093] A computer-readable storage medium may be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media may include, for example, but are not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a protruding structure in a groove on which instructions are stored, and any suitable combination thereof.

[0094] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A storage-computing integrated computing module based on OAM form, used to integrate multiple storage-computing integrated chips of different types and realize communication between CPU and storage-computing integrated chips, the external interface of the computing module adopts an interface designed by OAM protocol to connect with an external UBB backplane, the computing module includes: The power mezzanine card, the controller card and the storage and computing sub-card are arranged on the UBB base plate and are stacked in sequence, wherein: The power mezzanine card is configured to: use the power interface designed with the OAM protocol to perform power conversion, supply power to the controller card, storage and computing sub-card, and storage and computing integrated chip, and provide a path for data signal transmission between the controller card and the CPU on the external UBB backplane; The controller card is configured to: perform conversion between different protocols, and perform communication and data signal transmission between the storage and computing sub-card and the CPU on the external UBB backplane; The storage-computing daughter card is configured to: store data signals and provide a chip connection interface for one or more storage-computing integrated chips, wherein the data signal is transmitted to the storage-computing integrated chip connected to the interface through the chip connection interface.

2. The computing module according to claim 1, characterized in that: The controller card includes an FPGA chip, and the FPGA chip is configured as follows: Convert the private protocol on the storage and computing daughter card into the PCIE protocol, convert the PCIE protocol into the GPIO protocol, and control the data signal transmission between the CPU on the external UBB baseboard and the storage and computing integrated chip.

3. The computing module according to claim 2, characterized in that: The controller card includes multiple interfaces connected to the FPGA chip, including a logic interface, a high-speed GPIO interface, and a PCIE interface connected to an external UBB backplane. The logic interface adopts the OAM protocol design, and the high-speed GPIO interface adopts the private protocol design supported by each storage and computing integrated chip. Logical interface, used to receive the private protocol transmitted by the storage and computing subcard, and to transmit the PCIE protocol to the CPU on the external UBB backplane or receive the PCIE protocol from the CPU on the external UBB backplane; High-speed GPIO interface, used for data signal transmission between the controller card and the storage and computing sub-card; The PCIE interface is used to communicate with the CPU on the external UBB backplane based on the PCIE protocol.

4. The computing module according to claim 1, characterized in that: The computing module includes one or more layers of storage and computing sub-cards. When the computing module includes one layer of storage and computing sub-cards, the storage and computing sub-cards are connected to the high-speed IO physical interface of the controller card through their high-speed IO physical interface and perform data signal transmission; When the computing module includes multiple layers of storage and computing sub-cards, the multiple layers of storage and computing sub-cards are stacked and connected in sequence, and two adjacent layers of storage and computing sub-cards are connected through their respective high-speed IO physical interfaces, wherein a layer of storage and computing sub-cards adjacent to the controller card is connected to the high-speed IO physical interface of the controller card through its high-speed IO physical interface and performs data signal transmission, and a storage and computing sub-card not adjacent to the controller card is connected to the high-speed IO physical interface of the storage and computing sub-card stacked between it and the controller card through its high-speed IO physical interface, so as to realize its connection with the controller card and perform data signal transmission; Among them, the high-speed IO physical interfaces of the storage and computing sub-cards and controller cards all use high-speed GPIO interfaces designed with private protocols supported by each storage and computing integrated chip.

5. The computing module according to claim 4, characterized in that: When the computing module includes a layer of storage and computing sub-cards, a height enhancer of a preset height is provided between the storage and computing sub-cards and the controller card; When the computing module includes multiple layers of storage and computing sub-cards, a booster of a preset height is provided between a layer of storage and computing sub-cards adjacent to the controller card and the controller card, and a booster of a preset height is provided between any two adjacent layers of storage and computing sub-cards in the multiple layers of storage and computing sub-cards; The booster rigidly connects the high-speed IO physical interfaces of the two adjacent layers of cards. The booster is used to realize the electrical connection between the two adjacent layers of cards and the data signal transmission between the two adjacent layers of cards. After the booster rigidly connects the two adjacent layers of cards, the fixing holes of the two layers of cards are aligned.

6. The computing module according to claim 5, characterized in that: The computing module also includes a heat dissipation system, which includes: A first heat sink is provided between the controller card and a layer of storage and computing daughter cards adjacent thereto, and a second heat sink is provided on each layer of storage and computing integrated chips; Wherein, the first radiator and the second radiator both adopt air cooling and / or liquid cooling.

7. The computing module according to claim 1, characterized in that: The power mezzanine card includes a power conversion sub-board and a power baseboard with a hollow middle connected in sequence, and the power conversion sub-board is connected to the power baseboard through a power line passing through the hollow middle part of the power baseboard: The power baseboard is used for direct transmission of data signals between the controller card and the CPU on the external UBB baseboard; The power conversion daughter board is used to convert the power transmitted from the UBB baseboard into a lower voltage power supply, and provide the converted power supply to the controller card.

8. The computing module according to claim 1, characterized in that: The controller card includes a multi-layer printed circuit board, which includes a power layer, a signal layer and a ground layer, wherein: The power layer is used to convert and distribute power using power chips; The signal layer is used to transmit high-speed differential signals by using a serpentine routing method and / or a differential pair routing method; Ground plane, used to provide reference potential for various components in the controller card.

9. The computing module according to any one of claims 1 to 8, characterized in that: The multiple storage and computing integrated chips integrated in the computing module include SRAM storage and computing integrated chip, DRAM storage and computing integrated chip and RRAM storage and computing integrated chip or a combination thereof.

10. A storage and computing integrated computing system based on OAM morphology, characterized in that: The system includes a plurality of storage-computing integrated chips of different types, one or more computing modules according to any one of claims 1 to 9, a UBB baseboard and a CPU, wherein: Multiple storage and computing chips are integrated on the computing module. The computing module and the CPU are connected through a UBB baseboard. The UBB baseboard includes multiple groups of interfaces, each group of interfaces is used to connect a computing module, and multiple groups of interfaces are connected to multiple computing modules. High-speed network protocols are used between the multiple groups of interfaces to realize the interconnection of multiple computing modules connected to the UBB baseboard. Among them, the CPU transmits the data signal related to the computing task through the UBB baseboard to one or more computing modules connected to it according to the current computing task, and transmits the data signal to the storage and computing integrated chip thereon through the computing module; The storage and computing integrated chip performs calculations based on the transmitted data signals to obtain calculation results, and transmits the calculation results to the computing module, which then transmits the calculation results to the CPU through the UBB baseboard.

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