Semiconductor device for providing improved memory bandwidth and method for forming the same

Abstract

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers in which interposer metal interconnect structures are formed. A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers in which router metal interconnect structures are formed and a router substrate in which router substrate via structures are formed. A backside of the router substrate may be thinned to expose end surfaces of the router substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. The bonding pads of the memory dies are electrically connected to the router substrate via structures.

Description

RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 623,426, entitled "High Performance Memory - ASIC Array Integration," filed January 22, 2024, which is incorporated by reference into this application. BACKGROUND

[0002] Traditional integration schemes for application-specific integrated circuit (ASIC) and memory dies face challenges in delivering adequate memory bandwidth with ever-increasing power levels of both ASIC and memory dies. System performance and efficiency can be significantly limited by inadequate memory bandwidth and relatively slow data transfer rates. Consequently, memory bandwidth limitations hinder advances in high-performance computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be understood that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for the purpose of clarity of illustration. Fig. 1 is a vertical cross-sectional view of an exemplary structure including an interposer structure after forming interposer metal interconnect structures and front interposer bonding pads formed within interposer dielectric material layers, according to an embodiment of the present disclosure. Fig. 2 is a vertical cross-sectional view of the exemplary structure after bonding processor dies to the interposer structure according to an embodiment of the present disclosure. Fig. 3 is a vertical cross-sectional view of the exemplary structure after forming a dielectric matrix according to an embodiment of the present disclosure. Fig. 4 is a vertical cross-sectional view of a router die according to an embodiment of the present disclosure. Fig. 5 is a vertical cross-sectional view of the exemplary structure after bonding the router die to an array of processor dies according to an embodiment of the present disclosure. Fig. 6 is a vertical cross-sectional view of the exemplary structure after thinning a backside of the router die according to an embodiment of the present disclosure. Fig. 7 is a vertical cross-sectional view of the exemplary structure after forming a backside router dielectric layer and forming backside router bonding pads according to an embodiment of the present disclosure. Fig. 8 is a vertical cross-sectional view of the exemplary structure after attaching memory dies to the router die according to an embodiment of the present disclosure. Fig. 9 is a vertical cross-sectional view of the exemplary structure after removing a carrier substrate from the interposer structure according to an embodiment of the present disclosure. Fig. 10 is a vertical cross-sectional view of the exemplary structure after forming backside interposer bonding pads according to an embodiment of the present disclosure. Fig. Figure 11 is a top-down view of a semiconductor device obtained by sawing the exemplary structure of Fig. 10 is formed. Fig. 12 is a circuit diagram illustrating the operation of the semiconductor device shown in Fig. 10 and Fig. 11 is illustrated. Fig. 13 schematically illustrates a change in the operation of a computing device incorporating the semiconductor device of the present disclosure with respect to previously known computing devices. Fig. 14 is a flowchart illustrating the general processing steps for forming a semiconductor device of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Elements bearing the same reference numerals are assumed to be the same or similar elements and to have the same material composition and to provide the same function unless expressly stated to the contrary.

[0005] Furthermore, spatially related terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for convenience in describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly. Elements with the same reference numerals refer to the same element and are assumed to have the same material composition and thickness range unless expressly stated otherwise.As used herein, an element or system "configured for" or "configured to provide" a function or operation refers to an element or system provided with hardware and, if applicable, software to provide such function or operation, as described in the present disclosure and as known in the art, if any details of such hardware or software are not expressly described herein.

[0006] The present disclosure is generally directed to semiconductor devices, and more particularly, to a semiconductor assembly comprising application-specific integrated circuit (ASIC) dies and memory dies (such as high-bandwidth memory (HBM) dies) configured to improve memory bandwidth. The integration of ASIC dies and memory dies is facilitated by a network-on-chip (NoC) architecture that uses chip-on-wafer-on-substrate (CoWoS) technology and through-silicon vias (TSVs) for improved connectivity and performance. The integration scheme of the present disclosure uses a modular design framework that increases scalability and adaptability, optimizes data transmission and processing with its direct high-speed data paths, and provides efficient thermal management.

[0007] The network-on-chip architecture used in various embodiments disclosed herein integrates ASIC dies with memory dies through high-speed, low-latency data paths provided within a network-on-chip router. The physical distance between the ASIC dies and the memory dies can be reduced by using a network-on-chip router, which provides high operating efficiency and robust thermal tolerance. The network-on-chip router uses silicon via (TSV) structures to provide electrical connections to memory dies. The use of TSV structures can increase memory capacity and bandwidth and allows the integration of a large number of memory dies. The data flow through the network-on-chip router can be dynamically managed to optimize resource utilization.The network-on-chip architecture can be implemented in a semiconductor device formed by chip-on-wafer-on-substrate (CoWoS) technology and hybrid bonding, thereby reducing memory latency and increasing memory efficiency.

[0008] The memory capacity and bandwidth of a computing system can be increased using the network-on-chip architecture of the present disclosure. Furthermore, embodiments of the present disclosure provide performance enhancements, improved efficiency and reduced power consumption for environmental sustainability, exceptional thermal management for reliability, and design scalability for future advancements. The present disclosure provides a scalable, high-performance solution for improving the performance of high-end computing systems.

[0009] With reference to Fig. 1 illustrates an exemplary structure including an interposer structure 100 formed on a support substrate 108. The support substrate 108 may be a commercially available silicon wafer. An interface material layer 109 may be formed on a top surface of the support substrate 108. The interface material layer 109 may comprise a thermally decomposable adhesive material or any other material that can be used as a stopper material during subsequent removal of the support substrate 108.

[0010] The interposer structure 100 may be formed by depositing interposer dielectric material layers 160 over the support substrate 108. Interposer metal interconnect structures 180 and front interposer bonding pads 188 may be formed within the interposer dielectric material layers 160. The interposer dielectric material layers 160 may include interlayer dielectric (ILD) materials as known in the art, which may include, for example, undoped silicate glass, a doped silicate glass, silicon nitride, silicon carbide nitride, dielectric metal oxides, etc. In one embodiment, the interposer dielectric material layers 160 may comprise and / or consist of substantially inorganic dielectric materials. The interposer metal interconnect structures 180 may include metal via structures and metal line structures.In some embodiments, sidewalls of the metal via structures may be tapered such that a lateral dimension (such as a diameter) of each metal via structure increases with vertical distance from a top surface of the support substrate 108. The total number of levels of metal line structures may range from 1 to 12, although a larger number of levels may be used. The interposer metal interconnect structures 180 may comprise copper, aluminum, tungsten, titanium, or other metals that provide high electrical conductivity. The interposer metal interconnect structures 180 may be configured to provide electrical connections to and from a plurality of processor dies to be subsequently bonded thereto.

[0011] The front interposer bonding pads 188 may be formed on the top level of the interposer dielectric material layers 160. The topmost dielectric material layer selected from the interposer dielectric material layers 160 is also referred to as the interposer bonding dielectric layer. The interposer bonding dielectric layer may comprise a dielectric material that can be used for dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. In one embodiment, the interposer bonding dielectric layer may comprise undoped silicate glass or a doped silicate glass.

[0012] The front interposer bonding pads 188 may be configured for metal-to-metal bonding, such as copper-to-copper bonding. As used herein, "metal-to-metal" bonding refers to bonding in which two metal surfaces are bonded directly to each other without any intervening material portion, such as a solder portion. Thus, atomic interdiffusion of metal atoms occurs across a bonding interface, and grain growth and recrystallization of metal materials occur during metal-to-metal bonding. In one embodiment, the front interposer bonding pads 188 may include copper bonding pads having copper surfaces as bonding surfaces.

[0013] The front interposer bonding pads 188 may be arranged as multiple arrays, each having a respective spacing along repeat directions. In general, the structure of each array of the front interposer bonding pads 188 may be a mirror image structure of the structure of the front processor bonding pads of processor dies to be subsequently bonded to the interposer structure 100. According to one aspect of the present disclosure, the front interposer bonding pads 188 may be configured in a structure for bonding to multiple processor dies, such as a two-dimensional array of processor dies.

[0014] The Fig. 1 corresponds to the area of a single interposer structure 100. In general, a two-dimensional array of interposer structures 100 may be formed on a support substrate 108. It should be understood that the illustrated portion of the exemplary structure may be repeated in a two-dimensional array such that a plurality of interposer structures 100 are provided over the support substrate 108. The area of each interposer structure 100 may correspond to the area of a single reticle (which may be approximately 30 mm x 30 mm) or may span areas of multiple reticles. The area of each interposer structure 100 may be selected based on the total number of memory dies to be subsequently attached to an array including the interposer structure 100.

[0015] With reference to Fig. 2, a plurality of processor dies 300 may be attached to the interposer structure 100. In one embodiment, the plurality of processor dies 300 may be attached to the interposer structure 100 via metal-to-metal bonding and dielectric-to-dielectric bonding. Alternatively, at least one of the plurality of processor dies 300 may be attached to the interposer structure 100 via microbump bonding (also known as C2 bonding or die interconnect bonding), C4 bonding (controlled collapse die interconnect bonding), or alternative die attach techniques. Each processor die 300 includes a processor die substrate 308, which may be a semiconductor substrate, such as a single crystalline silicon substrate. Each processor die 300 includes substrate via structures 304 that extend vertically through the processor die substrate 308.The through-substrate via (TSV) structures 304 are electrically isolated from the processor die substrate 308 by isolation spacers 302, also referred to as processor die isolation spacers. The isolation spacers 302 may have a tubular configuration.

[0016] Each processor die 300 includes at least one processing unit 320. A processing unit 320 may be any of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a neural processing unit (NPU), an artificial intelligence accelerator (AI accelerator), etc. Furthermore, a processor die 300 may include multiple processing units, as in the case of a system-on-a-chip (SoIC) die. For example, a SoIC die may include a CPU, a GPU, a DSP, and / or an NPU. Additionally, a processor die 300 may optionally include a cache memory, referred to as an L1 cache (i.e., a first-level cache), which may include static random access memory (SRAM). Such cache memory present within a processor die 300 is generally referred to as an embedded cache memory.Additional cache memory, referred to as L2 cache memory (i.e., a second-level cache memory), may be included in one or more of the processor dies 300. In general, the L2 cache memory may have a larger storage capacity and a slower access speed relative to the L1 cache memory.

[0017] Each processor die 300 includes a group of die dielectric material layers 360 in which a group of die metal interconnect structures 380 is formed, and a group of front processor bonding pads 388. The die dielectric material layers 360 may include interlayer dielectric (ILD) materials, as known in the art. In one embodiment, the die dielectric material layers 360 may comprise and / or consist essentially of inorganic dielectric materials. The die metal interconnect structures 380 may include metal via structures and metal line structures. The total number of levels of metal line structures may range from 2 to 16, although a greater number of levels may be used.The die metal interconnect structures 380 may comprise copper, aluminum, tungsten, titanium, or other metals that provide high electrical conductivity.

[0018] The front processor bonding pads 388 may be formed on the top level of the die dielectric material layers 360. The topmost dielectric material layer selected from the die dielectric material layers 360 is also referred to as a processor bonding dielectric layer and may comprise a dielectric material that can be used for dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. In one embodiment, the processor bonding dielectric layer may comprise undoped silicate glass or a doped silicate glass. The front processor bonding pads 388 may be configured for metal-to-metal bonding, such as copper-to-copper bonding. In one embodiment, the front processor bonding pads 388 may comprise copper bonding pads that have copper pads as bonding surfaces.

[0019] Each processor die 300 may include a backside die dielectric layer 312 located on the backside surface of the processor die substrate 308. The backside die dielectric layer 312 may include a dielectric material that can be used for dielectric-to-dielectric bonding. For example, the backside die dielectric layer 312 may include undoped silicate glass or a doped silicate glass. The backside processor bonding pads 318 may be formed in the backside die dielectric layer 312 on backside end surfaces of the substrate via structure 304. The backside processor bonding pads 318 may be configured for metal-to-metal bonding, such as copper-to-copper bonding. In one embodiment, the backside processor bonding pads 318 may include copper bonding pads having copper surfaces as bonding surfaces.The backside processor bonding pads 318 are located on the die substrate via structures 304.

[0020] The processor dies 300 may be attached to the interposer structure 100 by bonding the backside processor bonding pads 318 to the front interposer bonding pads 188 of the interposer structure 100. Thus, after attaching the plurality of processor dies 300 to the interposer structure 100, the substrate via structures 304 are electrically connected to the front interposer bonding pads 188. The backside processor bonding pads 318 may be bonded to the front interposer bonding pads 188 via metal-to-metal bonding, such as copper-to-copper bonding. In one embodiment, the backside die dielectric layers 312 of the processor dies 300 may be bonded to surface segments of the interposer dielectric material layers 160 via dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding.

[0021] As previously explained, the interposer metal interconnect structures 180 may be configured to provide electrical connections to and from a plurality of processor dies 300. Direct data transfer may be performed between processing units 320 of different processor dies 300 using a subset of the interposer metal interconnect structures 180, which function as data buses. In general, in embodiments in which M processor dies 300 are bonded to an interposer structure 100, the interposer metal interconnect structures 180 may include up to M(M-1) / 2 groups of data buses configured to function as signal transmission paths to and from the M processor dies 300. Thus, the processing units 320 within the M processor dies 300 can exchange data to and from each other using the data transfer buses within the interposer structure 100.

[0022] With reference to Fig. 3, a dielectric matrix 390 may be formed by depositing a dielectric material within gaps between adjacent pairs of processor dies 300 and removing portions of the dielectric material from above the horizontal plane, including the top surfaces of the plurality of processor dies 300. The remaining portions of the dielectric material filling the gaps comprise the dielectric matrix 390.

[0023] In one embodiment, the dielectric material of the dielectric matrix may comprise a molding compound (MC). The MC may comprise an epoxy-containing compound that can be cured (e.g., hardened) to provide a dielectric material portion with sufficient stiffness and mechanical strength. The MC may include epoxy resin, curing agents, silica (as a filler), and other additives. The MC may be provided in a liquid form or in a solid form depending on its viscosity and flowability. Liquid MC typically provides better handling, good flow, fewer gaps, better filling, and fewer flow marks. Solid MC typically provides lower cure shrinkage, better spacing, and lower die deviation. A higher filler content (such as 85 wt.-%) within an MC can shorten the time in the mold, reduce mold shrinkage, and minimize mold warpage. A uniform filler size distribution within the MC can reduce flow marks and improve flowability. Excess portions of the molding compound can be removed from above the horizontal plane, including the top surfaces of the processor dies 300.

[0024] The MC may be cured at a curing temperature to form a dielectric matrix 390, which is a matrix made from the MC. The dielectric matrix 390 may extend laterally across the entire surface of the carrier substrate 108. Thus, a rebuilt wafer is formed, including the carrier substrate 108, a two-dimensional array of interposer structures 100, groups of processor dies 300 bonded to a respective one of the interposer structures 100, and the dielectric matrix 390. Within each surface of an interposer structure 100, in a top view, a plurality of processor dies 300 bonded to the interposer structure 100 may be formed within a dielectric matrix 390.

[0025] With reference to Fig. 4, a wafer may be provided having an array of router dies 600. Each router die 600 may have the same area as an interposer structure 100 described with reference to Fig. 1 - 3, in a plan view, such as a top-down view. The Fig. The area illustrated in Figure 4 corresponds to the area of a single router die 600. In general, a two-dimensional array of router dies 600 may be formed on a router substrate 608, which may be a semiconductor substrate, such as a single crystalline silicon substrate. It should be understood that instances of a router die 600 may be repeated in a two-dimensional array such that a plurality of router dies 600 comprise a respective portion of the router substrate 608. The area of each router die 600 may be the same as the area of an interposer structure 100 and may be selected based on the total number of memory dies to be subsequently attached to a router die 600.

[0026] Via cavities may be formed in an upper portion of the router substrate 608. For example, a photoresist layer may be applied over the upper surface of the router substrate 608 and lithographically patterned to form an array of discrete openings. An anisotropic etching process may be performed to transfer the pattern of the discrete openings in the photoresist layer to the upper portion of the router substrate 608. The gaps formed in the upper portion of the router substrate 608 comprise the via cavities. The depth of the via cavities may range from 5 micrometers to 30 micrometers. The lateral dimension (such as a diameter) of each via cavity may range from 1 micrometer to 10 micrometers, although smaller and larger lateral dimensions may also be used.The photoresist layer can then be removed, for example by ashing.

[0027] An insulating material may be conformally deposited in peripheral regions of the via cavities in the router substrate 608. The insulating material may comprise a silicon oxide material, such as an undoped silicate glass or a doped silicate glass. At least one conductive material may be deposited in remaining volumes of the via cavities. The at least one conductive material may comprise, for example, a combination of a metallic barrier material (such as TiN, TaN, WN, and / or MoN) and a metallic fill material such as tungsten or copper. Excess portions of the insulating material and the at least one conductive material may be removed from above the horizontal plane, including the top surface of the router substrate 608, by a planarization process, which may use a chemical mechanical polishing (CMP) process and / or a recess etching process.Each remaining portion of the insulating material includes an insulating spacer, referred to as a router insulating spacer 602. Each remaining portion of the at least one conductive material includes a router substrate via structure 604, also referred to as a router substrate via structure. The router substrate via structures 604 do not extend through the entire thickness of the router substrate 608 in this processing step. However, after the subsequent thinning of the backside of the router substrate 608, the router substrate via structures 604 may extend through the thinned router substrate 608.

[0028] Router dielectric material layers 660 may then be deposited over the router substrate 608. Router metal interconnect structures 680 and front router bonding pads 688 may be formed within the router dielectric material layers 660. The router dielectric material layers 660 may include interlayer dielectric (ILD) materials as known in the art, which may include, for example, undoped silicate glass, a doped silicate glass, silicon nitride, silicon carbide nitride, dielectric metal oxides, etc. In one embodiment, the router dielectric material layers 660 may include and / or consist essentially of inorganic dielectric materials. The router metal interconnect structures 680 may include metal via structures and metal line structures.In some embodiments, the sidewalls of the metal via structures may be tapered so that a lateral dimension (such as a diameter) of each metal via structure increases with vertical distance from a top surface of the router substrate 608. The total number of levels of metal line structures may range from 2 to 16, although a larger number of levels may be used. The router metal interconnect structures 680 may comprise copper, aluminum, tungsten, titanium, or other metals that provide high electrical conductivity.

[0029] The front router bonding pads 688 may be formed on the top level of the router dielectric material layers 660. The topmost dielectric material layer selected from the router dielectric material layers 660 is also referred to as a router bonding dielectric layer and may comprise a dielectric material that can be used for dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. In one embodiment, the router bonding dielectric layer may comprise undoped silicate glass or a doped silicate glass. The front router bonding pads 688 may be configured for metal-to-metal bonding, such as copper-to-copper bonding. In one embodiment, the front router bonding pads 688 may comprise copper bonding pads having copper pads as bonding surfaces.

[0030] The front router bonding pads 688 may be arranged as a plurality of arrays, each having a respective spacing along repeat directions. In general, the structure of each array of the front router bonding pads 688 may be a mirror image structure of the structure of the front processor bonding pads 388 of the processor dies 300 described with reference to Fig. 2. According to one aspect of the present disclosure, the structure of the front router bonding pads 688 may be a mirror image structure of the structure of the front processor bonding pads 388 of the processor dies 300 located within the array of an interposer structure 100 and a plurality of processor dies 300, as in the exemplary structure of Fig. 3 provided.

[0031] In general, the router metal interconnect structures 680 provide electrically conductive paths between each array of router substrate via structures 604 and each array of front router bonding pads 688. In particular, each array of router substrate via structures 604 configured to be electrically connected to a respective memory die in a subsequent processing step includes a plurality of groups of router substrate via structures 604. Each array of front router bonding pads 688 may include a plurality of groups of front router bonding pads 688. Each group of front router bonding pads 688 may be electrically connected to a respective group of router substrate via structures 604.

[0032] In one embodiment, the front router bonding pads 688 within a router die 600 may comprise M arrays of front router bonding pads 688. The integer M may be the total number of processor dies 300 to be bonded to the router die 600. The integer M may be in a range from 2 to 2 6 The router substrate via structures 604 within a router die 600 may comprise N arrays of router substrate via structures 604. The integer N may be the total number of memory dies to be subsequently bonded to the router die 600. The total number N may be in a range from 2 to 2 6 lay.

[0033] In one embodiment, each array of front router bonding pads 688 selected from the M arrays of front router bonding pads 688 may include N groups of front router bonding pads 688. In one embodiment, each array of router substrate via structures 604 selected from the N arrays of router substrate via structures 604 may include M groups of router substrate via structures 604. In one embodiment, a total of M x N groups of front router bonding pads 688 may be provided, and a total of M x N groups of router substrate via structures 604 may be provided.In one embodiment, each group of front router bonding pads 688 selected from the M x N groups of front router bonding pads 688 may be electrically connected to a respective group of router substrate via structures 604 selected from the M x N groups of router substrate via structures 604.

[0034] In one embodiment, for each selected combination of an array of front router bonding pads 688 and an array of router substrate via structures 604, electrical connections, which may include a respective subset of the router metal interconnect structures 680, are provided between a group of front router bonding pads 688 within the selected array of front router bonding pads 688 and a group of router substrate via structures 604 within the selected array of router substrate via structures 604.

[0035] With reference to Fig. 5, the wafer including a two-dimensional array of router dies 600 may be bonded by wafer-to-wafer bonding to the wafer including a bonded arrangement of a two-dimensional array of interposer structures 100 and a two-dimensional array of groups of processor dies 300. In particular, the front router bonding pads 688 of each router die 600 are bonded to first processor bonding pads (such as the front processor bonding pads 388) within a plurality of processor dies 300 bonded to a respective interposer structure 100. The front router bonding pads 688 are formed within the router dielectric material layers 660 within each router die 600. The front processor bonding pads 388 of the plurality of processor dies 300 are formed within the die dielectric material layers 360 of the plurality of processor dies 300.

[0036] Each router die 600 may be attached to a respective interposer structure 100 via a respective plurality of processor dies 300 located entirely within the area of the router die 600. In one embodiment, each router die 600 may have the same area as a respective underlying interposer structure 100. Each router die 600 includes router dielectric material layers 660 in which router metal interconnect structures 680 are formed, and a router substrate 608 in which router substrate via structures 604 are formed. Each of the plurality of processor dies 300 includes a respective group of die dielectric material layers 360 in which a respective group of die metal interconnect structures 380 and a respective group of front processor bonding pads 388 are formed. Front router bonding pads 688 are formed in the router dielectric material layers 660.

[0037] Within each face of a router die 600, the front router bonding pads 688 are electrically connected to a respective one of the front processor bonding pads 388 after attaching the router die 600 to the plurality of processor dies 300. In one embodiment, each router die 600 may be attached to the plurality of processor dies 300 by performing a hybrid bonding process, which is a combination of a metal-to-metal bonding process to and from bonding pads and a dielectric-to-dielectric bonding process to dielectric faces. In one embodiment, the front router bonding pads 688 are bonded to the front processor bonding pads 388 via metal-to-metal bonding, such as copper-to-copper bonding. The surfaces of the die dielectric material layers 360 are bonded to surface segments of the interposer dielectric material layers 160 via dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding.Alternatively, the two-dimensional array of router dies 600 may be bonded to the two-dimensional array of groups of processor dies 300 via microbump bonding (also known as C2 bonding or chip interconnect bonding), C4 bonding (controlled collapse chip interconnect bonding), or alternative chip attach techniques.

[0038] With reference to Fig. 6, the backside of the router substrate 608 may be thinned, for example, by grinding, polishing, an anisotropic etching process, an isotropic etching process, or a combination thereof. A final step of the thinning process that thins the backside of the router substrate 608 may include a chemical mechanical polishing step that uses the router substrate via structures 604 as stop structures. The backside end surfaces of the router substrate via structures 604 are exposed after thinning the backside of the router substrate 608. A recess etch process may optionally be performed to vertically recess the physically exposed backside surface of the router substrate 608.

[0039] With reference to Fig. 7, a backside router dielectric layer 612 may be deposited on the physically exposed backside surface of the router substrate 608. The backside router dielectric layer 612 may comprise a dielectric material suitable for dielectric-to-dielectric bonding, such as silicon oxide-to-silicon oxide bonding. The thickness of the backside router dielectric layer 612 may range from 100 nm to 600 nm, although smaller and larger thicknesses may be used. Pad cavities may be formed in the backside router dielectric layer 612 over the areas of the router substrate via structures 604, and end surfaces of the router substrate via structures 604 may be physically exposed below the pad cavities.At least one conductive material may be deposited in the pad cavities, and excess portions of the at least one conductive material may be removed from above the horizontal plane, including the top surface of the backside router dielectric layer 612. The at least one conductive material may comprise a combination of a metallic barrier material (such as TiN, TaN, WN, and / or MoN) and a metallic fill material, such as copper. Any remaining portion of the at least one conductive material filling a pad cavity forms a backside router bonding pad 618.

[0040] The backside router bonding pads 618 within the area of an interposer structure 100 may be arranged as arrays of backside router bonding pads 618. As previously explained, the router substrate via structures 604 within a router die 600 may comprise N arrays of router substrate via structures 604. The integer N may be the total number of memory dies to be subsequently bonded to the router die 600. The integer N may range from 2 to 2 6 In this embodiment, the backside router bonding pads 618 within a router die 600 may include N arrays of backside router bonding pads 618. The backside router bonding pads 618 may be configured for metal-to-metal bonding, such as copper-to-copper bonding.

[0041] Alternatively, the backside router bonding pads 618 may be configured for C4 bonding. In this embodiment, each of the backside router bonding pads 618 may include a layer stack including a metallic nitride barrier liner comprising a conductive metallic nitride material (such as TiN, TaN, WN, or MoN), a copper layer, an adhesion layer that improves the adhesion strength of subsequently deposited layers and comprises a material such as Cr, Ti, or a Cr / Ti alloy, a metallic barrier layer comprising a metallic diffusion barrier material such as W, Mo, or Mo, and an under-bump metallization (UBM) layer. The UBM layer may include a multilayer stack, such as a layer stack of a copper layer, a nickel layer, and a gold layer. Alternative UBM layer compositions may also be used.

[0042] Generally, router die 600 includes a backside router dielectric layer 612 located on a backside surface of router substrate 608 and backside router bonding pads 618 formed therein. Backside router bonding pads 618 contact end surfaces of router substrate via structures 604.

[0043] With reference to Fig. 8, memory dies 800 may be bonded to the backside of router die 600. Each memory die 800 may include bonding pads arranged in a mirror image structure of the structure of an array of backside router bonding pads 618. The bonding pads of memory dies 800 are referred to herein as memory die bonding pads 888. Memory die bonding pads 888 may be bonded to backside router bonding pads 618 by metal-to-metal bonding (such as copper-to-copper bonding) or by solder bonding (such as microbump bonding, i.e., die interconnect bonding). If the backside router bonding pads 618 within a router die 600 comprise N arrays of backside router bonding pads 618, N memory dies 800 can be bonded to the N arrays of backside router bonding pads 618. The memory die bonding pads 888 of the memory dies 800 are electrically connected to the router substrate via structures 604.

[0044] In one embodiment, memory dies 800 comprise high bandwidth memory (HBM) dies 800 including a respective vertical stack of dynamic random access memory (DRAM) dies 820 interconnected by die interconnect (C2) bonding. Each die interconnect bond may utilize a pair of arrays of microbump structures 838 interconnected by an array of solder portion 835.Each microbump structure 838 may include a metal pillar structure comprising a vertical layer stack including a metal nitride barrier liner comprising a conductive metallic nitride material (such as TiN, TaN, WN, or MoN), a copper layer, an adhesion layer that improves the adhesion strength of subsequently deposited layers and comprises a material such as Cr, Ti, or a Cr / Ti alloy, a metallic barrier layer comprising a metallic diffusion barrier material such as W, Mo, or Mo, and an under-bump metallization (UBM) layer. A mold compound encapsulation structure 840 may be provided such that the microbump structures 838 and the solder material portions 835 are encapsulated by the mold compound encapsulation structure 840.

[0045] The memory die bonding pads 888 may be configured for metal-to-metal bonding or for solder bonding. In embodiments in which the memory die bonding pads 888 are configured for metal-to-metal bonding, each of the memory die bonding pads 888 may include a layer stack including a metal barrier nitride liner comprising a conductive metallic nitride material (such as TiN, TaN, WN, and / or MoN) and a copper layer. In this embodiment, the copper surfaces of the memory die bonding pads 888 may be bonded to the copper surfaces of the backside router bonding pads 618 by metal-to-metal bonding, which is copper-to-copper bonding. Additionally, the bottom surface of each memory die 800 may include a dielectric material (such as silicon oxide) that may be used for dielectric-to-dielectric bonding.In this embodiment, dielectric-to-dielectric bonding may be provided between the bottom surfaces of the memory dies 800 and the backside router dielectric layer 612.

[0046] Alternatively, in embodiments in which the memory die bonding pads 888 and the backside router bonding pads 618 are configured for solder bonding (such as die interconnect bonding), each of the memory die bonding pads 888 and the backside router bonding pads 618 may include a respective microbump structure, which may include a metal pillar structure comprising a vertical layer stack including a metal nitride barrier liner comprising a conductive metal nitride material (such as TiN, TaN, WN, or MoN), a copper layer, an adhesion layer that improves the adhesion strength of subsequently deposited layers and comprises a material such as Cr, Ti, or a Cr / Ti alloy, a metallic barrier layer comprising a metallic diffusion barrier material such as W, Mo, or Mo, and an under-bump metallization (UBM) layer.In this embodiment, solder material portions (not illustrated) may be used to provide chip interconnect (C2) bonding (also referred to as microbump bonding) between the memory dies 800 and the router die 600.

[0047] Generally, the memory dies 800 include bonding pads, i.e., memory die bonding pads 888, that are electrically connected to the router substrate via structures 604. In one embodiment, the memory dies 800 include memory die bonding pads 888 that are electrically connected to the router substrate via structures 604. In one embodiment, the memory die bonding pads 888 are bonded to the backside router bonding pads 618 via metal-to-metal bonding. A recovered wafer including a carrier substrate 108, a two-dimensional array of interposer structures 100, a two-dimensional array of groups of M processor dies 300, a two-dimensional array of router dies 600, and a two-dimensional array of groups of N memory dies 800 is provided.

[0048] With reference to Fig. 9, the carrier substrate 108 may be detached from the assembly comprising the two-dimensional array of interposer structures 100, the two-dimensional array of groups of M processor dies 300, the two-dimensional array of router dies 600, and the two-dimensional array of groups of N memory dies 800. For example, the carrier substrate 108 may be cleaved by decomposing the interface material layer 109 if the interface material layer 109 comprises a decomposable material that can be decomposed upon thermal activation or by other means. Alternatively, the carrier substrate 108 may be removed by grinding or polishing. Any remaining portion of the interface material layer 109 may then be removed by performing a suitable cleaning process.

[0049] With reference to Fig. 10, bump structures may be formed on the backside surface of the interposer structures 100. In one embodiment, the bump structures may include backside interposer bonding pads 118 and solder material portions 105. In this embodiment, each backside interposer bonding pad 118 may include a stack of a metal pad structure 118P and a metal bump layer 118B. Each metal pad structure 118P may include a stack of a metal nitride barrier liner comprising a conductive metallic nitride material (such as TiN, TaN, WN, or MoN) and a copper pad structure. Each metal bump layer 118B may include a stack of an adhesion layer that improves the adhesion strength of subsequently deposited layers and comprises a material such as Cr, Ti, or a Cr / Ti alloy, a metallic barrier layer that comprises a metallic diffusion barrier material such as W, Mo, or Mo, and an under-bump metallization (UBM) layer.Alternatively, the bump structures on the backside surface of the interposer structures 100 may include alternative bump structures such as metal pads (e.g., copper pads) configured for direct metal-to-metal bonding. The bump structures on the backside surface of the interposer structures 100 may or may not be configured for hybrid bonding. In embodiments in which the bump structures on the backside surface of the interposer structures 100 are configured for hybrid bonding, the bump structures may be embedded in the interposer dielectric material layers 160 such that the physically exposed surfaces of the metal pads are substantially coplanar with the backside surface of the interposer dielectric material layers 160.

[0050] Subsequently, the assembly comprising the two-dimensional array of interposer structures 100, the two-dimensional array of groups of M processor dies 300, the two-dimensional array of router dies 600, the two-dimensional array of groups of N memory dies 800, and the backside interposer bonding pads 118 may be sawn along sawing channels. The sawing channels correspond to boundaries between adjacent pairs of interposer structures 100, which coincide with boundaries between adjacent pairs of router dies 600 in a plan view, such as a top-down view. Each sawed portion of the assembly comprises a semiconductor assembly including an interposer structure 100, a group of M processor dies 300, a router die 600, and a group of N memory dies 800.The physically exposed sidewalls of the interposer structure 100, the router die 600, and the dielectric matrix 390 within each semiconductor device may vertically coincide with each other. As used herein, a first surface and a second surface vertically coincide with each other when the second surface is above or below the first surface and when the first surface and the second surface are within a same vertical plane.

[0051] With reference to Fig. 11 illustrates a semiconductor device formed by dicing the recovered wafer. In the illustrated example, the number N of memory dies (800) attached to a router die (600) is 2. 4 , i.e., 16.

[0052] Fig. 12 is a circuit diagram illustrating the operation of a semiconductor device used in Fig. 10 and Fig. 11. Each processor die 300 may include a processing unit comprising a combination of a core and a register. Each processor die 300 may further include an L1 cache (i.e., a first-level cache) and an L2 cache (i.e., a second-level cache) in communication with the processing unit. M processor dies may be electrically connected to the router die 600, which acts as a network-on-chip router, i.e., a chip that provides a network connection to the processor dies 300 and the memory dies 800. The memory dies 800 may act as L3 caches (i.e., third-level caches) that each of the processor dies 300 may access through the router die 600.

[0053] In general, router die 600 may be a passive router die that does not include any switching devices. Thus, the activation of electrical connections between a processor die 300 and a memory die 800 may be controlled by input / output control circuits of processor die 300. As previously explained, in embodiments in which M processor dies 300 and N memory dies 800 are interconnected by router metal interconnect structures 680, M x N groups of electrical connections may be provided between M arrays of front router bonding pads 688 and N arrays of back router bonding pads 618.

[0054] In one embodiment, the M x N groups of electrical connections may be electrically isolated from each other. Alternatively, the M x N groups of electrical connections may comprise a group of electrical signal paths shared with a plurality of arrays of front-side router bonding pads 688 or shared with a plurality of arrays of back-side router bonding pads 618. In this embodiment, input / output controllers in the processor die 300 or in the memory die 800 may electrically disconnect inactive signal paths by setting the state of the input / output controllers of unselected processor dies 300 and / or unselected memory dies 800 in a high impedance state, i.e., a disconnect state.Thus, data transfer between the M processor dies 300 and the N memory dies 800 can be performed by the router die 600 without the use of any intermediary device.

[0055] The bandwidth for data transmission provided by the router die 600 of the present disclosure may be greater than bandwidths provided by previously known data transmission schemes between processor dies and memory dies. Fig. 13 schematically illustrates a change in the operation of a computing device that may include the semiconductor device of the present disclosure with respect to previously known computing devices. In general, the performance of a computing system may be compute-bound, i.e., limited by the performance of the processing units, or memory-bound, i.e., limited by the data transfer rate from the memory dies to the processor dies. Curve 1310 represents a limitation of performance (measured in gigaflops per second) due to a memory wall problem in prior art computing systems. Curve 1320 represents a limitation of performance in a system using a semiconductor device described with reference to Fig. 10 and Fig. 11. The semiconductor device of the present disclosure can provide the highest level of performance, limited only by the performance of the processing units 320, with a lower operating intensity (measured in flops per byte) for the processing units 320. This mode of operation consumes less power, generates less heat, and provides the highest possible level of performance by increasing the bandwidth for data transfer between the memory dies 800 and the processor dies 300.

[0056] In embodiments where the memory dies 800 comprise high-bandwidth memory dies, it is estimated that the router substrate via structures 604 may be formed with a pitch in a range of 10 micrometers to 60 micrometers, such as 20 micrometers to 40 micrometers. The area of a keep-out zone (KOZ) for the router substrate via structures 604 may be in a range of 1% to 10% of the total area of the router die 600 in a plan view, such as a top-down view. The memory dies 800 may be arranged in a rectangular regular array, or may be arranged in a tiered structure, or in any other basic design structure optimized for performance based on the arrangement of the processor dies 300.

[0057] The architecture provided by the bonded arrangement of an interposer, M processor dies 300, a router die 600, and N memory dies can increase the total memory capacity and reduce the memory latency, resulting in the shift with respect to the top edge line (such as curve 1310 or 1320) in a performance graph, as shown in Fig. 13. The total number N of memory dies 800 that can be attached to a router die 600 generally depends on the area of the router die 600, which may be the same as the area of the interposer structure 100. In embodiments where the router die 600 has a size of about three reticles (corresponding to an area of about 3 by 30 mm by 30 mm), up to 20 high bandwidth memory (HBM) dies can be attached to the router die 600 as memory dies 800. The memory capacity per memory die 800 and the total number of memory dies 800 can be increased to provide an increase in memory capacity for a computing system, and use of the increased memory capacity can be through the data paths provided within the router die 600.

[0058] With reference to Fig. 14 is a flowchart illustrating the general processing steps for forming a semiconductor device of the present disclosure.

[0059] Referring to step 1410 and Fig. 1 and Fig. 2, a plurality of processor dies 300 may be attached to an interposer structure 100 including interposer dielectric material layers 160 in which interposer metal interconnect structures 180 are formed.

[0060] Referring to step 1420 and Fig. 3, a dielectric matrix 390 may be formed around the plurality of processor dies 300 over the interposer structure 100.

[0061] Referring to step 1430 and Fig. 4 and Fig. 5, a router die 600 may be attached to the plurality of processor dies 300. The router die 600 includes router dielectric material layers 660 in which router metal interconnect structures 680 are formed, and a router substrate 608 in which router substrate via structures 604 are formed.

[0062] Referring to step 1440 and Fig. 6 and Fig. 7, a backside of the router substrate 608 can be thinned. The end surfaces of the router substrate via structures 604 are exposed.

[0063] Referring to step 1450 and Fig. 8-11, the memory dies 800 can be attached to the router substrate 608 after thinning the backside of the router substrate 608. The bonding pads of the memory dies 800, ie, the memory die bonding pads 888, are electrically connected to the router substrate via structures 604.

[0064] With reference to all the drawings and in accordance with various embodiments of the present disclosure, a semiconductor device is provided comprising: a plurality of processor dies 300 bonded to an interposer structure 100 including interposer dielectric material layers 160 in which interposer metal interconnect structures 180 are formed; a dielectric matrix 390 laterally surrounding the plurality of processor dies 300; a router die 600 bonded to the plurality of processor dies 300 and including router dielectric material layers 660 in which router metal interconnect structures 680 are formed, and a router substrate 608 in which router substrate via structures 604 are formed; and memory dies 800 including bonding pads (i.e., memory die bonding pads 888) electrically connected to router substrate via structures 604.

[0065] In one embodiment, the plurality of processor dies 300 includes: processor die substrates 308 in which die substrate via structures 304 are formed; and backside processor bonding pads 318 located on the die substrate via structures 304 and bonded to the front interposer bonding pads 188 formed within the interposer dielectric material layers 160 of the interposer structure 100.

[0066] In one embodiment, the plurality of processor dies 300 includes back-die dielectric layers 312 that laterally surround the die dielectric layers 312. Surfaces of the back-die dielectric layers 312 are bonded to surface segments of the interposer dielectric material layers 160 via dielectric-to-dielectric bonding. In one embodiment, the sidewalls of the interposer structure 100 vertically coincide with the sidewalls of the router die 600. In one embodiment, the front router bonding pads 688 formed within the router dielectric material layers 660 are bonded to the front processor bonding pads 388 formed within the die dielectric material layers 360 of the plurality of processor dies 300.

[0067] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: an interposer structure 100 including interposer dielectric material layers 160 in which interposer metal interconnect structures 180 and front interposer bonding pads 188 are formed; a plurality of processor dies 300 embedded within a dielectric matrix 390 and including first processor bonding pads (such as backside processor bonding pads 318) bonded to front interposer bonding pads 188;a router die 600 comprising router dielectric material layers 660 in which router metal interconnect structures 680 and front router bonding pads 688 are formed, and further comprising a router substrate 608 in which router substrate via structures 604 are formed, wherein the front router bonding pads 688 are bonded to first processor bonding pads (such as the front processor bonding pads 388) within the plurality of processor dies 300; and memory dies 800 bonded to the router die 600, wherein the memory dies 800 include memory die bonding pads 888 electrically connected to the router substrate via structures 604.

[0068] In one embodiment, router die 600 includes a backside router dielectric layer 612 located on a backside surface of router substrate 608 and having backside router bonding pads 618 formed therein, which contact end surfaces of router substrate via structures 604. In one embodiment, memory dies 800 include bonding pads (i.e., memory die bonding pads 888) bonded to backside router bonding pads 618 via metal-to-metal bonding.

[0069] In one embodiment, the sidewalls of router die 600 vertically coincide with the sidewalls of dielectric matrix 390. In one embodiment, the plurality of processor dies 300 includes die dielectric material layers 360 in which die metal interconnect structures and front processor bonding pads 388 are formed; front router bonding pads 688 are formed in router dielectric material layers 660; and front router bonding pads 688 are bonded to front processor bonding pads 388 via metal-to-metal bonding.

[0070] Embodiments of the present disclosure may be used to provide a computing system that uses a passive router die to provide increased bandwidth between the processor dies 300 and the memory dies 800. For example, high-bandwidth memory (HBM) dies (such as used as the memory dies 800) may be integrated with application-specific integrated circuit (ASIC) dies (such as used as the processor dies 300) to provide a computing system with enhanced computing performance. The router die 600 acts as a network-on-chip (NoC) die, providing data paths for the HBM dies, and data flow may be controlled by the ASIC dies. The computing system of the present disclosure may be fabricated using chip-on-wafer-on-substrate (CoWoS) technology, which utilizes via substrate structures and hybrid bonding.The processor dies 300 may include any type of processing units and thus may be any type of processor die known in the art.

[0071] The foregoing illustrates features of various embodiments so that one skilled in the art may better understand aspects of the present disclosure. Any embodiment described using the term "comprises" generally also discloses additional embodiments in which the term "comprises" is replaced with "consists essentially of" or with the term "consisting of," unless expressly disclosed to the contrary herein. Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, a Markush group including a listing of the two or more elements is also implicitly disclosed.Whenever the auxiliary verb "can" is used in this disclosure to describe the formation of an element or the performance of a processing step, an embodiment in which such an element or processing step is not performed is also expressly contemplated, provided that the resulting device or apparatus can provide an equivalent result. Therefore, the auxiliary verb "can," as applied to the formation of an element or the performance of a processing step, should also be interpreted as "can" or "may or may not" whenever omitting the formation of such an element or processing step can provide the same result or equivalent results, where the equivalent results include slightly better results and slightly worse results.One skilled in the art should recognize that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages of the embodiments presented herein. One skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

A method of forming a semiconductor device comprising: attaching a plurality of processor dies to an interposer structure including interposer dielectric material layers in which interposer metal interconnect structures are formed; forming a dielectric matrix around the plurality of processor dies over the interposer structure; attaching a router die to the plurality of processor dies, the router die comprising router dielectric material layers in which router metal interconnect structures are formed and a router substrate in which router substrate via structures are formed; thinning a backside of the router substrate, exposing end surfaces of the router substrate via structures;andattaching memory dies to the router substrate after thinning the backside of the router substrate, wherein bonding pads of the memory dies are electrically connected to the router substrate via structures.; The method of claim 1, wherein:the interposer structure comprises front interposer bonding pads formed within the interposer dielectric material layers;the plurality of processor dies comprises processor die substrates in which die-substrate via structures are formed; andthe substrate via structures are electrically connected to the front interposer bonding pads after attaching the plurality of processor dies to the interposer structure. The method of claim 2, wherein: the plurality of processor dies comprise backside processor bonding pads located on the die substrate via structures; and the backside processor bonding pads are bonded to the front interposer bonding pads via metal-to-metal bonding after attaching the plurality of processor dies to the interposer structure. The method of claim 3, wherein: the plurality of processor dies comprise backside die dielectric layers laterally surrounding a respective subset of the backside processor bonding pads; and the backside die dielectric layers are bonded to surface segments of the interposer dielectric material layers via dielectric-to-dielectric bonding. The method of any one of claims 1 to 4, wherein: the interposer structure is provided on a top surface of a carrier substrate; and the method comprises detaching the carrier substrate from an assembly comprising the interposer structure, the plurality of processor dies, and the router substrate after thinning the backside of the router substrate. The method of any one of claims 1 to 5, wherein:each of the plurality of processor dies comprises a respective group of die dielectric material layers in which a respective group of die metal interconnect structures and a respective group of front processor bonding pads are formed;front router bonding pads are formed in the router dielectric material layers; andthe front router bonding pads are electrically connected to a respective one of the front processor bonding pads after attaching the router die to the plurality of processor dies. The method of claim 6, wherein the router die is attached to the plurality of processor dies by performing a hybrid bonding process such that: the front router bonding pads are bonded to the respective one of the front processor bonding pads via metal-to-metal bonding; and the surfaces of the die dielectric material layers are bonded to surface segments of the interposer dielectric material layers via dielectric-to-dielectric bonding. The method of any one of claims 1 to 7, wherein the dielectric matrix is formed by:depositing a dielectric material within gaps between adjacent pairs of processor dies selected from the plurality of processor dies; andremoving portions of the dielectric material from above a horizontal plane including the top surfaces of the plurality of processor dies, wherein the remaining portions of the dielectric material filling the gaps comprise the dielectric matrix. The method of any one of claims 1 to 8, further comprising:forming a backside router dielectric layer on a backside surface of the router substrate after thinning the router substrate; andforming backside router bonding pads within the backside router dielectric layer on the end surfaces of the router substrate via structures. The method of claim 9, wherein:the memory dies comprise high bandwidth memory (HBM) dies including a vertical stack of dynamic random access memory (DRAM) dies; andbonding pads of the memory dies are bonded to the backside router bonding pads via metal-to-metal bonding. A semiconductor device comprising: a plurality of processor dies bonded to an interposer structure including interposer dielectric material layers in which interposer metal interconnect structures are formed; a dielectric matrix laterally surrounding the plurality of processor dies; a router die bonded to the plurality of processor dies and including router dielectric material layers in which router metal interconnect structures are formed, and a router substrate in which router substrate via structures are formed; and memory dies comprising bonding pads electrically connected to the router substrate via structures. The semiconductor device of claim 11, wherein the plurality of processor dies comprises:processor die substrates in which die substrate via structures are formed; andbackside processor bonding pads located on the die substrate via structures and bonded to the front interposer bonding pads formed within the interposer dielectric material layers of the interposer structure. The semiconductor device of claim 11 or 12, wherein: the plurality of processor dies comprise backside die dielectric layers laterally surrounding the backside processor bonding pads; and surfaces of the backside die dielectric layers are bonded to surface segments of the interposer dielectric material layers via dielectric-to-dielectric bonding. Semiconductor device according to one of claims 11 to 13, wherein the side walls of the interposer structure vertically coincide with the side walls of the router die. The semiconductor device of any of claims 11 to 14, wherein the front router bonding pads formed within the router dielectric material layers are bonded to the front processor bonding pads formed within the die dielectric material layers of the plurality of processor dies. A semiconductor device comprising:an interposer structure comprising interposer dielectric material layers in which interposer metal interconnect structures and front interposer bonding pads are formed;a plurality of processor dies formed within a dielectric matrix and comprising first processor bonding pads bonded to the front interposer bonding pads;a router die comprising router dielectric material layers in which router metal interconnect structures and front router bonding pads are formed, and further comprising a router substrate in which router substrate via structures are formed, the front router bonding pads being bonded to second processor bonding pads within the plurality of processor dies; andmemory dies bonded to the router die, the memory dies comprising memory die bonding pads electrically connected to the router substrate via structures. The semiconductor device of claim 16, wherein the router die comprises a backside router dielectric layer located on a backside surface of the router substrate and having backside router bonding pads formed therein that are in contact with end surfaces of the router substrate via structures. The semiconductor device of claim 17, wherein the memory dies comprise bonding pads bonded to the backside router bonding pads via metal-to-metal bonding. A semiconductor device according to any one of claims 16 to 18, wherein the sidewalls of the router die vertically coincide with the sidewalls of the dielectric matrix. The semiconductor device of any of claims 16 to 19, wherein: the plurality of processor dies comprise die dielectric material layers in which die metal interconnect structures and front processor bonding pads are formed; front router bonding pads are formed in the router dielectric material layers; and the front router bonding pads are bonded to the front processor bonding pads via metal-to-metal bonding.

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