System and method for implementing scalable system

Abstract

The invention relates to a system and method for implementing a scalable system. A multi-chip system (100) and structure for modular extension is described. In some embodiments, bonding strips (150) are used to couple adjacent chips (102, 104). For example, a communication bar (150) may be used to couple a logic chip (104), and a memory bar (150) may be used to couple a plurality of memory chips (102) to the logic chip (104).

Description

[0001] Related Patent Applications

[0002] This application is a divisional of application number 20221044091.0, filed on March 28, 2019, having the title “System and method for implementing a scalable system”. Application number 20221044091.0 is a divisional of application number 201980024144.1, filed on March 28, 2019, having the title “System and method for implementing a scalable system”.

[0003] This patent application claims priority to U.S. Provisional Application 62 / 656,584, filed on April 12, 2018, which is incorporated by reference herein. TECHNICAL FIELD

[0004] The embodiments described herein relate to scalable systems, and more specifically to scalable logic components and modular memory. BACKGROUND

[0005] Scalable systems require both logic components and memory that can be increased in a practical and cost-effective method. Furthermore, they should reasonably allow for independent scaling of logic components and memory to allow for computation, memory bandwidth, and storage capacity adjustments according to system requirements. Dynamic random access memory (DRAM) has long been a product of the computer and electronics industry. With the advent of a large market of end applications starting from desktop computers, mobile electronics, data centers, and networking platforms, competitive memory platforms have rapidly evolved according to certain requirements such as bandwidth, capacity, power, latency, and footprint. However, increasing one parameter is typically met by a trade-off of other parameters. For example, increasing DRAM bandwidth is typically accompanied by a loss of other parameters.

[0006] Low power double data rate (LPDDR) standards have long been adopted in various markets, including mobile electronics, to meet performance and capacity requirements. LPDDR platforms and next generation (LPDDR-x) typically include an arrangement of memory chips or packages around a system on a chip (SOC), which can include a central processing unit (CPU) and / or a graphics processing unit (GPU). To meet the demand for increased bandwidth, various 3D solutions have been proposed, including stacked DRAM dies such as high bandwidth memory (HBM) and hybrid memory cube (HMC). BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 Schematic top view illustration of a plurality of memory chips arranged around a system on a chip.

[0008] Figure 2 is a schematic top view illustration of a multi-chip system with extended logic according to an embodiment.

[0009] Figure 3 is a schematic top view and side view illustration of a multi-chip system with extended logic according to an embodiment.

[0010] Figure 4 is a schematic top view illustration of an extended logic die with on-die inter-die routing according to an embodiment.

[0011] Figure 5 is a schematic top view illustration of an extended logic according to an embodiment with 2.5D inter-chip routing.

[0012] Figure 6 is a schematic top view illustration of an extended logic according to an embodiment with 2.5D inter-chip routing and bridges.

[0013] Figure 7 is a schematic top view illustration of an extended logic according to an embodiment with a mix of on-die inter-die routing and 2.5D inter-chip routing.

[0014] Figure 8 is a schematic top view illustration of a modular extension of a logic die with added periphery according to an embodiment.

[0015] Figure 9 is a schematic top view illustration of an extended logic die connection according to an embodiment.

[0016] Figure 10A is a schematic top view illustration of a logic die connection overhead according to an embodiment.

[0017] Figure 10B is a schematic top view illustration of an extended logic die connection overhead according to an embodiment.

[0018] Figure 11A is a schematic top view illustration of a logic die connection overhead according to an embodiment.

[0019] Figure 11B is a schematic top view illustration of an extended logic die connection overhead with a communication strip according to an embodiment.

[0020] Figure 12A is a schematic top view illustration of a 3D extension of a logic die with a communication strip according to an embodiment.

[0021] Figure 12Bis a schematic top view illustration of a planar extension of a logic chip with a communication strip according to one embodiment.

[0022] Figure 13 is a schematic top view illustration of a multi-chip system with an extended logic section, memory, and high capacity according to one embodiment.

[0023] Figure 14 is a schematic top view illustration of a multi-chip system with an extended logic section, memory, and short logic connections according to one embodiment.

[0024] Figure 15 is a schematic cross-sectional side view illustration of a bonded strip metal routing layer according to one embodiment.

[0025] Figure 16 is a schematic top view illustration of an extended system with inter-die routing according to one embodiment.

[0026] Figure 17 is a schematic top view illustration of a bonded strip routing according to one embodiment.

[0027] Figure 18A is a schematic cross-sectional side view and top view illustration of a bonded strip and routing according to one embodiment.

[0028] Figure 18B is a schematic cross-sectional side view illustration of a BGA side mounted bonded strip according to one embodiment.

[0029] Figure 18C is a schematic top view illustration of an optical communication strip according to one embodiment.

[0030] Figure 19 is a schematic top view illustration of a bonded strip with a hammerhead shape according to one embodiment.

[0031] Figure 20 is a schematic top view illustration of a bonded strip including a repositioned die logic section according to one embodiment.

[0032] Figure 21 is a schematic top view illustration of an interface strip active area according to one embodiment.

[0033] Figure 22 is a schematic top view and cross-sectional side view illustration of a bonded strip with multiple discrete active components according to one embodiment.

[0034] Figure 23 is a schematic top view illustration of an extended system including a memory strip bridge according to one embodiment.

[0035] Figure 24 is a schematic top view illustration of an extended system including an extension region according to an embodiment.

[0036] Figures 25-26 is a schematic top view illustration of bonded strips having different form factors according to an embodiment.

[0037] Figure 27 is a schematic top view and cross-sectional side view illustration of a bonded strip having discrete active regions and a head region according to an embodiment.

[0038] Figure 28 is a schematic top view and cross-sectional side view illustration of a bonded strip package according to an embodiment.

[0039] Figure 29A is a schematic top view illustration of an extended system having a bridge connecting a logic chip to a memory strip according to an embodiment.

[0040] Figure 29B is a schematic cross-sectional side view illustration of an extended system according to an embodiment. Figure 29A

[0041] Figure 30 is a schematic top view illustration of an extended system having board wiring connecting a logic chip to a memory strip according to an embodiment.

[0042] Figure 31A is a schematic top view illustration of a package-on-package extended system according to an embodiment.

[0043] Figures 31B-31C is a schematic cross-sectional side view illustration of various package-on-package extended systems according to an embodiment.

[0044] Figure 32A is a schematic top view illustration of a 3D extended system according to an embodiment.

[0045] Figure 32B is a schematic cross-sectional side view illustration of a 3D extended system taken along line B-B of Figure 32A DETAILED DESCRIPTION

[0046] Embodiments describe multi-chip systems and structures for modular extension. In some embodiments, bonded strips are used to couple adjacent chips. In one aspect, the bonded strips can increase the total capacity and available peripherals for inter-chip connections. In another aspect, the bonded strips can be used to increase the bandwidth of inter-chip communications and reduce latency.

[0047] ​​In one implementation, the interconnect strip can be used as a communication strip between logic chips. In such implementations, the interconnect strip can be communication facing, meeting bandwidth, power, latency, and cost targets. The logic chips, such as system on a chip (SOC), can include central processing units (CPUs) or graphics processing units (GPUs). Further, the logic chip periphery can be formatted to enable memory integration and other input / output (I / O) to other devices. The interconnect strip can support metal stacks and logic components (e.g., transistor types) compatible with communication functions. The interconnect strip can be packaged in multiple configurations, including chip on wafer (CoW) and 2.5D packaging techniques. For example, CoW can also be 2.5D or 3D arrangements. Here, individual chips are bonded together (chip to chip), or to an interposer (chip-interposer-chip). The interconnect technology can be micro-bumps (dense I / O), or ACF, or hybrid bonding (metal-to-metal) that supports very dense IO, or even optical interconnects. Instead of individual chips, wafer-to-wafer (W2W) bonding is also possible, and can be used depending on the application. For example, CoW can involve a support wafer or panel with a split area larger than the chips mounted on the support wafer, while W2W can involve equal split wafer or panel areas. 2.5D packaging can use smaller dense interconnect connections between two chips. The small chips for 2.5D packaging can be passive bridges of shorter length or longer lengths arranged as interconnect strips. These interconnect strips provide options to balance bandwidth, power, complexity, heat and power delivery, and other architectural requirements. Further, the interconnect strips can be active silicon (or other device technologies such as GaAs). The interconnect strips can also be encapsulated in molding compound, and optionally include multiple components connected by bridges. Thus, the interconnect strips for 2.5D packaging can also be formed separately and packaged using 2.5D packaging. Larger interconnect strips can also have special requirements for assembly to a substrate to manage mechanical stress and other assembly issues. The connections between the chips and the interconnect strips can use solder (micro-bumps) or ACF and hybrid bonding (metal-to-metal). In some example implementations, CoW integration can be used for performance logic components with dense I / O using micro-bumps or even denser hybrid bonding. In some implementations, CoW integration can include hybrid bonding of silicon small chips with an interposer. In some embodiments, CoW integration can include silicon small chips connected with back end of line (BEOL) interconnects in a chip-like fashion. For example, the silicon small chips can have a partial BEOL build-up structure and interconnects, with a subsequent second level BEOL build-up structure connecting the silicon small chips in a chip-like fashion. The silicon small chips can be embedded in an inorganic gap fill (e.g., oxide) material, on which the second level BEOL build-up structure is formed. In some embodiments, 2.5D packaging can be used for chip set lighting functions with moderate bandwidth and latency requirements.

[0048] In one embodiment, the bonding strip can be used as a memory strip to couple a group of memory chips to a logic chip. The group of memory chips can be laterally separated. In addition, the laterally separated memory chips can be packaged separately, or as part of a die stack or module with multiple dies. Therefore, the laterally separated chips according to the embodiment can be part of a laterally separated package, die stack or module. In one aspect, the bonding strip can enable the logic chip to communicate with various types of DRAM chips including LPDDR-x, DDR, HMB, etc. According to the embodiment, the memory chip is not limited to a variant of DRAM, or LPDDR-x, DDR, HBM, etc. Similarly, the logic chip may include multiple functions, such as but not limited to SOC, CPU, GPU, cache, signal processor, glue logic components, etc., and may be based on silicon or other technologies (e.g., GaAs). The bonding strip may include a local controller compatible with the memory type, and a physical interface (PHY) compatible with the memory (e.g., PHY analog and PHY digital controller). In some embodiments, the memory strip is packaged in configurations such as 2.5D packaging, multi-chip module (MCM) and MCM plus bridge. Additionally, memory sticks can be packaged into various shapes for routing, such as an L-shape.

[0049] According to an embodiment, a configuration for modular expansion of logic components and / or memory is shown. In one aspect, on-chip resources can be used to expand logic components. For example, on-chip wiring can be used to connect multiple dies on the same silicon layer. Such available on-chip resources can facilitate high-density, low-power expansion and can also utilize CoW technology.

[0050] On the other hand, bonding strips can be used for die expansion from logic components to logic components. Such bonding strips or communication strips may include active silicon, increase the area for logic connections, and provide expansion flexibility (e.g., SOC+CPU+GPU+other). Various cost control implementations may be included. For example, logic components can be moved from logic chips to communication strips to reduce the cost of logic chips. Communication strips can also provide voltage shifting capabilities. In addition, the communication strips may include discrete extended segment areas, tapered structures, or hammerhead structures to reduce silicon costs as more dies are implemented per wafer.

[0051] In another aspect, bonding bars can be used to increase the logic chip periphery for memory expansion. Such bonding bars or memory bars can facilitate expansion to large storage capacities. Additionally, a chain of memory bars can be used to further increase capacity. According to embodiments, metal layer prioritization and consolidation can be used for latency management, particularly for memory chips located farther away from the logic chip. Similar to the connectivity bars, various cost control measures can be included. Notably, the memory bars can be compatible with a variety of memory types including LPDDR-x, DDR, HBM, etc. In some embodiments, the memory bars can contain physical interfaces (PHYs) and memory (e.g., DRAM) controllers. The memory bars can also provide voltage shifting capabilities.

[0052] In various embodiments, descriptions are made with reference to the accompanying drawings. However, certain embodiments can be implemented without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are illustrated, such as specific configurations, dimensions, and processes, to provide a thorough understanding of the embodiments. In other instances, well-known components, semiconductor processes, and manufacturing techniques have not been described in detail in order to not unnecessarily obscure the embodiments. References made throughout this specification to "an embodiment" mean that a particular feature, structure, configuration, or characteristic being described is included in at least one embodiment. Therefore, appearances of the phrase "in one embodiment" throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics can be combined in any suitable manner in one or more embodiments.

[0053] As used herein, the terms "over," "above," "to," "between," and "on" can refer to a relative position of one layer with respect to other layers. A layer can be "over," "above," or "on" another layer or bonded "to" or "in contact with" another layer can be directly in contact with the other layer or can have one or more intervening layers. A layer can be "between" a plurality of layers can be directly in contact with the plurality of layers or can have one or more intervening layers.

[0054] Figure 1is a schematic top view illustration of a plurality of memory chips 102 (e.g., DRAM) arranged around a logic chip 104 (e.g., SOC) on a board 106 (e.g., printed circuit board (PCB) or multi-chip module (MCM)) in a conventional memory system. It has been observed that such systems can suffer from a limited logic chip 104 footprint (e.g., peripheral length of the SOC) for the memory chips 102. This limited area / perimeter can constrain the ability to scale the storage capacity of the system. It has also been observed that direct chip attachment of the logic chip 104 and / or memory chips 102 to the board 106 can be problematic due to coefficient of thermal expansion (CTE) mismatch, which can result in coarser pitch I / O and lower pin count.

[0055] Figure 2 is a schematic top view illustration of a multi-chip system 100 having an extended logic component according to one embodiment. Such a configuration can simplify the interconnect hierarchy of a more conventional memory system with CTE matching and without mechanically pinning larger silicon (or interposer) to a highly mismatched substrate (e.g., board 106). Further, the system can increase the logic chip periphery and memory chip footprint with the SOC. In the illustrated embodiment, one or more logic chips 104 (e.g., SOC) and memory chips 102 can be mounted on a CTE matched substrate 120, such as glass, silicon, interposer, matched metal stable substrate, MCM substrate, etc. Such CTE matching can allow for finer pitch bump or anisotropic conductive film (ACF) attachment of the memory chips 102 and / or logic chips 104, as well as allowing for larger silicon chip integration. Tight CTE matching to silicon can be obtained, for example, with glass, silicon, or organics with a large inorganic (e.g., glass) content. As used herein, the term "CTE matched" means that the "effective CTE" of a "composite material" or "composite topology" having different components matches the CTE of another single material or the effective CTE of another composite material. Within a composite material, each of its components has its own CTE and elastic modulus. One non-limiting example of a so-called "composite material" can be an MCM substrate having multiple layers of materials. Another example of a "composite material" can be a memory (e.g., DRAM) chip or package that is silicon, molding compound, and a memory package substrate. In such an example, the "effective CTE" of the MCM substrate can be designed to match the effective CTE of the memory chip or package to minimize overall MCM warpage. The memory chip or package can also be considered a "composite topology" on the substrate. In a larger system example, all components on top of the (e.g., MCM) substrate can be considered a "composite topology." The effective CTE of the composite topology can be calculated and the MCM substrate is designed to have an effective CTE that matches the effective CTE of the composite topology.

[0056] According to embodiments, the substrate can be characterized by a composite coefficient of thermal expansion (CTE) that matches within + / - 4 ppm / C, or even more particularly within + / - 2 ppm / C, of the effective CTE of the composite topology on the substrate. The effective CTE and the CTE match are temperature dependent. For example, silicon has a CTE of approximately 2.6 ppm / C at 20°C and a CTE of approximately 3.6 ppm / C at 250°C.

[0057] For silicon-based composite topologies, an example of CTE matching is to bring the effective CTE of the package substrate (e.g., MCM substrate) close to 3 ppm / C. In this case, a glass core, as well as other high modulus and low CTE cores, are suitable options for the MCM or package substrate. For an MCM composite topology with both a silicon SOC and a multi-memory (e.g., DRAM) package, the overall effective CTE of the composite topology on top of the MCM substrate can be calculated using finite element method (FEM) simulation. The effective CTE of the composite topology can have a typical value in the range of 3 ppm / °C to 10 ppm / °C over a temperature range of 20°C to 150°C. At higher temperatures, such as near the solder reflow temperature of approximately 250°C, the effective CTE of the composite topology including the molding compound can have an even higher effective CTE due to the CTE increase of the molding compound beyond its glass transition temperature (Tg), which can typically be about 125°C. For example, the effective CTE of the DRAM package can be in the range of 8 ppm / C to 18 ppm / C at temperatures beyond the molding compound Tg (e.g., 150°C to 250°C), depending on the molding compound material properties and their relative volume to the DRAM die. By properly selecting the material properties of the MCM substrate, as well as the appropriate material properties and geometry parameters (such as DRAM die thickness) of the DRAM package, the effective CTE of the MCM substrate can be matched to the DRAM package.

[0058] Additional components 108, such as disks, and components 110, such as local area network (LAN), wireless, optical, etc. connections, can also be mounted on the substrate 120. In one embodiment, the substrate 120 is flexibly connected to the board 106 using a flexible circuit 112, rather than rigidly connected. Figure 2 The system 100 can additionally provide high bandwidth and cost-effective memory expansion. For example, a long peripheral SOC can be obtained by using on-chip resources, CoW technology, or connecting smaller logic chips 104 (e.g., SOCs) with a ribbon. Additionally, the connection of the memory chips 102 to the logic chips 104 can be expanded with high bandwidth and reduced latency and power loss using memory ribbons.

[0059] In another embodiment, the multi-chip system 100 includes routing through the MCM (including the substrate 120 and silicon chips mounted thereon) to a board 106 (e.g., PCB, other MCM, module, etc.) and attachment. The attachment can be a suitable structure that allows assembly and at the same time does not exert stress on the silicon chips on top. Such systems that can allow the substrate 120 to be mounted on a PCB can employ sockets with pins, soft solder, etc. to manage mechanical stress.

[0060] Figure 3 A schematic top view and side view illustration of a multi-chip system with an extended logic die according to an embodiment is shown. Similar to the embodiment shown in Figure 2 The system 100 can include a single large logic die 104 or multiple logic dies 104, as shown in the embodiment. The increased perimeter can facilitate positioning of a larger number of memory chips 102. In addition, the routing length to each memory chip 102 can be reduced due to the increased perimeter, which can further improve I / O speed. To increase strength, and to control any CTE mismatch, a stiffener 122 (e.g., ring) can be placed on or in the substrate 120. As shown in the cross-sectional side view illustration, the substrate 120 can include a plurality of vias 124 (or interconnects) to the backside. The memory chips 102 (or packages or die stacks) and the logic die 104 can be mounted with solder bumps 105 (including micro bumps) allowing very large scale integration (VLSI) and fine pitch I / O due to CTE matching. As shown, attachment with a flexible circuit 112 to the board 106 allows the substrate 120 to be secured to the board 106 using a suitable loose mechanical coupling 113 such as an adhesive film (or pressure sensitive adhesive).

[0061] Reference is now made to the drawings in which Figures 4-7 schematic top view and corresponding cross-sectional side view illustrations of various extended logic dies according to embodiments are provided. Figure 4 A schematic top view illustration of an extended logic die with on-die die-to-die routing according to an embodiment is shown. As shown, the logic die 104 includes two dies 103 that can be routed together using on-die routing 130 (such as with a common back end of line (BEOL) process to form a build-up structure with M0-Mn metal layers). In one embodiment, each die 103 can have its own metal seal ring 132, with the on-die routing 130 extending through the seal ring 132. In Figure 4 In the embodiment shown, the two dies 103 share the same silicon layer and are interconnected with an on-die build-up structure (on-die routing 130). In addition, the two dies 103 can be provided separately cut apart, or left together.

[0062] Figure 5A schematic top view and corresponding cross-sectional side view illustration of an extended logic component with 2.5D inter-chip routing according to one embodiment is shown. As shown, logic chips 104 are connected together in a chip-on-wafer (CoW) package 107. In some embodiments, the logic chips can be embedded in a mold compound (shown as the shaded material). In other embodiments, the logic chips 104 are embedded in an inorganic gap fill material (e.g., oxide shown as the shaded material). The logic chips 104 can be bonded to the wiring layer 136 with micro-bumps, hybrid bonding, or the wiring layer 136 can be a second level BEOL build-up structure formed on the logic chips 104 (e.g., small chips). The logic chips 104 can be from different wafers (same or different technology). In this configuration, the wiring layer 136 can be used to connect two discrete logic chips 104. In one embodiment, the wiring layer 136 is an interposer or a second level BEOL build-up structure. In such embodiments, multiple micro-bumps or hybrid bonding can be utilized to mount the two discrete logic chips 104 on the wiring layer 136 (interposer). For example, the wiring layer 136 can be a silicon substrate interposer (with through-silicon vias for backside connections) for connection with the logic chips 104.

[0063] Figure 6 A schematic top view and corresponding cross-sectional side view illustration of an extended logic component with 2.5D inter-chip routing and a bridge according to one embodiment is shown. Figure 6 Essentially similar to Figure 5 shown, where a bridge 140 is added within the wiring layer 136 (interposer). For example, the bridge 140 can be a silicon strip with routing layers. In one embodiment, rather than forming the wiring layer 136 from a silicon interposer, the wiring layer can include a dielectric material with dielectric vias and embedded bridge 140. In one embodiment, the bridge 140 can include active silicon, similar to a communication strip. In one embodiment, the bridge 140 is passive.

[0064] Figure 7 A schematic top view and corresponding cross-sectional side view illustration of an extended logic component with a mix of on-die inter-die routing and 2.5D inter-chip routing according to one embodiment is shown. Figure 7 Essentially similar to Figure 5 shown, where some on-die routing 130 is added in conjunction with the wiring layer 136.

[0065] Reference is now made to Figure 8 which provides a schematic top view illustration of various configurations for modular expansion of a logic component with added peripherals according to one embodiment. As shown, various logic chips 104 (or dies 103) can be used, but are not limited to, reference to Figures 4-7Any of the exemplary configurations shown and described extend to have a die-to-die or chip-to-chip interconnect means (shown generally as a thick oval line) including passive and active communication bars. Other network-on-chip (NOC) topologies can also be used. As shown, peripheral can be added as additional chips / dies are connected. In other embodiments, the logic chip 104 is connected with a bond or communication bar 160 as described in further detail herein. Figure 8 Also shown in the middle is the inclusion of additional bond or memory bars 150 that can extend from the logic chip 104. As described in further detail herein, the memory bars 150 can be used to couple the logic chip to additional memory chips 102, thereby further increasing the connection density of the peripheral to the logic chip 104.

[0066] Figure 9 is a schematic top view illustration of an extended logic package connection according to one embodiment. The exemplary illustration provided has four logic chips 104, but this is intended to be exemplary and embodiments are not limited thereto. As shown, each logic chip 104 can be connected. Additionally, the logic chips can have connections to external packages.

[0067] Figure 10A is a schematic top view illustration of a logic package connection overhead according to one embodiment. Figure 10B is a schematic top view illustration of an extended logic package connection overhead according to one embodiment. As shown, each logic chip 104 can include areas reserved for inter-logic chip connections 162 as well as for external I / O connections 164. Alternatively, the connections 162 and 164 can be universal ports. Generally, for high performance, high bandwidth interconnect means can use serializer / deserializer (SerDes) technology and the area and power overhead of these ports can be significant. The area committed on-chip can be greater than the area effectively used on the logic chip 104 in the case of including routing in a multi-chip module (MCM) or PCB. Figures 11A-11B is shown an alternative logic package connection overhead according to one embodiment, where the extended logic package connection overhead has one or more communication bars 160. As shown, each of the logic chips 104 can be fabricated with similar built-in connections 162, 164. In the illustrated embodiment, the total area reserved for the connections 162, 164 can be significantly reduced, thus requiring less overhead in the logic chip 104. Additionally, the bandwidth and power are more scalable. The one or more communication bars 160 can be used to connect multiple logic chips.

[0068] Referring now to Figures 12A-12B , Figure 12A is a schematic top view of a 3D extension of a logic chip with a communication bar 160 according to one embodiment, and Figure 12BA schematic top view of a planar expansion of a logic chip with a connectivity strip 160 according to an embodiment. As shown, the connectivity strip 160 can be used to provide modularity to the logic chip 104 including CPUs, GPUs, caches, signal processors, glue logic, etc., as well as various combinations of SOCs. In Figure 12A In the illustrated embodiment, the connectivity strip 160 can be placed above / below the logic chip 104. In Figure 12B In the illustrated embodiment, the connectivity strip 160 can be placed laterally adjacent to the logic chip 104.

[0069] The connectivity strip 160 according to an embodiment can be used to provide high bandwidth, low power, scalable connectivity between two or more chips. Using the connectivity strip allows I / O terminals to be flexibly positioned on the logic die without having to be at the die / chip edge. In addition, there is flexibility in the start and end point locations. In some embodiments, the connectivity strip 160 can include active silicon blocks and can provide flexibility and design convenience to the logic chip 104.

[0070] Referring now to Figures 13-14 provides a schematic top view illustration of a multi-chip system with expanded logic components and memory according to an embodiment. As shown in each of the figures, the logic chip 104 is electrically connected, optionally, for example, using any of the arrangements of Figures 4-7 In addition, the logic chip 104 can be electrically connected with the connectivity strip 160. The logic chip / die can also be connected with the connectivity strip 160 using a combination of Figures 4-7 Other connectivity strips that complete the "X" connection can be implemented with crossbars or jumpers between them. In addition, the set of memory chips 102 are coupled with the logic chip 104 with a memory strip 150, which can optionally be placed in series to increase memory density. Thus, according to an embodiment, the connectivity organization can be customized, even the bandwidth and latency. In addition, the logic chip 104 does not need to be pre-submitted to provide maximum bandwidth and wiring resources. In particular, Figure 13 The arrangement in Figure 14 The arrangement in Figure 13 Referring again to Figure 18C such long joining strips can be optical interconnects, as described in further detail with reference to

[0071] Figure 15is a schematic cross-sectional side view illustration of a bonded strip metal wiring layer according to an embodiment. As described above, both the communication strip 160 and the memory strip 150 can be more generally characterized as a bonded strip 1500. In the illustrated embodiment, the bonded strip 1500 includes a substrate 1502 and a wiring layer 1510. The substrate 1502 can be formed of a semiconductor material such as silicon to support front-end semiconductor manufacturing of the device. Thus, the silicon substrate 1502 can include active silicon 1504 (or other material) to include features such as logic components, repeaters, flip-flops, caches, memory compressors and decompressors, controllers, local processing elements, etc. If appropriate, other non-silicon technologies such as, but not limited to, GaAs, or even optical interconnect technologies (many of which are supported by silicon) can be used for the substrate 1502. The wiring layer 1510 can include one or more metal layers and dielectric layers. The wiring layer 1510 can be formed using thin film technology or traditional BEOL processing technology such as metal damascene, etc. The wiring layer 1510 can include wiring layers such as a lower wiring layer M A , an intermediate wiring layer M B , a middle wiring layer M C , and an upper wiring layer M D , etc. As shown, the wiring layers can optionally have different thicknesses, where M D is the thickest and M A is the thinnest. In some embodiments, quality of service can be used to organize metal usage based on requirements such as latency, power, etc. In one embodiment, high priority communications with low latency requirements can be on higher (thicker) layers, while bulk communications with greater latency ranges can be in lower (thinner) layers. In one embodiment, longer connections to chips located farther away from the bonded strip 1500 or farther along the longitudinal length of the bonded strip 1500 can be formed with higher (thicker) layers, while shorter connections within the bonded strip 1500 can be formed with lower layers. In some embodiments, the bonded strip 1500 (e.g., the communication strip 160 or the memory strip 150) includes a via (e.g., a through-silicon via) extending through the substrate 1502. For example, the via can be similar to those shown in Figure 18A .

[0072] Referring again to Figures 13-14 , in one embodiment, a multi-chip system includes a first chip (e.g., the logic chip 104), a bonded strip 1500 (e.g., the memory strip 150) coupled with the first chip, and a second chip (e.g., the memory chip 102) coupled with the bonded strip. The bonded strip includes a wiring layer 1510 that optionally extends a substantial portion of the longitudinal length of the bonded strip 1500. Referring back to Figure 11BIn particular, in other embodiments, the wiring layer 1510 can not necessarily extend a substantial portion of the longitudinal length of the bond strip 1500. Thus, such configurations depend on the particular implementation. Still referring to Figures 13-15 The wiring layer 1510 includes a plurality of metal layers including a lower wiring layer (e.g., M A ) and an upper wiring layer (e.g., M D , or M A of the above) characterized by wider wiring than the lower wiring layer. In one embodiment, a second die (e.g., a memory die 102) is electrically coupled to a first die (e.g., the same memory die 102) by a first wire that extends a substantial distance along the longitudinal length in the upper wiring M D A third die (e.g., another memory die 102) can be electrically coupled to the first die (104) by a second wire in the lower wiring layer MA, where the first wire is wider than the second wire and the second die (102) is positioned further from the first die (104) than the third die (102). Thus, the second die can be a second memory die 102 positioned further from the logic die 104 than the first memory die 102, both connected to the logic die 104 by the same memory strip 150.

[0073] According to embodiments, the bond strip 1500 not only serves for wiring, but can also include active silicon. Figure 16 is a schematic top view illustration of an extended system with inter-die wiring according to an embodiment. The particular embodiment shown is similar to the particular embodiment provided in Figure 5 or Figure 7 where a plurality of logic dies 104 are connected together with a wiring layer 136 (or interposer). Each logic die 104 can also include a die-to-die input / output (I / O) region 1602 and an on-die wiring tunnel 1604. The actual die-to-die wiring 1610 is located on the wiring layer 136 (interposer). Thus, each logic die 104 includes a die region for the on-die wiring tunnel 1604, which can include resources such as wires, repeaters, flip-flops, etc. Each logic die 104 (or die) can additionally include a high performance logic region 1607 that can be located in proximity to an adjacent logic die 104. The high performance logic region 1607 can also be partitioned out.

[0074] Figure 17 is a schematic top view illustration of a bond strip wiring according to an embodiment. As shown, the bond strip can be a communication strip 160 that couples a plurality of logic dies 104. The logic dies 104 are connected together with a wiring layer 136 (or interposer). Each logic die 104 can also include a die-to-die input / output (I / O) region 1602 and an on-die wiring tunnel 1604. The actual die-to-die wiring 1610 is located on the wiring layer 136 (interposer). Thus, each logic die 104 includes a die region for the on-die wiring tunnel 1604, which can include resources such as wires, repeaters, flip-flops, etc. Each logic die 104 (or die) can additionally include a high performance logic region 1607 that can be located in proximity to an adjacent logic die 104. The high performance logic region 1607 can also be partitioned out. Figure 16The difference from those shown is that the area previously reserved for on-chip wiring tunnels 1604 can be relocated to the via bars 160 as wiring tunnels 1704. This provides greater flexibility in designing high-performance logic areas 1607. In addition, the die-to-die wiring 1610 is moved to the via bars 160. Therefore, the wiring layer 136 (interposer) can optionally be omitted or supplemented with via bars 160. In one embodiment, the via bars 160 are located in the wiring layer 136, similar to Figure 6 Furthermore, the location of the I / O region 1602 is flexible and the I / O region 1602 does not have to be located at the edge of the die. The vias 160 may optionally include vias for I / O and power / ground connections (see Figure 18A ).

[0075] Figure 18A 18 is a schematic cross-sectional side view and top view diagram of a bonding strip and wiring according to one embodiment. In the specific embodiment shown, the bonding strip can be a connecting strip 160 coupling multiple logic chips 104. As shown, the logic chip 104 and the connecting strip 160 can be connected by multiple solder bumps 105 (including microbumps). The connecting strip 160 may include active devices, such as a deserializer 1812, a serializer 1814, and multiple channels 1820 extending between the deserializer 1812 and the serializer 1814. The channel 1820 can be coupled to an active device 1822, such as a repeater, a trigger, etc. The corresponding logic chip 104 may further include a transceiver 1802 and a receiver 1804. In one embodiment, the bonding strip or connecting strip 160 includes a deserializer 1812, a serializer 1814, and multiple repeaters (e.g., active devices 1822) located between the deserializer and the serializer. Where appropriate, the feedthrough 160 may also support other signaling schemes, such as pulse amplitude modulation (PAM), simultaneous bidirectional (SBD), low-swing differential, and the like. Where appropriate, the feedthrough 160 may support other non-silicon technologies, such as, but not limited to, GaAs. Depending on the embodiment, the feedthrough 160 may provide level conversion capabilities as needed. Additionally, for longer interconnects, optical interconnects may be used as the feedthrough 160. Figure 18Cis a schematic top view illustration of an optical connectivity strip according to an embodiment. For example, connectivity strip 160 can be an optical interconnect device including one or more waveguides 1850 that interface with transmitters / receivers in the first logic chip / die 104 / 103 and transmitters / receivers in the second logic chip. Optical transmitters can be located in electro-optical converter components 1852. The optical transmitters can be of a suitable type such as lasers, light emitting diodes or other light sources, modulators, etc. Optical receivers can be located in opto-electrical converter components 1854. The optical receivers can also be selected based on optical link requirements from a variety of photodetectors (avalanche photodiodes, p-i-n photodiodes, etc.) and conversion electronics. Such optical connectivity strips can be optically dedicated or can be mixed with electrical signaling. For example, depending on requirements, shorter distances can use electrical signaling while longer distances are via optical signaling. In addition, the waveguides can be flexible, allowing for mechanical relief (from mechanical stress) or system integration (non-planar selection), and selection up to longer distances. Such optical connectivity strips can have non-rigid waveguides 1850 (e.g., fiber-like) that allow for mechanical twisting. This flexibility can allow for turning, folding, etc., allowing for more system selection.

[0076] Referring again to Figure 18A , according to embodiments, higher raw data rates can be achieved with deserializer 1812, serializer 1814 structures. According to embodiments, further efficiency can be achieved by providing alternate channels 1820 for selection between deserializer 1812, serializer 1814. In the event of a failure on one channel, the alternate channel can be switched in. For example, the failure can be a hard failure such as a broken or shorted wire, or a soft failure such as an edge wire that causes a voltage rise on all channels compared to other wires in the same link. The alternate channel can be switched in and can result in a lower voltage and thus a recovery of power when the voltage can be reduced.

[0077] Referring now to Figure 18AFIG. 18 is a cross-sectional side view providing a 2.5D package implementation in which a through-bar 160 connects two logic chips 104. As shown, the through-bar 160 is encapsulated in an insulating material 1838 (e.g., molding compound) and wired through a redistribution layer (RDL) 1832. In the illustrated implementation, the logic chips 104 are encapsulated in a molding compound 1840 with the redistribution layer (RDL) 1832 on the front side of the logic chips 104. For example, the RDL 1832 can be formed using thin film processing techniques. The through-bar 160 can be mounted on the RDL 1832 using solder bumps 105 (e.g., micro-bumps) that are optionally encapsulated between the through-bar 160 and the RDL 1832 with an underfill material 1830. An insulating material 1838 is formed over the through-bar 160. The insulating material 1838 can then be optionally planarized, after which a RDL 1834 is formed and solder bumps 105 are placed. In Figure 18A In the middle, only one direction is shown, but the coupling can extend in both directions. Further, the capability in both directions can be the same or different depending on the application.

[0078] Still referring to Figure 18A In some implementations, the 2.5D package structure 1835 can include conductive pillars 1836 extending between the RDLs 1832, 1834. For example, these can be formed in a pillar-first technique in which the conductive pillars 1836 are electroplated, after which the insulating material 1838 is applied, or in a pillar-after technique in which vias are etched into the insulating material 1838, after which the conductive pillars 1836 are deposited or grown. Additionally, the through-bar 160 can also include vias 166 for backside connections to the RDL 1834.

[0079] As a cost saving option, the use of the additional RDL 1832 and insulating material 1838 (e.g., molding compound) can be avoided. In Figure 18B In the illustrated implementation, the through-bar 160 or device can be directly attached to the outside of a wiring layer 1839 (e.g., including multiple RDLs and dielectric layers) on the side of the solder bumps 105 (e.g., ball grid array, BGA side). There can be some tradeoff in pin density. The through-bar 160 can still have the option of TSVs 166 and it connects to the solder bumps 105.

[0080] According to implementations, the through-bar 160 can be passive or include active silicon. Additionally, the use of the through-bar 160 can form a short connection length (e.g., in the range of the solder bump 105 size) between the through-bar 160 and the wiring in the logic chips 104, which can reduce the voltage requirements for power gain. Additionally, simple coding can be used to increase the effective bandwidth of the connection.

[0081] While Figure 18AThe illustrated embodiment is specific to a 2.5D packaging structure 1835, but the embodiments are not so limited and can be extended to other packaging solutions, such as CoWs, which can have higher signal densities. For example, the logic chips 104 and the interconnect bar 160 can be implemented into various CoW structures for the logic chip 104 connections. Figures 5-7

[0082] In some aspects, various cost control implementations can be included. For example, logic components can be moved from the logic chips 104 to the interconnect bar 160 to reduce the cost of the logic chips 104. Additionally, the interconnect bar can include discrete extension segment areas, tapered structures, or hammerhead structures to reduce silicon costs. Figure 19 is a schematic top view illustration of an interconnect bar having a hammerhead shape, according to one embodiment. As illustrated, the interconnect bar can be an interconnect bar 160 connecting multiple logic chips 104. As described above, the interconnect bar 160 can have a chip-to-chip connection 162 area that is reserved for interfacing with the logic chip 104 die-to-die input / output (I / O) area 1602. This area can be larger than the area needed for routing or repositioning logic components. In one embodiment, the interconnect bar includes a head component 170 and an extension segment 172 extending along the longitudinal length of the interconnect bar 160, where the head component 170 is wider than the extension segment 172. For example, the extension segment 172 can include repeaters or the like. In this way, the amount of silicon cost can be reduced. In other embodiments, the extension segment 172 is passive, rather than active.

[0083] Figure 20 is a schematic top view illustration of an interconnect bar including repositioned die logic components, according to one embodiment. In one aspect, one logic component on an active logic chip 104 can add area, and it can be difficult to provide redundancy for such logic components, particularly for active logic chips 104 such as SOCs, as compared to array elements such as GPUs, which can be more easily provided with spares having area efficiency. According to embodiments, a portion of such logic components 2010 can be repositioned to the interconnect bar 160, where space can be available. This can improve the efficiency of the logic chips 104. By way of example, the logic components 2010 can include non-I / O intensive or ultra-high power random logic components (e.g., glue logic components). In another implementation, a necessary logic component remains as one component on the main logic area of the first logic die, while the additional logic components needed for a second component (e.g., a spare) can be moved to the interconnect bar. In other embodiments, duplicate logic components remain in the main logic chip 104. However, the logic components needed once or a few times (not every operational instance of the logic chip 104) can be moved to the interconnect bar 160. Alternatively, such logic components can be separate but connected using the interconnect bar 160. ​

[0084] Figure 21 is a schematic top view illustration of a bond strip active area according to one embodiment. According to some embodiments, the bond strip or interconnect strip 160 can include a head component 170 for supporting a chip-to-chip connector and solder bumps 105 (e.g., micro bumps), as well as an extension segment 172. In some embodiments, these can be integral components or discrete components. In one embodiment, the head component 170 and the extension segment 172 are encapsulated in an insulating material 174. Alternatively, Figure 21 The area shown in the middle as insulating material 174 can be inactive silicon. In some embodiments, additional cost savings can be realized by dividing the active silicon area of the extension segment into discrete active components 176. Figure 22 is a schematic top view and corresponding cross-sectional side view illustration of a bond strip having multiple discrete active components 176 according to one embodiment. Such a configuration can provide lower cost (by reducing the active silicon area), scalable bandwidth strip without changing the silicon (by increasing the width of the components 176 and re-integrating into a wider strip), lower power (by selecting the appropriate technology and voltage, and possible merged process corner components), improved power noise (by including decoupling capacitors in the strip). In one embodiment, the bond strip or interconnect strip 160 includes one or more discrete head components 170 and one or more discrete active components 176 (e.g., active silicon dielets), where the discrete head components 170 and the one or more discrete active components 176 are electrically coupled with a wiring layer 180. In this regard, the active silicon area can be significantly reduced. By way of example, the components 176 can be simple repeaters, retimers, or other more complex structures such as crossbars. Additionally, the interconnect strip can be dual ported, point-to-point, or have several ports.

[0085] The discrete head components 170 and the one or more discrete active components 176 can be (encapsulated) in an insulating layer 174. Various encapsulation methods can be used to form the interconnect strip 160, including CoW, 2.5D packaging. The discrete head components 170 and the discrete active components 176 can be bonded to the wiring layer 180, for example, with micro bumps (not shown), or alternatively, the wiring layer 180 can be formed over the encapsulated discrete head components 170 and the discrete active components 176.

[0086] To this point, the interconnect bar has been generally described, and several specific examples have been given with reference to the interconnect bar 160. It should be understood that many of the concepts apply equally to both the memory bar 150 and the interconnect bar 160, although there can be some differences due to functionality. For example, the interconnect bar 160 can be passive, or active, with the primary activity being repeaters. Other areas can be less densely used, and thus employ several cost saving implementations, although cost saving implementations can also apply to the memory bar 150. Another difference can be that the memory bar 150 can support physical interfaces (PHYs) / controllers that require space. In addition, the memory bar 150 can also include a lower cache, and upper wiring. Thus, by comparison, the memory bar 150 silicon can be used efficiently. The memory bar 150 can also include additional functionality, such as memory compressors and decompressors, reliability enhancements such as chip hunting, controllers for non-volatile memory as a memory extension, and local processing elements close to the memory.

[0087] Figure 23 is a schematic top view illustration of an extended system 100 including a memory bar bridge 190, according to one embodiment. In an example embodiment, the system includes multiple chips and bars supported by a substrate 120, such as glass, silicon, an interposer, etc. The system includes a first logic die 103 coupled with a second logic die 103, a first set of laterally separated memory chips 102 connected with the first logic die 103, and a second set of memory chips 102 connected with the second logic die 103. As described with reference to Figures 4-7 , the logic dies 103 can be formed from the same piece of silicon, or contained in separate logic chips 104. In one embodiment, the first logic die 103 and the second logic die 103 share the same layer of silicon, and are interconnected with on-die wiring 130, similar to that described with reference to Figure 4 . In one embodiment, the first logic die 103 and the second logic die 103 are separate chips, and are connected with a shared wiring layer 136 (or interposer). For example, the shared wiring layer 136 can include a silicon bridge 140 connecting the first logic die and the second logic die. The silicon bridge can be passive, or contain active silicon. In one embodiment, the first logic die and the second logic die are logic chips 104 and are connected with an interconnect bar 160. For example, the interconnect bar can include a deserializer 1812, a serializer 1814, and a plurality of repeaters (active devices 1822) between the deserializer and the serializer. The interconnect bar 160 can be a packaged component. In one embodiment, the interconnect bar 160 includes a discrete active component 176 (also covering a discrete active section 172) and a discrete head component 170 packaged in an insulating layer 174, and a wiring layer 180 connecting the discrete active component 176 and the discrete head component 170.

[0088] According to embodiments, scalable systems are described in which the logic chip 104 perimeter to memory chip 102 is increased. Additionally, these systems are scalable with high bandwidth, low latency, and with power and cost optimization. The logic chip 104 perimeter can be extended not only by connecting multiple logic chips 104, but also with memory strip 105 for peripheral extension. In Figure 23 In the illustrated embodiment, some memory chips 102 can be routed directly to the logic chip 104 with wiring 121. The storage capacity can also be extended with memory strip 150 and additional memory chips 102 routed to the memory strip 150 with wiring 123. The memory strip 150 can also be extended using a high density bridge 190, which can be similar to a silicon picocell with a wiring layer.

[0089] It should be appreciated that while the above description is made with reference to memory chips 102, it should be appreciated that this term includes configurations with stacked memory dies and memory packages. Thus, embodiments can be compatible with a variety of memories, such as but not limited to LPDDR-x, HBM, HMC, etc.

[0090] The memory strip 150 according to embodiments can support a physical interface (PHY) / controller that requires space with the logic die 104. In addition, the memory strip 150 can also include a lower level cache and an upper level wiring. The memory strip 150 can also include additional functionality, such as memory compressors and decompressors, devices for reliability enhancement such as chip hunting, controllers for non-volatile memory as a memory extension, and local processing elements close to the memory. According to embodiments, the connectivity strip 150 can provide level conversion capability as needed.

[0091] In one particular embodiment, the memory strip 150 can include error correcting code (ECC) to enhance reliability, availability, and serviceability (RAS). In particular, the ECC can correct memory chip 102 errors due to soft errors, such as electrical or magnetic interference, that cause a single bit of dynamic random access memory (DRAM) to spontaneously flip to the opposite state. In contrast, conventional LPDDR-x memory systems can not include ECC on the external I / O. The memory strip 150 according to embodiments can store ECC data, which can be combined with the main data from the DRAM (e.g., memory chip 102). A parity check or cyclic redundancy check (CRC) of the data can also be stored on the memory strip 150. These can help to detect errors. Upon an error, the data can be re-requested from the memory. In one embodiment, some memory can be protected with ECC (e.g., operating system, critical software), while other memory is protected with parity or CRC.

[0092] According to embodiments, the system can include wiring 123 to an expansion area of miscellaneous components 2400, as shown. Figure 24 Miscellaneous components 2400 can be expanded to a variety of miscellaneous components 2400, such as spare memory, alternative memory expansion, and spare die or variable retention time (VRT) support. In one embodiment, miscellaneous components 2400 are spare memory chips 102 or packages for efficiency and RAS. A spare rank (or channel) group can be provided in the active logic die 104 and memory strip 150 to provide full redundancy of memory chips 102 or packages. In such an embodiment, the system can be tested after assembly to check for failed dies, chips, packages. If a particular memory die or rank (or channel) is detected, a replacement can be populated. Alternatively, a complete memory chip 102 or package can be added. Additionally, the spare components can be initially populated during assembly. The spare components are activated and logged during testing. The controller then maps the failed devices / chips and maps the spare components to the failed devices / chips.

[0093] In one embodiment, miscellaneous components 2400 are spare dies to assist in VRT checking. Thus, the spare dies can be used to detect potential DRAM errors and take appropriate action. In such an embodiment, application data is located in the spare dies. The empty memory chips 102 (DRAM) are VRT tested and possibly flagged so that the device can be isolated, repaired, or partially empty. Alternatively, the memory chips 102 being tested are kept cool to assist in maintaining retention time, margin.

[0094] In one embodiment, miscellaneous component 2400 is an alternative memory component for memory extension. For example, the alternative memory component can be a non-volatile memory (NVM), such as but not limited to flash memory and phase change memory (PCM). Memory strip 150 can include an interface / logic component to support NVM, which can provide a significant increase in capacity for uses such as program code storage, static storage, etc. In addition, NVM can be less expensive, but also slower and less reliable. In one embodiment, NVM can have a strict write or read occurrence rate (such as once per day) or wear limit. In one embodiment, the NVM can provide a fast checkpoint service (under operating system / software control). Upon being prompted, all memory contents can be extracted and stored into NVM. Another use can be for search engine extended memory (where reads are prioritized over writes), where less information can be held here. However, long memory sleds can have longer latency and use more power. However, average latency and power can be relevant for many applications. In addition, software or logic on the memory strip (or controller) can allocate memory such that, in general, frequently used memory lines / pages / blocks can be closer to the logic chip (e.g., SOC), while less frequently used lines are farther away.

[0095] According to embodiments, various cost control solutions can be implemented into the bonded strip or memory strip 150 design. Figures 25-26 is a schematic top view illustration of a bonded strip with different form factors according to embodiments. Figure 25 is similar to the previously described and illustrated hammerhead memory strip 150 for Figure 19 is an illustration of a hammerhead memory strip 150 similar to the previously described and illustrated bonded strip 160 in Figure 26 is an illustration of a tapered memory strip 150 design that can save silicon cost. In this configuration, the width of the extended segment 172 decreases along the longitudinal length. This can be reasonable since the number of interfaces, lanes / channels, and logic components required for the memory chips 102 to be maintained along the longitudinal length is reduced. In one embodiment, the wiring layer 1510 (see Figure 15 ) includes at least a lower wiring layer M A and an upper wiring layer M D . The wiring layer 1510 can extend a substantial portion of the longitudinal length of the memory strip. As illustrated, the wiring layers can optionally have different thicknesses, where M D is the thickest and M Ais the thinnest. The memory chip 102 farthest from the active logic chip 104 can be electrically coupled to the active chip by first conductive lines in the upper wiring layer M D that extend a substantial distance along the longitudinal length, while chips 102 located closer to the active logic chip 104 can be electrically coupled to the active chip by second conductive lines in the lower wiring layer M A .

[0096] Figure 27 is a schematic top view and cross-sectional side view illustration of a bond strip having discrete active regions and head regions, according to one embodiment. According to some embodiments, the bond strip or memory strip 150 can include head components 170 for supporting PHY connections, hybrid bonding, anisotropic conductive film (ACF), high-density intermetallic bonding (CoW), or other high-density attachment with logic chips 104 and solder bumps 105 (e.g., micro bumps), as well as an extension segment 172. In some embodiments, these can be integral components or discrete components. In one embodiment, the head components 170 and the extension segment 172 are encapsulated in an insulating material 174. Alternatively, Figure 27 the regions shown as insulating material 174 in Figure 30 may be inactive silicon. The head components 170 can be coupled with the logic chips 104 by wiring 129, which can optionally be on the substrate 120. In a similar configuration, as shown and described with reference to ,

[0097] Various packaging methods can be used to form the memory strip 150, including CoW, 2.5D packaging. The discrete head components 170 and the discrete extension segment 172 can be bonded to the wiring layer 180, for example, with micro bumps (not shown), hybrid bonding, anisotropic conductive film (ACF), high-density intermetallic bonding (CoW), or other high-density attachment, or alternatively, the wiring layer 180 can be formed over the encapsulated discrete head components 170 and discrete active components 176.

[0098] Referring now to Figure 28 , Figure 22The wiring layer 180 can be a 2.5D package structure 2835 that includes high-density bridge 200 and optionally one or more high-density bridges 190. As shown, the head component 170 and one or more active regions 172 are encapsulated in an insulating material 174 (e.g., molding compound) and optionally wired with a redistribution layer (RDL) 2832. In the particular implementation shown, the high-density bridges 200, 190 are encapsulated in an insulating material 2838, with an optional redistribution layer (RDL) 2832 connecting the head component 170, the extended sections 172, and the high-density bridges 200, 190. The RDL 2832 can be formed, for example, using thin-film processing techniques. The high-density bridges 200, 190 can be mounted on the RDL 2832 using suitable techniques such as, but not limited to, solder bumps 105 (e.g., micro-bumps) that are optionally encapsulated between the high-density bridges 200, 190 and the RDL 2832 with an underfill material 2830. An insulating material 2838 is formed over the communication strip 160. The insulating material 1838 can then be optionally planarized, after which an optional RDL 2834 is formed and solder bumps 105 are placed.

[0099] Still referring to Figure 28 In some implementations, the 2.5D package structure 2835 can include conductive pillars 2836 extending between the RDLs 2832, 2834. These can be formed, for example, in a pillar-first technique in which the conductive pillars 2836 are electroplated, after which the insulating material 2838 is applied, or in a pillar-after technique in which vias are etched into the insulating material 2838, after which the conductive pillars 2836 are deposited or grown. Although Figure 28 The implementation shown is specific to a 2.5D package structure 2835, but the implementation is not limited as such and can be extended to other packaging solutions such as CoW. In addition, the high-density bridges 200, 190 can also support through-silicon vias.

[0100] Multi-chip systems according to implementations can be assembled with various packaging solutions. Referring briefly back to Figures 2-3 The system 100 can include a multi-chip module (MCM) with a glass core substrate 120 CTE that matches silicon, for example, to keep the mismatch to the logic chips 104 and memory chips 102 in the composite topology small, and to allow fine-pitch flip-chip integration, to allow thinner cores of the substrate 120, and to reduce the overall z-height. In addition, the flex circuit 112 to the board 106 can reduce the z-height by reducing or eliminating the height caused by ball grid array (BGA) attachment. BGA attachment thermal temperature is also avoided, as is warpage associated with BGA. The stiffener 122 can also improve warpage at low temperatures and warpage associated with handling.

[0101] Now see Figures 29A-29B , which provides schematic top view and cross-sectional side view illustrations of an expanded system with bridges connecting a logic chip to a memory bank, according to one embodiment. As shown, the system may include a substrate 120, such as an MCM substrate. For example, substrate 120 may optionally include a core 2910 (e.g., a glass core), a top wiring layer 125, an optional bottom wiring layer 127, and optional vias 124 extending between top wiring layer 125 and bottom wiring layer 127. Substrate 120 may be formed from a variety of materials, such as, but not limited to, glass, silicon, an interposer, a matching metal stabilization substrate, and the like. Core 2910 may be formed from a variety of materials, such as, but not limited to, a glass core, a metal core, and the like. As shown, bridge 2900 (e.g., a localized high-density bridge) may be located within wiring layer 125, with logic chip 104 and memory bank 150 mounted on wiring layer 125 (e.g., using a flip chip and solder bumps), and bridge 2900 may electrically couple logic chip 104 and memory bank 150. This can be a direct coupling, and / or coupling using additional wiring in the wiring layer 125. Such a configuration can be used to improve the connectivity (e.g., bandwidth, power complexity) of the substrate 120. Figure 29A As shown, the memory bank 150 can couple a plurality of memory chips 102 mounted on a wiring layer 125 and electrically coupled to the memory bank 150 via wiring 123 in the wiring layer 125. In one embodiment, the bridge 2900 (e.g., a high-density bridge) includes an active component. For example, the bridge can include active silicon.

[0102] Figure 30 is a schematic top view illustration of an expanded system 100 having substrate wiring 129 in wiring layer 125 connecting logic chip 104 to memory bank 150 according to one embodiment. Thus, wiring on substrate 120 is used to electrically connect to memory bank 150, which is similar to Figures 29A-29B The bridge member 2900 is different. Figure 30 As shown, the logic chip 104 and the memory bar 150 are mounted on the wiring layer 125 (for example, using flip chips and solder bumps) and are electrically coupled via wiring 129 in the wiring layer 125. Similarly, multiple memory chips 102 can be mounted on the wiring layer 125 and electrically coupled to the memory bar 150 via wiring 123 in the wiring layer 125. The specific embodiment shown may involve a 2.5D package of the memory bar 150, but this can also be manufactured using a CoW-like attachment. For example, the microbumps used to attach the memory bar 150 can be replaced by a hybrid bond that can be denser. The dielectric used for the hybrid bond can be oxide-based. Examples similar to Figure 12A CoW-like attachments can also optionally support hammerhead or cone-shaped structures.

[0103] In particular, Figure 30 The illustrated memory strip 150 can be formed using a 2.5D packaging configuration similar to that described with reference to Figure 27 The illustrated and described 2.5D packaging configuration includes a head component 170, an extension segment 172, and a high-density bridge 200. Notably, the components can be arranged in an L-shaped configuration, which can increase the logic die 104 perimeter, improve the packaging density of the memory chips 102, and thus reduce the cost of the memory strip 150. Further, the vertically oriented head component 170 increases the area between the logic die 104 edge and the head component 170, which can allow for more wiring 129 conductors and higher bandwidth to be integrated.

[0104] Referring now to Figures 31A-31C illustrates various 2.5D package-on-package (PoP) configurations for an extended system. Figure 31A is a schematic top view of a PoP extended system according to one embodiment, while Figures 31B-31C is a cross-sectional side view illustration of different implementations taken along Figure 31A the illustrated wiring (arrows). In particular, Figure 31B The illustrated embodiments can be used in place of or in conjunction with the substrate 120. Figure 31C The illustrated embodiments can be used in conjunction with the substrate 120. Referring in particular to Figures 31A-31B , the system 100 includes a lower RDL 3102, a first molding layer 3110 on the lower RDL 3102, and a memory strip 150 packaged in the first molding layer 3110. A second RDL 3124 can be formed over the packaged memory strip 150 and the first molding layer 3110. In one embodiment, the memory strip 150 is a flip chip bonded to the second RDL 3124 with solder bumps 105. A second molding layer 3120 is over the second RDL 3124 and the first molding layer 3110, and a logic chip 104 can be packaged in the second molding layer 3120. A plurality of vias 3112 can connect the lower RDL 3102 and the second RDL 3124. Additionally, a second plurality of vias 3122 can be formed through the second molding layer 3120. In the illustrated embodiment, a plurality of memory chips 102 are mounted on top of the second molding layer 3120. The plurality of memory chips 102 can be electrically coupled to the logic chip 104 through the memory strip 150 and the plurality of vias 3122. As described herein, the memory chips 102 can be single memory devices, stacks, or modules.

[0105] Referring now to Figure 31A and Figure 31CIn one embodiment, the system includes a memory strip 150 encapsulated in a first molding layer 3210. The logic chip 104 and the plurality of memory chips 102 are all mounted on top of a second molding layer. For example, they can be connected with the memory strip 150 and optionally an RDL formed on the first molding layer 3210. A bottom RDL can also be optionally formed under the first molding layer 3120 and the encapsulated memory strip 150. The package structure can be bonded to the substrate 120, for example, using flip chip and solder bumps 105. As Figure 31C shown, in such a configuration, the heights of the logic chip 104 and the memory chips 102 are not cumulative, which can facilitate a low z-height package configuration.

[0106] According to embodiments, a junction strip 1500, such as the communication strip 160 and the memory strip 150, can be combined to form an extended memory system and can be packaged with the configurations previously described and shown. For example, referring again to Figures 13-14 In one embodiment, the memory system includes a first logic chip 104, a second logic chip 104, and a communication strip 160 coupling the first logic chip 104 and the second logic chip 104. A first memory strip 150 is coupled with the first logic chip 104 and a second memory strip 150 is coupled with the second logic chip 104. A first set of laterally separated memory chips 102 is coupled with the first memory strip 150 and a second set of laterally separated memory chips 102 is coupled with the second memory strip 150.

[0107] The memory strips can also be bridged. For example, referring again to Figure 23 The system can additionally include a third memory strip 150 and a third set of laterally separated memory chips 102 coupled with the third memory strip 150. Further, a bridge 190 couples the second memory strip 150 to the third memory strip 150. In other configurations, such as shown in Figure 28 The memory strip 150 can include a plurality of extension segments 172 coupled with one or more bridges 190.

[0108] According to embodiments, the first and second logic chips 104 and the first and second sets of laterally separated memory chips 102 can be mounted on a substrate 120. While shown herein as rectangular, it should be understood that the substrate can have any suitable shape. As shown in Figures 2-3 The substrate 120 can be coupled with the board 106 using a flexible circuit 112. As described herein, the communication strip 160 and the memory strip 150 can be independently packaged or packaged with the system. In particular embodiments, such as shown in Figures 29A-29B and Figure 30 The first and second memory strips 150 are mounted on the substrate 120. In other embodiments, such as shown inFigures 31B-31C As shown in the 2.5D-PoP structure described in FIG. 2, the first memory strip 150 and the second memory strip 150 are encapsulated in a first molding layer, the first logic chip 104 and the second logic chip 104 are mounted on top of the first molding layer, and the first set and the second set of laterally separated memory chips 102 are mounted on top of the first molding layer 3120, and the first set and the second set of laterally separated memory chips 102 are mounted on top of the first molding layer.

[0109] Figure 32A is a schematic top view illustration of a 3D extended system according to an embodiment. Figure 32B is a schematic cross-sectional side view illustration taken along line B-B of Figure 32A As shown, the semi-flexible circuit 3200, which includes a base portion 3210 (e.g., a base plate) and one or more side portions 3212 (e.g., side plates) can be connected by flexible connections 3214 that provide a horizontal to vertical transition. The base portion 3210 can be mounted on the substrate 120 using suitable techniques such as, but not limited to, micro-bumps. The memory chips 102 can be mounted on one or both sides of the side portions 3212 (as shown). Such a 3D arrangement can significantly increase memory capacity, with some associated z-height to the system. In other embodiments, a more rigid 3D structure can be used, for example, similar to a dual in-line memory module (DIMM) with pin connections, sockets, etc. In some embodiments, the flexible connections 3214 can be further folded so that the memory chips (devices) 102 are now parallel to the substrate 120, and the memory chips (devices) 102 are now stacked on the base portion 310. This configuration can help control z-height, which in turn increases memory capacity.

[0110] In the above description, various multi-chip system 100 configurations were described in which a large substrate 120 can be effectively CTE matched with multiple chips, modules, strips mounted on or assembled within the substrate 120. These configurations can provide mechanical reliability. Such a substrate 120 can additionally be used to provide a basis for mechanical handling and heat dissipation solutions attachment.

[0111] In such large systems, cooling can be an important factor. Cooling plates, two-phase (e.g., heat pipes), liquid cooling, loop heat pipes, and microchannels are possible options. Other options can be considered, including immersion in a liquid such as mineral oil, custom hydrocarbon, or others. Further, the liquid can be cooled, as the storage capacity can be high, and the cooling solution can be scaled to cover it.

[0112] Exemplary substrates 120 may be glass core, organic, metal stabilized core (such as copper-invar-copper or molybdenum (CTE matched and with higher Young's modulus) substrates), or CTE matched glass or organic materials. Such large substrates 120 may be mechanically coupled or weakly coupled to other substrates such as board 106 through sockets, soft solder, flex circuits, etc. Such CTE matched substrates 120 may also reduce the thickness of the system, thereby keeping the z-height small. Mechanical stiffeners 122 may also be strategically added to the surface of the larger substrate 120 to increase stiffness for mechanical handling capabilities and reduce warping. The stiffeners 122 may be metal, package substrate core, or other high elastic modulus material with an appropriate CTE.

[0113] When utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible to form an expandable system. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features and acts disclosed should be understood as exemplary embodiments of the claims.

Claims

1. A stacked package structure: Lower redistribution layer RDL; a first molding layer on the lower RDL; a bonding strip encapsulated in the first molding layer; a second RDL, the second RDL being over the first molding layer; a first chip on top of the second RDL; a package comprising a plurality of stacked chips on top of the second RDL; wherein the first chip is a logic chip, and the plurality of stacked chips are a plurality of stacked memory chips; as well as A second molding compound layer is on the second RDL. 2 . The package-on-package structure of claim 1 , further comprising a plurality of through-vias extending through the first mold layer connecting the lower RDL and the second RDL. 3 . The package-on-package structure according to claim 1 , wherein the first chip is encapsulated in the second molding compound layer. 4 . The package-on-package structure of claim 3 , further comprising a second plurality of through-vias extending through the second molding compound layer and connected to the second RDL. The package-on-package structure of claim 4 , wherein the package is bonded to the second plurality of through-vias. 6 . The package-on-package structure of claim 1 , wherein the bond bar comprises a wiring layer extending a substantial portion of a longitudinal length of the bond bar.

7. The package-on-package structure according to claim 6, wherein: The wiring layers of the bonding strip include a plurality of metal layers including a first wiring layer and a second wiring layer characterized by wider wiring than the first wiring layer.

8. The package-on-package structure according to claim 7 , wherein: a first memory chip of the plurality of stacked memory chips electrically coupled to the logic chip through a first conductive line in the first wiring layer; and A second memory chip among the plurality of stacked memory chips is electrically coupled to the logic chip through a second conductive line in the second wiring layer.

9. The package-on-package structure according to claim 8, wherein: And the second memory chip is farther away from the logic chip than the first memory chip. 10 . The package stacking structure according to claim 9 , wherein the first wiring layer is a lower wiring layer, and the second wiring layer is an upper wiring layer. The package-on-package structure according to claim 1 , wherein the bonding bar comprises a cache memory. 12 . The package-on-package structure according to claim 11 , wherein the plurality of stacked memory chips are a plurality of stacked dynamic random access memory (DRAM) chips. 13 . The package-on-package structure of claim 1 , further comprising a plurality of solder bumps on a bottom side of the lower RDL. The package-on-package structure according to claim 1 , wherein the bonding bar comprises a plurality of repeaters. 15 . The package-on-package structure of claim 14 , wherein the plurality of repeaters are arranged along a longitudinal length of the bonding bar.

16. The stacked packaging structure of claim 14, wherein the bonding strip comprises a wiring layer extending along a substantial portion of the longitudinal length of the bonding strip, wherein the wiring layer of the bonding strip comprises a plurality of metal layers, the plurality of metal layers comprising a lower wiring layer and an upper wiring layer, the upper wiring layer being characterized by a wider wiring than the lower wiring layer. The package-on-package structure of claim 1 , wherein the bonding bar comprises a local processing element.

18. The package-on-package structure of claim 1, wherein logic in the bonding strip is used to allocate memory such that memory blocks with higher usage frequencies in the package are closer to the logic chip, while memory blocks with lower usage frequencies in the package are farther away.

19. The package-on-package structure of claim 1, wherein the bond bars include channel wiring between the logic chip and the package and a memory controller for controlling a plurality of stacked memory chips of the package.

20. The stacked package structure of claim 19, wherein the bonding strip is coupled to a first input / output region along a first chip edge of the logic chip and to a second input / output region located inside edges of the plurality of stacked memory chips of the package. The package-on-package structure according to claim 19 , wherein the bonding stripe comprises an error correction code. 22 . The package-on-package structure of claim 19 , wherein the bonding bar comprises a memory compressor. 23 . The package-on-package structure of claim 19 , wherein the bonding bar comprises a memory decompressor. 24 . The package-on-package structure according to claim 19 , wherein the bonding bar comprises chip hunting logic. The package-on-package structure according to claim 19 , wherein the bonding bar comprises a cache memory. The package-on-package structure according to claim 19 , wherein the bonding bar has a level conversion capability. The package-on-package structure according to claim 19 , wherein the bonding bar comprises a physical interface (PHY) controller. The package-on-package structure of claim 27 , wherein the PHY controller comprises an analog controller. 29 . The package-on-package structure of claim 27 , wherein the PHY controller comprises a digital controller. 30 . The package-on-package structure of claim 19 , further comprising a second package comprising a second plurality of second stacked memory chips on top of a second RDL, wherein the bond bar is electrically connected to the second package. The package-on-package structure according to claim 19 , wherein the bonding strip comprises a spare channel wiring.

32. The package-on-package structure of claim 19, further comprising a nonvolatile memory die on top of the second RDL, wherein the bond bar is electrically connected to the nonvolatile memory die.

33. A multi-chip system, comprising: First Chip; Second chip; a bonding bar coupled to the first chip and the second chip, the bonding bar comprising: electro-optical converter components; a photoelectric converter component; and One or more waveguides extending between the electro-optical converter component and the opto-electrical converter component.

34. The multi-chip system according to claim 33 further includes a third chip, which is coupled to the bonding strip along the longitudinal length of the bonding strip, wherein the second chip is coupled to the bonding strip along the longitudinal length of the bonding strip farther away from the first chip than the third chip.

35. The multi-chip system of claim 34, wherein the bond strip comprises a wiring layer comprising one or more metal wiring layers. 36 . The multi-chip system according to claim 35 , wherein the first chip and the third chip are electrically connected through the one or more metal wiring layers.

37. The multi-chip system of claim 33, further comprising a wiring layer between the bond bar and the first and second chips.

38. The multi-chip system of claim 37, wherein the first chip and the second chip are embedded in a molding compound layer.

39. The multi-chip system of claim 38, wherein the bond bar is bonded to the wiring layer using a plurality of solder bumps.

40. The multi-chip system of claim 38, wherein the plurality of solder bumps are microbumps.

41. The multi-chip system of claim 33, wherein the bonding bar is embedded in a 2.5D packaging structure.

42. The multi-chip system of claim 41, wherein the bonding bar is laterally adjacent to a plurality of conductive pillars in the 2.5D package structure. 43 . The multi-chip system according to claim 42 , wherein the 2.5D package structure comprises a top redistribution layer (RDL), a bottom RDL, and an insulating material between the top RDL and the bottom RDL, wherein the bonding bar is embedded in the insulating material.

44. The multi-chip system of claim 43, wherein the bond bar is bonded to the top RDL using a plurality of solder bumps.

45. The multi-chip system of claim 44, wherein the plurality of solder bumps are microbumps.

46. ​​The multi-chip system of claim 33, wherein the bonding strip is coupled to a first input / output region along a first chip edge of the first chip and to a second input / output region inside a chip edge of the second chip.

47. The multi-chip system according to claim 33, wherein the first chip is a first logic chip.

48. The multi-chip system of claim 47, wherein the second chip is a memory chip.

49. The multi-chip system according to claim 47, wherein the second chip is a second logic chip.

50. The multi-chip system according to claim 33, wherein the first chip and the second chip are both memory chips.

51. The multi-chip system according to claim 33, further comprising: a third chip coupled to the bonding strip along a longitudinal length of the bonding strip, wherein the second chip is coupled to the bonding strip further away from the first chip along the longitudinal length of the bonding strip than the third chip; as well as A second bonding bar is coupled to the first chip and the third chip, the second bonding bar including inter-die wiring that electrically connects the first chip and the third chip within one or more metal wiring layers of the second bonding bar.

52. The multi-chip system of claim 51, wherein the bonding strips are flexible.

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