Packaging structure and forming method of packaging structure

Abstract

According to the packaging structure and the forming method of the packaging structure, an electric function chip in the packaging structure is used for electronic signal processing, an optical chip can achieve big data throughput, a storage chip can achieve data storage, and when a second packaging body works, signals can be led out from the electric function chip, so that the second packaging body works. And photoelectric conversion and high-speed optical transmission are carried out through the optical chip, and data are stored by the storage chip, so that big data throughput can be realized. Therefore, the formed second packaging body can realize integration of multiple functions of electronic signal processing, optical signal transmission, data storage and the like, the function density and the integration level of the whole packaging are improved, the requirements of high bandwidth, large-capacity storage and rapid data processing are met, and the performance of the packaging structure is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a method for forming the packaging structure. Background Art

[0002] Packaging technology improves system integration, performance density and interconnection efficiency by integrating chips with different functions into a single package.

[0003] In the field of advanced packaging technology, 2.5D packaging technology integrates different functional chips, such as processors and memory, within a single package structure, enabling the package structure to realize complete system functions. While achieving efficient chip interconnection, 2.5D packaging technology reduces the interconnect length between chips and improves interconnection efficiency. This allows the integration of multifunctional chips within a limited space, effectively improving system integration and performance density.

[0004] However, with the continuous improvement of the integration of 2.5D packaging technology, especially in the face of the growing demand for big data throughput, traditional interconnection methods based on electrical signal transmission have gradually exposed bandwidth bottlenecks and power consumption limitations. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a method for forming the packaging structure, so as to realize the integration of multiple functions such as electronic signal processing, optical signal transmission and data storage.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a packaging structure, including: providing an optical chip and an electrical function chip, wherein the optical chip includes an optical coupling region; providing a first carrier board, bonding the optical chip and the electrical function chip to the first carrier board to form a first package body; providing a second carrier board and a storage chip, bonding the first package body and the storage chip to the second carrier board to form a second package body; providing a substrate, bonding the second package body to the substrate; after bonding the second package body to the substrate, coupling an optical fiber to the optical coupling region of the optical chip in the second package body.

[0007] Optionally, in the step of bonding the optical chip and the electrical function chip on the first carrier board, the optical coupling region is located on the side of the optical chip that is not close to the electrical function chip; in the step of coupling the optical fiber to the optical coupling region of the optical chip in the second package, the optical coupling region is located on the side wall of the optical chip, and the optical fiber is connected to the optical coupling region on the side wall of the optical chip.

[0008] Optionally, in the step of providing the optical chip, the optical coupling region is exposed on a side wall of the optical chip.

[0009] Optionally, in the step of bonding the first package body and the memory chip to the second carrier, the optical coupling region of the optical chip is located on a side not close to the memory chip.

[0010] Optionally, in the step of providing the optical chip, the optical coupling region of the optical chip is used to perform optical coupling in a direction parallel to a main plane of the optical chip.

[0011] Optionally, the step of forming the second package body further includes: forming a second plastic packaging layer covering the first package body and the side wall of the memory chip on the second carrier; the method for forming the package structure further includes: removing the second plastic packaging layer covering the optical coupling area.

[0012] Optionally, in the step of providing the optical chip, the optical coupling region is located inside the optical chip; and in the step of removing the second plastic packaging layer covering the optical coupling region, part of the material of the optical chip is also removed to expose the optical coupling region.

[0013] Optionally, in the step of bonding the first package body and the memory chip to the second carrier, the optical coupling area of ​​the optical chip is located on a side that is not close to the memory chip; the step of removing the second plastic packaging layer covering the optical coupling area includes: removing the second plastic packaging layer on the side of the optical chip having the optical coupling area.

[0014] Optionally, the step of forming the first package body includes: after bonding the optical chip and the electrical function chip to the first carrier board, forming a third electrical connection bump on the first side of the optical chip and the electrical function chip; after forming the third electrical connection bump, forming a first plastic packaging layer covering the optical chip and the electrical function chip on the first carrier board, the first plastic packaging layer exposing the top of the third electrical connection bump; forming a fourth electrical connection bump on the third electrical connection bump exposed by the first plastic packaging layer; in the step of bonding the first package body and the storage chip to the second carrier board, the optical chip and the electrical function chip are connected to the second carrier board through the fourth electrical connection bump.

[0015] Optionally, in the step of forming the second plastic sealing layer, the second plastic sealing layer also covers the first plastic sealing layer; in the step of removing the second plastic sealing layer covering the optical coupling area, the first plastic sealing layer covering the optical coupling area is also removed.

[0016] Optionally, the step of forming the second package body includes: after bonding the first package body and the memory chip to the second carrier board, forming a second electrical connection bump on the side of the second carrier board facing away from the first package body; in the step of bonding the second package body to the substrate, the second package body is connected to the substrate through the second electrical connection bump.

[0017] Optionally, the step of forming the second package body includes: in the step of forming a second plastic encapsulation layer covering the first package body and the side wall of the memory chip on the second carrier, the second plastic encapsulation layer is exposed on a side of the first carrier facing away from the second carrier.

[0018] Optionally, the step of forming a second plastic encapsulation layer covering the first package body and the side wall of the memory chip on the second carrier includes: forming a second plastic encapsulation material layer covering the first package body and the memory chip on the second carrier; removing the second plastic encapsulation material layer higher than the first carrier, and the remaining second plastic encapsulation material layer serves as the second plastic encapsulation layer.

[0019] Optionally, in the step of providing the optical chip, the optical chip includes a first side and a second side opposite to the first side, and a silicon through-hole is formed on the first side; the method for forming the packaging structure also includes: after providing the optical chip, before bonding the optical chip to the first carrier, thinning the second side of the optical chip to expose the end of the silicon through-hole; in the step of bonding the optical chip to the first carrier, bonding the second side of the optical chip to the first carrier.

[0020] Optionally, in the step of providing the optical chip, the optical coupling region is formed on the first side.

[0021] Optionally, the step of bonding the optical chip to the first carrier board includes adopting hybrid bonding.

[0022] Optionally, in the step of providing the electrical function chip, the electrical function chip includes a signal layer, a bonding layer and a power supply layer stacked in sequence; the step of bonding the electrical function chip to the first carrier includes: bonding the signal layer surface of the electrical function chip to the first carrier.

[0023] Optionally, the step of forming the first package body also includes: after bonding the optical chip and the electrical function chip to the first carrier board, forming a first electrical connection bump on the first side of the optical chip and the electrical function chip; in the step of bonding the first package body and the storage chip to the second carrier board, the optical chip and the electrical function chip are connected to the second carrier board through the first electrical connection bump.

[0024] An embodiment of the present invention also provides a packaging structure, comprising: a substrate; a second packaging body formed on the substrate, the second packaging body comprising: a second carrier board and a first packaging body and a storage chip bonded to the second carrier board; the first packaging body comprising: a first carrier board and an optical chip and an electrical function chip bonded to the first carrier board, the optical chip comprising an exposed optical coupling area; and an optical fiber coupled to the optical coupling area of ​​the optical chip.

[0025] Optionally, the optical coupling region is located on a side wall of the optical chip that is not close to the electrical function chip, and the optical fiber is connected to the optical coupling region on the side wall of the optical chip.

[0026] Optionally, the optical chip includes a first side and a second side opposite to the first side, and the optical coupling region is located on the first side; the second side of the optical chip is bonded to the first carrier board.

[0027] Optionally, the optical coupling region of the optical chip is used to perform optical coupling in a direction parallel to a main plane of the optical chip.

[0028] Optionally, the optical coupling region of the optical chip is located on a side not close to the memory chip.

[0029] Optionally, the second package body further includes: a second plastic packaging layer covering the first package body and the side wall of the memory chip on the second carrier board, and the second plastic packaging layer exposes the optical coupling area.

[0030] Optionally, the second plastic packaging layer exposes a side of the first carrier board facing away from the second carrier board, and a side of the memory chip facing away from the second carrier board.

[0031] Optionally, the first package body also includes: a third electrical connection bump, located on the first side of the optical chip and the electrical function chip; a first plastic packaging layer, located on the first carrier, covering the side walls of the optical chip and the electrical function chip, and exposing the end of the third electrical connection bump; a fourth electrical connection bump, located on the third electrical connection bump exposed by the first plastic packaging layer, and the optical chip and the electrical function chip are connected to the second carrier through the fourth electrical connection bump.

[0032] Optionally, the second plastic sealing layer also covers the first plastic sealing layer; the first plastic sealing layer and the second plastic sealing layer expose the optical coupling area.

[0033] Optionally, the optical chip includes a first side and a second side opposite to the first side, and the optical chip includes a through silicon via passing through the first side and the second side.

[0034] Optionally, hybrid bonding is performed between the optical chip and the first carrier board.

[0035] Optionally, the electrical function chip includes a signal layer, a bonding layer, and a power supply layer stacked in sequence, and the signal layer of the electrical function chip is bonded to the first carrier board.

[0036] Optionally, the first package body further includes: a first electrical connection bump located on the first side of the optical chip and on the power supply layer of the electrical function chip, and the optical chip and the electrical function chip are connected to the second carrier board through the first electrical connection bump.

[0037] Optionally, the second package body includes: a second electrical connection bump located on a side of the second carrier away from the first package body, and the second package body is connected to the substrate via the second electrical connection bump.

[0038] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0039] The method for forming a packaging structure provided by an embodiment of the present invention first bonds an optical chip and an electrical chip to a first carrier to form a first package, then bonds the first package and a memory chip to a second carrier to form a second package, then bonds the second package to a substrate, and finally couples an optical fiber to the optical coupling region of the optical chip in the second package. This multi-level formation method enables orderly packaging of optical chips, electrical chips, and memory chips. First, the optical chip and the electrical chip are formed on the first carrier to encapsulate the optical chip and the electrical chip into a first package; second, a second carrier and a memory chip are provided, and the first package containing the optical chip and the electrical chip and the memory chip are bonded to the second carrier to form a second package, thereby integrating the optoelectronic processing unit and the data storage unit onto a common platform. High-speed data exchange and collaborative operation between the first package and the memory chip are then achieved through interconnection on the second carrier. Because the electrical chip processes electronic signals, the optical chip enables high-volume data throughput, and the memory chip stores data, when the second package is operating, signals can be extracted from the electrical chip, converted to photoelectricity, and transmitted at high speeds through the optical chip, with the data then stored by the memory chip, enabling high-volume data throughput. The resulting second package integrates multiple functions, including electronic signal processing, optical signal transmission, and data storage. This improves the overall package's functional density and integration, meeting the demands for high bandwidth, large-capacity storage, and rapid data processing, and ultimately enhancing the performance of the package structure.

[0040] The packaging structure provided by an embodiment of the present invention includes: a substrate; a second package body formed on the substrate, the second package body including: a second carrier board, and the first package body and the memory chip bonded to the second carrier board; the first package body including: a first carrier board, and an optical chip and the electrical chip bonded to the first carrier board, the optical chip including an optical coupling region, the electrical chip being used for electronic signal processing; an optical fiber coupled to the optical coupling region of the optical chip. The optical chip and the electrical chip are located on the first carrier board, thereby packaging the optical chip and the electrical chip into the first package body; the first package body and the memory chip are located on the second carrier board, forming the second package body, and the optical fiber is coupled to the optical coupling region of the optical chip. Because the electrical function chip is used for electronic signal processing, the optical chip can achieve big data throughput, and the storage chip can achieve data storage, when the second package body is working, the signal can be drawn out from the electrical function chip and subjected to photoelectric conversion and high-speed optical transmission through the optical chip. The data is stored in the storage chip, which can achieve big data throughput. The second package body thus formed can realize the integration of multiple functions such as electronic signal processing, optical signal transmission and data storage, which is conducive to improving the functional density and integration of the overall package, meeting the needs of high bandwidth, large-capacity storage and fast data processing, and is conducive to improving the performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flow chart of key steps of a first embodiment of a method for forming a packaging structure of the present invention;

[0042] Figures 2 to 7 2 is a schematic structural diagram corresponding to the key steps in the first embodiment of the method for forming a packaging structure of the present invention;

[0043] Figures 8 to 15 2 is a schematic structural diagram corresponding to the key steps in the second embodiment of the method for forming a packaging structure of the present invention;

[0044] Figures 16 to 18 It is a structural schematic diagram corresponding to the key steps in the third embodiment of the method for forming a packaging structure of the present invention. DETAILED DESCRIPTION

[0045] As can be seen from the background technology, with the continuous improvement of the integration of 2.5D packaging technology, especially in the face of the growing demand for big data throughput, traditional interconnection methods based on electrical signal transmission have gradually exposed bandwidth bottlenecks and power consumption limitations.

[0046] To address the aforementioned technical issues, an embodiment of the present invention provides a method for forming a packaging structure. The method involves first bonding an optical chip and an electrical chip to a first carrier to form a first package, then bonding the first package and a memory chip to a second carrier to form a second package, then bonding the second package to a substrate, and finally coupling an optical fiber to the optical coupling region of the optical chip in the second package. This multi-level formation method enables orderly packaging of optical chips, electrical chips, and memory chips. First, the optical chip and the electrical chip are formed on a first carrier to package the optical chip and the electrical chip into a first package. Second, a second carrier and a memory chip are provided, and the first package containing the optical chip and the electrical chip and the memory chip are bonded to the second carrier to form a second package. This integrates the optoelectronic processing unit and the data storage unit onto a common platform, enabling high-speed data exchange and collaborative operation between the first package and the memory chip through interconnection on the second carrier. Because the electrical chip processes electronic signals, the optical chip enables high-volume data throughput, and the memory chip stores data, when the second package is operating, signals can be extracted from the electrical chip, converted to photoelectricity, and transmitted at high speeds through the optical chip, with the data then stored by the memory chip, enabling high-volume data throughput. The resulting second package integrates multiple functions, including electronic signal processing, optical signal transmission, and data storage. This improves the overall package's functional density and integration, meeting the demands for high bandwidth, large-capacity storage, and rapid data processing, and ultimately enhancing the performance of the package structure.

[0047] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Correspondingly, the present invention also provides a method for forming a packaging structure. Figure 1 is a flow chart of key steps of a first embodiment of a method for forming a packaging structure of the present invention; Figures 2 to 7 2 is a schematic structural diagram corresponding to the key steps in the first embodiment of the method for forming a packaging structure of the present invention;

[0049] Combine Figure 1 ,refer to Figure 2 and Figure 3 , providing an optical chip 100a and an electrical function chip 200a, wherein the optical chip 100a includes an optical coupling region 101a.

[0050] The optical chip 100a includes an optical coupling region 101a for realizing the input and output of optical signals, and the electrical function chip 200a is used for electronic signal processing, thereby laying the device foundation for subsequent photoelectric signal conversion, high-speed data transmission and complex logical operations, thereby enabling the subsequently formed packaging structure to have both optical domain communication capabilities and electrical domain computing and control capabilities, enabling the subsequently formed packaging structure to achieve high-bandwidth, low-latency data exchange, which is conducive to meeting large data throughput requirements.

[0051] In this embodiment, in the step of providing the optical chip 100 a , the optical coupling region 101 a is located on the sidewall of the optical chip 100 a , and the optical coupling region 101 a is exposed on the sidewall of the optical chip 100 a .

[0052] In the step of providing the optical chip 100a, the optical coupling region 101a is set on the side wall of the optical chip 100a, which clarifies the specific positions of the optical signal input and output ports, simplifies the alignment and connection process between the optical fiber and the optical coupling region 101a, and enables the optical signal to efficiently enter and exit from the side of the optical chip 100a, thereby reducing the height of the packaging structure formed subsequently.

[0053] It should be noted that, in the step of providing the optical chip 100a, the optical coupling region 101a of the optical chip 100a is used to perform optical coupling in a direction X parallel to the main plane of the optical chip 100a, that is, horizontal light output is adopted, which can avoid the vertical optical path conversion components required when a vertical optical path is adopted, thereby simplifying the optical path design and the complexity of packaging integration.

[0054] It should also be noted that the optical chip 100a does not rely on built-in reflective structures to achieve optical path redirection. In other words, the optical chip 100a directly outputs light from the end face or directly outputs the optical signal to the sidewall optical coupling region 101a via a waveguide. This simplifies the internal structure of the optical chip 100a, making the optical signal path more direct and correspondingly reducing the cost of the optical chip 100a.

[0055] As an example, the optical chip 100a includes a photonic integrated circuit (PIC), which is mainly responsible for functions such as generation, modulation, transmission and reception of optical signals.

[0056] In this embodiment, in the step of providing the optical chip 100a, the optical chip 100a includes a first side 103a and a second side 104a opposite to the first side 103a, and a through silicon via (TSV) 105a is formed on the first side 103 extending toward the second side.

[0057] The optical chip 100a includes a first side 103a and a second side 104a opposite to the first side 103a, and a through-silicon via 105a is formed in a direction extending from the first side 103a toward the second side, providing a vertical electrical signal transmission path for the optical chip 100a, thereby achieving electrical connectivity between the first side 103a and the second side 104a of the chip. This allows the optical chip 100a to perform optical functions on the first side 103a while also being electrically connected to an external circuit on a subsequent first carrier through its second side 104a.

[0058] Specifically, a plurality of first pads 106a are formed on the surface of the first side 103a of the optical chip 100a. The photonic components and waveguide structure 102a, as well as the through-silicon vias 105a, are located below the first pads 106a and are electrically connected to corresponding first pads 106a. The photonic components and waveguide structure 102a, as well as the through-silicon vias 105a, are disposed below the first pads 106a and can serve as electrical connection points for the photonic components, waveguide structure 102a, and through-silicon vias 105a.

[0059] In this embodiment, in the normal direction of the top surface of the optical chip 100a, the photonic component and the waveguide structure 102a are close to the first side 103a of the optical chip 100, and the optical coupling region 101a is connected to the photonic component and the waveguide structure 102a.

[0060] The first side 103a of the optical chip 100a is formed with photonic components (such as light sources, modulators, detectors, etc.) and a waveguide structure 102a, and the optical coupling region 101a is connected to the photonic components and the waveguide structure 102a, so that optical signals can be generated, transmitted, processed inside the optical chip 100a, and coupled with the outside through the optical coupling region 101a. The processed optical signals can be effectively guided to the optical coupling region 101a, so that the external optical fiber can be effectively optically connected to the photonic components and the waveguide structure 102a inside the chip through the optical coupling region 101a, which is conducive to achieving efficient optical signal input and output.

[0061] It should be noted that the optical coupling region 101a is the end portion of the photonic component and the waveguide structure 102a exposed on the side wall of the optical chip 100a, so that the optical fiber subsequently coupled on the optical coupling region 101a can be effectively optically connected to the photonic component and the waveguide structure 102a inside the chip through the optical coupling region 101a.

[0062] In this embodiment, in the step of providing the electrical function chip 200a, the electrical function chip 200a includes a logic chip structure with telecom separation. Specifically, the electrical function chip 200a includes a signal layer 201a, a bonding layer 202a, and a power layer 203a stacked in sequence. In other words, the signal layer 201a and the power layer 203a are respectively located on either side of the bonding layer 202a, reducing crosstalk and noise coupling between the signal layer 201a and the power layer 203a. While improving signal integrity, it also reduces the impedance of the power supply network of the power layer 203a.

[0063] In this embodiment, the electrical function chip 200a is a back-powered chip, that is, the power input of the electrical function chip 200a is realized through the back of the chip, thereby separating the power distribution network (PDN) and the signal network in the vertical direction of the chip, thereby freeing up more space for the signal wiring layer on the front of the electrical function chip 200a, allowing a denser transistor layout and a more optimized signal path design, thereby significantly reducing the resistance and inductance of the power network, improving power supply efficiency and voltage stability, and improving signal integrity.

[0064] As an example, the electrical function chip 200a includes an integrated electronic circuit (EIC) chip, which is mainly responsible for processing and calculating electronic signals.

[0065] Combine Figure 1 ,refer to Figure 4 and Figure 5 , provide a first carrier board 300a, bond the optical chip 100a and the electrical function chip 200a on the first carrier board 300a to form a first package body 10a.

[0066] A first carrier board 300a is provided, and the optical chip 100a and the electrical chip 200a are bonded thereto to form a first package body 10a. This allows the two heterogeneous chips, the optical chip 100a and the electrical chip 200a, to function as a preliminary integrated unit, ensuring a precise relative positional relationship between the optical chip 100a and the electrical chip 200a, paving the way for subsequent bonding of the optical chip 100a and the electrical chip 200a to a second carrier board. Furthermore, the first carrier board 300a provides mechanical support and protection for the electrical chip 200a and the optical chip 100a, effectively preventing warping, cracking, or damage that might occur due to insufficient rigidity of the optical chip 100a and the electrical chip 200a during subsequent packaging steps, thereby improving the yield and reliability of the package structure.

[0067] It should be noted that during the step of bonding the optical chip 100a and the electrical chip 200a to the first carrier 300a, the optical coupling region 101a is located on a side of the optical chip 100a that is not adjacent to the electrical chip 200a. Specifically, the optical coupling region 101a is located on a side of the optical chip 100a that is not adjacent to the electrical chip 200a. That is, except for the side of the optical chip 100a that is adjacent to the electrical chip 200a, the optical coupling region 101a can be located on any of the remaining three sides of the optical chip 100a. Therefore, the location of the optical coupling region 101a on the side of the optical chip 100a that is not adjacent to the electrical chip 200a helps increase the process space for coupling the optical fiber to the optical coupling region 101a in subsequent processes.

[0068] In this embodiment, the first substrate 300a comprises a silicon substrate, which can integrate a high-density redistribution layer (RDL), passive components, and through-silicon vias 105a (TSVs). In other embodiments, the first substrate can also comprise a silicon germanium substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0069] It should be noted that the surface of the first carrier 300a has an interconnection structure and a second pad 112a for achieving metal bonding with the optical chip 100a and the electrical function chip 200a.

[0070] In this embodiment, the step of bonding the electrical function chip 200a to the first carrier 300a includes: bonding the surface of the signal layer 201a of the electrical function chip 200a to the first carrier 300a.

[0071] The surface of the signal layer 201a of the electrical function chip 200a is bonded to the first carrier board 300a, that is, the signal layer 201a is the electrical connection and mechanical connection interface between the electrical function chip 200a and the first carrier board 300a, so that the signal input and output ports of the signal layer 201a in the electrical function chip 200a can be connected to the corresponding second pads 112a (which can also be an interconnection structure) on the first carrier board 300a, thereby realizing the transmission of electrical signals between the electrical function chip 200a and the first carrier board 300a, providing a basis for the functional realization of the electrical function chip 200a and the communication between the electrical function chip 200a and the optical core through the first carrier board 300a.

[0072] In this embodiment, the thickness of the electrical function chip 200a is less than 50 μm. The thickness of the electrical function chip 200a is less than 50 μm, which is beneficial to improving the integration of the subsequent packaging structure.

[0073] In this embodiment, the method for forming the packaging structure further includes: after providing the optical chip 100a, before bonding the optical chip 100a to the first carrier 300a, thinning the second side 104a of the optical chip 100a to expose the through silicon via 105a.

[0074] Before bonding the optical chip 100a to the first carrier 300a, the second side 104a of the optical chip 100a is thinned to expose the through-silicon via 105a. That is, the through-silicon via 105a passes through the first side 103a and the second side 104a. This is a pre-processing step to achieve electrical connection between the optical chip 100a and the first carrier 300a through the second side 104a. By removing excess material from the second side 104a of the optical chip 100a, the endpoints of the through-silicon via 105a inside the optical chip 100a are exposed, thereby providing a connection between the optical chip 100a and the first carrier. The hybrid bonding between 300a provides a contact surface. In order to facilitate the subsequent connection of the optical chip 100a and the electrical function chip 200a with the second carrier board, the thickness of the optical chip 100a after thinning is the same as that of the electrical function chip 200a. Of course, the thickness of the optical chip 100a after thinning may also be different from that of the electrical function chip 200a. When the thickness of the optical chip 100a after thinning is different from that of the electrical function chip 200a, when subsequently connected to the second carrier board, the optical chip 100a and the electrical function chip 200a must use first electrical connection bumps of different adaptive sizes.

[0075] In this embodiment, in the step of bonding the optical chip 100 a to the first carrier 300 a , the second side 104 a of the optical chip 100 a is bonded to the first carrier 300 a .

[0076] The second side 104a of the optical chip 100a is bonded to the first carrier 300a, that is, the side of the optical chip 100a opposite to the photonic component and the through-silicon via 105a is bonded to the first carrier 300a, so that the through-silicon via 105a exposed on the second side 104a of the optical chip 100a can be electrically connected to the first carrier 300a, and the optical coupling region 101a on the first side 103a of the optical chip 100a is farther away from the first carrier 300a, thereby reducing the coupling between the subsequent optical fiber and the optical coupling region 101a. The difficulty of the optical chip 100a is reduced, so that the electrical signal of the optical chip 100a can be transmitted from the first side 103a to the second side 104a through the through silicon via 105a, and then communicated with the interconnection structure on the first carrier 300a through the bonding interface between the second side 104a and the first carrier 300a, forming a key link in the electrical signal transmission path of the optical chip 100a, so that the optical coupling area 101a of the optical chip 100a can be optical fiber coupled, thereby improving the alignment accuracy and connection reliability of the optical fiber coupling, and facilitating the improvement of the quality of the packaging structure.

[0077] In this embodiment, the step of bonding the optical chip 100a to the first carrier board 300a includes adopting hybrid bonding.

[0078] Hybrid bonding technology is employed between the optical chip 100a and the first carrier 300a. This technology utilizes a combination of dielectric bonding and metal bonding to achieve a secure connection between the two substrates. Direct bonding between dielectrics creates a high-strength mechanical connection, while bonding between metals (e.g., the first pads 106a on the optical chip 100a and the second pads 112a on the first carrier, as well as the interconnect structure) enables high-density electrical interconnection, thereby increasing interconnect density. Hybrid bonding enables finer pitch connections, which improves signal transmission rate and power transmission efficiency.

[0079] Accordingly, the step of bonding the electrical function chip 200 a to the first carrier board 300 a includes adopting hybrid bonding.

[0080] Hybrid bonding is used between the electrical function chip 200a and the first carrier 300a, which is conducive to forming a high-density, low-resistance electrical path and firm mechanical fixation between the surface of the signal layer 201a of the electrical function chip 200a and the first carrier 300a, thereby improving the rate and integrity of signal transmission and the efficiency of power distribution, preparing for subsequent integration with the optical chip 100a or the memory chip 500, and facilitating the realization of a high-performance, highly integrated 2.5D packaging structure.

[0081] refer to Figure 5 The step of forming the first package body 10a also includes: after bonding the optical chip 100a and the electrical function chip 200a to the first carrier board 300a, forming a first electrical connection bump 107a on the first side 103a of the optical chip 100a and the electrical function chip 200a.

[0082] In the step of forming the first package body 10a, after the optical chip 100a and the electrical function chip 200a are bonded to the first carrier 300a, first electrical connection bumps 107a are formed on the first side 103a of the optical chip 100a and the electrical function chip 200a, so as to facilitate the subsequent electrical connection of the optical chip 100a and the electrical function chip 200a with the second carrier, thereby realizing signal transmission between the optical chip 100a and the electrical function chip 200a and the second carrier. In other words, the first package body 10a can be connected to the second carrier through the first electrical connection bumps 107a, which is the key to realizing vertical electrical interconnection in multi-level packaging. In the subsequent process, the first package body 10a can be integrated into a larger packaging structure as a functional module, which is conducive to building a high-density, high-performance 2.5D packaging structure.

[0083] Specifically, the first electrical connection bumps 107a are formed on the power supply layer 203a of the electrical function chip 200a and on the first pads 106a of the photonic component and waveguide component 102a.

[0084] The first electrical connection bump 107a is formed on the power supply layer 203a of the electrical function chip 200a and on the pad 106a of the photonic component and waveguide component 102a on the first side 103a of the optical chip 100a. In other words, the first electrical connection bump 107a is an electrical node for the first package body 10a to be connected to the outside, so that the power supply of the electrical function chip 200a can be introduced from the second carrier board 400 through the first electrical connection bump 107a, and the photoelectric signal processed by the optical chip 100a or the bias / control signal required for its operation can be transmitted through its first electrical connection bump 107a. The first electrical connection bump 107a on the first solder pad 106a of the side 103a is exchanged with the second carrier board 400, thereby providing a physical connection point for the stable power supply of the electrical function chip 200a and the signal transmission / control of the optical chip 100a. Therefore, the path of the electrical signal is optimized, so that power and signals can be transmitted through the shortest path, so that the first package body 10a can efficiently obtain power from the second carrier board 400 and exchange data with it, which is conducive to ensuring signal integrity, reducing power consumption, and achieving subsequent reliable electrical connection with the second carrier board 400.

[0085] As an example, the first electrical connection bumps 107a include solder balls.

[0086] It should be noted that the optical chip 100a needs to be sealed with the electrical function chip 200a. The difference in the manufacturing processes of the two requires cutting from different wafers, which promotes the use of 2.5D packaging to solve the problem of co-packaged optics (CPO). Specifically, if the optical chip 100a wafer is directly used as a silicon interposer in a 2.5D package, the area of ​​the optical chip will be greatly wasted, and its wafer size or material will be incompatible with the current mainstream advanced packaging production line equipment and process flow based on 12-inch silicon wafer specifications. To overcome this obstacle, the embodiment of the present invention first cuts the optical chip 100a manufactured on the wafer. Subsequently, the optical chip 100a and the silicon-based electrical function chip 200a cut from the 12-inch wafer are heterogeneously integrated on the first carrier 300a. By pre-integrating the optical chip 100a and the electrical chip 200a on the first substrate 300a, the subsequent 2.5D packaging process can be performed on 12-inch silicon-based equipment and process lines. This eliminates the need to modify or adapt existing packaging lines to process optical wafers, significantly reducing manufacturing costs. Furthermore, by leveraging the mature 12-inch silicon-based process platform, the overall packaging process stability and production efficiency are improved.

[0087] Combine Figure 1 ,refer to Figure 6 , provide a second carrier board 400a and a memory chip 500a, and bond the first package body 10a and the memory chip 500a to the second carrier board 400a to form a second package body 20a.

[0088] A second carrier board 400a and a memory chip 500a are provided, and the first package 10a including the optical chip 100a and the electrical function chip 200a and the memory chip 500a are bonded to the second carrier board 400a to form a second package 20a, thereby integrating the optoelectronic processing unit and the data storage unit onto a common platform, and then realizing high-speed data exchange and collaborative work between the first package 10a and the memory chip 500a through the interconnection on the second carrier board 400a. Because the electrical function chip 200a is used for electronic signal processing, the optical chip 100a can realize large-scale data processing. Data throughput, the memory chip 500a can realize data storage. When the second package body 20a is working, the signal can be drawn out from the electrical function chip 200a and undergo photoelectric conversion and high-speed optical transmission through the optical chip 100a. The data is stored in the memory chip 500a, which can realize large data throughput. The second package body 20a thus formed can realize the integration of multiple functions such as electronic signal processing, optical signal transmission and data storage, which is conducive to improving the functional density and integration of the overall package, meeting the needs of high bandwidth, large-capacity storage and fast data processing, and is conducive to improving the performance of the packaging structure.

[0089] It should be noted that, in the step of bonding the first package body 10a and the memory chip 500a to the second carrier 400a, the optical coupling region 101a is located on the side of the optical chip 100a that is not close to the electrical function chip 200a.

[0090] The optical coupling region 101a is located on a side of the optical chip 100a that is not close to the memory chip 500a. Specifically, when the first package body 10a and the memory chip 500a are bonded to the second carrier board 400a, the optical coupling region 101a of the optical chip 100a does not face the memory chip 500a, thereby reserving a convenient interface path for the subsequent coupling of the optical fiber and the optical coupling region 101a of the optical chip 100a, simplifying the alignment and connection of the optical fiber and the optical coupling region 101a, and facilitating the efficiency and quality of optical signal transmission. This enables the optical chip 100a to effectively perform its photoelectric conversion and high-speed optical transmission functions to meet the needs of large data throughput, thereby improving the functional density and integration of the overall package, meeting the needs of high bandwidth, large-capacity storage and fast data processing, and improving the performance of the package structure.

[0091] Specifically, the first package body 10 a and the memory chip 500 a are bonded on the second carrier 400 a through a flip-chip process.

[0092] In this embodiment, the second carrier board 400a is a photonic interposer. While performing electrical interconnection functions, the second carrier board 400a can also transmit optical signals. The second carrier board 400a provides mechanical support and electrical connections for the first package 10a and the memory chip 500a, facilitating interaction between the optical chip 100a, the electrical chip 200a, and the memory chip 500a. This allows for the conversion, processing, storage, and transmission of optical and electrical signals to be completed within the second package 20a.

[0093] In this embodiment, in the step of bonding the first package body 10a and the memory chip 500a to the second carrier 400a, the optical chip 100a and the electrical function chip 200a are connected to the second carrier 400a via the first electrical connection bumps 107a.

[0094] In the step of bonding the first package body 10a and the memory chip 500a to the second carrier board 400a, the optical chip 100a and the electrical function chip 200a in the first package body 10a are connected to the second carrier board 400a through the first electrical connection bumps 107a, thereby achieving electrical interconnection between the first package body 10a and the memory chip 500a and the second carrier board 400a.

[0095] As an example, the second carrier board 400a has a third solder pad (not shown in the figure) corresponding to the optical chip 100a, the electrical function chip 200a and the memory chip 500a. By connecting the first electrical connection bump 107a on the optical chip 100a, the electrical function chip 200a and the memory chip 500a with the third solder pad on the second carrier board 400, a stable and reliable electrical signal transmission path can be established, so that control signals and data signals can be transmitted between the optical chip 100a, the electrical function chip 200a and the memory chip 500a and the second carrier board 400a, which is conducive to ensuring that the second package body 20a can work normally.

[0096] In this embodiment, the memory chip 500a is a high-bandwidth memory chip, for example, a high-bandwidth memory (HBM) chip.

[0097] It should be noted that the optical chip 100a is used for optical communication, the back-powered electrical function chip 200a is used for efficient electrical signal processing, and the memory chip 500a is used to provide high-speed data cache, which is used to realize high-speed transmission and reception of optical signals, complex calculations of electrical signals and rapid access to data in the final packaging structure. This is conducive to the packaging structure being able to realize the requirements of big data throughput for high-bandwidth optical interconnection and powerful computing and storage capabilities, and optimizes the integration method and optical path design between chips, so that the 2.5D packaging can support demanding high-performance computing and communication applications while taking into account process feasibility and structural stability.

[0098] In this embodiment, the step of forming the second package body 20a includes: bonding the first package body 10a and the memory chip 500a to the second carrier 400a, and then forming second electrical connection bumps 401a on a side of the second carrier 400a away from the first package body 10a and the memory chip 500.

[0099] By forming a second electrical connection bump 401a on the side of the second carrier 400a away from the first package body 10a and the memory chip 500a, preparation is made for the subsequent electrical connection between the optical chip 100a, the electrical function chip 200a and the memory chip 500a in the second package body 20a and the substrate. In other words, the second electrical connection bump 401a is the structural basis for the electrical connection between the second package body 20a and the substrate.

[0100] Combine Figure 1 ,refer to Figure 7 , providing a substrate 600a, and bonding the second package body 20a to the substrate 600a.

[0101] The second package body 20a is bonded to the substrate 600a, providing an interface for external connection for the optical chip 100a, the electrical function chip 200a and the memory chip 500a in the second package body 20a. Therefore, while carrying the second package body 20a, the substrate 600a also generally includes wiring and interface structures for signal fan-out, power distribution and connection with other parts of the system, so that the second package body 20a can be conveniently integrated into a larger electronic system.

[0102] Specifically, the second package body 20a is bonded on the substrate 600a through a flip-chip process.

[0103] In this embodiment, the material of the substrate 600a includes silicon. In other embodiments, the material of the substrate may also include silicon carbide, germanium, or a III-V compound semiconductor substrate.

[0104] In this embodiment, in the step of bonding the second package body 20 a to the substrate 600 a , the second package body 20 a is connected to the substrate 600 through the second electrical connection bumps 401 a .

[0105] In the step of bonding the second package body 20a to the substrate 600a, the second package body 20a is connected to the substrate 600a through the second electrical connection bumps 401a pre-formed at the bottom of the second carrier 400a, completing the electrical connection and mechanical fixation between the second package body 20a and the substrate 600a.

[0106] In this embodiment, after the second package body 20a is bonded to the substrate 600a, an optical fiber 111a is coupled to the optical coupling region 101a of the optical chip 100a in the second package body 20a.

[0107] After the second package body 20a is bonded to the substrate 600a, the optical fiber 111a is coupled to the optical coupling region 101a of the optical chip 100a in the second package body 20a, which is beneficial to improving the coupling accuracy between the optical fiber 111a and the optical coupling region 101a, and is beneficial to ensuring that the optical signal can be efficiently and stably input or output from the optical chip 100a, so that the packaging structure can meet the requirements of high bandwidth, large-capacity storage and fast data processing, and is beneficial to improving the performance of the packaging structure.

[0108] Specifically, in the step of coupling the optical fiber 111a to the optical coupling region 101a of the optical chip 100a in the second package 20a, the optical coupling region 101a is located on the side wall of the optical chip 100a, and the optical fiber 111a is connected to the optical coupling region 101a on the side wall of the optical chip 100a.

[0109] In the step of coupling the optical fiber 111a to the optical coupling area 101a of the optical chip 100a in the second package body 20a, the specific docking position of the optical fiber 111a is clarified by connecting the optical fiber 111a to the optical coupling area 101a on the side wall of the optical chip 100a, thereby utilizing the horizontal light emitting characteristics of the side wall of the optical chip 100a to achieve end-face docking of the optical fiber 111a with the chip optical port, thereby simplifying the optical path design, eliminating the need for additional beam steering elements, reducing alignment difficulty and potential optical losses, and enabling the external optical fiber 111a to be accurately connected to the optical coupling area 101a of the optical chip 100a, which is beneficial to improving the performance of the packaging structure.

[0110] In this embodiment, in the step of coupling the optical fiber 111 a to the optical coupling region 101 a of the optical chip 100 a in the second package 20 a , the optical fiber 111 a is welded to the optical coupling region 101 a using a welding process.

[0111] The optical fiber 111a is fixed to the optical coupling region 101a through a welding process, so that the optical fiber 111a is stably connected to the optical coupling region 101a, reducing the problem of displacement of the optical fiber 111a and reduction in coupling efficiency due to environmental factors such as vibration or temperature changes, which is conducive to improving the quality of the packaging structure.

[0112] As an example, the optical fiber 111 a is welded to the optical coupling region 101 a using a laser welding process.

[0113] It should also be noted that the method for forming the packaging structure further includes: after coupling light on the optical coupling region 101a of the optical chip 100a in the second package body 20a, forming substrate bumps 601a on the side of the substrate 600a away from the second package body 20a.

[0114] The substrate bumps 601a facilitate connecting the structure in the second package body 20a with the external structure, thereby achieving electrical connection and mechanical fixation.

[0115] refer to Figures 8 to 16 , the embodiment of the present invention further provides a second embodiment. The similarities between the second embodiment and the first embodiment are not repeated here, and the differences are:

[0116] In this embodiment, the steps of forming the first package body 10b include: bonding the optical chip 100b and the electrical function chip 200b to the first carrier 300b, and forming third electrical connection bumps 108b (such as 108b) on the first side 103b of the optical chip 100b and the electrical function chip 200b. Figure 8 shown).

[0117] After the optical chip 100b and the electrical function chip 200b are bonded to the first carrier 300b, a third electrical connection bump 108b is formed on the first side 103b of the optical chip 100b and the electrical function chip 200b to prepare for the signal output, power input or ground connection of the optical chip 100b and the electrical function chip 200b; in addition, in the subsequent process of forming the first plastic encapsulation layer 110b, grinding is required. The third electrical connection bump 108b serves as the grinding stop position for forming the first plastic encapsulation layer 110b. By exposing the third electrical connection bump 108b, it is connected to the subsequent second carrier, which is beneficial to improving the stability and flexibility of the packaging structure.

[0118] It should be noted that, in the step of providing the optical chip 100b, the optical coupling region 101b is located inside the optical chip, that is, the photonic components and waveguide components 103b in the optical chip 100b are completely inside the chip 100b.

[0119] It should be noted that in the step of providing the electrical function chip 200b, the electrical function chip 200b includes a signal layer 201b, a bonding layer 202b, and a power layer 203b stacked in sequence; and the third electrical connection bump 108b is formed on the power layer 203b of the electrical function chip 200b. The third electrical connection bump 108b is formed on the power layer 203b of the electrical function chip 200b and is a structure for connecting the electrical function chip 200b to the outside world.

[0120] Specifically, the third electrical connection bumps 108b are formed on the power supply layer 203b of the electrical function chip 200b and on the first pads 106b of the photonic component and waveguide component 102b on the first side 103b of the optical chip 100b.

[0121] As an example, the third electrical connection bump 108b is a copper column. In other embodiments, the third electrical connection bump can also be a column made of other metal materials, and the third electrical connection bump serves as a grinding stop position during the step of forming the first plastic encapsulation layer.

[0122] In this embodiment, after forming the third electrical connection bumps 108b, a first plastic encapsulation layer 110b covering the optical chip 100b and the electrical function chip 200b is formed on the first carrier 300b, and the first plastic encapsulation layer 110b exposes the top of the third electrical connection bumps 108b.

[0123] The first plastic encapsulation layer 110b covers the optical chip 100b and the electrical functional chip 200b, which can enhance the mechanical strength of the optical chip 100b and the electrical functional chip 200b and prevent the optical chip 100b and the electrical functional chip 200b from being damaged during subsequent processing; in addition, the first plastic encapsulation layer 110b exposes the third electrical connection bumps 108b on the top of the optical chip 100b and the electrical functional chip 200b, so that the optical chip 100b and the electrical functional chip 200b can be prepared for connection with the second carrier board 400b.

[0124] Specifically, the step of forming the first plastic encapsulation layer 110b covering the optical chip 100b and the electrical function chip 200b on the first carrier board 300b includes: Figure 9 As shown, a first plastic packaging material layer 113b covering the optical chip 100b and the electrical function chip 200b is formed on the first carrier 300b; Figure 10 As shown, the first molding material layer 113b above the third electrical connection bump 108b is removed, and the remaining first molding material layer 113b serves as the first molding layer 110b.

[0125] In this embodiment, a chemical mechanical polishing (CMP) process is used to remove the first molding material layer 113 b above the third electrical connection bump 108 b .

[0126] like Figure 11 As shown, a fourth electrical connection bump 109b is formed on the third electrical connection bump 108b exposed by the first plastic encapsulation layer 110b; in the step of bonding the first package body 10b and the storage chip 500b to the second carrier 400b, the optical chip 100b and the electrical function chip 200b are connected to the second carrier 400b through the fourth electrical connection bump 109b.

[0127] A fourth electrical connection bump 109b is formed on top of the third electrical connection bump 108b, completing the construction of the external connection interface of the first package body 10b; subsequently, when the first package body 10b and the storage chip 500b are bonded to the second carrier board 400b, the optical chip 100b and the electrical function chip 200b are electrically and mechanically connected to the corresponding electrical connection structure (for example, the third solder pad 106b) on the second carrier board 400b through the fourth electrical connection bump 109b, thereby utilizing this double-layer bump structure (the grind-resistant third electrical connection bump 108b is the base solder pad, and the solderable fourth electrical connection bump 109b is the connector) to achieve reliable interconnection between the optical chip 100b and the electrical function chip 200b based on plastic encapsulation protection.

[0128] As an example, the fourth electrical connection bump 109b includes a solder ball.

[0129] refer to Figures 12 to 14, provide a second carrier board 400b and a memory chip 500b, and bond the first package body 10b and the memory chip 500b to the second carrier board 400b to form a second package body 20b.

[0130] Specifically, if Figure 12 As shown, the step of forming the second package body 20b includes: bonding the first package body 10b and the memory chip 500b to the second carrier 400b, and then forming a second electrical connection bump 401b on a side of the second carrier 400b away from the first package body 10b.

[0131] By forming a second electrical connection bump 401b on the side of the second carrier 400b away from the first package body 10b and the memory chip 500b, preparation is made for the subsequent electrical connection between the optical chip 100b, the electrical function chip 200b and the memory chip 500b in the second package body 20b and the substrate 600b. In other words, the second electrical connection bump 401b is the structural basis for the electrical connection between the second package body 20b and the substrate 600b.

[0132] like Figure 13 As shown, after the second electrical connection bumps 401b are formed, a second plastic encapsulation layer 204b is formed on the second carrier 400b to cover the side walls of the first package body 10b and the memory chip 500b, and the second plastic encapsulation layer 204b is exposed on the side of the first carrier 300b away from the second carrier 400b.

[0133] A second plastic encapsulation layer 204b is formed on the second carrier 400b to cover the side walls of the first package body 10b and the memory chip 500b, and the second plastic encapsulation layer 204b exposes the side of the first carrier 300b facing away from the second carrier 400b. That is, the second plastic encapsulation layer 204b covers and protects the optical chip 100b, the electrical function chip 200b and the memory chip 500b, and prevents the optical chip 100b, the electrical function chip 200b and the memory chip 500b from moisture, pollutants or physical damage. In addition, because the side of the first carrier 300b facing away from the second carrier 400b is exposed, the heat dissipation of the optical chip 100b and the electrical function chip 200b is taken into account, which is conducive to improving the reliability and long-term stability of the second package body 20b.

[0134] It should be noted that the second plastic packaging layer 204 b also exposes the side of the memory chip 500 b away from the second carrier board 400 b , which is beneficial to heat dissipation of the memory chip 500 b .

[0135] Specifically, the step of forming a second plastic encapsulation layer 204b covering the side walls of the first package body 10b and the memory chip 500b on the second carrier 400b includes: forming a second plastic encapsulation material layer (not shown in the figure) covering the first plastic encapsulation body and the memory chip 500b on the second carrier 400b; removing the second plastic encapsulation material layer that is higher than the first package body 10b and the memory chip 500b, and the remaining second plastic encapsulation material layer serves as the second plastic encapsulation layer 204b.

[0136] It should be noted that, in the step of forming the second plastic sealing layer 204b, the second plastic sealing layer 204b also covers the first plastic sealing layer 110b; in the step of removing the second plastic sealing layer 204b covering the optical coupling area 101b to expose the optical coupling area 101b of the optical chip 100b, the first plastic sealing layer 110b covering the optical coupling area 101b is also removed.

[0137] Because in the embodiment of the present invention, the first plastic sealing layer 110b is in direct contact with the surface of the optical coupling region 101b of the optical chip 100b, after removing the second plastic sealing layer 204b covering the optical coupling region 101b, the first plastic sealing layer 110b is removed to expose the optical coupling region 101b, thereby facilitating the subsequent coupling of the optical fiber 111b to the optical coupling region 101b.

[0138] refer to Figure 13 and Figure 14 The step of forming the second package body 20b further includes: forming a second plastic encapsulation layer 204b covering the sidewalls of the first package body 10b and the memory chip 500b on the second carrier 400b; and removing the second plastic encapsulation layer 204b covering the optical coupling region 101b.

[0139] It should be noted that in the step of removing the second plastic encapsulation layer 204b covering the optical coupling region 101b, part of the material of the optical chip 100b is also removed, specifically, the material on the side of the optical chip 100b having the optical coupling region 101b is removed to expose the optical coupling region 101b.

[0140] The second plastic encapsulation layer 204b covering the optical coupling region 101b and the material on the side of the optical chip 100b with the optical coupling region 101b are removed to expose the optical coupling region 101b, in preparation for the subsequent coupling of the optical fiber with the optical coupling region 101b. After the second package body 20b is protected by plastic encapsulation, an optical path can still be formed with the optical coupling region 101b, thereby taking into account both the structural stability of the package structure and the requirements of optical coupling, thereby facilitating reliable optical signal transmission and improving the yield and stability of the package structure.

[0141] Specifically, the step of removing the second plastic sealing layer 204b covering the optical coupling area 101b includes: removing the second plastic sealing layer 204b on the side of the optical chip 100b having the optical coupling area 101b, that is, removing the second plastic sealing layer 204b on the side of the optical chip 100b that is not close to the storage chip 500b.

[0142] Because the optical coupling region 101b is located on the side of the optical chip 100b that is not close to the storage chip 500b, a larger operating process space is provided in the step of removing the second plastic encapsulation layer 204b on the side of the optical chip 100b having the optical coupling region 101. At the same time, the coupling operation space between the optical fiber 111b and the optical coupling region 101b of the optical chip 100b is larger, which simplifies the alignment and connection between the optical fiber 111b and the optical coupling region 101b, is beneficial to the efficiency and quality of optical signal transmission, and enables the optical chip 100b to effectively perform its photoelectric conversion and high-speed optical transmission functions to meet the needs of large data throughput, which is beneficial to improving the functional density and integration of the overall package, meeting the needs of high bandwidth, large-capacity storage and fast data processing, and is beneficial to improving the performance of the package structure.

[0143] In this embodiment, the step of removing the second plastic encapsulation layer 204b covering the optical coupling region 101b includes removing the first plastic encapsulation layer 110b and the second plastic encapsulation layer 204b on the side of the optical chip 100b having the optical coupling region 101.

[0144] The first plastic encapsulation layer 110b and the second plastic encapsulation layer 204b on the side of the optical chip 100b having the optical coupling region 101 are removed so that the optical coupling region 101b is exposed, thereby providing a physical space for alignment and connection of the optical fiber 111b.

[0145] It should be noted that during the step of providing the optical chip 100b, the photonic components and waveguide component 103b in the optical chip 100b are completely located within the chip 100b. Accordingly, during the step of removing the first plastic encapsulation layer 110b and the second plastic encapsulation layer 204b on the side of the optical chip 100b having the optical coupling region 101, a portion of the material of the optical chip 100b is also removed to expose one end of the photonic components and waveguide component 103b.

[0146] It should also be noted that, in the step of forming the second package, the second plastic encapsulation layer 204b on the side of the memory chip 500b facing away from the first package 10b is removed, but the sidewall of the memory chip 500b is still covered by the second plastic encapsulation layer 204b. Figure 2 The second plastic encapsulation layer 204b on both sides of the first package body 10b and the memory chip 500b are removed, but the two side walls perpendicular to the direction X of the first package body 10b and the memory chip 500b are still covered by the second plastic encapsulation layer 204b.

[0147] In the step of removing the second plastic packaging layer 204b covering the light coupling region 101b, a portion of the first carrier board 300b is also removed.

[0148] As an example, a diamond blade is used to remove the first plastic encapsulation layer 110b and the second plastic encapsulation layer 204b on the side of the optical chip 100b having the optical coupling region 101b.

[0149] refer to Figure 15 , providing a substrate, bonding the second package body to the substrate; after bonding the second package body to the substrate, coupling the optical fiber to the optical coupling area of ​​the optical chip in the second package body.

[0150] It should be noted that, in the step of bonding the second package body 20b to the substrate 600b, the second electrical connection bumps 401b are connected to the substrate 600b.

[0151] In the step of bonding the second package body 20b to the substrate 600b, the second package body 20b is connected to the substrate 600b through the second electrical connection bumps 401b pre-formed at the bottom of the second carrier 400b, completing the electrical connection and mechanical fixation between the second package body 20b and the substrate 600b.

[0152] It should be noted that the optical fiber coupled to the optical coupling region can directly establish an effective optical connection with the photonic component and the waveguide structure 102a.

[0153] refer to Figures 16 to 18 The embodiment of the present invention further provides a third embodiment of a method for forming a package structure. The similarities between the embodiment of the present invention and the first embodiment are not repeated here. The differences are as follows:

[0154] like Figure 16 As shown, the step of forming the second package body 20c also includes: after forming a second electrical connection bump 401c on a side of the second carrier 400c facing away from the first package body 10c, forming a second plastic encapsulation layer 204 on the second carrier 400c covering the side walls of the first package body 10c and the memory chip 500c, with the second plastic encapsulation layer 204c exposed on a side of the first carrier 300c facing away from the second carrier 400c.

[0155] In the step of forming the second package body 20c, a second plastic encapsulation layer 204c is formed on the second carrier board 400c to cover the side walls of the first package body 10c and the memory chip 500c, and the second plastic encapsulation layer 204c exposes the side of the first carrier board 300c facing away from the second carrier board 400c. That is, the second plastic encapsulation layer 204c covers and protects the optical chip 100c, the electrical functional chip 200c and the memory chip 500c, and prevents the optical chip 100c, the electrical functional chip 200c and the memory chip 500c from moisture, pollutants or physical damage. In addition, because the side of the first carrier board 300c facing away from the second carrier board 400c is exposed, the heat dissipation of the optical chip 100c and the electrical functional chip 200c is taken into account, which is conducive to improving the reliability and long-term stability of the second package body 20c.

[0156] It should be noted that the second plastic packaging layer 204 c also exposes the side of the memory chip 500 c facing away from the second carrier board 400 c , which is beneficial to heat dissipation of the memory chip 500 c .

[0157] Specifically, the step of forming a second plastic encapsulation layer 204c covering the side walls of the first package body 10c and the memory chip 500c on the second carrier 400c includes: forming a second plastic encapsulation material layer covering the first plastic encapsulation body and the memory chip 500c on the second carrier 400c; removing the second plastic encapsulation material layer higher than the first package body 10c and the memory chip 500c, and the remaining second plastic encapsulation material layer serves as the second plastic encapsulation layer 204c.

[0158] refer to Figure 17 and Figure 18 The step of coupling the optical fiber 111c to the optical coupling region 101c of the optical chip 100c in the second package 20c includes: removing the second plastic encapsulation layer 204c covering the optical coupling region 101c to expose the optical coupling region 101c of the optical chip 100c; and connecting the optical fiber 111c to the optical coupling region 101c on the side wall of the optical chip 100c.

[0159] The second plastic packaging layer 204c covering the optical coupling region 101c is removed to expose the optical coupling region 101, and then the optical fiber 111c is connected to the optical coupling region 101c. This allows an optical path to be formed with the optical coupling region 101c after the second packaging body 20c is protected by plastic packaging. This balances the structural stability of the packaging structure and the requirements of optical coupling, facilitates reliable optical signal transmission, and improves the yield and stability of the packaging structure.

[0160] Specifically, the step of removing the second plastic encapsulation layer 204 c covering the optical coupling region 101 c includes: removing the second plastic encapsulation layer 204 c on a side of the optical chip 100 c having the optical coupling region 101 .

[0161] Because the optical coupling region 101c of the optical chip 100c is located on a side that is not close to the storage chip 500c, a larger process space is provided for removing the second plastic encapsulation layer 204c on the side of the optical chip 100c having the optical coupling region 101c. This also allows for a larger space for coupling operations between the optical fiber 111c and the optical coupling region 101c of the optical chip 100c, thereby simplifying the alignment and connection between the optical fiber 111c and the optical coupling region 101c. This is beneficial to the efficiency and quality of optical signal transmission, enabling the optical chip 100c to effectively perform its photoelectric conversion and high-speed optical transmission functions to meet the needs of large data throughput, thereby improving the functional density and integration of the overall package, meeting the needs of high bandwidth, large-capacity storage, and fast data processing, and improving the performance of the package structure.

[0162] It should be noted that, in the step of removing the second plastic encapsulation layer 204c on the side of the optical chip 100c having the optical coupling area 101, the material on the side of the optical chip 100c having the optical coupling area 101 is also removed to expose the optical coupling area 101c of the optical chip 100c, so that the optical coupling area 101c is exposed.

[0163] The embodiment of the present invention also provides a packaging structure, Figure 2 and Figure 6 ,refer to Figure 7 , which illustrates a structural diagram of the first embodiment of the packaging structure of the present invention.

[0164] The packaging structure includes: a substrate 600a; a second packaging body 20a formed on the substrate 600a, the second packaging body 20a including: a second carrier board 400a and a first packaging body 10a bonded to the second carrier board 400a and the memory chip 500a; the first packaging body 10a including: a first carrier board 300a and an optical chip 100a and the electrical function chip 200a bonded to the first carrier board 300a, the optical chip 100a including an exposed optical coupling region 101a; and an optical fiber 111a coupled to the optical coupling region 101a of the optical chip 100a.

[0165] The packaging structure provided by an embodiment of the present invention includes: a substrate 600a; a second packaging body 20a, formed on the substrate 600a, the second packaging body 20a including: a second carrier board 400a and a first packaging body 10a bonded to the second carrier board 400a and the memory chip 500a; the first packaging body 10a including: a first carrier board 300a and an optical chip 100a and the electrical function chip 200a bonded to the first carrier board 300a, the optical chip 100a including an optical coupling region 101a, the electrical function chip 200a being used for electronic signal processing; an optical fiber 111a, coupled to the optical coupling region 101a of the optical chip 100a. The optical chip 100a and the electrical chip 200a are located on a first substrate 300a, packaging the optical chip 100a and the electrical chip 200a into a first package 10a. Furthermore, the first package 10a and the memory chip 500a are located on a second substrate 400a, forming a second package 20a. An optical fiber 111a is coupled to the optical coupling region 101a of the optical chip 100a. Because the electrical chip 200a is used for electronic signal processing, the optical chip 100a is capable of large data throughput, and the memory chip 500a is capable of data storage. When the second package 20a is operating, signals can be extracted from the electrical chip 200a and subjected to photoelectric conversion and high-speed optical transmission via the optical chip 100a. The data is then stored by the memory chip 500a, enabling large data throughput. The resulting second package 20a integrates multiple functions, including electronic signal processing, optical signal transmission, and data storage. This improves the functional density and integration of the overall package, meeting the requirements of high bandwidth, large-capacity storage, and fast data processing, and enhancing the performance of the package structure.

[0166] The optical coupling region 101a is used to realize the input and output of optical signals, and the electrical function chip 200a is used for electronic signal processing, thereby laying the device foundation for photoelectric signal conversion, high-speed data transmission and complex logical operations, thereby enabling the packaging structure to have both optical domain communication capabilities and electrical domain computing and control capabilities, so that the subsequently formed packaging structure can achieve high-bandwidth, low-latency data exchange, which is conducive to meeting large data throughput requirements.

[0167] In this embodiment, the optical coupling region 101a is located on the sidewall of the optical chip 100a, and the optical fiber 111a is connected to the optical coupling region 101a on the sidewall of the optical chip 100a. The connection of the optical fiber 111a to the optical coupling region 101a on the sidewall of the optical chip 100a clarifies the specific location of the optical fiber 111a for connection. This utilizes the horizontal light emission characteristics of the sidewall of the optical chip 100a to achieve end-to-end connection between the optical fiber 111a and the chip's optical port. This simplifies the optical path design, eliminates the need for additional beam steering components, reduces alignment difficulty and potential optical losses, and enables the external optical fiber 111a to be precisely connected to the optical coupling region 101a of the optical chip 100a, thereby improving the performance of the packaging structure.

[0168] It should be noted that the optical coupling region 101a of the optical chip 100a is used to perform optical coupling in a direction X parallel to the main plane of the optical chip 100a, that is, horizontal light output is adopted, which can avoid the vertical optical path conversion components required when a vertical optical path is adopted, thereby simplifying the optical path design and the complexity of packaging integration.

[0169] It should also be noted that the optical chip 100a does not rely on built-in reflective structures to achieve optical path redirection. In other words, the optical chip 100a directly outputs light from the end face or directly outputs the optical signal to the sidewall optical coupling region 101a via a waveguide. This simplifies the internal structure of the optical chip 100a, making the optical signal path more direct and correspondingly reducing the cost of the optical chip 100a.

[0170] As an example, the optical chip 100a includes a photonic integrated circuit (PIC), which is mainly responsible for functions such as generation, modulation, transmission and reception of optical signals.

[0171] In this embodiment, a photon component and a waveguide structure 102a are formed on the first side 103a, and the light coupling region 101a is in communication with the photon component and the waveguide structure 102a.

[0172] The first side 103a of the optical chip 100a is formed with photonic components (such as light sources, modulators, detectors, etc.) and a waveguide structure, and the optical coupling region 101a is connected to the photonic components and the waveguide structure 102a, so that optical signals can be generated, transmitted, processed inside the optical chip 100a and coupled with the outside through the optical coupling region 101a. The processed optical signals can be effectively guided to the optical coupling region 101a, so that the external optical fiber 111a can be effectively optically connected to the photonic components and the waveguide structure 102a inside the chip through the optical coupling region 101a, which is conducive to achieving efficient optical signal input and output.

[0173] In this embodiment, the optical chip 100a includes a first side 103a and a second side 104a opposite the first side 103a. The optical chip 100a includes a through-silicon via (TSV) 105a extending through the first side 103a and the second side 104a. The TSV 105a provides a vertical electrical signal transmission path for the optical chip 100a, enabling electrical connectivity between the first side 103a and the second side 104a. This allows the optical chip 100a to perform optical functions on the first side 103a while also being electrically connected to external circuitry on a subsequent first carrier 300a via the second side 104a.

[0174] Specifically, a plurality of first pads 106a are formed on the surface of the first side 103a of the optical chip 100a. The photonic components, waveguide structure 102a, and through-silicon vias 105a are located below the first pads 106a. The photonic components, waveguide structure, and through-silicon vias 105a are disposed below the first pads 106a, and the first pads 106a can serve as electrical connection points for the photonic components, waveguide structure 102a, and through-silicon vias 105a.

[0175] In this embodiment, in the normal direction of the top surface of the optical chip 100a, the photonic component and waveguide structure 102a are close to the first side 103a of the optical chip 100, and the optical coupling region 101a is connected to the photonic component and waveguide structure 102a, so that the optical signal can be generated, transmitted, processed inside the optical chip 100a and coupled with the outside through the optical coupling region 101a. The processed optical signal can be effectively guided to the optical coupling region 101a, so that the external optical fiber 111a can be effectively optically connected to the photonic component and waveguide structure 102a inside the chip through the optical coupling region 101a, which is conducive to achieving efficient optical signal input and output.

[0176] It should be noted that the optical coupling region 101a is the end portion of the photonic component and waveguide structure 102a exposed on the side wall of the optical chip 100a, so that the optical fiber 111a coupled on the optical coupling region can be effectively optically connected to the photonic component and waveguide structure 102a inside the chip through the optical coupling region 101a.

[0177] In this embodiment, the electrical function chip 200a comprises a logic chip structure with telecom separation. Specifically, the electrical function chip 200a comprises a signal layer 201a, a bonding layer 202a, and a power layer 203a, which are stacked in sequence. In other words, the signal layer 201a and the power layer 203a are located on either side of the bonding layer 202a, respectively. This reduces crosstalk and noise coupling between the signal layer 201a and the power layer 203a, improving signal integrity while also lowering the impedance of the power supply network of the power layer 203a.

[0178] In this embodiment, the electrical function chip 200a is a back-powered chip, that is, the power input of the electrical function chip 200a is realized through the back of the chip, thereby separating the power distribution network (PDN) and the signal network in the vertical direction of the chip, thereby freeing up more space for the signal wiring layer on the front of the electrical function chip 200a, allowing a denser transistor layout and a more optimized signal path design, thereby significantly reducing the resistance and inductance of the power network, improving power supply efficiency and voltage stability, and improving signal integrity.

[0179] As an example, the electrical function chip 200a includes an integrated electronic circuit (EIC) chip, which is mainly responsible for processing and calculating electronic signals.

[0180] The optical chip 100a and the electrical chip 200a are bonded to the first substrate 300a to form the first package 10a. This allows the two heterogeneous chips, optical chip 100a and electrical chip 200a, to function as a preliminary integrated unit. This ensures a precise relative positional relationship between the optical chip 100a and the electrical chip 200a, paving the way for subsequent bonding of the optical chip 100a and the electrical chip 200a to the second substrate 400a. Furthermore, the first substrate 300a provides mechanical support and protection for the electrical chip 200a and the optical chip 100a, effectively preventing warping, cracking, or damage that could occur due to insufficient rigidity of the optical chip 100a and the electrical chip 200a during subsequent packaging steps, thereby improving the yield and reliability of the package structure.

[0181] In this embodiment, the thickness of the electrical function chip 200a is less than 50 μm. The thickness of the electrical function chip 200a is less than 50 μm, which is beneficial to improving the integration of the packaging structure.

[0182] It should be noted that the optical coupling region 101a is located on a side of the optical chip 100a that is not close to the electrical function chip 200a, which is beneficial to increasing the process space for coupling the optical fiber 111a with the optical coupling region 101a.

[0183] In this embodiment, the first substrate 300a comprises a silicon substrate, which can integrate a high-density redistribution layer (RDL), passive components, and through-silicon vias 105a (TSVs). In other embodiments, the first substrate can also comprise a silicon germanium substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0184] It should be noted that the surface of the first carrier 300a has an interconnection structure and a second pad 112a for achieving metal bonding with the optical chip 100a and the electrical function chip 200a.

[0185] In this embodiment, the signal layer 201a of the electrical function chip 200a is bonded to the first carrier board 300a, that is, the signal layer 201a is the electrical connection and mechanical connection interface between the electrical function chip 200a and the first carrier board 300a, so that the signal input and output ports of the signal layer 201a in the electrical function chip 200a can be connected to the corresponding pads 106a (which can also be an interconnection structure) on the first carrier board 300a, thereby realizing the transmission of electrical signals between the electrical function chip 200a and the first carrier board 300a, providing a basis for the functional realization of the electrical function chip 200a and the communication between the electrical function chip 200a and the optical chip 100 through the first carrier board 300a.

[0186] In this embodiment, the second side 104a of the optical chip 100a is bonded to the first carrier 300a. The second side 104a of the optical chip 100a is bonded to the first carrier 300a, meaning that the side of the optical chip 100a facing away from the photonic components and the through-silicon vias 105a is bonded to the first carrier 300a. This allows the through-silicon vias 105a exposed on the second side 104a of the optical chip 100a to be electrically connected to the first carrier 300a. Furthermore, the optical coupling region 101a on the first side 103a of the optical chip 100a is further away from the first carrier 300a, reducing the difficulty of coupling the optical fiber 111a to the optical coupling region 101a. , so that the electrical signal of the optical chip 100a can be transmitted from the first side 103a to the second side 104a through the through silicon via 105a, and then communicated with the interconnection structure on the first carrier 300a through the bonding interface between the second side 104a and the first carrier 300a, forming a key link in the electrical signal transmission path of the optical chip 100a, so that the optical coupling area 101a of the optical chip 100a can be coupled to the optical fiber 111a, thereby improving the alignment accuracy and connection reliability of the coupling of the optical fiber 111a, and facilitating the improvement of the quality of the packaging structure.

[0187] In this embodiment, hybrid bonding is used between the optical chip 100 a and the first carrier 300 a.

[0188] Hybrid bonding technology is employed between the optical chip 100a and the first carrier 300a. This technology utilizes a combination of dielectric bonding and metal bonding to achieve a secure connection between the two substrates. Direct bonding between dielectrics creates a high-strength mechanical connection, while bonding between metals (the first pads 106a on the optical chip 100a and the first pads 106a on the second carrier 300, as well as the interconnect structure) enables high-density electrical interconnection, improving interconnect density. Hybrid bonding enables finer pitch connections, which improves signal transmission rate and power transmission efficiency.

[0189] Accordingly, hybrid bonding is adopted between the electrical function chip 200 a and the first carrier board 300 a.

[0190] Hybrid bonding is used between the electrical function chip 200a and the first carrier 300a, which is conducive to forming a high-density, low-resistance electrical path and firm mechanical fixation between the surface of the signal layer 201a of the electrical function chip 200a and the first carrier 300a, thereby improving the rate and integrity of signal transmission and the efficiency of power distribution, preparing for subsequent integration with the optical chip 100a or the memory chip 500a, and facilitating the realization of a high-performance, highly integrated 2.5D packaging structure.

[0191] The first package body 10a further includes: a first electrical connection bump 107a, located on the first side 103a of the optical chip 100a and the power supply layer 203a of the electrical function chip 200a, and the optical chip 100a and the electrical function chip 200a are connected to the second carrier 400a through the first electrical connection bump 107a.

[0192] The first side 103a of the optical chip 100a and the first electrical connection bump 107a on the electrical function chip 200a are used to electrically connect the optical chip 100a and the electrical function chip 200a to the second carrier 400a, thereby realizing signal transmission between the optical chip 100a and the electrical function chip 200a and the second carrier 400a. In other words, the first package body 10a can be connected to the second carrier 400a through the first electrical connection bump 107a, which is the key to realizing vertical electrical interconnection in multi-level packaging and is conducive to building a high-density, high-performance 2.5D packaging structure.

[0193] Specifically, the first electrical connection bumps 107 a are located on the power supply layer 203 a of the electrical function chip 200 a and on the first pads 106 a of the photonic component and waveguide component 102 .

[0194] The first electrical connection bump 107a is located on the power supply layer 203a of the electrical function chip 200a and on the pad 106a of the photonic component and waveguide component of the first side 103a of the optical chip 100a. In other words, the first electrical connection bump 107a is an electrical node for connecting the first package body 10a to the outside, so that the power supply of the electrical function chip 200a can be introduced from the second carrier board 400a through the first electrical connection bump 107a, and the photoelectric signal processed by the optical chip 100a or the bias / control signal required for its operation can be transmitted through its first side 103a. The first electrical connection bump 107a on the 3a pad 106a is exchanged with the second carrier board 400a, thereby providing a physical connection point for the stable power supply of the electrical function chip 200a and the signal transmission / control of the optical chip 100a. Therefore, the path of the electrical signal is optimized, so that power and signals can be transmitted through the shortest path, so that the first package body 10a can efficiently obtain power from the second carrier board 400a and exchange data with it, which is conducive to ensuring signal integrity, reducing power consumption, and achieving subsequent reliable electrical connection with the second carrier board 400a.

[0195] As an example, the first electrical connection bumps 107a include solder balls.

[0196] In this embodiment, the second package body 20 a includes: a second carrier board 400 a , and the first package body 10 a and the memory chip 500 a bonded to the second carrier board 400 a .

[0197] The first package body 10a includes an optical chip 100a and an electrical function chip 200a. The second package body 20a and the memory chip 500a are bonded to the second carrier board 400a to form the second package body 20a, thereby integrating the optoelectronic processing unit and the data storage unit onto a common platform, and then realizing high-speed data exchange and collaborative work between the first package body 10a and the memory chip 500a through the interconnection on the second carrier board 400a. Because the electrical function chip 200a is used for electronic signal processing, the optical chip 100a can achieve large data throughput, and the memory chip 500a can achieve data storage. When the second package body 20a is working, the signal can be drawn out from the electrical function chip 200a and subjected to photoelectric conversion and high-speed optical transmission through the optical chip 100a. The data is stored in the memory chip 500a, which can achieve large data throughput. The second package body 20a thus formed can realize the integration of multiple functions such as electronic signal processing, optical signal transmission and data storage, which is conducive to improving the functional density and integration of the overall package, meeting the requirements of high bandwidth, large-capacity storage and fast data processing, and is conducive to improving the performance of the packaging structure.

[0198] It should be noted that the optical coupling region 101 a of the optical chip 100 a is located on a side of the optical chip 100 a that is not close to the memory chip 500 a .

[0199] The optical coupling region 101a of the optical chip 100a is located on a side that is not close to the storage chip 500a, thereby reserving a convenient interface path for coupling the optical fiber 111a with the optical coupling region 101a of the optical chip 100a, simplifying the alignment and connection between the optical fiber 111a and the optical coupling region 101a, and facilitating the efficiency and quality of optical signal transmission. This enables the optical chip 100a to effectively perform its photoelectric conversion and high-speed optical transmission functions to meet the needs of large data throughput, thereby improving the functional density and integration of the overall package, meeting the needs of high bandwidth, large-capacity storage and fast data processing, and improving the performance of the package structure.

[0200] Specifically, the first package body 10 a and the memory chip 500 a are bonded on the second carrier 400 a through a flip-chip process.

[0201] In this embodiment, the second carrier board 400a is a photonic interposer. While performing electrical interconnection functions, the second carrier board 400a can also transmit optical signals. The second carrier board 400a provides mechanical support and electrical connections for the first package 10a and the memory chip 500a, facilitating interaction between the optical chip 100a, the electrical chip 200a, and the memory chip 500a. This allows for the conversion, processing, storage, and transmission of optical and electrical signals to be completed within the second package 20a.

[0202] In this embodiment, the optical chip 100a and the electrical function chip 200a are connected to the second carrier 400a through the first electrical connection bumps 107a. The corresponding first electrical connection bumps 107a connect the optical chip 100a and the electrical function chip 200a in the first package body 10a to the second carrier 400a, thereby realizing electrical interconnection between the first package body 10a and the storage chip 500a and the second carrier 400a.

[0203] As an example, the second carrier board 400a has a third solder pad 106a corresponding to the optical chip 100a, the electrical function chip 200a and the memory chip 500a. By connecting the first electrical connection bump 107a on the optical chip 100a, the electrical function chip 200a and the memory chip 500a and the third solder pad on the second carrier board 400, a stable and reliable electrical signal transmission path can be established, so that control signals and data signals can be transmitted between the optical chip 100a, the electrical function chip 200a and the memory chip 500a and the second carrier board 400a, which is conducive to ensuring that the second package body 20a can work normally.

[0204] In this embodiment, the memory chip 500a is a high-bandwidth memory chip, for example, a high-bandwidth memory (HBM) chip.

[0205] It should be noted that the optical chip 100a is used for optical communication, the back-powered electrical function chip 200a is used for efficient electrical signal processing, and the memory chip 500a is used to provide high-speed data cache, which is used to realize high-speed transmission and reception of optical signals, complex calculations of electrical signals and rapid access to data in the final packaging structure. This is conducive to the packaging structure being able to realize the requirements of big data throughput for high-bandwidth optical interconnection and powerful computing and storage capabilities, and optimizes the integration method and optical path design between chips, so that the 2.5D packaging can support demanding high-performance computing and communication applications while taking into account process feasibility and structural stability.

[0206] In this embodiment, the second package body 20a includes second electrical connection bumps 401a located on a side of the second carrier 400a facing away from the first package body 10a. The second package body 20a is connected to the substrate 600a via the second electrical connection bumps 401a. The second electrical connection bumps 401a are used to electrically connect the optical chip 100a, the electrical function chip 200a, and the memory chip 500a in the second package body 20a to the substrate 600a.

[0207] In this embodiment, the substrate 600a provides an interface for external connection for the optical chip 100a, the electrical function chip 200a and the memory chip 500a in the second package body 20a. Therefore, while carrying the second package body 20a, the substrate 600a also generally includes wiring and interface structures for signal fan-out, power distribution, and connection with other parts of the system, so that the second package body 20a can be conveniently integrated into a larger electronic system.

[0208] In this embodiment, the material of the substrate 600a includes silicon. In other embodiments, the material of the substrate may also include silicon carbide, germanium, or a III-V compound semiconductor substrate.

[0209] In this embodiment, the optical fiber 111a is coupled to the optical coupling region 101a of the optical chip 100a. Because the optical chip 100a is located in the second package 20a, coupling the optical fiber 111a to the optical coupling region 101a of the optical chip 100a in the second package 20a helps improve the coupling accuracy between the optical fiber 111a and the optical coupling region 101a, ensuring that optical signals can be efficiently and stably input or output from the optical chip 100a. This enables the package structure to meet the requirements of high bandwidth, large-capacity storage, and fast data processing, thereby improving the performance of the package structure.

[0210] The package structure further includes: a substrate bump 601 a located on a side of the substrate 600 a away from the second package body 20 a .

[0211] The substrate bumps 601a facilitate connecting the structure in the second package body 20a with the external structure, thereby achieving electrical connection and mechanical fixation.

[0212] Combine Figure 8 and Figure 14 ,refer to Figure 15 , which illustrates a schematic structural diagram of the second embodiment of the packaging structure of the present invention. The similarities between the second embodiment of the packaging structure of the present invention and the first embodiment are not repeated here, and the differences are:

[0213] In this embodiment, the first package body 10b further includes a third electrical connection bump 108b located on the first side 103b of the optical chip 100b and the electrical function chip 200b. The third electrical connection bump 108b is used to provide signal output, power input, or ground connection for the optical chip 100b and the electrical function chip 200b.

[0214] In this embodiment, the electrical function chip 200b includes a signal layer 201b, a bonding layer 202b, and a power layer 203b stacked in sequence. A third electrical connection bump 108b is formed on the power layer 203b of the electrical function chip 200b. The third electrical connection bump 108b is located on the power layer 203b of the electrical function chip 200b and serves as a structure for connecting the electrical function chip 200 to the outside world.

[0215] Specifically, the third electrical connection bumps 108b are formed on the power supply layer 203b of the electrical function chip 200b and on the first pads 106b of the photonic component and waveguide component 102b on the first side 103b of the optical chip 100b.

[0216] As an example, the third electrical connection bump 108b is a copper column. In other embodiments, the third electrical connection bump can also be a column made of other metal materials, and the third electrical connection bump serves as a grinding stop position during the step of forming the first plastic encapsulation layer.

[0217] In this embodiment, the first package body 10b further includes: a first plastic layer 110b, located on the first carrier board 300b, covering the sidewalls of the optical chip 100b and the electrical function chip 200b, and exposing the ends of the third electrical connection bumps 108b.

[0218] The first plastic encapsulation layer 110b covers the optical chip 100b and the electrical functional chip 200b, which can enhance the mechanical strength of the optical chip 100b and the electrical functional chip 200b and prevent the optical chip 100b and the electrical functional chip 200b from being damaged during subsequent processing; in addition, the first plastic encapsulation layer 110b exposes the third electrical connection bumps 108b on the top of the optical chip 100b and the electrical functional chip 200b, so that the optical chip 100b and the electrical functional chip 200b can be prepared for connection with the second carrier board 400b.

[0219] The first plastic package further includes: fourth electrical connection bumps 109b located on the third electrical connection bumps 108b exposed by the first plastic package layer 110b. The optical chip 100b and the electrical function chip 200b are connected to the second carrier 400b via the fourth electrical connection bumps 109b.

[0220] The fourth electrical connection bump 109b is located on top of the third electrical connection bump 108b and serves as the external connection interface of the first package body 10. The fourth electrical connection bump 109b is electrically and mechanically connected to the corresponding electrical connection structure (such as the third solder pad) on the second carrier board 400b. Through this double-layer bump structure (the grind-resistant third electrical connection bump 108b is the base solder pad, and the solderable fourth electrical connection bump 109 is the connector), reliable interconnection is achieved while plastic encapsulating and protecting the optical chip 100b and the electrical functional chip 200b.

[0221] As an example, the fourth electrical connection bump 109b includes a solder ball.

[0222] In this embodiment, the second package body 20b includes: a second electrical connection bump 401b, located on the side of the second carrier 400b facing away from the first package body 10b, and the second package body 20b is connected to the substrate 600b through the second electrical connection bump 401b, thereby achieving electrical connection and mechanical fixation between the second package body 20b and the substrate 600b.

[0223] The second package body 20b further includes a second plastic encapsulation layer 204b covering the sidewalls of the first package body 10b and the memory chip 500b on the second carrier board 400b, and the second plastic encapsulation layer 204b exposes the optical coupling region 101b.

[0224] Because the optical coupling region 101b of the optical chip 100b is located on a side not close to the storage chip 500b, the coupling operation space between the optical fiber 111b and the optical coupling region 101 of the optical chip 100b is larger, which simplifies the alignment and connection between the optical fiber 111b and the optical coupling region 101b, is beneficial to the efficiency and quality of optical signal transmission, and enables the optical chip 100b to effectively perform its photoelectric conversion and high-speed optical transmission functions to meet the needs of large data throughput, which is beneficial to improving the functional density and integration of the overall package, meeting the needs of high bandwidth, large-capacity storage and fast data processing, and is beneficial to improving the performance of the package structure.

[0225] In this embodiment, the second plastic layer 204 b exposes a side of the first carrier 300 b facing away from the second carrier 400 b .

[0226] The second plastic encapsulation layer 204b covers the side walls of the first package body 10b and the memory chip 500b on the second carrier board 400b, and exposes the side of the first carrier board 300b facing away from the second carrier board 400b. In other words, the second plastic encapsulation layer 204b covers and protects the optical chip 100b, the electrical function chip 200b, and the memory chip 500b, preventing the optical chip 100b, the electrical function chip 200b, and the memory chip 500b from moisture, pollutants, or physical damage. In addition, because the side of the first carrier board 300b facing away from the second carrier board 400b is exposed, the heat dissipation of the optical chip 100b and the electrical function chip 200b is taken into account, which is conducive to improving the reliability and long-term stability of the second package body 20b.

[0227] It should be noted that the second plastic packaging layer 204 b also exposes the side of the memory chip 500 b away from the second carrier board 400 b , which is beneficial to heat dissipation of the memory chip 500 b .

[0228] In this embodiment, the second plastic sealing layer 204b also covers the first plastic sealing layer 110b.

[0229] In this embodiment, the first plastic encapsulation layer 110b and the second plastic encapsulation layer 204b expose the optical coupling region 101b, providing physical space for alignment and connection of the optical fiber 111b, so that the optical fiber 111b and the optical coupling region 101b are smoothly coupled.

[0230] Combine Figure 16 and Figure 17 ,refer to Figure 18 , which illustrates a schematic structural diagram of the third embodiment of the packaging structure of the present invention. The similarities between the third embodiment of the packaging structure of the present invention and the first embodiment are not repeated here. The differences are:

[0231] The second package body 20c further includes a second plastic layer 204c covering the sidewalls of the first package body 10c and the memory chip 500c on the second carrier 400c and exposing a side of the first carrier 300c that is not adjacent to the second carrier 400c.

[0232] The second plastic encapsulation layer 204c covers the side walls of the first package body 10c and the memory chip 500c on the second carrier board 400c, and exposes the side of the first carrier board 300c facing away from the second carrier board 400c. In other words, the second plastic encapsulation layer 204c covers and protects the optical chip 100c, the electrical function chip 200c, and the memory chip 500c, preventing the optical chip 100c, the electrical function chip 200c, and the memory chip 500c from moisture, pollutants, or physical damage. In addition, because the side of the first carrier board 300c facing away from the second carrier board 400c is exposed, the heat dissipation of the optical chip 100c and the electrical function chip 200c is taken into account, which is conducive to improving the reliability and long-term stability of the second package body 20c.

[0233] It should be noted that the second plastic packaging layer 204 c also exposes the side of the memory chip 500 c facing away from the second carrier board 400 c , which is beneficial to heat dissipation of the memory chip 500 c .

[0234] In this embodiment, the second plastic encapsulation layer 204c exposes the light coupling region 101c.

[0235] Because the optical coupling region 101c of the optical chip 100c is located on a side not close to the memory chip 500c, the second plastic encapsulation layer 204c exposes the optical coupling region 101c, thereby providing a larger space for coupling operation between the optical fiber 111c and the optical coupling region 101c of the optical chip 100c. This simplifies the alignment and connection between the optical fiber 111c and the optical coupling region 101c, and is beneficial to the efficiency and quality of optical signal transmission. This enables the optical chip 100c to effectively perform its photoelectric conversion and high-speed optical transmission functions to meet the requirements of large data throughput, thereby improving the functional density and integration of the overall package, meeting the requirements of high bandwidth, large-capacity storage, and fast data processing, and improving the performance of the package structure.

[0236] The packaging structure can be formed by the forming method described in the above embodiment, or by other forming methods. For the detailed description of the packaging structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0237] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a packaging structure, characterized in that: include: Providing an optical chip and an electrical function chip, wherein the optical chip includes an optical coupling region; Providing a first carrier board, and bonding the optical chip and the electrical function chip to the first carrier board to form a first package; Providing a second carrier board and a memory chip, and bonding the first package body and the memory chip to the second carrier board to form a second package body; Providing a substrate, and bonding the second package body to the substrate; After the second package body is bonded to the substrate, an optical fiber is coupled to the optical coupling region of the optical chip in the second package body.

2. The method for forming a package structure according to claim 1, wherein: In the step of bonding the optical chip and the electrical function chip to the first carrier board, the optical coupling region is located on a side of the optical chip that is not close to the electrical function chip; In the step of coupling an optical fiber to the optical coupling region of the optical chip in the second package, the optical coupling region is located on a side wall of the optical chip, and the optical fiber is connected to the optical coupling region on the side wall of the optical chip.

3. The method for forming a package structure according to claim 1, wherein: In the step of providing the optical chip, the optical coupling region is exposed on a side wall of the optical chip.

4. The method for forming a package structure according to claim 1, wherein: In the step of bonding the first package body and the memory chip to the second carrier, the optical coupling region of the optical chip is located on a side not close to the memory chip.

5. The method for forming a package structure according to claim 1, wherein: In the step of providing the optical chip, the optical coupling region of the optical chip is used to perform optical coupling in a direction parallel to a main plane of the optical chip.

6. The method for forming a package structure according to claim 1, wherein: The step of forming the second package body further includes: forming a second plastic packaging layer on the second carrier board covering the first package body and the side wall of the memory chip; The method for forming the packaging structure further includes: removing the second plastic packaging layer covering the optical coupling region.

7. The method for forming a package structure according to claim 6, wherein: In the step of providing an optical chip, the optical coupling region is located inside the optical chip; In the step of removing the second plastic encapsulation layer covering the optical coupling region, part of the material of the optical chip is also removed to expose the optical coupling region.

8. The method for forming a package structure according to claim 6, wherein: In the step of bonding the first package body and the memory chip to the second carrier, the optical coupling region of the optical chip is located on a side not close to the memory chip; The step of removing the second plastic encapsulation layer covering the optical coupling region includes: removing the second plastic encapsulation layer on a side of the optical chip having the optical coupling region.

9. The method for forming a package structure according to claim 6, wherein: The steps of forming the first package body include: After bonding the optical chip and the electrical function chip to the first carrier board, forming third electrical connection bumps on the first side of the optical chip and the electrical function chip; After forming the third electrical connection bumps, forming a first plastic encapsulation layer covering the optical chip and the electrical function chip on the first carrier, wherein the first plastic encapsulation layer exposes the tops of the third electrical connection bumps; forming a fourth electrical connection bump on the third electrical connection bump exposed by the first plastic encapsulation layer; In the step of bonding the first package body and the memory chip to the second carrier board, the optical chip and the electrical function chip are connected to the second carrier board via the fourth electrical connection bumps.

10. The method for forming a package structure according to claim 9, wherein: In the step of forming the second plastic sealing layer, the second plastic sealing layer also covers the first plastic sealing layer; In the step of removing the second plastic sealing layer covering the light coupling region, the first plastic sealing layer covering the light coupling region is also removed.

11. The method for forming a package structure according to claim 1, wherein: The step of forming the second package body includes: After bonding the first package body and the memory chip to the second carrier, forming a second electrical connection bump on a side of the second carrier away from the first package body; In the step of bonding the second package body to the substrate, the second package body is connected to the substrate through the second electrical connection bumps.

12. The method for forming a package structure according to claim 6, wherein: The step of forming the second package body includes: In the step of forming a second plastic encapsulation layer covering the first package body and the sidewall of the memory chip on the second carrier, the second plastic encapsulation layer is exposed on a side of the first carrier facing away from the second carrier.

13. The method for forming a package structure according to claim 12, wherein: The step of forming a second plastic encapsulation layer covering the first package body and the sidewall of the memory chip on the second carrier includes: A second molding material layer covering the first package body and the memory chip is formed on the second carrier; the second molding material layer higher than the first carrier is removed, and the remaining second molding material layer serves as the second molding layer.

14. The method for forming a package structure according to claim 1, wherein: In the step of providing the optical chip, the optical chip includes a first side and a second side opposite to the first side, wherein the first side is formed with a through silicon via; The method for forming the package structure further includes: after providing the optical chip, and before bonding the optical chip to the first carrier, thinning the second side of the optical chip to expose an end portion of the through silicon via; In the step of bonding the optical chip to the first carrier, the second side of the optical chip is bonded to the first carrier.

15. The method for forming a package structure according to claim 14, wherein: In the step of providing the optical chip, the light coupling region is formed on the first side.

16. The method for forming a package structure according to claim 1, wherein: The step of bonding the optical chip to the first carrier board includes adopting hybrid bonding.

17. The method for forming a package structure according to claim 1, wherein: In the step of providing the electrical function chip, the electrical function chip includes a signal layer, a bonding layer, and a power supply layer stacked in sequence; The step of bonding the electrical function chip to the first carrier includes: bonding the signal layer surface of the electrical function chip to the first carrier.

18. The method for forming a package structure according to claim 1, wherein: The step of forming the first package further includes: after bonding the optical chip and the electrical function chip to the first carrier board, forming first electrical connection bumps on the first side of the optical chip and the electrical function chip; In the step of bonding the first package body and the memory chip to the second carrier board, the optical chip and the electrical function chip are connected to the second carrier board through the first electrical connection bumps.

19. A packaging structure, characterized in that: include: substrate; A second package body is formed on the substrate, the second package body comprising: a second carrier board and the first package body and the memory chip bonded to the second carrier board; The first package body includes: a first carrier board and an optical chip and an electrical function chip bonded to the first carrier board, wherein the optical chip includes an exposed optical coupling area; An optical fiber is coupled to the optical coupling region of the optical chip.

20. The package structure according to claim 19, wherein: The optical coupling region is located on a side wall of the optical chip that is not close to the electrical function chip, and the optical fiber is connected to the optical coupling region on the side wall of the optical chip.

21. The package structure according to claim 19, wherein: The optical chip comprises a first side and a second side opposite to the first side, and the optical coupling region is located on the first side; The second side of the optical chip is bonded to the first carrier board.

22. The package structure according to claim 19, wherein: The optical coupling region of the optical chip is used for optical coupling in a direction parallel to a main plane of the optical chip.

23. The package structure according to claim 19, wherein: The optical coupling region of the optical chip is located on a side not close to the memory chip.

24. The package structure according to claim 23, wherein: The second package further includes: The second plastic packaging layer covers the first package body and the side wall of the memory chip on the second carrier, and the second plastic packaging layer exposes the optical coupling area.

25. The packaging structure according to claim 24, wherein: The second plastic packaging layer exposes a side of the first carrier board facing away from the second carrier board, and a side of the memory chip facing away from the second carrier board.

26. The package structure according to claim 24, wherein: The first package further includes: a third electrical connection bump, located on the first side of the optical chip and on the electrical function chip; a first plastic packaging layer, located on the first carrier board, covering the side walls of the optical chip and the electrical function chip, and exposing the ends of the third electrical connection bumps; The fourth electrical connection bumps are located on the third electrical connection bumps exposed by the first plastic packaging layer, and the optical chip and the electrical function chip are connected to the second carrier board through the fourth electrical connection bumps.

27. The package structure according to claim 26, wherein: The second plastic sealing layer also covers the first plastic sealing layer; The first plastic encapsulation layer and the second plastic encapsulation layer both expose the light coupling region.

28. The package structure according to claim 19, wherein: The optical chip includes a first side and a second side opposite to the first side, and the optical chip includes a through silicon via (TSV) penetrating the first side and the second side.

29. The package structure according to claim 19, wherein: The optical chip and the first carrier are hybrid bonded.

30. The package structure according to claim 19, wherein: The electrical function chip includes a signal layer, a bonding layer, and a power supply layer stacked in sequence, and the signal layer of the electrical function chip is bonded to the first carrier board.

31. The package structure according to claim 19, wherein: The first package further includes: The first electrical connection bumps are located on the first side of the optical chip and on the power supply layer of the electrical function chip. The optical chip and the electrical function chip are connected to the second carrier board through the first electrical connection bumps.

32. The package structure according to claim 19, wherein: The second package includes: The second electrical connection bumps are located on a side of the second carrier away from the first package body, and the second package body is connected to the substrate via the second electrical connection bumps.

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