Method of manufacturing a semiconductor package

Abstract

A method of manufacturing a semiconductor package can include forming a first barrier layer on a first carrier; forming a sacrificial layer including an opening exposing at least a portion of the first barrier layer on the first barrier layer; forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer can include a portion formed on the sacrificial layer. The method can also include forming a first insulating layer in the opening, the first insulating layer protruding beyond a top surface of the portion of the second barrier layer, a top surface of the first insulating layer being further from the first barrier layer than the top surface of the portion of the second barrier layer; forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier to the semiconductor chip and removing the first carrier; removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure; and forming solder balls on the portions of the redistribution structure, respectively.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0107487, filed on August 30, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a method for manufacturing semiconductor packages. Background Technology

[0004] Recently, with the increasing popularity of high-performance devices, not only are the sizes of semiconductor chips increasing, but the sizes of semiconductor packages are also increasing accordingly. In contrast, as electronic devices become thinner, the thickness of semiconductor packages is decreasing.

[0005] Semiconductor packaging is the process of encapsulating semiconductor chips to electrically connect the semiconductor chip (or semiconductor die) to an electronic device. As the size of semiconductor chips decreases, fan-out wafer-level packaging (FOWLP) has been proposed. In FOWLP, the input and output terminals of the semiconductor package are disposed outside the semiconductor chip via a redistribution layer. Because FOWLP is simple and can be used to form thin semiconductor packages, it is suitable for miniaturization and thinning of semiconductor packages, and can provide improved thermal and electrical characteristics. Summary of the Invention

[0006] Embodiments of the present invention provide semiconductor packages with improved product reliability.

[0007] Embodiments of the present invention also provide a method for manufacturing semiconductor packages with improved product reliability.

[0008] According to some embodiments of the inventive concepts, a method of manufacturing a semiconductor package can include forming a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including an opening exposing at least a portion of the first barrier layer; forming a second barrier layer on the first barrier layer and on the sacrificial layer, the second barrier layer including a portion formed on the sacrificial layer; forming a first insulating layer in the opening, the first insulating layer protruding beyond a top surface of the portion of the second barrier layer, a top surface of the first insulating layer being further from the first barrier layer than the top surface of the portion of the second barrier layer; forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier to the semiconductor chip and removing the first carrier; removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure; and forming solder balls on the portions of the redistribution structure, respectively.

[0009] According to some embodiments of the inventive concepts, a method of manufacturing a semiconductor package can include sequentially forming a release layer and a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including a metal material and an opening exposing at least a portion of the first barrier layer; forming a second barrier layer extending on the first barrier layer and on the sacrificial layer; forming a first insulating layer in the opening that is thicker than the sacrificial layer; forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier to the semiconductor chip and removing the first carrier and the release layer; removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution layer; and forming solder balls on the portions of the redistribution layer, respectively.

[0010] According to some embodiments of the inventive concepts, a method of manufacturing a semiconductor package can include sequentially forming a release layer and a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including an opening exposing at least a portion of the first barrier layer; conformally forming a second barrier layer on the first barrier layer and on the sacrificial layer; forming a first insulating layer in the opening, a top surface of the first insulating layer being further from the first barrier layer than a top surface of a portion of the second barrier layer formed on the sacrificial layer; forming a redistribution structure on the first insulating layer and on the second barrier layer, the redistribution structure including a redistribution layer and a second insulating layer stacked on the redistribution layer to surround the redistribution layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier to the semiconductor chip and removing the first carrier; removing the release layer; sequentially removing the first barrier layer, the sacrificial layer, and the second barrier layer; and forming a solder ball in a space where the sacrificial layer has been removed, the solder ball electrically connected to the redistribution layer.

[0011] The inventive concepts are not limited to the example embodiments provided herein. The above and other embodiments of the inventive concepts will become more apparent to one of ordinary skill in the art with reference to the following detailed description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] Example embodiments and features of the inventive concepts will become more apparent from the description provided herein with reference to the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view of a semiconductor package according to some embodiments of the inventive concepts;

[0014] Figure 2 is Figure 1 is a magnified cross-sectional view of a region S1 of

[0015] Figure 3 is a cross-sectional view of a semiconductor package according to some embodiments of the inventive concepts;

[0016] Figures 4 to 16 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the inventive concepts; and

[0017] Figure 17 and Figure 18 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the inventive concepts. DETAILED DESCRIPTION

[0018] Figure 1 is a cross-sectional view of a semiconductor package according to some embodiments of the inventive concepts.

[0019] Referring to Figure 1 , a semiconductor package according to some embodiments of the inventive concept can include a redistribution structure 100, a semiconductor chip 200, a molding member 300, and a solder ball 400.

[0020] The redistribution structure 100 can include a first surface 100a and a second surface 100b opposite each other. For example, the first surface 100a can be a top surface of the redistribution structure 100, and the second surface 100b can be a bottom surface of the redistribution structure 100.

[0021] The redistribution structure 100 can include a plurality of redistribution layers (120, 125, 126, and 128), a plurality of insulating layers (110, 112, 114, and 116), and a plurality of vias (132 and 134).

[0022] The redistribution layers (120, 125, 126, and 128) can extend in a first direction D1. Each of the redistribution layers (120, 125, 126, and 128) can include a plurality of redistribution layers spaced apart from each other in the first direction D1.

[0023] The redistribution layers (120, 125, 126, and 128) can be sequentially stacked from the second surface 100b to the first surface 100a. That is, the redistribution layers (120, 125, 126, and 128) can be spaced apart from each other in a second direction D2 and can be disposed at different horizontal levels along the second direction D2. Here, the second direction D2 can be a direction perpendicular to the first direction D1.

[0024] The redistribution layers (120, 125, 126, and 128) can be electrically connected by the plurality of vias (132 and 134). The number of the redistribution layers (120, 125, 126, and 128) and the positions and arrangements of the redistribution layers (120, 125, 126, and 128) are not limited to those shown in Figure 1 and can be different from those shown in Figure 1 .

[0025] The redistribution layers (120, 125, 126, and 128) can be at least partially exposed through a trench 100t. For example, a first redistribution layer 125 can be at least partially exposed through the trench 100t. The first redistribution layer 125 can include an electrode pad 122 and a sub-redistribution layer 124, which will be described later with reference to Figure 2 . In some embodiments, as shown in Figure 1 , at least a portion of the redistribution layers (120, 125, 126, and 128) can contact an insulating layer (e.g., 110) in the trench 100t.

[0026] The redistribution layers (120, 125, 126, and 128) can include, for example, copper (Cu), but the inventive concept is not limited thereto. In addition, the redistribution layers (120, 125, 126, and 128) can include, for example, at least one of aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof.

[0027] The vias (132 and 134) can connect the redistribution layers (120, 125, 126, and 128) formed at different levels to each other. For example, the first via 132 can connect the first redistribution layer 125 and the second redistribution layer 126 through the second insulating layer 112, and the second via 134 can connect the second redistribution layer 126 and the third redistribution layer 128 through the third insulating layer 114. The number of the vias (132 and 134), and the position and arrangement of the vias (132 and 134) are not limited to Figure 1 those shown, and can be different from those shown. Figure 1

[0028] The vias (132 and 134) can include an electrically conductive material. Accordingly, an electrical path connecting the first surface 100a and the second surface 100b can be formed in the redistribution structure 100. For example, the vias (132 and 134) can include the same material as the redistribution layers (120, 125, 126, and 128). The vias (132 and 134) can include, for example, Cu. In addition, the vias (132 and 134) can include, for example, at least one of Al, Ag, Sn, Au, Ni, Pb, Ti, and alloys thereof.

[0029] The insulating layers (110, 112, 114, and 116) can surround the redistribution layers (120, 125, 126, and 128) and the vias (132 and 134).

[0030] The insulating layers (110, 112, 114, and 116) can include the same material. The insulating layers (110, 112, 114, and 116) can include, for example, a photoimageable dielectric (PID) material. The insulating layers (110, 112, 114, and 116) can include, for example, an epoxy or a polyimide. Accordingly, the insulating layers (110, 112, 114, and 116) can be formed at a wafer level by photolithography. The insulating layers (110, 112, 114, and 116) can be formed to be thin, and the vias (132 and 134) can be formed to have a fine pitch.

[0031] ​The semiconductor chip 200 can be mounted on the first surface 100a of the redistribution structure 100. The redistribution structure 100 can include a fan-in region overlapping the semiconductor chip 200 and a fan-out region (i.e., a region other than the fan-in region) not overlapping the semiconductor chip 200. That is, the semiconductor package according to some embodiments of the inventive concept can be a fan-out wafer level package, but the inventive concept is not limited thereto. In some embodiments, the semiconductor package according to some embodiments of the inventive concept can be a wafer level package.

[0032] The semiconductor chip 200 can be, for example, an integrated circuit (IC) in which hundreds to millions of devices are integrated. The semiconductor chip 200 can be, for example, a processor chip (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor), or a microprocessor, particularly a logic chip such as an application processor (AP). In some embodiments, the semiconductor chip 200 can be a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In some embodiments, the semiconductor chip 200 can be a combination of a logic chip and a memory chip, but the inventive concept is not limited thereto.

[0033] The semiconductor chip 200 can include a connection pad 210, a passivation layer 220, and a bump 230.

[0034] The connection pad 210 can electrically connect the semiconductor chip 200 with other elements. The connection pad 210 can include, for example, a conductive material such as Al.

[0035] The passivation layer 220 can at least partially expose the connection pad 210. The passivation layer 220 can be, for example, an oxide film, a nitride film, a double layer of an oxide film and a nitride film. The passivation layer 220 can include an insulating material, for example, a thermosetting resin (e.g., an epoxy resin), a thermoplastic resin (e.g., a polyimide), or a mixture of a thermosetting or thermoplastic resin and an inorganic filler, or a resin such as a prepreg, an Ajinomoto Build-up Film (ABF), FR-4, or a bismaleimide triazine (BT) obtained by impregnating a core material such as glass fiber with an inorganic filler.

[0036] Bumps 230 can be disposed between the first surface 100a of the redistribution structure 100 and the connection pads 210. The bumps 230 can be in contact with the connection pads 210 and the redistribution layer 120. The bumps 230 can electrically connect the semiconductor chip 200 and the redistribution structure 100. The bumps 230 can include, for example, at least one of Au, Ag, Ni, Cu, Sn, and alloys thereof, but the inventive concept is not limited thereto.

[0037] The molding member 300 can cover the side surface and the top surface of the semiconductor chip 200. The molding member 300 can fill a gap between the side surface and the top surface of the semiconductor chip 200, the first surface 100a of the redistribution structure 100, and the bumps 230. The side surface of the molding member 300 can form the same plane as the side surface of the redistribution structure 100. It will be understood that "element A covers element B" (or similar language) means that piece A extends over element B, but does not necessarily mean that element A completely covers element B. It will also be understood that "element A fills element B" (or similar language) as used herein means that element A is in element B, but does not necessarily mean that element A completely fills element B.

[0038] The molding member 300 can include, for example, an epoxy molding compound (EMC) or a silicone hybrid material.

[0039] The solder balls 400 can be disposed in one or more trenches 100t formed on the second surface 100b of the redistribution structure 100. The solder balls 400 can be disposed on the first redistribution layer 125. Accordingly, the solder balls 400 can be electrically connected to the redistribution structure 100. In addition, the semiconductor package according to some embodiments of the inventive concept can be electrically connected to an external device through the solder balls 400. The number of the solder balls 400, and the shape and arrangement of the solder balls 400 are not limited to Figure 1 those shown, and can differ from Figure 1 those shown.

[0040] The solder balls 400 can include, for example, at least one of Sn, indium (In), lead (Pb), zinc (Zn), Ni, Au, Ag, Cu, antimony (Sb), bismuth (Bi), and combinations thereof, but the inventive concept is not limited thereto.

[0041] Figure 2 is Figure 1 an enlarged sectional view of the area S1.

[0042] Referring to Figure 2 , the second redistribution layer 126 can be disposed on the first redistribution layer 125. The first redistribution layer 125 and the second redistribution layer 126 can be in contact with the first via 132.

[0043] The first redistribution layer 125 can include a first portion I having a first thickness T1 in the second direction D2 and a second portion II having a second thickness T2 in the second direction D2. A top surface of the first portion I and a top surface of the second portion II in the second direction D2 can together form a same plane. The first thickness T1 can be greater than (i.e., thicker than) the second thickness T2. In some embodiments, the top surface of the first portion I and the top surface of the second portion II face the second redistribution layer 126 and are coplanar with each other, as shown in Figure 2 .

[0044] The first redistribution layer 125 can include the electrode pad 122 and the sub- redistribution layer 124. The first portion I can include the electrode pad 122 and the sub- redistribution layer 124, and the second portion II can include the sub-redistribution layer 124.

[0045] The electrode pad 122 can have a first height H1 from the second surface 100b (i.e., in the second direction D2). The sub-redistribution layer 124 can have a second height H2 from the second surface 100b (i.e., in the second direction D2). The second height H2 can be greater than the first height H1.

[0046] The electrode pad 122 can have a first width W1. The sub-redistribution layer 124 can have a second width W2 that is greater than the first width W1. The electrode pad 122 can be disposed in a portion of the sub-distribution layer 214 with the first width W1. In some embodiments, the electrode pad 122 can include a lower surface that faces the solder ball 400, and the lower surface of the electrode pad 122 can have the first width W1, as shown in Figure 2 . In some embodiments, the electrode pad 122 can contact the solder ball 400, and the electrode pad 122 can have the first width W1 at or near an interface with the solder ball 400, as shown in Figure 2 . The term “a portion of” as used herein can be interchangeable with the term “a part of,” and “a portion of element A” (or similar language) can refer to “a part of element A.”

[0047] The electrode pad 122 and the sub-redistribution layer 124 can have an integrated structure. The term “integrated structure” as used herein can refer to a structure having components that are manufactured by a same process. That is, the electrode pad 122 and the sub- redistribution layer 124 can be formed by a same process. Accordingly, the electrode pad 122 and the sub-redistribution layer 124 can include a same material. The electrode pad 122 and the sub-redistribution layer 124 can include, for example, Cu.

[0048] The redistribution structure 100 can include a trench 100t formed on the second surface 100b. In some embodiments, the trench 100t can be connected to the second surface 100b, as shown inFigure 2 is shown.

[0049] The trench 100t can be defined by the first insulating layer 110.

[0050] The trench 100t can be defined by the first insulating layer 110 and the electrode pad 122. That is, the electrode pad 122 can be exposed by the trench 100t. The electrode pad 122 can extend along a portion of a sidewall of each trench 100t. That is, the electrode pad 122 can extend in the second direction D2.

[0051] The solder ball 400 can be disposed in the trench 100t. That is, the solder ball 400 can include a portion disposed in the redistribution structure 100 and a portion disposed outside the redistribution structure 100. The first redistribution layer 125 and the solder ball 400 can be at least partially surrounded by the first insulating layer 110. Accordingly, it is possible to improve the reliability of the bonding between the solder ball 400 and the electrode pad 122.

[0052] Figure 3 is a cross-sectional view of a semiconductor package according to some embodiments of the inventive concept. For convenience, hereinafter, the semiconductor package of Figure 1 will be mainly focused on the differences from the semiconductor package of Figure 3 .

[0053] Referring to Figure 3 , the molding member 300 can cover the side surface of the semiconductor chip 200 and the first surface 100a of the redistribution structure 100. The molding member 300 can expose the top surface of the semiconductor chip 200. The top surface of the molding member 300 can be disposed on the same plane as the top surface of the semiconductor chip 200.

[0054] A heat spreader (not shown) can be disposed on, for example, the top surface of the molding member 300 and the top surface of the semiconductor chip 200. Since the semiconductor chip 200 and the heat spreader can be in direct contact with each other, heat generated by the semiconductor chip 200 can be easily released through the heat spreader.

[0055] Figure 1 or Figure 3 The semiconductor package of Figure 1 or Figure 3 The semiconductor package of

[0056] Figures 4 to 16is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to some embodiments of the inventive concepts. Hereinafter, some embodiments of the inventive concepts will be described with reference to Figures 4 to 16 A method of manufacturing a semiconductor package according to some embodiments of the inventive concepts is described.

[0057] Referring to Figure 4 A release layer 510 can be formed on the first carrier 500. The first carrier 500 can include, for example, silicon, metal, glass, plastic, or ceramic.

[0058] The release layer 510 can be formed to have a predetermined thickness. For example, the release layer 510 can be in the form of a film, but the inventive concepts are not limited thereto. The release layer 510 can be formed by deposition or coating.

[0059] The release layer 510 can include a PID material. The release layer 510 can be, for example, a positive type that reacts based on radiation.

[0060] For example, an adhesion layer (not shown) can be further formed between the first carrier 500 and the release layer 510. The adhesion layer can include, for example, a polymer-based light-to-heat conversion (LTHC) material that can be removed together with the first carrier 500. In some embodiments, the adhesion layer can include, for example, an epoxy-based heat dissipation material or an ultraviolet (UV) adhesive.

[0061] Referring to Figure 5 A first barrier layer 512 can be formed on the release layer 510. The first barrier layer 512 can include a metal material. The first barrier layer 512 can include, for example, Ti.

[0062] The first barrier layer 512 can be formed by, for example, physical vapor deposition (PVD), sputtering, or chemical vapor deposition (CVD), but the inventive concepts are not limited thereto.

[0063] Referring to Figure 6 A sacrificial layer 514 can be formed on the first barrier layer 512. The sacrificial layer 514 can expose a portion of the first barrier layer 512. For example, the sacrificial layer 514 can include an opening 515.

[0064] A mask pattern (not shown) can be formed on the first barrier layer 512. The mask pattern can be formed above the opening 515. The mask pattern can be formed by applying and patterning a photoresist.

[0065] A sacrificial layer 514 can be formed on the exposed portion of the first barrier layer 512. The sacrificial layer 514 can be formed by, for example, PVD, sputtering, or CVD. In some embodiments, the sacrificial layer 514 can be formed by, for example, electroplating. Once the sacrificial layer 514 is formed, the mask pattern can be removed. An opening 515 can be defined by the top surface of the portion of the first barrier layer 512 exposed by the mask pattern.

[0066] The sacrificial layer 514 can include a different metallic material than the first barrier layer 512. The sacrificial layer 514 can include, for example, Cu.

[0067] Referring to Figure 7 The second barrier layer 516 can be formed conformally in the opening 515 and on the sacrificial layer 514. The second barrier layer 516 can cover the top surface and the side surface of the sacrificial layer 514. The second barrier layer 516 can cover the top surface of the exposed portion of the first barrier layer 512. In some embodiments, the second barrier layer 516 can have a uniform thickness along the surfaces of the first barrier layer 512 and the sacrificial layer 514, as shown in FIG. 5B. Figure 7

[0068] The second barrier layer 516 can include a different metallic material than the sacrificial layer 514. The second barrier layer 516 can include, for example, at least one of Ti, chromium (Cr), tungsten (W), Al, palladium (Pd), and combinations thereof, although the inventive concepts are not limited thereto.

[0069] The second barrier layer 516 can be formed by, for example, PVD, sputtering, or CVD, although the inventive concepts are not limited thereto.

[0070] Referring to Figure 8 The first insulating layer 110 can be formed on the second barrier layer 516. The first insulating layer 110 can expose a portion of the second barrier layer 516. For example, the first insulating layer 110 can expose the top surface 516u of the portion of the second barrier layer 516 on the sacrificial layer 514.

[0071] The first insulating layer 110 can be thicker than the sacrificial layer 514. That is, the top surface 110u of the first insulating layer 110 can be higher than the top surface 516u of the portion of the second barrier layer 516 on the sacrificial layer 514. In some embodiments, the upper portion of the first insulating layer 110 can protrude upward beyond the top surface 516u of the portion of the second barrier layer 516, and thus, the top surface of the first insulating layer 110 can be farther from the first barrier layer 512 than the top surface 516u of the portion of the second barrier layer 516, as shown in FIG. 5C. Figure 8

[0072] The first insulating layer 110 can include the same material as the release layer 510. The first insulating layer 110 can include, for example, a PIDs material. ​​

[0073] A top surface 516u of the portion of the second barrier layer 516 on the sacrificial layer 514 can be exposed by, for example, lithography.

[0074] Referring to Figure 9 A first redistribution layer 125 can be formed on the first insulating layer 110 and on the top surface 516u of the portion of the second barrier layer 516 on the sacrificial layer 514.

[0075] The first redistribution layer 125 can include the same material as the sacrificial layer 514. For example, the first redistribution layer 125 can include Cu.

[0076] Referring to Figure 10 A redistribution structure 100 including the first redistribution layer 125 can be formed. For example, the plurality of vias (132 and 134) and the plurality of redistribution layers (120, 126, and 128) can be formed by electroplating. For example, the first via 132 and the second redistribution layer 126 can be formed simultaneously by a damascene process. In some embodiments, the first via 132 and the second redistribution layer 126 can be formed by the same process (e.g., a damascene process).

[0077] Thereafter, the semiconductor chip 200 can be mounted on the first surface 100a of the redistribution structure 100. The connection pads 210 of the semiconductor chip 200 and the bumps 230 disposed on the connection pads 210 can be disposed on the redistribution layer 120.

[0078] Thereafter, a molding member 300 can be formed to cover the semiconductor chip 200 and the first surface 100a of the redistribution structure 100.

[0079] Referring to Figure 11 A second carrier 600 can be attached on the molding member 300. The second carrier 600 can be disposed on a surface facing the first carrier 500. For example, an adhesive layer (not shown) can be further formed between the second carrier 600 and the molding member 300. The adhesive layer can include, for example, an LTHC material that can be removed together with the second carrier 600. In some embodiments, the adhesive layer can include, for example, an epoxy-based thermal dissipation material or an ultraviolet adhesive.

[0080] The second carrier 600 can include, for example, silicon, metal, glass, plastic, or ceramic. In some embodiments, the second carrier 600 can include the same material as the first carrier 500.

[0081] Thereafter, the respective semiconductor package can be flipped. Thereafter, the first carrier 500 can be removed from the semiconductor package. As a result, the release layer 510 can be exposed.

[0082] Referring to Figure 12The release layer 510 can be removed.

[0083] The release layer 510 can be irradiated with light or laser. The exposed portion of the release layer 510 can be removed by a mold development process.

[0084] Referring to Figure 13 The first barrier layer 512 can be removed. The first barrier layer 512 can be removed by, for example, wet etching. In some embodiments, the first barrier layer 512 can be removed by, for example, dry etching.

[0085] Referring to Figure 14 The sacrificial layer 514 can be removed. The sacrificial layer 514 can be removed by, for example, wet etching. In some embodiments, the sacrificial layer 514 can be removed by, for example, dry etching.

[0086] Referring to Figure 15 The second barrier layer 516 can be removed. As a result, the first redistribution layer 125 can be at least partially exposed. The electrode pad 122 of the first redistribution layer 125 can be exposed. That is, a trench 100t defined by the first insulating layer 110 and the electrode pad 122 can be formed. The trench 100t can be formed by removing the first barrier layer 512, the second barrier layer 516, and the sacrificial layer 514.

[0087] The second barrier layer 516 can be removed by, for example, wet etching. In some embodiments, the second barrier layer 516 can be removed by, for example, dry etching.

[0088] Referring to Figure 16 A solder ball 400 can be formed in the trench 100t. The solder ball 400 can include a portion disposed inside the redistribution structure 100 and a portion disposed outside the redistribution structure 100. The first redistribution layer 125 and the solder ball 400 can be at least partially surrounded by the first insulating layer 110. Accordingly, reliability of a bond between the solder ball 400 and the electrode pad 122 can be improved.

[0089] The solder ball 400 can be formed on the exposed portion of the second barrier layer 516. Accordingly, the solder ball 400 can be electrically connected to the redistribution layers (120, 125, 126, and 128).

[0090] Figure 17 and Figure 18 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to some embodiments of the inventive concept. Figure 17 The semiconductor package of Figures 4 to 10 is a semiconductor package formed by the same or similar processes as those illustrated in Figure 17 and Figure 18 will be described below with reference to a method of manufacturing a semiconductor package according to some embodiments of the inventive concept.

[0091] Referring to Figure 17 The molding member 300 can be partially etched by a planarization process. The molding member 300 can expose the top surface of the semiconductor chip 200. That is, the top surface of the molding member 300 can be disposed on the same plane as the top surface of the semiconductor chip 200.

[0092] Thereafter, referring to Figure 18 The second carrier 600 can be attached on the semiconductor chip 200 and the molding member 300. The second carrier 600 can be disposed on a surface facing the first carrier 500. For example, an adhesion layer (not shown) can be further formed between the second carrier 600, the semiconductor chip 200, and the molding member 300.

[0093] Thereafter, the corresponding semiconductor package is reversed. The first carrier 500 can be removed from the semiconductor package. As a result, the release layer 510 can be exposed.

[0094] Thereafter, the same or similar process as the process shown in Figures 13 to 16 is performed, thereby obtaining the semiconductor package of Figure 3 .

[0095] At the end of the detailed description, those skilled in the art will understand that many changes and modifications to the example embodiments described herein can be made without departing from the principles of the inventive concept. Therefore, the example embodiments of the inventive concept are used in a generic and descriptive sense, and not for purposes of limitation.

Claims

1. A method of fabricating a semiconductor package, the method comprising: forming a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including an opening exposing at least a portion of the first barrier layer; forming a second barrier layer on the first barrier layer and on the sacrificial layer, the second barrier layer including a portion formed on the sacrificial layer; forming a first insulating layer in the opening, the first insulating layer protruding beyond a top surface of the portion of the second barrier layer, a top surface of the first insulating layer being further from the first barrier layer than the top surface of the portion of the second barrier layer; forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier to the semiconductor chip and removing the first carrier; removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure; and forming solder balls on the portions of the redistribution structure, respectively, wherein the redistribution layer and the solder balls are at least partially surrounded by the first insulating layer.

2. The method of claim 1, wherein, The sacrificial layer and the redistribution layer include a same material.

3. The method of claim 1, wherein, The sacrificial layer includes a metallic material.

4. The method of claim 3, wherein, The metallic material includes copper.

5. The method of claim 1, wherein, The first barrier layer and the second barrier layer include a different material than the sacrificial layer.

6. The method of claim 1, wherein, Removing the first barrier layer, the sacrificial layer, and the second barrier layer includes performing a wet etch process.

7. The method of claim 1, wherein, The second insulating layer extends on sides of the redistribution layer, and wherein the first insulating layer and the second insulating layer include a photo- imageable dielectric material.

8. The method of claim 1, wherein, Removing the first barrier layer, the sacrificial layer, and the second barrier layer includes forming trenches in the first insulating layer.

9. The method of claim 8, wherein, Forming the solder balls includes forming the solder balls in the trenches, respectively.

10. The method of claim 9, wherein, The trenches expose portions of the redistribution layer, respectively, and the solder balls contact the portions of the redistribution layer, respectively.

11. A method of fabricating a semiconductor package, the method comprising: sequentially forming a release layer and a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including a metallic material and an opening exposing at least a portion of the first barrier layer; forming a second barrier layer extending on the first barrier layer and on the sacrificial layer; forming a first insulating layer in the opening that is thicker than the sacrificial layer; forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier to the semiconductor chip and removing the first carrier and the release layer; removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution layer; and forming solder balls on the portions of the redistribution layer, respectively, wherein the redistribution layer and the solder balls are at least partially surrounded by the first insulating layer.

12. The method of claim 11, wherein, The metallic material includes copper.

13. The method of claim 11, wherein, the first insulating layer includes a first bottom surface facing the first barrier layer and a first top surface opposite the first bottom surface, and the second barrier layer includes a second bottom surface facing the first barrier layer and a second top surface opposite the second bottom surface, and the first top surface of the first insulating layer is farther from the first barrier layer than the second top surface of the second barrier layer.

14. The method of claim 11, wherein, the first barrier layer and the second barrier layer include different materials than the sacrificial layer.

15. The method of claim 11, wherein, removing the first barrier layer, the sacrificial layer, and the second barrier layer includes sequentially removing the first barrier layer, the sacrificial layer, and the second barrier layer by performing an etching process.

16. The method of claim 11, wherein, the release layer includes the same material as the first insulating layer.

17. A method of manufacturing a semiconductor package, the method comprising: sequentially forming a release layer and a first barrier layer on a first carrier; forming a sacrificial layer on the first barrier layer, the sacrificial layer including an opening exposing at least a portion of the first barrier layer; conformally forming a second barrier layer on the first barrier layer and on the sacrificial layer; forming a first insulating layer in the opening, a top surface of the first insulating layer being farther from the first barrier layer than a top surface of a portion of the second barrier layer formed on the sacrificial layer; forming a redistribution structure on the first insulating layer and on the second barrier layer, the redistribution structure including a redistribution layer and a second insulating layer stacked on the redistribution layer to surround the redistribution layer; mounting a semiconductor chip on the redistribution structure; attaching a second carrier to the semiconductor chip and removing the first carrier; removing the release layer; sequentially removing the first barrier layer, the sacrificial layer, and the second barrier layer; and forming a solder ball in a space where the sacrificial layer has been removed, the solder ball electrically connected to the redistribution layer, wherein the redistribution layer and the solder ball are at least partially surrounded by the first insulating layer.

18. The method of claim 17, further comprising: forming a molded part covering at least a portion of the semiconductor chip and at least a portion of the redistribution structure.

19. The method of claim 18, wherein, a top surface of the molded part is coplanar with a top surface of the semiconductor chip.

20. The method of claim 17, wherein, sequentially removing the first barrier layer, the sacrificial layer, and the second barrier layer includes performing a wet etching process.

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