Chip package structure and method of manufacturing the same

Abstract

A chip package structure including a first chip stack and a redistribution layer is provided. The first chip stack includes a plurality of first chips, a first molding layer, and at least one first vertically conductive element. The plurality of first chips are stacked in sequence, wherein each of the plurality of first chips includes at least one first bonding pad, and the first bonding pads are not covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. The at least one first vertically conductive element passes through the first molding layer, wherein the at least one first vertically conductive element is disposed on and electrically connected to at least one of the first bonding pads. The redistribution layer is disposed on the first chip stack and electrically connected to the at least one first vertically conductive element.

Description

[0001] This application is a divisional application of the patent application filed on November 29, 2019, with application number 201980003370.1 and invention title "Chip Packaging Structure and Manufacturing Method Thereof". Technical Field

[0002] This invention relates to a chip packaging structure and its manufacturing method, and more specifically to a chip packaging structure having a plurality of chips stacked in sequence and its manufacturing method. Background Technology

[0003] In semiconductor manufacturing processes, packaging processes encapsulate semiconductor components, such as one or more chips, to form semiconductor package structures, thereby protecting the semiconductor components. Currently, the industry has made significant efforts to develop package structures with superior characteristics. For example, in 3D semiconductor devices (e.g., 3D memory devices), package structures are developed to possess features such as low cost, small size, short design time, strong protection, and / or preferred electrical characteristics (e.g., short electrical connection distances). However, conventional package structures cannot simultaneously meet these superior characteristics. Summary of the Invention

[0004] This invention provides a chip packaging structure having multiple chips stacked in sequence and a method for manufacturing the same.

[0005] In one embodiment, the chip package structure includes a first chip stack and a redistribution layer. The first chip stack includes a plurality of first chips, a first molding layer, and at least one first vertical conductive element. The plurality of first chips are stacked sequentially, wherein each of the plurality of first chips includes at least one first bonding pad, and the first bonding pad is not covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. The at least one first vertical conductive element passes through the first molding layer, wherein the at least one first vertical conductive element is disposed on and electrically connected to at least one of the first bonding pads. The redistribution layer is disposed on the first chip stack and electrically connected to the at least one first vertical conductive element.

[0006] In another embodiment, a method for manufacturing a chip package structure is provided. The method includes: stacking a plurality of first chips on a carrier substrate, wherein each of the plurality of first chips has at least one first bonding pad, and the first bonding pad is not covered by the plurality of first chips; forming at least one first vertical conductive element on at least one of the first bonding pads to be electrically connected to at least one of the first bonding pads; forming a first molding layer encapsulating the plurality of first chips to form a first chip stack, wherein the at least one first vertical conductive element passes through the first molding layer, and the first chip stack includes the plurality of first chips, the at least one first vertical conductive element, and the first molding layer; and forming a redistribution layer on the first molding layer to be electrically connected to the at least one first vertical conductive element.

[0007] Due to the design of the chip packaging structure of the present invention, the chip packaging structure has a reduced lateral dimension and can shorten the signal transmission path between the chip in the chip packaging structure and external devices. Furthermore, it can reduce the design time and cost of the chip packaging structure. On the other hand, in the manufacturing process, the reliability of the chip packaging structure can be improved when chip misalignment exists.

[0008] These and other objectives of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of preferred embodiments illustrated in the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a first embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a second embodiment of the present invention.

[0011] Figure 3 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a third embodiment of the present invention.

[0012] Figure 4 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a fourth embodiment of the present invention.

[0013] Figure 5 This is a flowchart illustrating a method for manufacturing a chip packaging structure according to an embodiment of the present invention.

[0014] Figures 6A to 6K These are schematic diagrams illustrating the states in a manufacturing method of a chip packaging structure according to embodiments of the present invention.

[0015] Figure 7This is a flowchart illustrating a method for manufacturing a chip packaging structure according to another embodiment of the present invention.

[0016] Figure 8 This is a schematic diagram illustrating the state in a method for manufacturing a chip packaging structure according to another embodiment of the present invention. Detailed Implementation

[0017] Although specific configurations and arrangements have been discussed, it should be understood that the discussion is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used in a wide variety of other applications.

[0018] Throughout this specification and the claims below, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to components. This document is not intended to distinguish between components with different names but different functions. In the following description and claims, the words “comprising,” “including,” and “having” are used in an open-ended manner and should therefore be interpreted as “including, but not limited to…”. Thus, when the words “comprising,” “including,” and / or “having” are used in the description of this disclosure, the corresponding feature, area, step, operation, and / or component is specified as present, but not limited to the presence of one or more of the stated corresponding feature, area, step, operation, and / or component.

[0019] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," or "some embodiments" in the specification indicates that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when describing a specific feature, structure, or characteristic in conjunction with embodiments, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0020] Generally speaking, terms should be understood at least in part by their use in context. For example, the word "one or more" can be used, at least in part by context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the words "a," "one," or "the" can be understood to convey either a singular or a plural usage, at least in part by context.

[0021] It should be readily understood that the terms “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only being directly on something, but also being contained on something with an intermediate feature or layer therebetween, and “above” or “on top of” means not only being above or on something, but also being contained above or on something without an intermediate feature or layer therebetween (i.e., being directly on something).

[0022] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0023] The term "substrate" as used in this text refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be formed from non-conductive materials, such as glass, plastic, or sapphire wafers.

[0024] As used herein, the term "layer" can refer to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (forming contacts, interconnect lines, and / or vias therein) and one or more dielectric layers.

[0025] As used herein, the term "nominal / nominally" refers to the expected or target value of a feature or parameter of a component or process operation set during the design phase of a product or process, along with a range of values ​​higher and / or lower than said expected value. This range may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "around" means that a given value can vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, "around" can indicate that a given value can vary within, for example, 10% to 30% of that value (e.g., ±10%, ±20%, or 30% of that value).

[0026] Although terms such as first, second, third, etc., may be used to describe different constituent elements, such constituent elements are not limited by these terms. These terms are used only to distinguish one constituent element from others in the specification. These terms are not intended to order the constituent elements, and / or to order the manufacturing process of the constituent elements. The claims may not use the same terms, but may use terms such as first, second, third, etc., relative to the order in which the elements are claimed. Accordingly, the first constituent element in the following description may be the second constituent element in the claims.

[0027] refer to Figure 1 , Figure 1 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a first embodiment of the present invention. Figure 1 As shown, the chip package structure 100 includes a first chip stack CS1 and a redistribution layer 140. In this embodiment, the first chip stack CS1 includes a plurality of first chips 110, a first molding layer 130, and at least one first vertical conductive element 120, but is not limited thereto. Any other suitable components may optionally be included in the first chip stack CS1.

[0028] The first chip 110 may be formed using semiconductor fabrication processes, and the first chip 110 may be the same or different. For example, in some embodiments, the first chip 110 may be the same and have storage functionality; in some embodiments, the first chip 110 may be different and may have the same or different functionality, but is not limited thereto. Any type of chip can be selected as the first chip 110 based on requirements. Furthermore, in some embodiments, the first chip 110 may have a substrate and electronic components disposed on the substrate. The electronic components may include 2D memory cells, 3D memory cells, and / or other suitable components. For example, the electronic components may be 3D memory cells, such that the first chip 110 can have storage functionality, and the chip package structure 100 may be a 3D memory device, but is not limited thereto. Note that the term "3D memory device" refers to a semiconductor device having a vertically oriented string of memory cell transistors (i.e., referred to herein as a "memory string") situated on a laterally oriented substrate, such that the memory string extends vertically relative to the substrate.

[0029] exist Figure 1 In this embodiment, the first chip stack CS1 includes four first chips 110 stacked sequentially (i.e., 110a, 110b, 110c, and 110d, respectively), but is not limited thereto. In this embodiment, the first chips 110 can be adhered to each other via multiple die attachment films (DAFs) 114, wherein the die attachment films 114 can be respectively disposed on the bottom surfaces of three of the first chips 110b, 110c, and 110d, but is not limited thereto. Furthermore, each of the first chips 110 includes at least one first bonding pad 112, which is configured as a component of a signal transmission path between the corresponding first chip 110 and an external device (such as a signal source or power supply). To enable... Figure 1 Simple and clear, Figure 1 Only one first bonding pad 112 is shown for each of the first chips 110; however, in practice, each of the first chips 110 may have one or more first bonding pads 112. The first bonding pad 112 may include at least one conductive material, such as a metal and / or a transparent conductive material, but is not limited thereto. The first bonding pad 112 is not covered by the first chip 110, allowing conductive elements (such as vertical conductive elements and / or interconnects discussed below) to be disposed on and electrically connected to the first bonding pad 112. In this embodiment, Figure 1 The first chip 110 shown is stacked in a stepped manner to expose the first bonding pad 112, but is not limited thereto.

[0030] The first molding layer 130 may encapsulate and cover the first chip 110 to protect the first chip 110 and reduce physical and / or chemical damage (such as oxidation, damage caused by moisture) to the first chip 110. The first molding layer 130 may include epoxy resin and / or any other suitable molding compound.

[0031] Each first vertical conductive element 120 can be disposed on and electrically connected to at least one of the first bonding pads 112. Figure 1 In this embodiment, the first chip stack CS1 includes a plurality of first vertical conductive elements 120, and each of the first vertical conductive elements 120 may be disposed on one of the first bonding pads 112, but is not limited thereto. Moreover, in this embodiment, each of the first vertical conductive elements 120 may contact a corresponding first bonding pad 112, but is not limited thereto.

[0032] Furthermore, the first vertical conductive element 120 can pass through the first molding layer 130, allowing the first chip 110 to be electrically connected to components disposed on the first molding layer 130. Figure 1 In this embodiment, the extension direction of the first vertical conductive element 120 may be substantially parallel to the normal direction Dn of the first chip stack CS1 (i.e., the direction perpendicular to the surface of the first chip stack CS1), but is not limited thereto. Furthermore, the first vertical conductive element 120 may include at least one conductive material, such as gold, copper, aluminum, silver, and / or other suitable metals, but is not limited thereto.

[0033] A redistribution layer 140 is disposed on the first chip stack CS1 and is electrically connected to the first vertical conductive element 120. In detail, the redistribution layer 140 may include at least one conductive layer 142 and at least one insulating layer 144, wherein the conductive layer 142 may be electrically connected to the first vertical conductive element 120. The conductive layer 142 may include a metal, any other suitable conductive material, or a combination thereof, and the insulating layer 144 may include an organic or inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, any other suitable insulating material, or a combination thereof). In some embodiments, such as Figure 1 As shown, the redistribution layer 140 may include a conductive layer 142 and an insulating layer 144. In some embodiments (not shown in the figures), the redistribution layer 140 may include multiple conductive layers 142 and multiple insulating layers 144.

[0034] exist Figure 1 In the redistribution layer 140, the insulating layer 144 may have multiple openings 146 to expose multiple portions of the conductive layer 142. Furthermore, as... Figure 1As shown, the chip package structure 100 may further include a plurality of solder balls 150 in contact with the exposed portion of the conductive layer 142. That is, each of the solder balls 150 corresponds to one of the openings 146. In this case, each of the solder balls 150 may function as a signal input / output terminal. Through the solder balls 150 (i.e., signal input / output terminals), signals from external devices can be input into the chip package structure 100, and / or signals from the chip package structure 100 can be output to external devices. Note that each of the solder balls 150 may be electrically connected to at least one of the first vertical conductive elements 120.

[0035] Specifically, the solder balls 150 may be arranged by designing the redistribution layer 140. Therefore, the chip package structure 100 can be more easily bonded to a circuit board for electrical connection to external devices. In some embodiments, the distance between two adjacent solder balls 150 may be greater than the distance between two adjacent first vertical conductive elements 120 corresponding to these solder balls 150, but is not limited thereto. In some embodiments, the chip package structure 100 may be a fan-out package, but is not limited thereto.

[0036] Because the first chips 110 are stacked together, the lateral dimension of the chip package structure can be reduced. Since the chip package structure 100 uses the first vertical conductive element 120 and the redistribution layer 140, instead of conventional wire bonding technology (i.e., bent wires bonded between pads and bonding substrates), the lateral dimension of the chip package structure 100 can be further reduced (because the ends of the bent wires cannot be too close together), and the signal transmission path between the first chip 110 and external devices can be shortened. Furthermore, the bonding substrate used in conventional wire bonding technology is not present within the chip package structure 100, thus saving design time and cost for the bonding substrate. On the other hand, in the manufacturing process of the chip package structure 100, when there is an offset of the first chip 110, the reliability of forming the first vertical conductive element 120 and the redistribution layer 140 is higher than that of conventional wire bonding technology.

[0037] The chip package structure 100 may optionally include any other suitable components or structures. For example, in Figure 1 In this embodiment, the chip package structure 100 may further include a protective layer 160 disposed on the side of the first chip stack CS1 opposite to the redistribution layer 140. The protective layer 160 is configured to provide stress compensation for the chip package structure 100 to reduce package warpage.

[0038] The chip packaging structure of the present invention is not limited to the embodiments described above. Other embodiments of the present invention will be described below. For ease of comparison, the same reference numerals will be used to designate the same components in the following description. The following description addresses the differences between each of the embodiments, and repeated parts will not be described in detail again.

[0039] refer to Figure 2 , Figure 2 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a second embodiment of the present invention. In order to... Figure 2 Simple and clear Figure 2 Only one first bonding pad 112 is shown for each of the first chips 110; however, in practice, each of the first chips 110 may have one first bonding pad 112 or multiple first bonding pads 112. Figure 2 As shown, the difference between this embodiment and the first embodiment is that the chip package structure 200 in this embodiment further includes at least one connecting wire 210, and each connecting wire 210 is electrically connected between two of the first bonding pads 112, which belong to two first chips in the first chip 110 respectively, so that one of the first vertical conductive elements 120 can be electrically connected to at least two of the first chips 110. For example, Figure 2A connecting wire 210 is shown electrically connected between two first bonding pads belonging to two first chips 110c and 110d respectively in the first bonding pad 112, and an uppermost first vertical conductive element 120 is electrically connected to these two first chips 110c and 110d, but is not limited thereto. The connecting wire 210 can be provided in any other suitable location, and any suitable number of connecting wires 210 can be used based on requirements. As an example, in some embodiments, one connecting wire 210 is electrically connected between two first bonding pads 112 belonging to two first chips 110c and 110d respectively in the first bonding pad 112, and another connecting wire 210 is electrically connected between two first bonding pads 112 belonging to two first chips 110b and 110c respectively in the first bonding pad 112, such that the uppermost first vertical conductive element 120 (or another first vertical conductive element 120) is electrically connected to these three first chips 110b, 110c, and 110d, but is not limited thereto. As another example, in some embodiments, a connecting wire 210 is electrically connected between two first bonding pads 112 belonging to two first chips 110c and 110d respectively, another connecting wire 210 is electrically connected between two first bonding pads 112 belonging to two first chips 110b and 110c respectively, and yet another connecting wire 210 is electrically connected between two first bonding pads 112 belonging to two first chips 110a and 110b respectively, such that the uppermost first vertical conductive element 120 (or another first vertical conductive element 120) is electrically connected to these four first chips 110a-110d, but is not limited thereto.

[0040] Furthermore, the connecting wire 210 may be formed by a wire bonding process, and the connecting wire 210 may include at least one conductive material, such as gold, copper, aluminum, silver and / or other suitable metals, but is not limited thereto.

[0041] refer to Figure 3 , Figure 3 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a third embodiment of the present invention. In order to... Figure 3 Simple and clear Figure 3 Only one first bonding pad 112 is shown for each of the first chips 110; however, in practice, each of the first chips 110 may have one first bonding pad 112 or multiple first bonding pads 112. Figure 3As shown, the difference between this embodiment and the first embodiment is that the chip package structure 300 in this embodiment further includes a second chip stack CS2 disposed between the first chip stack CS1 and the redistribution layer 140. The second chip stack CS2 may include, but is not limited to, a plurality of second chips 310, a second molding layer 330, and at least one second vertical conductive element 320. Any other suitable components may optionally be included in the second chip stack CS2.

[0042] The second chip 310 may be formed using semiconductor fabrication processes, and the second chip 310 may be the same as or different from other chips. For example, in some embodiments, the second chip 310 may be the same and have storage functionality; in some embodiments, the second chip 310 may be different and may have the same or different functionality, but is not limited thereto. Any type of chip can be selected as the second chip 310 based on requirements. Furthermore, in some embodiments, the second chip 310 may have a substrate and electronic components disposed on the substrate. The electronic components may include 2D memory cells, 3D memory cells, and / or other suitable components.

[0043] In some embodiments, at least one of the second chips 310 may be the same as at least one of the first chips 110, but is not limited thereto. In some embodiments, all the second chips 310 may be different from all the first chips 110.

[0044] exist Figure 3 In this embodiment, the second chip stack CS2 includes four second chips 310 stacked sequentially (i.e., 310a, 310b, 310c, and 310d, respectively), but is not limited thereto. In this embodiment, the second chips 310 can be adhered to each other via multiple die attachment films 314, wherein the die attachment films 314 can be respectively disposed on the bottom surfaces of three second chips 310b, 310c, and 310d, but is not limited thereto. Furthermore, each of the second chips 310 includes at least one second bonding pad 312, which functions as a component in the signal transmission path between the corresponding second chip 310 and external devices. To enable... Figure 3 Simple and clear Figure 3 Only one second bonding pad 312 is shown for each of the second chips 310; however, in practice, each of the second chips 310 may have one or more second bonding pads 312. The second bonding pad 312 may include at least one conductive material, such as a metal and / or a transparent conductive material, but is not limited thereto. The second bonding pad 312 is not covered by the second chip 310, allowing conductive elements (discussed below) to be disposed on and electrically connected to the second bonding pad 312. In this embodiment, Figure 3The second chip 310 shown is stacked in a stepped manner to expose the second bonding pad 312, but is not limited thereto.

[0045] The second molding layer 330 may encapsulate and cover the second chip 310 to protect the second chip 310 and reduce physical and / or chemical damage (such as oxidation, damage caused by moisture) to the second chip 310. The second molding layer 330 may include epoxy resin and / or any other suitable molding compound. In some embodiments, the material of the second molding layer 330 may be the same as, but is not limited to, the material of the first molding layer 130.

[0046] Each second vertical conductive element 320 can be disposed on and electrically connected to at least one of the second bonding pads 312. Figure 3 In this embodiment, the second chip stack CS2 includes a plurality of second vertical conductive elements 320, and each of the second vertical conductive elements 320 may be disposed on one of the second bonding pads 312, but is not limited thereto. Moreover, in this embodiment, each of the second vertical conductive elements 320 may contact a corresponding second bonding pad 312, but is not limited thereto.

[0047] Furthermore, the second vertical conductive element 320 can pass through the second molding layer 330, allowing the second chip 310 to be electrically connected to components disposed on the second molding layer 330. Figure 3 In this embodiment, the extension direction of the second vertical conductive element 320 may be substantially parallel to the normal direction of the second chip stack CS2 (i.e., the direction perpendicular to the surface of the second chip stack CS2), but is not limited thereto. In some embodiments, the extension direction of the second vertical conductive element 320 may be substantially parallel to the extension direction of the first vertical conductive element 120 (i.e., the extension direction of the second vertical conductive element 320 is substantially parallel to the normal direction Dn of the first chip stack CS1), but is not limited thereto. Furthermore, the second vertical conductive element 320 may comprise at least one conductive material, such as gold, copper, aluminum, silver and / or other suitable metals, but is not limited thereto. In some embodiments, the material of the second vertical conductive element 320 may be the same as the material of the first vertical conductive element 120, but is not limited thereto.

[0048] exist Figure 3 In this configuration, the redistribution layer 140 is electrically connected to the second vertical conductive element 320. Similarly, in the redistribution layer 140, the insulating layer 144 may further have more openings 146, thereby exposing more portions of the conductive layer 142, and each of the solder balls 150 corresponding to one of the openings 146 may be electrically connected to at least one of the first vertical conductive elements 120 and / or at least one of the second vertical conductive elements 320.

[0049] Specifically, the function of the first chip stack CS1 can be the same as or different from the function of the second chip stack CS2. Moreover, the number of the first chips 110 can be the same as or different from the number of the second chips 310.

[0050] Furthermore, the chip package structure 300 may further include a die attachment film 340 disposed on the bottom surface of the second chip stack CS2, such that the second chip stack CS2 can be adhered to the first chip stack CS1 through the die attachment film 340. Figure 3 In this configuration, the second chip stack CS2 is stacked on top of the first chip stack CS1 in a stepped manner, but is not limited thereto. Furthermore, in some embodiments, the first vertical conductive element 120 and the second vertical conductive element 320 may be located at different portions relative to the center of the chip package structure 300. For example, in... Figure 3 In this embodiment, the first vertical conductive element 120 may be located on the left side of the chip package structure 300 relative to its center, and the second vertical conductive element 320 may be located on the right side of the chip package structure 300 relative to its center, but is not limited thereto. In some embodiments, the first vertical conductive element 120 and the second vertical conductive element 320 may be located at the same portion relative to the center of the chip package structure 300. For example, the first vertical conductive element 120 and the second vertical conductive element 320 may be located on the left side of the chip package structure 300 relative to its center. Furthermore, Figure 3 The second chip stack CS2 shown does not cover the first bonding pad 112 and the first vertical conductive element 120, but is not limited thereto.

[0051] Specifically, the chip package structure 300 may further include a third molding layer 360 and at least one third vertical conductive element 350. The third molding layer 360 may encapsulate the first chip stack CS1 and the second chip stack CS2. Figure 3 In this process, the third molding layer 360 can be filled into the gaps between the first chip stack CS1 and the redistribution layer 140, and between the second chip stack CS2 and the protective layer 160. The third molding layer 360 may include epoxy resin and / or any other suitable molding compound. In some embodiments, the material of the third molding layer 360 may be the same as, but not limited to, the material of the first molding layer 130 and / or the second molding layer 330.

[0052] Each third vertical conductive element 350 can be disposed on and electrically connected to one of the first vertical conductive elements 120, and each third vertical conductive element 350 can be electrically connected to the redistribution layer 140. That is, the first bonding pad 112 of the first chip 110 can be electrically connected to the redistribution layer 140 through the first vertical conductive element 120 and the third vertical conductive element 350. Figure 3In the chip package structure 300, there are multiple third vertical conductive elements 350, and each of the third vertical conductive elements 350 can contact a corresponding first vertical conductive element 120, but is not limited thereto.

[0053] Furthermore, the third vertical conductive element 350 can pass through the third molding layer 360. Figure 3 In this embodiment, the extension direction of the third vertical conductive element 350 may be substantially parallel to the normal direction Dn of the first chip stack CS1, but is not limited thereto. In some embodiments, the extension direction of the third vertical conductive element 350 may be substantially parallel to the extension direction of the first vertical conductive element 120 and / or the extension direction of the second vertical conductive element 320, but is not limited thereto. Furthermore, the second vertical conductive element 320 may include at least one conductive material, such as gold, copper, aluminum, silver and / or other suitable metals, but is not limited thereto. In some embodiments, the material of the third vertical conductive element 350 may be the same as the material of the first vertical conductive element 120 and / or the material of the second vertical conductive element 320, but is not limited thereto.

[0054] In some embodiments, the chip package structure 300 may further include other chip stacks disposed between the second chip stack CS2 and the redistribution layer 140. In this case, the third molding layer 360 may also encapsulate the chip stack disposed between the second chip stack CS2 and the redistribution layer 140.

[0055] Therefore, since the chips are stacked, the lateral dimension of the chip package structure 300 can be reduced. Furthermore, the use of vertical conductive elements further reduces the lateral dimension of the chip package structure 300. On the other hand, during manufacturing, the reliability of forming the vertical conductive elements and the redistribution layer 140 is higher than that of conventional wire bonding techniques when chip misalignment occurs.

[0056] refer to Figure 4 , Figure 4 This is a schematic diagram showing a cross-sectional view of a chip packaging structure according to a fourth embodiment of the present invention. In order to... Figure 4 Simple and clear Figure 4 Only one first bonding pad 112 is shown, and one second bonding pad 312 is shown for each of the first chips 110; however, in practice, each of the first chips 110 may have one or more first bonding pads 112, and each of the second chips 310 may have one or more second bonding pads 312. Figure 4As shown, the difference between this embodiment and the third embodiment is that the first chip stack CS1 of the chip package structure 400 in this embodiment further includes a sub-redistribution layer 440, wherein the sub-redistribution layer 440 is disposed between the first vertical conductive element 120 and the third vertical conductive element 350. In other words, the sub-redistribution layer 440 is located on the first molding layer 130.

[0057] The sub-redistribution layer 440 has a similar structure to the redistribution layer 140. In detail, the sub-redistribution layer 440 may include at least one conductive layer 442 and at least one insulating layer 444, wherein the conductive layer 442 may be electrically connected between the first vertical conductive element 120 and the third vertical conductive element 350. The conductive layer 442 may include a metal, any other suitable conductive material, or a combination thereof, and the insulating layer 444 may include an organic or inorganic material. In some embodiments, such as... Figure 3 As shown, the sub-redistribution layer 440 may include a conductive layer 442 and an insulating layer 444. In some embodiments (not shown in the figures), the sub-redistribution layer 440 may include multiple conductive layers 142 and multiple insulating layers 144.

[0058] exist Figure 4 In this configuration, due to the sub-redistribution layer 440, the third vertical conductive element 350 does not necessarily need to be directly disposed on the corresponding first vertical conductive element 120. That is, the corresponding third vertical conductive element 350 and the first vertical conductive element 120 can be staggered within the normal direction Dn of the first chip stack CS1. Therefore, the third vertical conductive element 350 can be disposed in any other suitable location. Furthermore, in this case, Figure 4 The second chip stack CS2 shown may overlap with the first bonding pad 112 and the uppermost first vertical conductive element 120 of the first chip 110d, but is not limited thereto. Therefore, the overlap area between the first chip stack CS1 and the second chip stack CS2 is increased, thereby reducing the lateral dimension of the chip package structure 400.

[0059] An exemplary method for manufacturing the aforementioned chip package structure is disclosed below.

[0060] refer to Figure 5 , Figure 5 This is a flowchart illustrating a method for manufacturing a chip packaging structure according to an embodiment of the present invention. It should be understood that... Figure 5 The flowchart shown is merely exemplary. In some embodiments, it may be performed simultaneously or in accordance with... Figure 5 Some of the steps are performed in different orders as shown. In some embodiments, any other appropriate steps may be added to method 500 before or after one of the existing steps of method 500. Reference will be made to the following content. Figure 5 Method 500 is described. However, method 500 is not limited to these exemplary embodiments.

[0061] For a clearer explanation of method 500, please refer to further references. Figures 6A to 6K as well as Figure 3 . Figures 6A to 6K These are schematic diagrams illustrating various states of a manufacturing method for a chip package structure 300 according to an embodiment of the present invention. Note that further reference... Figures 6A to 6K as well as Figure 3 , to show Figure 3 The manufacturing process of the chip package structure 300 shown (i.e., the chip package structure 300 of the third embodiment).

[0062] exist Figure 5 In step 510a, the first chip 110 is stacked onto the carrier board CB1 (e.g., Figure 6A (As shown). For example, in Figure 6A In this configuration, the first chips 110 are stacked in a stepped manner, so that the first bonding pads 112 are not covered by the first chips 110. In addition, a die attachment film 114 can be disposed on the bottom surface of some of the first chips 110b, 110c and 110d, so that the first chips 110 can adhere to each other.

[0063] exist Figure 5 In step 520a, a first vertical conductive element 120 is formed onto the first bonding pad 112, thereby electrically connecting to the first bonding pad 112 (e.g., Figure 6B (as shown in the diagram). In some embodiments, the first vertical conductive element 120 may be formed by a bonding process, wherein one end of the first vertical conductive element 120 is bonded to the first bonding pad 112, while the other end of the first vertical conductive element 120 does not come into contact with anything. Thus, the extension direction of the first vertical conductive element 120 may be substantially parallel to the normal direction Dn of the first chip stack CS1.

[0064] Optionally, in some embodiments, a connecting wire 210 (see reference) may be formed between two first bonding pads belonging to two first chips 110, respectively, in the first bonding pad 112. Figure 2 (but not limited to this).

[0065] exist Figure 5 In step 530a, a first molding layer 130 is formed to encapsulate the first chip 110, thereby forming a first chip stack CS1 (e.g., Figure 6C and Figure 6D As shown in the figure, the first chip stack CS1 includes a first chip 110, a first vertical conductive element 120 and a first molding layer 130.

[0066] In terms of details, such as Figure 6C As shown, the first molding layer 130 is formed to cover the first chip 110 and the first vertical conductive element 120. Then, as... Figure 6D As shown, the surface of the first molding layer 130 is thinned to expose the end of each first vertical conductive element 120. In other words, the step of forming the first molding layer 130 may include thinning the surface of the first molding layer 130 to expose the end of each first vertical conductive element 120. Therefore, the first vertical conductive element 120 can be electrically connected to a component formed on the first molding layer 130 in a subsequent manufacturing process. Furthermore, this thinning step employs chemical mechanical polishing (CMP) or any other suitable process. Additionally, after the first molding layer 130 is formed, the first vertical conductive element 120 can extend through the first molding layer 130.

[0067] Optionally, in some embodiments, after the formation of the first molding layer 130, the sub-redistribution layer 440 (see reference) Figure 4 It can be formed onto the first molding layer 130, but is not limited thereto.

[0068] exist Figure 5 In step 510b, the second chip 310 is stacked onto the carrier board CB1 (e.g., Figure 6A (As shown). For example, in Figure 6A In this configuration, the second chips 310 are stacked in a stepped manner, so that the second bonding pads 312 are not covered by the second chips 310. In addition, a die attachment film 314 can be disposed on the bottom surface of some of the second chips 310b, 310c and 310d, so that the second chips 310 can adhere to each other.

[0069] exist Figure 5 In step 520b, the second vertical conductive element 320 is formed onto the second bonding pad 312, thereby electrically connecting to the second bonding pad 312 (e.g., Figure 6B (As shown in the diagram). In some embodiments, the second vertical conductive element 320 may be formed by a bonding process, wherein one end of the second vertical conductive element 320 is bonded to the second bonding pad 312, while the other end of the second vertical conductive element 320 does not contact anything. Thus, the extension direction of the second vertical conductive element 320 may be substantially parallel to the normal direction of the second chip stack CS2 (e.g., in some embodiments, the second vertical conductive element 320 may be substantially parallel to the normal direction Dn of the first chip stack CS1).

[0070] exist Figure 5 In step 530b, a second molding layer 330 is formed to encapsulate the second chip 310, thereby forming a second chip stack CS2 (e.g., Figure 6C and Figure 6D As shown in the figure, the second chip stack CS2 includes a second chip 310, a second vertical conductive element 320, and a second molding layer 330.

[0071] In terms of details, such as Figure 6C As shown, the second molding layer 330 is formed to cover the second chip 310 and the second vertical conductive element 320. Then, as... Figure 6D As shown, the surface of the second molding layer 330 is thinned to expose the end of each second vertical conductive element 320, allowing the second vertical conductive element 320 to be electrically connected to a component formed on the second molding layer 330 in a subsequent manufacturing process. Furthermore, this thinning step employs chemical mechanical polishing (CMP) or any other suitable process. Additionally, after the second molding layer 330 is formed, the second vertical conductive element 320 can extend through the second molding layer 330.

[0072] In some embodiments, such as Figure 5 and Figure 6A As shown, the carrier board in step 510a can be the same as the carrier board in step 510b; that is, the first chip 110 and the second chip 310 can be stacked on the same carrier board CB1, but are not limited thereto. Therefore, steps 510a and 510b can be performed simultaneously. In some embodiments (not shown in the figures), the carrier board in step 510a can be different from the carrier board in step 510b, and steps 510a and 510b can be performed at different times.

[0073] In some embodiments, such as Figure 5 as well as Figures 6B to 6D As shown, steps 520a and 520b can be performed simultaneously, and steps 530a and 530b can be performed simultaneously, such that the first chip stack CS1 and the second chip stack CS2 are formed on the same carrier board CB1, and the first molding layer 130 and the second molding layer 330 are formed of the same material, but are not limited thereto. Figure 6C and Figure 6D As shown, the first molding layer 130 and the second molding layer 330 are directly connected to each other, but are not limited thereto.

[0074] Subsequently, in some embodiments, a certain step may be added to method 500. For example, due to... Figure 6D The first chip stack CS1 and the second chip stack CS2 are formed on the same carrier board CB1, thus performing the steps of removing the carrier board CB1 and separating the first chip stack CS1 from the second chip stack CS2. More precisely, as Figure 6EAs shown, the carrier substrate CB1 can be removed, allowing the first chip stack CS1 and the second chip stack CS2 to be separated from the carrier substrate CB1. In some embodiments, a debonding process can be performed to separate the first chip stack CS1 and the second chip stack CS2 from the carrier substrate CB1, but this is not a limitation. Subsequently, the first chip stack CS1 and the second chip stack CS2 can be separated from each other. In some embodiments, a dicing process can be performed to separate the first chip stack CS1 from the second chip stack CS2, but this is not a limitation. Optionally, after separating the first chip stack CS1 from the second chip stack CS2, a die attachment film 340 can be further formed on the bottom surface of the second chip stack CS2.

[0075] exist Figure 5 In step 540, the second chip stack CS2 is stacked onto the first chip stack CS1 (e.g., ...). Figure 6F (As shown in the diagram). In detail, a first chip stack CS1 can be mounted on another carrier board CB2, after which a second chip stack CS2 is stacked on top of the first chip stack CS1, wherein the carrier board CB2 may be the same as or different from the aforementioned carrier board CB1. For example, in... Figure 6F In this configuration, the second chip stack CS2 can be stacked onto the first chip stack CS1 in a stepped manner, such that the first bonding pad 112 is not covered by the second chip stack CS2. Furthermore, in some embodiments, the second chip stack CS2 and the first chip stack CS1 are adhered to each other by a die attachment film 340 formed on the bottom surface of the second chip stack CS2.

[0076] exist Figure 5 In step 550, a third vertical conductive element 350 is formed onto the first vertical conductive element 120, thereby electrically connecting it to the first vertical conductive element 120 (e.g., Figure 6G (As shown in the diagram). The formation process of the third vertical conductive element 350 is similar to that of the first vertical conductive element 120. In some embodiments, the third vertical conductive element 350 may be formed by a bonding process, wherein one end of the third vertical conductive element 350 is bonded to the first vertical conductive element 120, while the other end of the third vertical conductive element 350 does not come into contact with anything. Thus, the extension direction of the third vertical conductive element 350 may be substantially parallel to the normal direction Dn of the first chip stack CS1.

[0077] exist Figure 5 In step 560, a third molding layer 360 is formed to encapsulate the first chip stack CS1 and the second chip stack CS2 (e.g., Figure 6H and Figure 6I (As shown). In detail, as Figure 6HAs shown, the third molding layer 360 is formed to cover the first chip stack CS1, the second chip stack CS2, and the third vertical conductive element 350. Then, as... Figure 6I As shown, the surface of the third molding layer 360 is thinned to expose the ends of each third vertical conductive element 350 and each second vertical conductive element 320. Therefore, the third vertical conductive elements 350 and the second vertical conductive elements 320 can be electrically connected to components formed in subsequent manufacturing processes. Furthermore, this thinning step employs chemical mechanical polishing or any other suitable process. Additionally, after the third molding layer 360 is formed, the third vertical conductive elements 350 can extend through the third molding layer 360.

[0078] exist Figure 5 In step 570, a redistribution layer 140 is formed onto the first chip stack CS1 and the second chip stack CS2, thereby electrically connecting to the first vertical conductive element 120, the second vertical conductive element 320, and the third vertical conductive element 350 (e.g., Figure 6J (As shown in the diagram). The redistribution layer 140 may include at least one conductive layer 142 and at least one insulating layer 144, wherein the conductive layer 142 may be electrically connected to the first vertical conductive element 120. Figure 6J In, for example, conductive layer 142 may be formed on and patterned onto the first chip stack CS1 and the second chip stack CS2 to be electrically connected to the first vertical conductive element 120, the second vertical conductive element 320 and the third vertical conductive element 350 (in Figure 6J In this process, the conductive layer 142 may contact the ends of the first vertical conductive element 120, the second vertical conductive element 320, and the third vertical conductive element 350; subsequently, an insulating layer 144 may be formed on the conductive layer 142, and the insulating layer 144 may be patterned to form openings 146 exposing multiple portions of the conductive layer 142, but is not limited thereto. Furthermore, the conductive layer 142 and the insulating layer 144 may be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; and the conductive layer 142 and the insulating layer 144 may be patterned by (but not limited to) photolithography.

[0079] Furthermore, a plurality of solder balls 150 may be formed on the redistribution layer 140. More precisely, the solder balls 150 may be formed on the redistribution layer 140 and correspond to the openings 146.

[0080] After that, Figure 6K In this process, the carrier board CB2 can be removed. In some embodiments, a debonding process can be performed to separate the first chip stack CS1 from the carrier board CB2, but this is not a limitation.

[0081] Optionally, the protective layer 160 can be formed on the side of the first chip stack CS1 opposite to the redistribution layer 140, thereby completing Figure 3 The chip package structure 300 shown is illustrated. In some embodiments, the protective layer 160 may be adhered to the first chip stack CS1, but is not limited thereto.

[0082] refer to Figure 7 , Figure 7 This is a flowchart of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. It should be understood that... Figure 7 The flowchart shown is merely exemplary. In some embodiments, it may be performed simultaneously or in accordance with... Figure 7 Some of the steps are performed in different orders as shown. In some embodiments, any other appropriate steps may be added to method 700 before or after one of the existing steps of method 700. Reference will be made to the following content. Figure 7 Method 700 is described. However, method 700 is not limited to these exemplary embodiments.

[0083] For a clearer explanation of method 700, please refer to further information. Figures 6A to 6D , Figure 8 as well as Figure 1 . Figure 8 This is a schematic diagram illustrating the state in a method for manufacturing a chip package structure according to another embodiment of the present invention. Note that further reference... Figures 6A to 6D , Figure 8 as well as Figure 1 , to show Figure 1 The manufacturing process of the chip package structure 100 shown (i.e., the chip package structure 100 of the first embodiment).

[0084] right Figure 7 The explanations for steps 510a, 520a, and 530a can be found in the above content and... Figure 5 Therefore, steps 510a, 520a, and 530a will no longer be described redundantly. Note that in this embodiment, it is not necessary to form Figures 6A to 6D The second chip stack CS2 is shown in the diagram.

[0085] exist Figure 7 In step 740, a redistribution layer 140 is formed on the first chip stack CS1, thereby electrically connecting it to the first vertical conductive element 120 (e.g., Figure 8 (As shown in the diagram). The method for forming the redistribution layer 140 can be referred to the above description, and redundant descriptions will not be made for repeated parts. In addition, solder balls 150 can be formed on the redistribution layer 140 and correspond to the openings 146.

[0086] The carrier board CB1 can then be removed. In some embodiments, a debonding process can be performed to separate the first chip stack CS1 from the carrier board CB1, but this is not a limitation.

[0087] Optionally, the protective layer 160 can be formed on the side of the first chip stack CS1 opposite to the redistribution layer 140, thereby completing Figure 1 The chip packaging structure 100 shown is shown.

[0088] In summary, due to the design of the chip package structure of the present invention, the chip package structure has a reduced lateral dimension and can shorten the signal transmission path between the chip in the chip package structure and external devices. Furthermore, it can reduce the design time and cost of the chip package structure. On the other hand, in the manufacturing process, the reliability of the chip package structure can be improved when chip misalignment exists.

[0089] The foregoing description of specific embodiments will fully reveal the overall essence of this disclosure. Those skilled in the art can easily modify and / or adjust such specific embodiments for various applications without departing from the overall principles of this disclosure, by applying their knowledge in the art, without extensive experimentation. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed embodiments and their equivalents. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes; therefore, those skilled in the art should interpret the terminology or terminology of this specification in accordance with the teachings and guidance provided.

[0090] The foregoing description of embodiments of this disclosure uses functional building blocks to illustrate implementations of the specified functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined. Alternative boundaries may be defined, provided that the specified functions and their relationships are appropriately performed.

[0091] The summary and abstract sections may set forth one or more exemplary embodiments of the present disclosure as conceived by the inventors, but not all of them, and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0092] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A chip packaging structure, comprising: Chip stacking, including: Multiple chips stacked together, each of the multiple chips including bonding pads not covered by the multiple chips; A molding layer encapsulating the plurality of chips, wherein the molding layer comprises: a first molding layer separating a first subset of the plurality of chips from a second subset of the plurality of chips; a second molding layer located on a second side of the second subset of the plurality of chips; and a third molding layer comprising a first portion located on the second side of the first subset of the plurality of chips and a second portion located on the first side of the second subset of the plurality of chips, wherein the first side and the second side are opposite each other in a direction perpendicular to the stacking direction of the plurality of chips, and wherein the second subset of the plurality of chips is located on top of the first subset of the plurality of chips; and Vertical conductive elements extending from the surface of the molding layer to and coupled to the bonding pads; and A redistribution layer having: A conductive layer coupled to the vertical conductive element; and An insulating layer is present on the conductive layer and partially exposed. In the stacking direction of the plurality of chips, the redistribution layer for the first subset and the second subset of the plurality of chips is located on the side of the second subset of the plurality of chips opposite to the first molding layer. The vertical conductive element includes a first vertical conductive element and a third vertical conductive element electrically coupled to each other. The bonding pads of each chip in the first subset of the plurality of chips are electrically coupled to the corresponding first vertical conductive element and the third vertical conductive element. The chip stack also includes a sub-redistribution layer between the first vertical conductive element and the third vertical conductive element, and in the stacking direction of the plurality of chips, the sub-redistribution layer is located between the second portion of the first molding layer and the third molding layer.

2. The chip packaging structure according to claim 1 further includes: Solder balls that contact the exposed portion of the conductive layer through the opening in the insulating layer.

3. The chip packaging structure according to claim 2, wherein, The solder ball includes a portion below the upper surface of the insulating layer.

4. The chip packaging structure according to claim 2, wherein, The solder ball is electrically connected to the vertical conductive element.

5. The chip packaging structure according to claim 1, further comprising: Two or more solder balls, each solder ball contacting a corresponding exposed portion of the conductive layer through a corresponding opening in the insulating layer.

6. The chip packaging structure according to claim 5, wherein, The chip stack includes two or more vertical conductive elements, and the distance between two adjacent vertical conductive elements is smaller than the distance between two adjacent solder balls.

7. The chip packaging structure according to claim 1, wherein, The conductive layer unfolds into a single layer on the molded layer.

8. The chip packaging structure according to claim 1, wherein, The conductive layer is electrically connected to the vertical conductive element.

9. The chip packaging structure according to claim 1, wherein, The redistribution layer comprises multiple conductive layers and multiple insulating layers.

10. A chip packaging structure, comprising: Chip stacking, including: Multiple chips stacked together, wherein each of the multiple chips includes multiple vertically oriented memory cell strings and bonding pads; A molding layer encapsulating the plurality of chips, wherein the molding layer comprises: a first molding layer separating a first subset of the plurality of chips from a second subset of the plurality of chips; a second molding layer located on a second side of the second subset of the plurality of chips; and a third molding layer comprising a first portion located on the second side of the first subset of the plurality of chips and a second portion located on the first side of the second subset of the plurality of chips, wherein the first side and the second side are opposite each other in a direction perpendicular to the stacking direction of the plurality of chips, and wherein the second subset of the plurality of chips is located on top of the first subset of the plurality of chips; and A vertical conductive element passing through the molding layer, wherein the vertical conductive element is disposed on and electrically connected to the bonding pad; and A redistribution layer disposed on the chip stack and electrically connected to the vertical conductive elements, wherein, in the stacking direction of the plurality of chips, the redistribution layer for the first subset and the second subset of the plurality of chips is located on the side of the second subset of the plurality of chips opposite to the first molding layer, wherein the vertical conductive elements include a first vertical conductive element and a third vertical conductive element electrically coupled to each other, the bonding pads of each chip in the first subset of the plurality of chips are electrically coupled to the corresponding first vertical conductive element and the third vertical conductive element electrically coupled to each other, and wherein the chip stack further includes a sub-redistribution layer between the first vertical conductive element and the third vertical conductive element, and in the stacking direction of the plurality of chips, the sub-redistribution layer is located between the second portion of the first molding layer and the third molding layer.

11. The chip packaging structure according to claim 10, wherein, The redistribution layer comprises two overlapping layers.

12. The chip packaging structure according to claim 10, wherein, Each of the plurality of chips also includes a substrate on opposite sides of the bonding pads, and the plurality of vertically oriented memory cell strings extending in a vertical direction relative to the substrate.

13. The chip packaging structure according to claim 10, wherein, The vertical conductive element extends substantially parallel to the normal direction of the chip stack.

14. The chip packaging structure according to claim 10, wherein, The multiple chips are stacked in a stepped manner to expose the bonding pads.

15. The chip packaging structure according to claim 10, further comprising: A protective layer is formed on the side of the chip stack opposite to the redistribution layer.

16. The chip packaging structure according to claim 10, wherein, The chip stack also includes: Electrically connected wires between two bonding pads of two chips belonging to the plurality of chips respectively.

17. The chip packaging structure according to claim 10, wherein, The vertical conductive element is electrically connected to at least two of the plurality of chips.

18. The chip packaging structure according to claim 10, wherein, At least one of the plurality of chips is electrically connected to a component disposed on the redistribution layer.

19. The chip packaging structure according to claim 10, wherein, The redistribution layer includes a conductive layer and an insulating layer disposed on the conductive layer, and the insulating layer has a plurality of openings exposing a plurality of portions of the conductive layer.

20. A method for manufacturing a chip package structure, comprising: Multiple chips are stacked on a carrier board, wherein the multiple chips include a first subset and a second subset, each of the multiple chips has bonding pads and multiple vertically oriented memory cell strings, and the bonding pads are not covered by the multiple chips; A vertical conductive element is formed on the bonding pad and electrically connected to the bonding pad; A molding layer is formed to encapsulate the plurality of chips to form a chip stack, wherein the vertical conductive element passes through the molding layer, and the chip stack includes the plurality of chips, the vertical conductive element, and the molding layer; A second subset of the plurality of chips is stacked on top of a first subset of the plurality of chips, wherein the molding layer comprises: a first molding layer separating the first subset of the plurality of chips from the second subset of the plurality of chips; a second molding layer located on a second side of the second subset of the plurality of chips; and a third molding layer comprising a first portion located on the second side of the first subset of the plurality of chips and a second portion located on the first side of the second subset of the plurality of chips, wherein the first side and the second side are opposite each other in a direction perpendicular to the stacking direction of the plurality of chips; and A redistribution layer to be electrically connected to the vertical conductive element is formed on a first subset of the plurality of chips and a second subset of the plurality of chips, wherein the redistribution layer includes a conductive layer coupled to the vertical conductive element and an insulating layer on the conductive layer and partially exposed thereon. In the stacking direction of the plurality of chips, the redistribution layer for the first subset and the second subset of the plurality of chips is located on the side of the second subset of the plurality of chips opposite to the first molding layer. The vertical conductive element includes a first vertical conductive element and a third vertical conductive element electrically coupled to each other. The bonding pads of each chip in the first subset of the plurality of chips are electrically coupled to the corresponding first vertical conductive element and the third vertical conductive element electrically coupled to each other. The chip stack also includes a sub-redistribution layer between the first vertical conductive element and the third vertical conductive element. In the stacking direction of the plurality of chips, the sub-redistribution layer is located between the second portion of the first molding layer and the third molding layer.

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