Electronic device with re-routed layer structure

Abstract

Embodiments of the present disclosure provide a redistribution layer structure. The redistribution layer structure includes a first metal layer, a first dielectric layer disposed on the first metal layer, a second metal layer disposed on the first dielectric layer, and a second dielectric layer disposed on the second metal layer. A coefficient of thermal expansion of the first dielectric layer is less than a coefficient of thermal expansion of the second dielectric layer.

Description

Technical Field

[0001] The embodiments disclosed herein relate to a circuit structure of an electronic device, and more particularly to a redistribution layer structure of an electronic device. Background Technology

[0002] With the continuous expansion of electronic device applications, display technology is also developing rapidly. As manufacturing processes change, the requirements for the structure and quality of electronic devices are becoming increasingly stringent, leading to various challenges. Therefore, the research and development of electronic devices requires continuous updating and adjustment. Summary of the Invention

[0003] This disclosure relates to a redistribution layer structure that has good structural strength or quality.

[0004] According to the embodiments disclosed herein, the redistribution layer structure includes a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer. The first dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the second metal layer. The coefficient of thermal expansion of the first dielectric layer is smaller than that of the second dielectric layer.

[0005] According to an embodiment of this disclosure, a method for fabricating a redistribution layer structure includes the following steps: Providing a substrate; Forming a first metal layer on the substrate; Forming a first dielectric layer on the first metal layer; Forming a second metal layer on the first dielectric layer; Forming a second dielectric layer on the second metal layer. The coefficient of thermal expansion of the first dielectric layer is smaller than that of the second dielectric layer.

[0006] In summary, in the redistribution layer structure of this disclosure, the coefficient of thermal expansion of the first dielectric layer is smaller than that of the second dielectric layer. This allows the first dielectric layer, with its lower coefficient of thermal expansion, to be matched with a substrate having a lower coefficient of thermal expansion, thereby reducing deformation differences caused by temperature fluctuations during manufacturing. Therefore, the probability of warpage in the redistribution layer structure can be reduced. The redistribution layer structure can then exhibit good structural strength or quality. Furthermore, the coefficients of thermal expansion of the multiple dielectric layers in the redistribution layer structure can gradually increase from bottom to top, reducing deformation differences between different dielectric layers and mitigating the impact of residual stress. Additionally, the redistribution layer structure achieves good manufacturing yield or quality in terms of manufacturing processes. Attached Figure Description

[0007] Figure 1 This is a cross-sectional schematic diagram of a redistribution layer structure according to an embodiment of the present disclosure;

[0008] Figure 2 This is a cross-sectional schematic diagram of a redistribution layer structure according to another embodiment of the present disclosure. Detailed Implementation

[0009] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0010] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Thus, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0011] The directional terms used herein, such as "up," "down," "front," "back," "left," and "right," are for reference only when referring to the accompanying drawings. Therefore, the directional terms used are illustrative and not intended to limit this disclosure. In the accompanying drawings, each figure illustrates general features of the methods, structures, and / or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, and / or structures may be reduced or enlarged.

[0012] In this disclosure, the length and width can be measured using an optical microscope, and the thickness can be measured from a cross-sectional image in an electron microscope, but is not limited thereto.

[0013] The terms “approximately,” “equal to,” “same as,” “substantially,” or “roughly” are generally interpreted as being within 20% of a given value, or within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value.

[0014] In this disclosure, a structure (or layer, component, substrate) located on top of another structure (or layer, element, substrate) can refer to the two structures being adjacent and directly connected, or to the two structures being adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate spacer) between the two structures. The lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer solid structure or a non-solid structure, without limitation. In this disclosure, when a structure is disposed "on" other structures, it may mean that the structure is "directly" on other structures, or that the structure is "indirectly" on other structures, meaning that at least one structure is sandwiched between the structure and other structures.

[0015] The terms "first," "second," etc., used in this disclosure may be used to describe various elements, components, regions, layers, and / or portions, but these elements, components, regions, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, the terms "first element," "component," "region," "layer," or "portion" discussed below are used to distinguish them from "second element," "component," "region," "layer," or "portion," and are not used to define a sequence or specific element, component, region, layer, and / or portion. Furthermore, the term "first" as used in the specification paragraphs may be changed to "second" in the claims.

[0016] The electronic device may have a redistribution layer structure as disclosed in this embodiment. The electronic device may include, but is not limited to, a display device, a packaging device, a backlight device, an antenna device, a sensing device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-emissive display device or a self-emissive display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device. The sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited to these. Electronic components may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes or photodiodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited to these. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited to these. It should be noted that the electronic device may be any arrangement and combination of the foregoing, but is not limited to these. The following description uses the redistribution layer structure in an electronic device as an example of an electronic device or splicing device to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0017] In this disclosure, the various embodiments described below can be used in combination without departing from the spirit and scope of this disclosure. For example, some features of one embodiment can be combined with some features of another embodiment to form another embodiment.

[0018] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0019] Figure 1 This is a schematic cross-sectional view of a redistribution layer structure according to an embodiment of this disclosure. The drawings are for clarity and ease of explanation. Figure 1 Several components are omitted from the diagram. Please refer to [link / reference]. Figure 1 The redistribution layer structure RD disposed on the substrate 100 is, for example, used to achieve redistribution circuitry for high-density integrated circuits (ICs), but is not limited thereto. The redistribution layer structure RD may include multiple conductive layers and multiple dielectric layers in the normal direction of the substrate 100 (e.g., along the direction of the substrate 100). Figure 1 They are stacked alternately along the Z-axis direction.

[0020] Figure 1A portion of the redistribution layer structure RD is shown. The redistribution layer structure RD comprises a stack of multiple redistribution layers. Each redistribution layer includes, for example, a stack of metal layers and dielectric layers, but is not limited thereto. In some embodiments, the redistribution layer structure RD is, for example, a stack of four redistribution layers RL1, RL2, RL3, and RL4, but is not limited thereto.

[0021] In some embodiments, the redistribution layer structure RD includes at least a first metal layer M1, a first dielectric layer IL1, a second metal layer M2, and a second dielectric layer IL2. In some embodiments, the redistribution layer structure RD further includes a third metal layer M3, a third dielectric layer IL3, a fourth metal layer M4, and a fourth dielectric layer IL4. In this embodiment, the first dielectric layer IL1 is disposed on the first metal layer M1. The second metal layer M2 is disposed on the first dielectric layer IL1. The second dielectric layer IL2 is disposed on the second metal layer M2. The third metal layer M3 is disposed on the second dielectric layer IL2. The third dielectric layer IL3 is disposed on the third metal layer M3. The fourth metal layer M4 is disposed on the third dielectric layer IL3. The fourth dielectric layer IL4 is disposed on the fourth metal layer M4. It should be noted that, in this disclosure, each metal layer M1, M2, M3, and M4 can be a circuit layer formed by patterning, but is not limited thereto. For clarity of the drawings, Figure 1 The diagram only schematically shows four redistribution layers RL1, RL2, RL3, and RL4, each consisting of four metal layers and four dielectric layers, but... Figure 1 The number of film layers shown is not intended to limit this disclosure. In other embodiments, the number of metal layers and dielectric layers may be more or less, depending on actual needs. Furthermore, this disclosure does not limit the layout of the redistribution layer structure RD. In this embodiment, since the coefficient of thermal expansion (CTE) of the first dielectric layer IL1 of the redistribution layer structure RD is less than that of the second dielectric layer IL2, the CTE of the first dielectric layer IL1 located at the bottom near the substrate 100 is closer to that of the carrier plate, thus reducing the deformation difference caused by temperature rise and fall during the manufacturing process. This reduces the probability of warping in the redistribution layer structure RD. The redistribution layer structure RD can have good structural strength or quality. Furthermore, in terms of manufacturing process, the redistribution layer structure RD can achieve good manufacturing yield or quality. The material and structural relationships of each film layer will be briefly explained below.

[0022] Please refer to Figure 1In this embodiment, the redistribution layer structure RD can be disposed on the substrate 100 during the manufacturing process, and the substrate 100 can be removed after the manufacturing process is completed. The material of the substrate 100 may include organic or inorganic materials, such as glass, quartz, sapphire, silicon wafer, stainless steel, ceramic, molding compound (e.g., polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), resin, epoxy resin, organosilicon compound), other suitable substrate materials, or combinations thereof, but is not limited thereto. For example, the coefficient of thermal expansion of glass ranges from 3 ppm / ℃ (parts per million per degree Celsius) to 16 ppm / ℃ (3 ppm / ℃ ≤ coefficient of thermal expansion ≤ 16 ppm / ℃).

[0023] In some embodiments, a release layer 120 may be selectively disposed on the substrate 100. The release layer 120 may be, for example, a photo-curable release film or a thermally curable release film, but is not limited thereto. The viscosity of the photo-curable release film is reduced by a photo-curing process; while the viscosity of the thermally curable release film is reduced by a thermal-curing process. In other embodiments, the release layer 120 may also be a laser debond release film. The thickness of the release layer 120 may be from 0.5 micrometers to 1.5 micrometers (0.5 micrometers ≤ thickness ≤ 1.5 micrometers), but is not limited thereto.

[0024] In this embodiment, the first redistribution layer RL1 of the redistribution layer structure RD is disposed on the substrate 100. For example, the first metal layer M1 is disposed on the release layer 120. The material of the first metal layer M1 may include molybdenum (Mo), tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co), zirconium (Zr), tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), other suitable metals, or alloys or combinations of the above materials. In some embodiments, the first metal layer M1 is, for example, a single metal layer or a stacked structure having multiple sub-metal layers. For example, the first metal layer M1 may be a single copper layer. Alternatively, the first metal layer M1 may include at least two stacked sub-metal layers, for example, one of the two sub-metal layers may include titanium, and the other may include copper. Therefore, the first metal layer M1 can be a multilayer stack of titanium and copper, but is not limited thereto.

[0025] The first dielectric layer IL1 is disposed on the first metal layer M1. The material of the first dielectric layer IL1 may include photosensitive polyimide, photosensitive polybenzoxazole (photosensitive PBO), benzocyclobutene (BCB), polyaromatic flurocarbons, photosensitive polyphenylene ether (photosensitive PPE), or other suitable materials.

[0026] In some embodiments, the first dielectric layer IL1 and the first metal layer M1 may constitute a first redistribution layer RL1. The thickness of the first dielectric layer IL1 may be defined as: in the normal direction of the substrate 100 (e.g., along the direction of the substrate 100), the thickness of the first dielectric layer IL1 may be defined as: Figure 1The maximum distance between the top and bottom surfaces of the first dielectric layer IL1 along the Z-axis (as shown). The thickness of the first dielectric layer IL1 is, for example, from 5 micrometers (μm) to 20 micrometers (5 μm ≤ thickness ≤ 20 μm), but is not limited thereto. In other embodiments, the thickness of the first dielectric layer IL1 may be from 11 micrometers to 19 micrometers (11 μm ≤ thickness ≤ 19 μm). The Young's modulus of the first dielectric layer IL1 is from 3 GPa (gigapascals) to 5 GPa (3 GPa ≤ Young's modulus ≤ 5 GPa), but is not limited thereto. The coefficient of thermal expansion of the first dielectric layer IL1 is 20 ppm / ℃, but is not limited thereto. In other embodiments, the coefficient of thermal expansion of the first dielectric layer IL1 may be from 20 ppm / ℃ to 40 ppm / ℃ (20 ppm / ℃ ≤ coefficient of thermal expansion ≤ 40 ppm / ℃).

[0027] In some embodiments, the thickness of the first metal layer M1 can be defined as the maximum distance between the top and bottom surfaces of the first metal layer M1 in the normal direction of the substrate 100. The thickness of the first metal layer M1 is, for example, 4 micrometers to 13 micrometers (4 micrometers ≤ thickness ≤ 13 micrometers), but is not limited thereto. The Young's modulus of the first metal layer M1 is 90 GPa to 120 GPa (90 GPa ≤ Young's modulus ≤ 120 GPa), but is not limited thereto. The coefficient of thermal expansion of the first metal layer M1 is 18 ppm / ℃, but is not limited thereto. In other embodiments, the coefficient of thermal expansion of the first metal layer M1 can be 16 ppm / ℃ to 20 ppm / ℃ (16 ppm / ℃ ≤ coefficient of thermal expansion ≤ 20 ppm / ℃). It should be noted that when the first metal layer M1 is composed of multiple sub-metal layers stacked together, the coefficient of thermal expansion of the first metal layer M1 will be adjusted by factors such as the material properties and thickness of each sub-metal layer. In this case, the value of the coefficient of thermal expansion of the first metal layer M1 can be obtained by calculation or actual measurement.

[0028] In this embodiment, the second redistribution layer RL2 of the redistribution layer structure RD is disposed on the first redistribution layer RL1. For example, the second metal layer M2 is disposed on the first dielectric layer IL1. The material of the second metal layer M2 may be the same as or different from the material of the first metal layer M1, and may include, for example, molybdenum, tantalum, niobium, hafnium, nickel, chromium, cobalt, zirconium, tungsten, aluminum, titanium, copper, other suitable metals, or alloys or combinations thereof. In some embodiments, similar to the first metal layer M1, the second metal layer M2 may be, for example, a single metal layer or a stacked structure having multiple sub-metal layers. For example, the second metal layer M2 may be a single copper layer. Alternatively, the second metal layer M2 may include at least two stacked sub-metal layers, one of which includes titanium and the other includes copper. Therefore, the second metal layer M2 may be a titanium-copper multilayer stack, but is not limited thereto.

[0029] In this embodiment, the first metal layer M1 and the second metal layer M2 can be separated by the first dielectric layer IL1, but this is not a limitation.

[0030] In other embodiments, a plurality of conductive vias (not shown) may be provided between the first metal layer M1 and the second metal layer M2. The first metal layer M1 and the second metal layer M2 can be electrically connected to each other through at least some of the conductive vias. That is, the first metal layer M1 and the second metal layer M2 can be interconnected lines in the redistribution layer structure RD.

[0031] The second dielectric layer IL2 is disposed on the second metal layer M2. Similar to the first dielectric layer IL2, the material of the second dielectric layer IL2 may include photosensitive polyimide, photosensitive polybenzoxazole (photosensitive PBO), benzocyclobutene (BCB), polyaromatic flurocarbons, photosensitive polyphenylene ether (photosensitive PPE), or other suitable materials.

[0032] In some embodiments, the second dielectric layer IL2 and the second metal layer M2 may constitute a second redistribution layer RL2. The thickness of the second dielectric layer IL2 may be defined as: in the normal direction of the substrate 100 (e.g., ... Figure 1 The maximum distance between the top and bottom surfaces of the second dielectric layer IL2 along the Z-axis direction. The thickness of the second dielectric layer IL2 is, for example, from 5 micrometers to 20 micrometers (5 micrometers ≤ thickness ≤ 20 micrometers), but is not limited thereto. In other embodiments, the thickness of the second dielectric layer IL2 may be from 9 micrometers to 11 micrometers (9 micrometers ≤ thickness ≤ 11 micrometers). In some embodiments, the thicknesses of the first dielectric layer IL1 and the second dielectric layer IL2 may be the same or different. Figure 1 As shown, the thicknesses of the first dielectric layer IL1 and the second dielectric layer IL2 can be substantially the same, for example.

[0033] The Young's modulus of the second dielectric layer IL2 is from 3 GPa to 5 GPa (3 GPa ≤ Young's modulus ≤ 5 GPa), but is not limited thereto. The coefficient of thermal expansion of the second dielectric layer IL2 is 30 ppm / ℃, but is not limited thereto. In other embodiments, the coefficient of thermal expansion of the second dielectric layer IL2 may be from 20 ppm / ℃ to 40 ppm / ℃ (20 ppm / ℃ ≤ coefficient of thermal expansion ≤ 40 ppm / ℃).

[0034] In some embodiments, the thickness of the second metal layer M2 can be defined as: in the normal direction of the substrate 100 (e.g., ... Figure 1 The maximum distance between the top and bottom surfaces of the second metal layer M2 along the Z-axis. The thickness of the second metal layer M2 is, for example, 4 micrometers to 13 micrometers (4 micrometers ≤ thickness ≤ 13 micrometers), but is not limited thereto. The Young's modulus of the second metal layer M2 is 90 GPa to 120 GPa (90 GPa ≤ Young's modulus ≤ 120 GPa), but is not limited thereto. The coefficient of thermal expansion of the second metal layer M2 is 18 ppm / ℃, but is not limited thereto. In some other embodiments, the coefficient of thermal expansion of the second metal layer M2 may be 16 ppm / ℃ to 20 ppm / ℃ (16 ppm / ℃ ≤ coefficient of thermal expansion ≤ 20 ppm / ℃).

[0035] It is worth noting that since the coefficient of thermal expansion of the first dielectric layer IL1 is smaller than that of the second dielectric layer IL2, the coefficient of thermal expansion of the first dielectric layer IL1 is closer to that of the substrate 100 (e.g., 3 ppm / ℃ to 16 ppm / ℃). Therefore, the closer the coefficient of thermal expansion of the first dielectric layer IL1 is to that of the substrate 100, the reduction of deformation differences caused by temperature fluctuations during manufacturing can be achieved. This reduces the probability of warpage in the redistribution layer structure RD. The redistribution layer structure RD can exhibit good structural strength or quality. Furthermore, the deformation difference between the first dielectric layer IL1 and the second dielectric layer IL2 can be reduced, thus mitigating the impact of residual stress. The structural reliability of the redistribution layer structure RD can be improved. Additionally, the redistribution layer structure RD can achieve good manufacturing yield or quality in its manufacturing process.

[0036] In addition to the first rerouting layer RL1 and the second rerouting layer RL2 mentioned above, the redistribution layer structure RD may also include a stack of a third rerouting layer RL3 and a fourth rerouting layer RL2 in sequence, but this disclosure is not limited to the number of redistribution layers shown above.

[0037] In some embodiments, the third dielectric layer IL3 and the third metal layer M3 may constitute a third redistribution layer RL3. The thickness of the third dielectric layer IL3 may be defined as: in the normal direction of the substrate 100 (e.g., ... Figure 1 The maximum distance between the top and bottom surfaces of the third dielectric layer IL3 along the Z-axis direction. The thickness of the third dielectric layer IL3 is, for example, from 5 micrometers to 20 micrometers (5 micrometers ≤ thickness ≤ 20 micrometers), but is not limited thereto. In other embodiments, the thickness of the third dielectric layer IL3 may be from 7 micrometers to 9 micrometers (7 micrometers ≤ thickness ≤ 9 micrometers). In some embodiments, the thicknesses of the first dielectric layer IL1 and the third dielectric layer IL3 may be the same or different. Figure 1As shown, the thicknesses of the first dielectric layer IL1 and the third dielectric layer IL3 are substantially the same, for example.

[0038] The Young's modulus of the third dielectric layer IL3 is from 1 GPa to 3 GPa (1 GPa ≤ Young's modulus ≤ 3 GPa), but is not limited thereto. The coefficient of thermal expansion of the third dielectric layer IL3 is 40 ppm / ℃, but is not limited thereto. In some other embodiments, the coefficient of thermal expansion of the third dielectric layer IL3 may be from 40 ppm / ℃ to 80 ppm / ℃ (40 ppm / ℃ ≤ coefficient of thermal expansion ≤ 80 ppm / ℃).

[0039] In some embodiments, the thickness of the third metal layer M3 can be defined as: in the normal direction of the substrate 100 (e.g., ... Figure 1 The maximum distance between the top and bottom surfaces of the third metal layer M3 along the Z-axis. The thickness of the third metal layer M3 is, for example, 4 micrometers to 13 micrometers (4 micrometers ≤ thickness ≤ 13 micrometers), but is not limited thereto. The Young's modulus of the third metal layer M3 is 90 GPa to 120 GPa (90 GPa ≤ Young's modulus ≤ 120 GPa), but is not limited thereto. The coefficient of thermal expansion of the third metal layer M3 is 18 ppm / ℃, but is not limited thereto. In some other embodiments, the coefficient of thermal expansion of the third metal layer M3 may be 16 ppm / ℃ to 20 ppm / ℃ (16 ppm / ℃ ≤ coefficient of thermal expansion ≤ 20 ppm / ℃).

[0040] In some embodiments, the fourth dielectric layer IL4 and the fourth metal layer M4 may constitute a fourth redistribution layer RL4. The thickness of the fourth dielectric layer IL4 may be defined as: in the normal direction of the substrate 100 (e.g., ... Figure 1 The maximum distance between the top and bottom surfaces of the fourth dielectric layer IL4 along the Z-axis. The thickness of the fourth dielectric layer IL4 is, for example, from 5 micrometers to 20 micrometers (5 micrometers ≤ thickness ≤ 20 micrometers), but is not limited thereto. In other embodiments, the thickness of the fourth dielectric layer IL4 may be from 5 micrometers to 9 micrometers (5 micrometers ≤ thickness ≤ 9 micrometers). In some embodiments, the thicknesses of the first dielectric layer IL1 and the fourth dielectric layer IL4 may be the same or different. Figure 1 As shown, the thicknesses of the first dielectric layer IL1 and the fourth dielectric layer IL4 can be substantially the same, for example.

[0041] The Young's modulus of the fourth dielectric layer IL4 is from 1 GPa to 3 GPa (1 GPa ≤ Young's modulus ≤ 3 GPa), but is not limited thereto. The coefficient of thermal expansion of the fourth dielectric layer IL4 is 50 ppm / ℃, but is not limited thereto. In other embodiments, the coefficient of thermal expansion of the fourth dielectric layer IL4 may be from 40 ppm / ℃ to 80 ppm / ℃ (40 ppm / ℃ ≤ coefficient of thermal expansion ≤ 80 ppm / ℃).

[0042] In some embodiments, the thickness of the fourth metal layer M4 can be defined as: in the normal direction of the substrate 100 (e.g., ... Figure 1 The maximum distance between the top and bottom surfaces of the fourth metal layer M4 along the Z-axis. The thickness of the fourth metal layer M4 is, for example, 4 micrometers to 13 micrometers (4 micrometers ≤ thickness ≤ 13 micrometers), but is not limited thereto. The Young's modulus of the fourth metal layer M4 is 90 GPa to 120 GPa (90 GPa ≤ Young's modulus ≤ 120 GPa), but is not limited thereto. The coefficient of thermal expansion of the fourth metal layer M3 is 18 ppm / ℃, but is not limited thereto. In some other embodiments, the coefficient of thermal expansion of the fourth metal layer M4 may be 16 ppm / ℃ to 20 ppm / ℃ (16 ppm / ℃ ≤ coefficient of thermal expansion ≤ 20 ppm / ℃).

[0043] In other embodiments, multiple conductive vias may be provided between the second metal layer M2 and the third metal layer M3, and between the third metal layer M3 and the fourth metal layer M4. The second metal layer M2 and the third metal layer M3 can be electrically connected to each other through at least some of the conductive vias. The third metal layer M3 and the fourth metal layer M4 can also be electrically connected to each other through at least some of the conductive vias. That is, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 can be interconnecting lines in the redistribution layer structure RD.

[0044] It is worth noting that in the redistribution layer structure RD, the coefficient of thermal expansion of the first dielectric layer IL1 can be lower than that of the other dielectric layers IL2, IL3, and IL4. This allows the first dielectric layer IL1, with its lower coefficient of thermal expansion, to match the substrate 100, which also has a low coefficient of thermal expansion, thus reducing the probability of warpage. The redistribution layer structure RD can achieve good structural strength or quality. Furthermore, by gradually increasing the coefficient of thermal expansion from bottom to top, the deformation differences between different dielectric layers can be reduced, thereby mitigating the impact of residual stress. Additionally, the redistribution layer structure RD can achieve good manufacturing yield or quality. Moreover, the upper dielectric layers, which are subject to fewer repeated temperature increases and decreases in the manufacturing process, can use dielectric materials with higher coefficients of thermal expansion to control manufacturing costs.

[0045] In other embodiments, the coefficient of thermal expansion of the first dielectric layer in the redistribution layer structure is smaller than that of the second dielectric layer IL2, while the coefficients of thermal expansion of the second dielectric layer IL2, the third dielectric layer IL3, and the fourth dielectric layer IL4 can be substantially the same. With the above-described configuration, the redistribution layer structure can also achieve the aforementioned superior technical effects.

[0046] The redistribution layer structure RD also includes a top connector 140 disposed on the uppermost dielectric layer (e.g., the fourth dielectric layer IL4 in this embodiment) of the redistribution layer structure RD and electrically connected to the metal layer corresponding to the uppermost dielectric layer (e.g., the fourth metal layer M4 in this embodiment). The top connector 140 may be, for example, the uppermost pad of the redistribution layer structure RD, but is not limited thereto. The top connector 140 may be, for example, a single metal layer or a stacked structure having multiple sub-metal layers. For example, the top connector 140 may be a single copper layer. Alternatively, the top connector 140 may include a stack of sub-metal layers. For example, the top connector 140 may be a multilayer titanium-copper stack, but is not limited thereto.

[0047] In some embodiments, an electronic component 160 and a packaging material layer (not shown) may also be disposed above the redistribution layer structure RD. The electronic component 160 is disposed on the fourth dielectric layer IL4 and / or the top connector 140. The electronic component 160 is, for example, a chip, die, diode, transistor, integrated circuit (IC), or a combination of the above components, or other suitable electronic components, and is not limited thereto. The electronic component 160 can be electrically connected to the fourth metal layer M4 via the top connector 140, but is not limited thereto. In some embodiments, since the metal layers are electrically connected to each other, the electronic component 160 can be electrically connected to the first metal layer M1 via the top connector 140.

[0048] In some embodiments, an encapsulation material layer is disposed on the fourth dielectric layer IL4 or on the top connector 140. The encapsulation material layer may encapsulate the electronic component 160 to embed the electronic component 160 within the encapsulation material layer. The material of the encapsulation material layer is, for example, epoxy resin, or other suitable materials, but is not limited thereto.

[0049] In other embodiments, taking a two-layer redistribution layer structure RD consisting only of a first redistribution layer RL1 and a second redistribution layer RL2 as an example, the top connector 140 may be disposed on the second dielectric layer IL2 of the second redistribution layer RL2. The top connector 140 may be electrically connected to the second metal layer M2 to be electrically connected to the first metal layer M1 of the first redistribution layer RL1, but is not limited thereto.

[0050] In short, in the redistribution layer structure RD, the coefficient of thermal expansion of the first dielectric layer IL1 is less than that of the second dielectric layer IL2, and the coefficient of thermal expansion of the second dielectric layer IL2 is less than or equal to that of the third dielectric layer IL3, and the coefficient of thermal expansion of the third dielectric layer IL3 is less than or equal to that of the fourth dielectric layer IL4. As a result, the first dielectric layer IL1, with its lower coefficient of thermal expansion, can be matched with the substrate 100, which has a low coefficient of thermal expansion, thus reducing the probability of warpage. The redistribution layer structure RD can have good structural strength or quality. Furthermore, in some embodiments, the coefficients of thermal expansion of the multiple dielectric layers in the redistribution layer structure RD can gradually increase in a gradient from bottom to top, reducing the deformation differences between different dielectric layers and thus reducing the impact of residual stress. Additionally, the redistribution layer structure RD can achieve good manufacturing yield or quality. Moreover, the upper dielectric layer, which is subjected to fewer repeated heating and cooling processes, can use a dielectric material with a higher coefficient of thermal expansion to control manufacturing costs.

[0051] Other embodiments will be listed below as examples of manufacturing processes. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0052] Figure 2 This is a cross-sectional schematic diagram of a redistribution layer structure according to another embodiment of the present disclosure. The redistribution layer structure RD' in this embodiment is generally similar to... Figure 1 The redistribution layer structure RD is used, so the same and similar components in the two embodiments will not be repeated here. Figure 2 and Figure 1 The main difference in the illustrated embodiments lies in the thickness of the dielectric layers (e.g., the thickness of the first dielectric layer is greater than the thickness of the third dielectric layer). This will be explained below through... Figure 2 This will illustrate the fabrication method of the rewiring layer structure (RD) in this disclosure.

[0053] First, a substrate 100 is provided. In this embodiment, the substrate 100 is, for example, a glass substrate, but is not limited thereto. The thickness of the substrate 100 is, for example, 500 micrometers to 1500 micrometers, but is not limited thereto.

[0054] Next, before setting the first metal layer M1, a release layer 120 may be selectively set. Then, the first metal layer M1 is set onto the release layer 120. The thickness of the release layer 120 is 0.5 micrometers to 1.5 micrometers, but is not limited thereto. The material of the release layer 120 includes photocurable release film or thermocurable release film, but is not limited thereto. For example, the material of the release layer 120 includes polyethylene (PE), polyethylene terephthalate (PET), oriented polypropylene (OPP) film, or other suitable materials or combinations thereof, but is not limited thereto. The release layer 120 can be decomposed by a light irradiation system or a heating system. For example, with a photodissociation system, the release layer 120 can be irradiated by a laser beam or an ultraviolet beam, causing the release layer 120 to absorb the energy of the beam and undergo a dissociation reaction. In this way, the release layer 120 can be easily separated from the first metal layer M1. In the case of a thermal dissociation system, the release layer 120 can be heated by a heat source, causing it to absorb energy from the heat source and undergo a dissociation reaction. In this way, the release layer 120 can be easily separated from the first metal layer M1. Other dissociation systems may also be used, and this disclosure is not limiting.

[0055] Next, a first redistribution layer RL1' is formed on the release layer 120. The step of forming the first redistribution layer RL1' includes forming a first metal layer M1 on the release layer 120 on the substrate 100. In this embodiment, the first metal layer M1 can be a single metal layer or a stacked structure with multiple sub-metal layers. For example, the first metal layer M1 may include a stack of three sub-metal layers. Specifically, a titanium metal layer with a thickness of 0.1 micrometers to 0.3 micrometers may first be formed on the release layer 120. Next, a thin copper metal layer with a thickness of 0.2 micrometers to 0.5 micrometers is formed on the titanium metal layer. Then, a thick copper metal layer with a thickness of 4 micrometers to 12 micrometers is formed on the copper metal layer. Methods for forming the first metal layer M1 may include, but are not limited to, processes such as sputtering, vapor deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), or plating. Under the above configuration, the first metal layer M1 can be, for example, a titanium-copper-copper stack.

[0056] Next, a first dielectric layer IL1' is formed on the first metal layer M1 to constitute a first redistribution layer RL1. The material of the first dielectric layer IL1' includes, but is not limited to, photosensitive polyimide, photosensitive polybenzoxazole (PBO), benzocyclobutene (BCB), polyaromatic flurocarbons, photosensitive polyphenylene ether (PPE), or other suitable materials. The method for forming the first dielectric layer IL1' includes chemical vapor deposition, physical vapor deposition, atomic layer deposition (ALD), spin coating, or screen printing, or other suitable methods. In some embodiments, the thickness of the first dielectric layer IL1' is, for example, 11 micrometers to 19 micrometers, but is not limited thereto. In some embodiments, the thickness of the first dielectric layer IL1' may be 5 micrometers to 20 micrometers.

[0057] Next, a second routing layer RL2' is formed on the first routing layer RL1'. Before forming the second routing layer RL2', a plurality of conductive vias may be selectively formed in the first dielectric layer IL1'.

[0058] The step of setting the second redistribution layer RL2' includes forming a second metal layer M2 on the first dielectric layer IL1'. The second metal layer M2 can be electrically connected to the first metal layer M1 through conductive vias in the first dielectric layer IL1', but is not limited thereto. In this embodiment, the second metal layer M2 can be a single metal layer or a stacked structure with multiple sub-metal layers. For example, the second metal layer M2 can be, for instance, a titanium-copper-copper stack, and its formation method can be similar to that of the first metal layer M1, which will not be described further here.

[0059] Next, a second dielectric layer IL2' is formed on the second metal layer M2 to constitute a second redistribution layer RL2'. The material and fabrication method of the second dielectric layer IL2' can be similar to those of the first dielectric layer IL1', and will not be described again here. In some embodiments, the thickness of the second dielectric layer IL2' is, for example, 9 micrometers to 11 micrometers, but is not limited thereto.

[0060] It is worth noting that in the redistribution layer structure RD' of this disclosure embodiment, since the coefficient of thermal expansion of the first dielectric layer IL1' is smaller than that of the second dielectric layer IL2', the coefficient of thermal expansion of the first dielectric layer IL1' can be closer to that of the substrate 100, thereby reducing the deformation difference caused by the heating and cooling processes during manufacturing. In this way, the redistribution layer structure RD' can reduce the probability of warpage. The redistribution layer structure RD' can have good structural strength or quality. Furthermore, the thickness of the first dielectric layer IL1' can be greater than the thickness of the second dielectric layer IL2', thus reducing the deformation difference between the first dielectric layer IL1' and the second dielectric layer IL2', or adjusting the stress difference between the first dielectric layer IL1' and the second dielectric layer IL2', thereby reducing the impact of residual stress. The structural reliability of the redistribution layer structure RD' can be improved. In addition, the redistribution layer structure RD' can achieve good manufacturing yield or quality in its manufacturing process.

[0061] Next, a third routing layer RL3' is formed on the second routing layer RL2'. Prior to forming the third routing layer RL3', multiple conductive vias may be selectively formed in the second dielectric layer IL2'.

[0062] The step of setting the third redistribution layer RL3' includes forming a third metal layer M3 on the second dielectric layer IL2'. The third metal layer M3 can be electrically connected to the second metal layer M2 through conductive vias in the second dielectric layer IL2', but is not limited thereto. In this embodiment, the third metal layer M3 can be a single metal layer or a stacked structure with multiple sub-metal layers, and its formation method can be similar to that of the first metal layer M1, which will not be described in detail here.

[0063] Next, a third dielectric layer IL3' is formed on the third metal layer M3 to constitute a third redistribution layer RL3'. The material of the third dielectric layer IL3' is similar to that of the second dielectric layer IL2', and the method of forming the third dielectric layer IL3' is similar to that of forming the second dielectric layer IL2', so it will not be described again here. In some embodiments, the thickness of the third dielectric layer IL3' may be, for example, 7 micrometers to 9 micrometers, but is not limited thereto.

[0064] Next, a fourth routing layer RL4' is formed on the third routing layer RL3'. Prior to forming the fourth routing layer RL4', a plurality of conductive vias may be selectively formed in the third dielectric layer IL3'. These conductive vias may be electrically connected to the third metal layer M3.

[0065] The step of setting the fourth redistribution layer RL4' includes forming a fourth metal layer M4 on the third dielectric layer IL3'. The fourth metal layer M4 may be electrically connected to the third metal layer M3 through conductive vias in the third dielectric layer IL2', but is not limited thereto. In this embodiment, the fourth metal layer M4 may be a single metal layer or a stacked structure with multiple sub-metal layers. For example, the fourth metal layer M4 may include a stack of three sub-metal layers, and its formation may be similar to that of the first metal layer M1, which will not be described further here.

[0066] Next, a fourth dielectric layer IL4' is formed on the fourth metal layer M4 to constitute a fourth redistribution layer RL4'. The material of the fourth dielectric layer IL4' is similar to that of the second dielectric layer IL2', and the method of forming the fourth dielectric layer IL4' is similar to that of forming the second dielectric layer IL2', so it will not be described again here. In some embodiments, the thickness of the fourth dielectric layer IL4' is, for example, 5 micrometers to 9 micrometers, but is not limited thereto.

[0067] Under the above configuration, the thickness of the first dielectric layer IL1' can be greater than the thickness of the other dielectric layers IL2', IL3', and IL4'. In some embodiments, the coefficient of thermal expansion of the multiple dielectric layers in the redistribution layer structure RD' can gradually increase in a bottom-up gradient. Alternatively, the thickness of the multiple dielectric layers in the redistribution layer structure RD' can gradually decrease in a bottom-up gradient. This reduces the deformation differences between different dielectric layers, thereby mitigating the impact of residual stress. Furthermore, the redistribution layer structure RD' can achieve good manufacturing yield or quality. Additionally, the upper dielectric layer, which is subjected to fewer repeated heating and cooling processes, can use a dielectric material with a higher coefficient of thermal expansion to control manufacturing costs.

[0068] Next, the top connector 140 may be disposed on the fourth dielectric layer IL4' prior to the step of removing the substrate 100. In some embodiments, the fourth dielectric layer IL4' may include an opening (not shown). The top connector 140 may be electrically connected to the fourth metal layer M4 through the opening. The top connector 140 may be, for example, a single metal layer or a stacked structure having multiple sub-metal layers. For example, the top connector 140 may be a single copper layer or a multilayer titanium-copper stack, but is not limited thereto.

[0069] Next, electronic component 160 is disposed on the fourth dielectric layer IL4' or the top connector 140. Electronic component 160 can be electrically connected to the fourth metal layer M4 by connecting to the top connector 140, but is not limited thereto.

[0070] Then, an encapsulation material layer (not shown) is disposed on the fourth dielectric layer IL4' or the top connector 140. The encapsulation material layer may encapsulate the electronic component 160 to embed the electronic component 160 within the encapsulation material layer. The material of the encapsulation material layer may be, for example, epoxy resin, or other suitable materials, but is not limited thereto.

[0071] Next, the substrate 100 is removed. Specifically, the release layer 120 can absorb energy and undergo a dissociation reaction by means of a light irradiation system or a heating system, thereby separating the substrate 100 from the redistribution layer structure RD'. In some embodiments, the steps of setting the top connector 140, setting the electronic component 160, or setting the encapsulation material layer can be performed after the step of removing the substrate 100; the embodiments disclosed herein are not limited.

[0072] In addition, in some embodiments, the fabrication methods of the redistribution layer structures RD and RD' disclosed herein can be applied to the fabrication of semiconductor packaged electronic devices, such as system-on-chip (SoC), system-in-package (SiP), or other electronic devices manufactured by the above methods. Specifically, the fabrication method of the redistribution layer structures RD and RD' of one embodiment of this disclosure can be applied to redistribution layer-first (RDL first) fabrication methods, chip-first / face-up fabrication methods, or chip-first / face-down fabrication methods. When the redistribution layer structures RD and RD' of one embodiment of this disclosure are applied to the redistribution layer-first fabrication method, the substrate 100 may include glass, quartz, sapphire, ceramic, stainless steel, silicon wafer, encapsulating colloid (e.g., resin, epoxy resin, silicone compound), other suitable substrate materials, or combinations thereof, but is not limited thereto. When the redistribution layer structures RD and RD' of an embodiment of this disclosure are applied to die-first / face-up fabrication methods and die-first / face-down fabrication methods, the substrate 100 may include glass, an integrated circuit chip encapsulated with an encapsulating colloid (e.g., resin, epoxy resin, silicone compound), a silicon wafer, other suitable substrate materials, or combinations thereof, but is not limited thereto. In some embodiments, when the redistribution layer structures RD and RD' of an embodiment of this disclosure are applied to a redistribution layer-first fabrication method, the substrate 100 may be removed after the redistribution layer structures RD and RD' are fabricated, so that the redistribution layer structures RD and RD' can be bonded to components such as integrated circuit chips and / or printed circuit boards in subsequent processes, but is not limited thereto. In some embodiments, when the redistribution layer structures RD and RD' of this disclosure are applied to a die-first / face-up fabrication method and a die-first / face-down fabrication method, a release layer may be selectively provided on the substrate 100 or no release layer may be provided, so that the redistribution layer structures RD and RD' can be bonded to components such as printed circuit boards in subsequent processes, but this is not a limitation.

[0073] In summary, in the redistribution layer structure of this disclosure, the coefficient of thermal expansion of the first dielectric layer is smaller than that of the second dielectric layer. This allows the first dielectric layer, with its lower coefficient of thermal expansion, to be matched with a substrate having a lower coefficient of thermal expansion, thus reducing deformation differences caused by the heating and cooling processes during manufacturing. Therefore, the probability of warpage in the redistribution layer structure can be reduced. The redistribution layer structure can have good structural strength or quality. Furthermore, the coefficient of thermal expansion of the multiple dielectric layers in the redistribution layer structure can gradually increase from bottom to top. The thickness of the multiple dielectric layers in the redistribution layer structure can gradually decrease from bottom to top. Therefore, the deformation differences between different dielectric layers can be reduced, thereby reducing the impact of residual stress. Additionally, the redistribution layer structure can achieve good manufacturing yield or quality. Furthermore, the upper dielectric layer, which is subjected to fewer heating and cooling processes, can use a dielectric material with a higher coefficient of thermal expansion to control manufacturing costs.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that, include: Glass substrate; A redistribution layer structure is disposed on the glass substrate; as well as Electronic components are disposed on the redistribution layer structure; The redistribution layer structure includes: A first metal layer is disposed on the glass substrate; The first dielectric layer is disposed on the first metal layer; The second metal layer is disposed on the first dielectric layer; The second dielectric layer is disposed on the second metal layer; A third metal layer is disposed on the second dielectric layer; The third dielectric layer is disposed on the third metal layer; A fourth metal layer is disposed on the third dielectric layer; and The fourth dielectric layer is disposed on the fourth metal layer. The coefficient of thermal expansion of the first dielectric layer is smaller than that of the second dielectric layer, the coefficient of thermal expansion of the second dielectric layer is smaller than that of the third dielectric layer, and the coefficient of thermal expansion of the third dielectric layer is smaller than that of the fourth dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, the thickness of the second dielectric layer is greater than the thickness of the third dielectric layer, and the thickness of the first dielectric layer is 11 micrometers to 19 micrometers.

2. The packaging structure according to claim 1, characterized in that, The Young's modulus of the first dielectric layer is 3 GPa to 5 GPa.

3. The packaging structure according to claim 1, characterized in that, The coefficient of thermal expansion of the first dielectric layer is 20 ppm / °C to 40 ppm / °C.

4. The packaging structure according to claim 1, characterized in that, The thickness of the second dielectric layer is 9 to 11 micrometers.

5. The packaging structure according to claim 1, characterized in that, The thickness of the first metal layer is 4 micrometers to 13 micrometers.

6. The packaging structure according to claim 1, characterized in that, The Young's modulus of the first metal layer is 90 GPa to 120 GPa.

7. The packaging structure according to claim 1, characterized in that, The coefficient of thermal expansion of the first metal layer is 16 ppm / °C to 20 ppm / °C.

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