Method for triggering an oscilloscope and oscilloscope using the method

Abstract

This application relates to a method for triggering an oscilloscope and an oscilloscope using the method. A method of operating an oscilloscope is disclosed. The method includes: providing a bitstream including pseudo-random data across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of an eye diagram based on receiving the pseudo-random data; inserting a predetermined bit sequence into the bitstream at predetermined periodic intervals to sufficiently open the eye diagram during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye diagram; and generating the eye diagram at least in part based on the pseudo-random data and excluding the predetermined bit sequence from the sweep of the eye diagram. An oscilloscope configured to trigger according to a predetermined bit pattern at a predetermined interval is also disclosed.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 896,793, filed Sep. 6, 2019, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] This disclosure generally relates to methods for triggering an oscilloscope and oscilloscopes using such methods. BACKGROUND ART

[0004] The quality of a synchronous digital output signal of a memory circuit can be monitored by observing an "eye diagram" formed by a digital signal. When the output of any digital synchronous circuit switches between one and zero and these transitions are captured on an oscilloscope, each trace can be displayed on top of the previous trace, and the resulting superimposed traces resemble an eye. SUMMARY OF THE INVENTION

[0005] One aspect of this application is directed to a method that includes: inserting a pre-determined bit sequence into a bit stream at a pre-determined period; providing the bit stream to an oscilloscope; and triggering the oscilloscope based on the inserted pre-determined bit sequence.

[0006] Another aspect of this application is directed to an oscilloscope that includes: a circuit configured to generate an eye diagram based on an input signal; and a circuit configured to trigger a sweep of the oscilloscope based on a pre-determined bit sequence having a pre-determined period in the input signal.

[0007] Another aspect of this application is directed to a method that includes: providing a bit stream including pseudo-random data to an oscilloscope across a data path characterized by sufficient signal degradation to prevent the oscilloscope from reliably triggering a sweep of the eye diagram based on receiving the pseudo-random data; inserting a pre-determined bit sequence into the bit stream at pre-determined periodic intervals to sufficiently open the eye diagram during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye diagram; and generating the eye diagram at least in part based on the pseudo-random data and excluding the pre-determined bit sequence from the sweep of the eye diagram.

[0008] Yet another aspect of this application is directed to a device that includes: a circuit configured to generate a bit stream for providing to an oscilloscope; a circuit configured to insert a pre-determined bit sequence into the bit stream at a pre-determined period. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a graph illustrating an eye diagram of an oscilloscope providing an input bit stream with good signal quality.

[0010] Figure 2 It is a graph showing the eye diagram of an oscilloscope that provides an input bitstream with degraded signal quality.

[0011] Figure 3 It is a graph showing the pseudo-random bitstream provided to the oscilloscope.

[0012] Figure 4 It is a graph showing another pseudo-random bitstream with pre-defined bit sequences inserted at a predetermined period according to an embodiment of the present disclosure.

[0013] Figure 5A and 5B are block diagrams schematically showing systems for respectively providing a modified bitstream to an oscilloscope and a device under test (DUT) according to various embodiments of the present disclosure.

[0014] Figure 6 is a block diagram schematically showing a system for providing a modified bitstream to an oscilloscope via a data path under test according to various embodiments of the present disclosure.

[0015] Figure 7 is a graph showing yet another pseudo-random bitstream with pre-defined bit sequences inserted at a predetermined period according to an embodiment of the present disclosure.

[0016] Figure 8 and 9 are flowcharts showing methods according to various embodiments of the present disclosure.

[0017] Figure 10 is a block diagram schematically showing a computer system according to an embodiment of the present disclosure. Detailed Description

[0018] Figure 1 An illustrative eye diagram is shown in the Detailed Description. Schematic diagram 100 shows an eye diagram 101 having several superimposed waveforms corresponding to high and low voltage rails and transitions from high to low and from low to high within one clock cycle. An oscilloscope can be set to observe the voltage of the input signal arriving at the oscilloscope and "trigger", i.e., start capturing the waveform of the input signal on the oscilloscope, based on both the input clock signal and the position of the signal relative to the eye diagram.

[0019] As Figure 1 shown, the eye diagram 101 is formed by the curves of the waveforms observed by the oscilloscope. The size of the perceived data eye corresponds to the quality of the input signal, where a higher data eye indicates a large voltage difference between the high and low signals, and a wider data eye indicates a fast transition from the low voltage state to the high voltage state, and vice versa. When the quality of the input signal is low (e.g., due to degradation caused by noise in the signal path, inter-symbol interference (ISI), etc.), the height of the data eye will be smaller and / or the width will be smaller, as referencedFigure 2 It can be seen that the schematic diagram 200 shows that Figure 1 the eye diagram 201 is shorter and narrower than the eye diagram 101 in

[0020] As the quality of the input signal continues to degrade, it may become challenging to trigger the oscilloscope properly at the appropriate time, making it difficult, if not impossible, to accurately measure the eye diagram of data received across a particular noisy channel or having other significant degradations.

[0021] To address the foregoing challenges, embodiments of the present disclosure provide methods for modifying a bitstream used to generate an eye diagram in an oscilloscope to allow the oscilloscope to reliably trigger sweeps even when the signal quality of the bitstream severely degrades. In one embodiment, a method includes: inserting a predetermined bit sequence into the bitstream at a predetermined period; providing the bitstream to the oscilloscope; and triggering the oscilloscope based on the inserted predetermined bit sequence. The inserted predetermined bit sequences may all have the same value (e.g., all zeros or all ones) to allow the eye diagram of the oscilloscope to open sufficiently to trigger reliably. If the oscilloscope optionally includes a decision feedback equalizer (DFE), the predetermined bit sequence may include as many or more bits as the number of taps of the DFE.

[0022] Figure 3 FIG. 300 is a graph illustrating a pseudo-random bitstream (PRBS) 301 that may be provided to an oscilloscope. When the PRBS 301 is provided via a data path that degrades the signal (e.g., due to noise, inter-symbol interference, etc.), it may be difficult for the oscilloscope to reliably trigger at the appropriate time to form an eye diagram that accurately characterizes the data path. To address this challenge, embodiments of the present disclosure may insert a predetermined bit sequence into the bitstream at a predetermined period, as described in more detail below with reference to Figure 4 FIG. 400 is a graph illustrating another pseudo-random bitstream 401 having predetermined bit sequences 402 and 403 inserted at a predetermined period in accordance with an embodiment of the present disclosure. As referenced in

[0023] Figure 4 FIG. 20 Figure 4It can be seen that after every n bits in the bitstream (for example, after every 16 bits, every 32 bits, every 64 bits, every 100 bits, etc.), a predetermined sequence of x bits (for example, four bits, eight bits, ten bits, 16 bits, etc.) having the same value (for example, logical "one") is inserted into the bitstream 401 (for example, at time n, a predetermined sequence 402 of x bits having a logical value of "one" is inserted into the bitstream, after n bits of the bitstream, at time 2n + x, a predetermined sequence 403 of x bits having a logical value of "one" is inserted into the bitstream, after another n bits of the bitstream, the insertion of the predetermined sequence 402 has been followed). Since the pre - defined bit sequence contains bits all having the same value (for example, all "ones" or all "zeros"), the degradation of the signal across channels will be reduced from being affected by inter - symbol interference (ISI) (for example, due to the low frequency of the constant voltage value), and at the oscilloscope receiving the modified signal, there will be a correspondingly higher signal - to - noise ratio, at least during the intervals in which the pre - defined bit sequence is being transmitted (for example, in the intervals between time n and n + x, between time 2n and 2n + 2x, etc.). By configuring the oscilloscope to trigger during these intervals when the signal quality is highest (and the eye diagram is correspondingly larger), the ability of the oscilloscope to accurately generate an eye diagram for the degraded input signal is greatly improved.

[0024] For example, Figure 5A and 5B are block diagrams schematically illustrating systems for respectively providing a modified bitstream to an oscilloscope and a device under test (DUT) according to various embodiments of the present disclosure. As can be seen with reference to Figure 5A the system 500 includes a device 510, which includes a bitstream generator 511 (for example, a PRBS) and a bit injector 512, the bit injector being configured to insert a pre - defined bit sequence into the bitstream at predetermined periodic intervals, as described in more detail above with reference to Figure 4 The device provides the modified bitstream (for example, a bitstream having a pre - defined bit sequence inserted at predetermined periodic intervals) to the oscilloscope 520. The pre - defined bit sequence is configured to sufficiently "open" the eye diagram generated by the oscilloscope 520 during each of the periodic intervals to permit the oscilloscope to trigger a sweep of a subsequent eye diagram.

[0025] According to one aspect of the present disclosure, the oscilloscope 520 may include a decision feedback equalizer (DFE) 521 for equalizing a signal received from the device 510. The DFE may include one or more taps for providing feedback on estimates of previous symbols when equalizing subsequent symbols. By providing a predetermined bit sequence that includes at least as many bits as there are taps (e.g., all having the same value), at the beginning of each sweep of the oscilloscope 520, the DFE may be placed in a known state (e.g., because the predetermined bit sequence corresponds to the triggering of each sweep), thereby providing improved DFE performance even for highly degraded input signals. This improved performance of the DFE 521 may provide a reliable metric for comparing the performance of a device under test (DUT) having a similarly configured DFE that is subsequently tested with the same bit stream.

[0026] For reference Figure 5B This benefit is better understood where the oscilloscope 520 has been removed from the system 550 and replaced by a device under test (DUT) 560. The apparatus 510 is configured to provide the same bit stream 511 that is provided to the DUT 560 so that the performance of the DUT 560 in interpreting the signal can be compared to the nearly ideal performance of the DFE 521 of the oscilloscope 520. For example, the apparatus 510 may be a bit error rate tester (BERT) configured to test the bit error rate (BER) of the DUT 560 by comparing the symbols of the bit stream as determined by the DFE 561 of the DUT 560 with the symbols determined by the DFE 521 of the oscilloscope 520 (e.g., when the DUT 560 is a memory device). In this regard, the device 510 may be configured to include an inserted predetermined bit sequence in the input signal provided to the DUT 560 (such that the DFE 561 may be similarly set to a known condition having a regular periodicity corresponding to the periodicity of the inserted sequence), or to omit the inserted sequence, to test the performance of the DUT 560 when the DFE 561 is provided with an unmodified bitstream generated by the bitstream generator 511 of the device 510.

[0027] In addition to testing the device receiving the input signal, such as Figure 5A and 5B As stated in , embodiments of the present disclosure may also be used to characterize data paths. In this regard, Figure 6 6 is a block diagram schematically illustrating a system 600 for providing a modified bit stream to an oscilloscope 620 via a data path to be tested 630 according to various embodiments of the present disclosure. Figure 6 It can be seen that the system 600 includes an apparatus 610, which includes a bit stream generator 611 (eg, PRBS) and a bit injector 612, which is configured to insert a predetermined bit sequence into the bit stream at predetermined periodic intervals, as described above with reference to Figure 4More specifically stated. The device 610 provides a modified bitstream (e.g., a bitstream having a predetermined bit sequence inserted at predetermined periodic intervals) to the oscilloscope 620 via the data path 630 to be tested and / or characterized. The predetermined bit sequence is configured to sufficiently "open" the eye diagram generated by the oscilloscope 620 during each of the periodic intervals to permit the oscilloscope to trigger a sweep of a subsequent eye diagram, such that even when the data path 630 significantly degrades the signal, an eye diagram corresponding to the data path 630 can be reliably generated beyond the range where reliable characterization by a conventional oscilloscope can be expected (e.g., due to the unreliability of triggering on a partially closed, mostly closed, or even fully closed eye diagram).

[0028] For example, in one embodiment of the present disclosure, the device 610 may include a CPU operably connected to a motherboard, and the oscilloscope 620 may be operably connected to a memory connector (e.g., a DIMM slot) of the same motherboard. By configuring the CPU of the device 610 to generate the bitstream and insert the predetermined bit sequence configured to open the data eye for reliable oscilloscope triggering, the data path 630 of the memory bus of the motherboard can be reliably characterized using the eye diagram. Alternatively, in another embodiment of the present disclosure, the device 610 may include a BERT configured to provide an input signal to a memory connector of the motherboard, and the oscilloscope 620 may be operably connected to the CPU slot of the motherboard, such that an eye diagram characterizing the memory bus of the motherboard in the other direction (e.g., from the memory slot to the CPU slot, rather than vice versa) can also be reliably generated. In yet another embodiment, a similar arrangement may be used to test the memory bus of a graphics card (e.g., from the GPU of the graphics card to its memory slot, or from its memory slot back to the GPU slot, with necessary adaptations).

[0029] According to one aspect of the present disclosure, an oscilloscope (e.g., oscilloscope 520 or oscilloscope 620) may be further configured to generate an eye diagram that omits information corresponding to a pre - defined sequence to more accurately characterize a device or data path under test (e.g., based only on PRBS and not on the pre - defined sequence). In this regard, when a bit stream contains a pre - defined sequence (e.g., having a known number x of bits, where x is a positive integer) with a predetermined periodicity (e.g., after every n data bits in a PRBS), the oscilloscope may be configured to trigger sweeps based on detecting the pre - defined sequence during a predetermined interval, but not include the voltages corresponding to the pre - defined sequence in the eye diagram. In this regard, when the oscilloscope includes a DFE (e.g., oscilloscope 520 having DFE 521), the oscilloscope may be further configured to similarly exclude bits that immediately follow the pre - defined sequence from the eye diagram to more accurately characterize the performance of the DFE of the device under test that is subsequently tested by excluding bits determined by the DFE when in a known state (e.g., because this cannot be the state corresponding to the DFE in the DUT). The number of bits omitted after the pre - defined sequence may be the same as the number of bits in the pre - defined sequence (e.g., when the number of bits in the sequence corresponds to the number of taps of the DFE), or it may be larger or smaller, as determined when optimizing the test protocol.

[0030] As stated above, the oscilloscope may be configured to trigger based on detecting a pre - defined sequence inserted into the bit stream with a known periodicity. It is still possible for the same bit sequence to occur in the bit stream itself at times other than the intervals corresponding to the predetermined periodicity, where the likelihood depends on the number of bits in the sequence. For example, Figure 7 is a graph illustrating another pseudo - random bit stream 701 having pre - defined sequences 702 and 703 inserted with a predetermined periodicity according to an embodiment of the present disclosure. As can be seen with reference to Figure 7 the bit sequence 704 (e.g., logic “one”) corresponding to the pre - defined sequences 702 and 703 occurs in the bit stream 701 outside of the periodic intervals (e.g., outside of the intervals between time n and n + x, time 2n and 2n+2x, etc.). By configuring the oscilloscope to trigger only during the intervals corresponding to the predetermined periodicity of the inserted pre - defined sequence, “false positive” trigger events, such as the sequence 704 of bits in the bit stream 701, can be avoided, and the reliability of the trigger timing of the oscilloscope can be improved.

[0031] Although in the foregoing example embodiments, the bit stream has been described and shown as being pseudo-random, in other embodiments of the present disclosure, other bit streams (such as data bit streams, other non-random bit streams) may also benefit from the insertion of a predetermined bit sequence to improve oscilloscope triggering. Additionally, although a predetermined sequence having four logical high bits (i.e., “ones”) has been described and illustrated, in other embodiments of the present disclosure, other predetermined sequences having different numbers of bits (such as any positive integer number of bits) with the same value (such as all “ones”, all “zeros”) or other patterns (such as alternating “ones” and “zeros”, etc.) may also be used.

[0032] Furthermore, although in the foregoing example embodiments, an oscilloscope having a decision feedback equalizer has been described and illustrated, in other embodiments, other equalizers (such as feed-forward equalizers, linear equalizers, etc.) may be used or no equalizer may be used. Additionally, although the data path between a memory slot and a processor (such as a CPU, GPU) has been described and illustrated in connection with a method of testing and characterizing the data path, any other data path between any two circuit devices in any system (whether a computing system or otherwise), including between non-memory devices (such as between an expansion card slot and a south bridge controller, between a graphics card slot and a north bridge controller, between an application specific integrated circuit (ASIC) device and any other device), may also benefit from the foregoing testing and characterizing methods.

[0033] Turning Figure 8 and 9 , a flowchart illustrating a method according to various embodiments of the present disclosure is provided to assist in understanding its different aspects. In this regard Figure 8 is a flowchart illustrating a method of operating an oscilloscope according to an embodiment of the present inventive technique. The method includes inserting a predetermined bit sequence into a bit stream at a predetermined period (block 810). According to one aspect of the present invention, the insertion feature of block 810 may be implemented using a bit injector 512, as described in more detail above in Figure 5A . The method further includes providing the bit stream to an oscilloscope (block 820). According to one aspect of the present disclosure, the providing feature of block 820 may be implemented using a data path 630, as described in more detail above in Figure 6 . The method further includes triggering the oscilloscope based on the inserted predetermined bit sequence (block 830). According to one aspect of the present invention, the triggering feature of block 830 may be implemented using an oscilloscope 520, as described in more detail above in Figure 5A .

[0034] Figure 9is a flow chart illustrating a method of operating an oscilloscope in accordance with an embodiment of the technology of the present invention. The method includes providing a bit stream including pseudo-random data across a data path characterized by sufficient signal degradation to an oscilloscope to prevent the oscilloscope from reliably triggering a sweep of an eye diagram based on receipt of the pseudo-random data (block 910). According to one aspect of the present disclosure, block 810's providing feature can be implemented using device 510 and bit stream generator 511, as described in more detail above in Figure 5A . The method further includes inserting a predetermined bit sequence into the bit stream at predetermined periodic intervals to sufficiently open the eye diagram during each of the periodic intervals to permit the oscilloscope to trigger a sweep of the eye diagram (block 920). According to one aspect of the present disclosure, block 910's inserting feature can be implemented using bit injector 512, as described in more detail above in Figure 5A . The method further includes generating an eye diagram based at least in part on the pseudo-random data and excluding the predetermined bit sequence from the sweep of the eye diagram (block 930). According to one aspect of the present disclosure, block 930's generating feature can be implemented using oscilloscope 520, as described in more detail above in Figure 5A .

[0035] Figure 10 is a block diagram schematically illustrating a computer system in accordance with an embodiment of the present disclosure. As can be seen with reference to Figure 10 , an example machine of computer system 1000 can include a set of instructions that when executed can cause the machine to perform any one or more of the methods discussed herein. In an alternative embodiment, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0036] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a network appliance, a server, a network router, a switch, or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by that machine. Further, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a (or multiple) set of instructions to perform any one or more of the methods discussed herein.

[0037] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1018, which communicate with each other via a bus 1030. The processing device 1002 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1002 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 1002 is configured to execute instructions 1026 for implementing the operations and steps discussed herein. The computer system 1000 may further include a network interface device 1008 to communicate on a network 1020.

[0038] The data storage system 1018 may include a non-transitory machine-readable storage medium 1024 (also referred to as a computer-readable medium) having stored thereon one or more instruction sets 1026 or software embodying any one or more of the methods or functions described herein. The instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002 during execution by the computer system 1000, and the main memory 1004 and the processing device 1002 also constitute machine-readable storage media.

[0039] Although the machine-readable storage medium 1024 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing a set or multiple sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0040] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has sometimes been convenient, for the sake of generality, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0041] However, it should be borne in mind that all such and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage systems.

[0042] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to the computer system bus.

[0043] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will be presented as will be set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be understood that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0044] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to implement a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read-only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, flash memory components, etc.

[0045] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0046] Those skilled in the art will appreciate that the components and blocks illustrated in the above-described Figures 1 to 10 may be changed in many ways. For example, the order of the logic may be rearranged, sub-steps may be performed in parallel, the illustrated logic may be omitted, other logic may be included, etc. In some embodiments, one or more of the components described above may perform one or more of the processes described below.

[0047] It should be noted that the methods described above describe possible embodiments, and the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. In addition, embodiments from two or more of the methods may be combined.

[0048] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, those of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0049] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and embodiments are within the scope of the present disclosure and the appended claims. The features implementing the functions may also be physically located at various positions, including being distributed such that parts of the functions are implemented at different physical positions.

[0050] References in this specification to "an embodiment" (e.g., "some embodiments", "various embodiments", "one embodiment", "an embodiment", etc.) mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The appearances of these phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are they separate or alternative embodiments mutually exclusive of other embodiments. Additionally, various features are described that may be presented by some embodiments and not by others. Similarly, various requirements are described that may be requirements for some embodiments and not for others.

[0051] As used herein, above a threshold means that the value of the item being compared is higher than another specified value, the item being compared is among a specified number of items having the maximum value, or the item being compared has a value within a specified top percentage value. As used herein, below a threshold means that the value of the item being compared is lower than another specified value, the item being compared is among a specified number of items having the minimum value, or the item being compared has a value within a specified bottom percentage value. As used herein, within a threshold means that the value of the item being compared is between two other specified values, the item being compared is among a specified middle number of items, or the item being compared has a value within a specified middle percentage range. For example, relative terms such as high or unimportant, when not otherwise defined, can be understood to assign a value and determine how that value will be compared to an established threshold. For example, the phrase "select a fast connection" can be understood to mean selecting a connection having a value assigned to its connection speed that is above the threshold.

[0052] As used herein (including in the claims), the "or" as used in a list of items (e.g., a list of items in a phrase followed by, for example, "at least one of" or "one or more of") indicates a list that includes the endpoints, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be understood to refer to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" can be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted equivalently to the phrase "at least partially based on".

[0053] As will be appreciated from the foregoing, specific embodiments of the present invention have been described herein for purposes of illustration, but various modifications may be made without departing from the scope of the invention. Conversely, in the foregoing description, numerous specific details have been set forth in order to provide a thorough and illuminating description of embodiments of the present invention's technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods, in addition to those specifically disclosed herein, may be within the scope of the present invention's technology.

Claims

1. A method for triggering an oscilloscope, which comprises: Inserting an instance of a pre - defined bit sequence into a bitstream at a predetermined periodicity such that the inserted instance of the pre - defined bit sequence is separated by a predetermined number of bits from the bitstream; Providing the bitstream to the oscilloscope; And Triggering the oscilloscope based on the inserted instance of the pre - defined bit sequence.

2. The method according to claim 1, wherein all bits in the pre - defined bit sequence have the same value.

3. The method according to claim 1, wherein triggering the oscilloscope based on the inserted instance of the pre - defined bit sequence includes ignoring occurrences of the pre - defined bit sequence in the bitstream that are not associated with the predetermined periodicity.

4. The method according to claim 1, wherein the bitstream includes pseudo - random data.

5. The method according to claim 4, wherein inserting the instance of the pre - defined bit sequence into the bitstream includes inserting an instance of the pre - defined bit sequence into the bitstream after every n bits of pseudo - random data, where n is a positive integer.

6. The method according to claim 1, wherein the oscilloscope includes a decision feedback equalizer (DFE) having x taps, wherein the pre - defined bit sequence includes x bits, and wherein x is a positive integer.

7. The method according to claim 6, further comprising generating an eye diagram with the oscilloscope based on triggering the oscilloscope.

8. The method according to claim 7, wherein the eye diagram excludes the inserted instance of the pre - defined bit sequence from each sweep of the eye diagram.

9. The method according to claim 8, wherein the eye diagram further excludes x bits in the bitstream after the inserted instance of the pre - defined bit sequence from each sweep of the eye diagram.

10. An oscilloscope, which comprises: A circuit configured to generate an eye diagram based on an input signal; And A circuit configured to trigger a sweep of the oscilloscope based on an instance of a pre - defined bit sequence having a predetermined periodicity in the input signal, wherein the instance of the pre - defined bit sequence is separated by a predetermined number of bits in the input signal.

11. The oscilloscope according to claim 10, which further comprises: A decision feedback equalizer (DFE) configured to equalize the input signal.

12. The oscilloscope according to claim 11, wherein the DFE includes x taps, and wherein the pre - defined bit sequence includes at least x bits having the same value.

13. The oscilloscope according to claim 12, wherein the circuit configured to generate the eye diagram is further configured to exclude the instance of the pre - defined bit sequence from the sweep of the eye diagram.

14. The oscilloscope according to claim 13, wherein the circuit configured to generate the eye diagram is further configured to exclude an additional x bits after the instance of the pre - defined bit sequence from the sweep of the eye diagram.

15. A method for operating an oscilloscope, which comprises: Providing a bit stream including pseudo-random data across a data path to the oscilloscope to prevent the oscilloscope from reliably triggering a sweep of an eye diagram based on receiving the pseudo-random data, the data path being characterized by sufficient signal degradation; Inserting an instance of a pre-determined bit sequence into the bit stream at pre-determined periodic intervals to sufficiently open the eye diagram during each of the periodic intervals to permit the oscilloscope to trigger the sweep of the eye diagram, wherein the inserted instance of the pre-determined bit sequence is separated by a pre-determined number of bits from the bit stream; and Generating the eye diagram at least in part based on the pseudo-random data and excluding the inserted instance of the pre-determined bit sequence from the sweep of the eye diagram.

16. The method according to claim 15, wherein all bits in the pre-determined bit sequence have the same value.

17. The method according to claim 15, further comprising ignoring the occurrence of the pre-determined bit sequence in the pseudo-random data.

18. The method according to claim 15, wherein inserting the instance of the pre-determined bit sequence into the bit stream at pre-determined periodic intervals includes inserting the instance of the pre-determined bit sequence into the bit stream after every n bits of the pseudo-random data, where n is a positive integer.

19. The method according to claim 15, wherein the pre-determined bit sequence includes x bits, and where x is a positive integer.

20. The method according to claim 15, wherein generating the eye diagram is further based on excluding x bits of pseudo-random data after the inserted instance of the pre-determined bit sequence from the sweep of the eye diagram.

21. The method according to claim 15, further comprising: Performing equalization on the bit stream before generating the eye diagram.

22. A device for triggering an oscilloscope, which comprises: A circuit configured to generate a bit stream to be provided to the oscilloscope, the oscilloscope being configured to trigger on a pre-determined bit sequence; A circuit configured to insert an instance of the pre-determined bit sequence into the bit stream at pre-determined periodicity such that the inserted instance of the pre-determined bit sequence is separated by a pre-determined number of bits from the bit stream.

23. The device according to claim 22, wherein the bit stream is a pseudo-random bit stream PRBS.

24. The device according to claim 22, wherein the device is a bit error rate tester BERT.

25. The device according to claim 22, wherein the device is one of a central processing unit CPU, a graphics processing unit GPU, a field programmable gate array FPGA, a memory controller, an application specific integrated circuit ASIC, a dynamic random access memory DRAM device, or a non-volatile memory device.

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