Method and apparatus for coupling a waveguide structure to an integrated circuit package

Abstract

A mechanism is provided for reducing the distance between a waveguide antenna and the transmit and receive circuitry in an integrated circuit device die. This distance reduction is achieved by vertically approaching a radio frequency connector on the top surface of the IC device die. A cavity can be formed in the encapsulant of the package to provide access to the connector and plated to provide a shielding function. A continuous connection from an RF pad serves as a vertical interconnect. The area surrounding the vertical interconnect can be filled with an encapsulant potting material and back-ground to form the surface of the semiconductor device package. A waveguide antenna feed line can be plated or printed onto the vertical interconnect on the surface of the package.

Description

Technical Field

[0001] The present disclosure relates generally to millimeter wave (mmWave) integrated circuits (e.g., integrated circuits used in automotive radar systems and high-speed communication systems), and more particularly, to incorporating waveguides and antenna feed lines into the top surface of an integrated circuit package, thereby reducing the footprint of the package, reducing signal loss between the integrated circuit and the antenna feed lines, and reducing the cost of the PCB on which the IC package is mounted. Background Art

[0002] Radar sensors and high-frequency radios (e.g., 5G-NR and WiGig) play a key role in the development of automated and autonomous driving concepts and applications. These devices may require several antennas for signal transmission and detection, and require a high degree of signal sensitivity. These antennas and the associated semiconductor device packages can occupy a considerable area on the circuit board. The use of automotive radar sensors and high-speed communication devices is expected to continue to grow in the coming years, necessitating a reduction in the size of such integrated circuit devices and an increase in their sensitivity.

[0003] Generating sufficient power for transmission and providing the required sensitivity to detect signals in millimeter-wave (mmWave or W-band) systems is limited by various semiconductor device constraints, including available area and signal attenuation with distance. To minimize power losses due to the transmission lines of the transmit and receive circuitry within the device die, various techniques have been used to reduce the distance between the waveguide antenna and the circuitry. In the past, one or more waveguide antennas have been mounted on the PCB associated with the radar integrated circuit, and the antenna feed lines were then moved closer to the circuitry by incorporating them onto the periphery of the integrated circuit package.

[0004] However, given that higher performance mmWave systems require minimal energy loss in the antennas and significant isolation between antennas, it is desirable to provide a package that minimizes the distance from the transmit / receive circuitry to the antennas. Summary of the Invention

[0005] According to one aspect of the present invention, there is provided a semiconductor device package, comprising:

[0006] a semiconductor device die comprising one or more radio frequency (RF) pads on an active major surface;

[0007] an encapsulation material over and around the semiconductor device die;

[0008] One or more antenna feed lines formed on a major surface of the sealing material, wherein

[0009] Each antenna feed line has a corresponding RF signal pad on the semiconductor device die, and

[0010] At least a portion of each antenna feed line is directly above the corresponding RF signal pad;

[0011] as well as

[0012] a vertical interconnect coupling each RF signal pad to a corresponding antenna feed line, wherein

[0013] The vertical interconnect comprises a continuous conductor formed by additive manufacturing, and

[0014] Each continuous conductor is disposed vertically through the sealing material.

[0015] According to one or more embodiments, further comprising:

[0016] one or more waveguide contact pads on the major surface of the sealing material corresponding to a first antenna feed line; and

[0017] A first electromagnetic shield is formed in a mold compound surrounding the antenna feed line and is electrically coupled to the waveguide contact pad.

[0018] In accordance with one or more embodiments, the electromagnetic shield extends to the active main surface of the semiconductor device die.

[0019] In accordance with one or more embodiments, the electromagnetic shield is configured to electromagnetically isolate the vertical interconnects.

[0020] According to one or more embodiments, further included is a waveguide electrically coupled to the first waveguide contact pad, wherein the waveguide is adhesively coupled to the major surface of the sealing material, and the waveguide is communicatively coupled to an associated antenna feed line.

[0021] According to one or more embodiments, the vertical interconnect further includes a conductive pillar formed vertically on each RF signal pad; and the continuous conductor couples the conductive pillar to the antenna feed line.

[0022] According to one or more embodiments, further included is a lead frame adhesively coupled to the inactive main surface of the semiconductor device die and including one or more leads; and one or more wire bonds electrically coupling one or more other signal pads on the active main surface of the semiconductor device die to corresponding leads of the one or more leads.

[0023] In accordance with one or more embodiments, the continuous conductor comprises a wire bond.

[0024] According to a second aspect of the present invention, there is provided a method for forming a semiconductor device package having one or more waveguide antenna feed lines formed vertically above a semiconductor device die included in the package, the method comprising:

[0025] coupling the semiconductor device die to a package lead frame, wherein the semiconductor device die includes a first radio frequency (RF) signal pad on an active major surface;

[0026] A vertical interconnect is formed from the first RF signal pad to the top major surface of the semiconductor device package, wherein

[0027] The vertical interconnect comprises a continuous conductor having a first end coupled to a connection point in the vertical interconnect and extending from the connection point to a height at least equal to a final thickness of the semiconductor device package, and

[0028] forming the continuous conductor over the connection point using additive manufacturing techniques;

[0029] forming an encapsulant over and around sides of the semiconductor device die and over and around the vertical interconnects; and

[0030] A second end of the continuous conductor is exposed at the first major surface of the semiconductor device package.

[0031] According to one or more embodiments, further including: forming a first electromagnetic shielding structure over the semiconductor device die and around the vertical interconnect, wherein the electromagnetic shielding structure extends to the first main surface of the semiconductor device package.

[0032] According to one or more embodiments, forming the encapsulant includes performing film assisted molding to form a surface on which the first electromagnetic shielding structure and a top region of the semiconductor device package are formed, wherein the film assisted molding is performed using a first sealing material.

[0033] According to one or more embodiments, forming the first electromagnetic shielding structure further includes: forming a conductive layer on a surface of the first sealing material.

[0034] According to one or more embodiments, forming the conductive layer includes sputtering or electroplating.

[0035] According to one or more embodiments, further comprising: exposing the connection point if the first electromagnetic shielding structure or the first sealing material covers the connection point in the vertical interconnect; and forming the continuous conductor vertically from the connection point to a height at least equal to the thickness of the semiconductor device package, and subsequently forming a wire bond to couple the wire bond to the surface of the electromagnetic shield.

[0036] According to one or more embodiments, exposing the second end of the continuous conductor includes: forming a second sealant over the continuous conductor and at least a portion of the first electromagnetic shielding structure; and grinding the second sealant, the first sealant, a portion of the continuous conductor, and a portion of the electromagnetic shielding structure to the final thickness of the semiconductor device package.

[0037] According to one or more embodiments, further comprising: attaching a mold barrier to the active main surface of the semiconductor device die, wherein the mold barrier surrounds the first RF signal pad; and performing the film-assisted molding such that the mold barrier prevents encapsulant from forming over the first RF signal pad.

[0038] According to one or more embodiments, forming the vertical interconnect includes forming a conductive pillar extending vertically from the first RF signal pad, wherein the connection point is a free end of the conductive pillar.

[0039] According to one or more embodiments, the connection point is the first RF signal pad.

[0040] According to one or more embodiments, further comprising: forming the one or more waveguide antenna feed lines on the top major surface of the semiconductor device package. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Embodiments of the present invention may be better understood with reference to the accompanying drawings.

[0042] Figure 1 is a simplified block diagram illustrating an example of a cross section of a high frequency RF semiconductor device including a semiconductor device package mounted on a PCB with an antenna feed line mounted externally to the semiconductor device package on the PCB.

[0043] Figure 2 is a simplified block diagram showing an example of a cross section of a high frequency RF semiconductor device with an antenna feed line disposed on a semiconductor device package.

[0044] Figure 3Ais a simplified block diagram showing a cross-section of an example high-frequency RF semiconductor device having an antenna feed line disposed on a semiconductor package in an area directly above the semiconductor device die incorporated into the package, thereby providing the shortest distance from the RF circuit system to the antenna structure.

[0045] Figure 3B It shows Figure 3A A simplified block diagram of a close-up cross-section of a semiconductor device package.

[0046] Figures 4A-4I is a set of simplified block diagrams illustrating a first process flow for forming a high frequency RF semiconductor package with vertical interconnects according to one embodiment of the present invention.

[0047] Figures 5A-5D is a set of simplified block diagrams illustrating an alternative process flow for forming a high frequency RF semiconductor package having vertical interconnects along with package-level electromagnetic (EM) shielding according to one embodiment of the present invention.

[0048] Figure 6A-6J is a set of simplified block diagrams illustrating an alternative process flow for forming a high frequency RF semiconductor package with vertical interconnects according to one embodiment of the present invention.

[0049] Figures 7A-7I is a set of simplified block diagrams illustrating an alternative process flow for forming a high frequency RF semiconductor package with vertical interconnects according to one embodiment of the present invention.

[0050] Unless otherwise indicated, the same reference numbers are used in different drawings to indicate the same items.The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0051] Embodiments of the present invention are configured to reduce the distance between a waveguide antenna and the transmit and receive circuitry in an integrated circuit (IC) device die. Embodiments achieve this reduction by vertically approaching a radio frequency (RF) connector on the top surface of the IC device die. A cavity can be formed in the encapsulant of the package to access the connector, and the cavity can be plated to perform a shielding function. A continuous connection starting from the RF pad is used as a vertical interconnect. The area around the vertical interconnect can be filled with an encapsulant potting material and back-ground to form the surface of the semiconductor device package. A waveguide antenna feed (e.g., an antenna transmitter) can be plated or printed on the vertical interconnect on the surface of the package. Such mmWave packages can be produced in a variety of package types, including, for example, multiple rows of quad flat no-leads (QFNs) in a strip or ball grid array package. Embodiments of the production process can produce high-quality, securely packaged devices.

[0052] In order to minimize the power loss caused by the transmission line from the transmit and receive circuitry in the semiconductor device die to the antenna structure, a variety of techniques have been used to reduce the distance between the antenna and the circuitry, as well as the number of connectors between different conductors in the path. In the past, waveguide antenna feeds were mounted on the PCB, and the transmission lines were mounted in the integrated circuit (IC) mounted on the PCB and in both the PCB. Subsequently, the antenna feed was moved closer to the circuitry by incorporating the antenna feed on the periphery of the integrated circuit package and mounting the waveguide antenna on both the package and the PCB on which the IC is mounted. Embodiments of the present invention minimize the distance between the transmission circuitry and the antenna structure by positioning the antenna feed directly above the IC in the package while moving the antenna feed of the waveguide antenna even closer.

[0053] Figure 1 1 is a simplified block diagram illustrating an example of a cross-section of a high-frequency RF semiconductor device 100, which includes a semiconductor device package mounted on a PCB, with antenna feed lines mounted externally to the semiconductor device package on the PCB. A semiconductor device die 110 is incorporated into a semiconductor device package 120 mounted on a PCB 130. PCB 130 includes traces 140 and 145 that electrically couple semiconductor device package 120 to antenna feed lines 150 and 155. Antenna feed lines 150 and 155 are associated with waveguide antennas 160 and 165, respectively. Waveguides 160 and 165 are associated with a receive antenna array 170 and a transmit antenna array 175, respectively.

[0054] Figure 1 One of the drawbacks of high-frequency RF semiconductor device 100 is that signal transmission lines to antenna feeds 150 and 155 require not only signal lines from device die 110 to signal contacts of semiconductor device package 120, but also need to be provided along PCB traces 140 and 145 via electronic coupling (e.g., solder balls). High-frequency signals provided over such distances may experience attenuation, resulting in a loss of sensitivity and power.

[0055] Figure 2FIG2 is a simplified block diagram illustrating an example of a cross-section of a high-frequency RF semiconductor device 200, which improves the sensitivity and power associated with the transmission and reception of high-frequency signals by locating antenna feed lines on the semiconductor device package. A semiconductor device die 210 is incorporated into a semiconductor device package 220 mounted on a PCB 230. Within semiconductor device package 220 are traces 240 and 245 that couple the circuitry within semiconductor device die 210 to antenna feed line structures 250 and 255. Incorporating antenna feed line structures 250 and 255 within semiconductor device package 220 reduces the signal path length from the circuitry within semiconductor device die 210 to the periphery of semiconductor device package 220 and eliminates solder balls from the signal path. Antenna feed lines 250 and 255 are associated with waveguide structures 260 and 265, respectively, which in turn are associated with receive antenna array 270 and transmit antenna array 275, respectively. The waveguide structure is mounted on both the semiconductor device package 220 and the PCB 230 .

[0056] While high-frequency RF semiconductor device 200 improves performance compared to semiconductor device 100 by reducing signal length, the demand for higher transmission power and receive sensitivity in current devices exceeds the transmission power and receive sensitivity that such structures can provide. This is due, in part, to inherent signal losses in interconnect transmission lines due to transmission line length and the number of transmission line interfaces, which become particularly relevant at higher frequencies (e.g., mmWave), such as increased conductive losses (e.g., skin effect) and increased dielectric losses (e.g., loss tangent). Therefore, embodiments of the present invention provide a solution for providing even shorter signal paths.

[0057] Figure 3A is a simplified block diagram illustrating a cross-section of an example high-frequency RF semiconductor device 300, which improves sensitivity associated with transmission and reception of high-frequency signals by providing an antenna feed line on the top surface of a semiconductor package in an area directly above the semiconductor device die incorporated within the package, thereby providing the shortest distance from the RF circuitry to the antenna structure. Embodiments further seek to reduce the number of interconnects between the transmit and receive circuitry and the antenna feed line to improve signal power.

[0058] The semiconductor device die 310 is incorporated into a semiconductor device package 320 mounted on a PCB 330. Antenna feed line structures 340 and 345 are formed in the area above the semiconductor device die 310. Figure 3AAn antenna feed structure formed on the surface of semiconductor device package 320 is shown, but alternative embodiments may provide antenna feeds formed within the dielectric of the package and having an exposed surface or covered by the dielectric but accessible to the top surface of the semiconductor device package. These alternative embodiments may provide the advantage of reducing RF power loss when transmitting from one waveguide structure formed within the package to another waveguide structure formed outside the package. Signal lines 350 and 355 are formed from contacts provided on the top surface of semiconductor device die 310 to the antenna feed structure. Signal lines 350 and 355 are formed to pass vertically through the packaging material of semiconductor device package 320. In addition, electromagnetic shielding structures 360 and 365 may be formed around the signal lines to electrically isolate the signal lines from each other. Electromagnetic shielding structures 360 and 365 may also be used to provide contacts for waveguide structures 370 and 375 that form receive and transmit antenna arrays. Waveguide structures 370 and 375 may be mounted on both the semiconductor device package and the PCB.

[0059] Figure 3B is a diagram showing an embodiment of the present invention Figure 3A A simplified block diagram of a close-up cross-section of a semiconductor device package 320 is shown. Semiconductor device die 310 has RF signal pads 342 and 343 on the top surface of the die. These RF signal pads are coupled to antenna feed structures 340 and 345 at the surface of the package via vertical signal lines 350 and 355. Electromagnetic shielding structures 360 and 365 form a shielding frame around the sides and bottom of the area where the signal lines are constructed. In one embodiment, the bottom portions of electromagnetic shielding structures 360 and 365 are approximately 100 μm from the top surface of semiconductor device die 310. The sides of the electromagnetic shielding structures extend approximately 200 μm to the top surface of package 320. The package cross-section also shows that semiconductor device die 310 is adhesively secured to package lead frame 380, and that wire bonds 385 electrically couple the signal pads on the perimeter of the device die to the leads of the lead frame. All of these structures, except the antenna feed shown, are enclosed in encapsulant 390. In the alternative antenna feed embodiments described above, those structures may also be encapsulated. Examples of how to form the above structures are discussed in more detail below.

[0060] Embodiments of the present invention provide various processes for forming semiconductor device packages with short signal paths required in high-frequency RF applications. Such signal paths can be formed using vertical interconnect technologies (e.g., wire bonding, additive manufacturing processes, etc.), combined with sealing and back-grinding techniques to produce optimal signal path distances, and employing shielding structures suitable for specific applications.

[0061] Figures 4A-4I is a set of simplified block diagrams illustrating a first process flow for forming a high frequency RF semiconductor package 400 with vertical interconnects according to one embodiment of the present invention. Figure 4A A semiconductor device die 405 is shown having a mold barrier frame 410 formed on the top surface of the semiconductor device die surrounding a top surface area including signal pads 415. The mold barrier frame 410 can be electroplated onto the top surface of the semiconductor device die while the die is still part of a wafer, prior to device die separation. Each appropriate semiconductor device die on the wafer can receive one or more mold barrier frames surrounding the signal pads, as shown. The barrier frames help prevent encapsulation material from covering the signal pads and also provide a cavity within which to form vertical interconnects to the signal pads.

[0062] In the embodiment shown herein, semiconductor device die 405 (and those semiconductor device dies subsequently shown, for example, as 605 and 705) have an active side oriented face-up toward the top surface of the semiconductor device package being formed. The active side includes a plurality of die pads connected to active circuitry within the semiconductor device, wherein the peripheral die pads of semiconductor device die 405 are attached (e.g., mechanically attached and electrically connected) to leads on a lead frame (e.g., lead frame 420) via wire bonding. Signal pads 415 are connected to signal lines of the active circuitry that carry radio frequency (RF) signals. As will be described more fully below, the RF signals are carried by conductive paths coupled between signal pads 415 and an antenna structure.

[0063] Semiconductor device die 405 may be separated from a semiconductor wafer, which may be made of any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, single crystal silicon, and combinations thereof. Such semiconductor dies include active circuitry, which may include integrated circuit components that are active when power is supplied to the die. The active circuitry is formed on the semiconductor wafer using a series of numerous process steps applied to the semiconductor wafer, including but not limited to: depositing semiconductor materials, including dielectric materials and metals, such as growth, oxidation, sputtering, and conformal deposition; etching the semiconductor materials, such as using wet or dry etchants; planarizing the semiconductor materials, such as by chemical mechanical polishing or planarization; performing photolithography for patterning, including depositing and removing photolithographic masks or other photoresist materials; ion implantation; annealing, and the like. In some embodiments, the active circuitry may be a combination of integrated circuit components or may be another type of microelectronic device. Examples of integrated circuit components include, but are not limited to, processors, memory, logic, oscillators, analog circuitry, sensors, such as resistors, inductors, capacitors, diodes, power transistors, and other discrete devices.

[0064] It should be noted that in the presently described embodiments, the active circuitry of die 405 includes a radio frequency (RF) block that implements an RF transmitter, an RF receiver, or both. In embodiments, RF signals are transmitted, received, or both transmitted and received via antennas on the resulting device (e.g., waveguides 370 and 375), which are communicatively coupled to the active circuitry of semiconductor device die 405 (e.g., via one or more external electrical connections between signal pad 415 and the waveguide antenna feed). The RF block may implement the front-end components of an RF transmitter, an RF receiver, or both, where the front-end components may include, but are not limited to, a transmitter power amplifier, a receiver low-noise amplifier, one or more baluns, one or more filters, a circulator or other coupling device to the antenna, impedance matching elements, an oscillator, a phase-locked loop, and other appropriate front-end components. The front-end components of the RF block may have configurable settings to adjust the transmitted or received signals. In some embodiments, the RF block may have an operating frequency within the 76 GHz to 81 GHz frequency band, but other operating frequencies within other radio frequencies may be implemented in other embodiments.

[0065] Figure 4B The semiconductor device die 405 is shown attached to a lead frame 420. Additionally, signal contact pads along the periphery of the semiconductor device die 405 are electrically coupled to the leads of the lead frame 420 by wire bonds 425. Figure 4C Semiconductor device package 400 is shown at a subsequent stage of manufacturing, performing a film-assisted molding process. A mold block 430 is provided over the semiconductor device die / leadframe assembly, wherein the mold block 430, or a film covering the mold block 430, is in contact with a mold barrier frame 410. This forms a sealing area in which a molding compound can be provided to form a package encapsulant. Encapsulant 435 is injected into the sealing area under heat and pressure until all the encapsulant material is cured. The mold barrier frame 410 prevents the encapsulant from forming over the top surface signal pads 415, leaving a cavity 440 in the area of ​​the mold barrier frame.

[0066] The sealing material can be any suitable sealing material, including, for example, epoxy molding compounds filled with silicon dioxide, plastic sealing resins, and other polymeric materials such as silicones, polyimides, phenolic resins, and polyurethanes. As discussed above, once the sealing material is applied, the encapsulated panel or strip can be cured by exposing the material to a specific temperature for a period of time, by applying a curing agent, or both, depending on the nature of the sealing material and the components being sealed. Low-loss RF properties are not required for sealant 435, as this sealant will not be part of the dielectric that encloses the RF connector.

[0067] Figure 4D Shown in Figure 4CSemiconductor device package 400 is then fabricated at a subsequent stage. Mold block 430 is removed, and resist material 445 is applied to cover top surface signal pads 415. Conductive layer 450 is then sputtered over the surfaces of sealing material 435 and resist material 445, also contacting the conductive material of mold barrier frame 410. Conductive layer 450 and mold barrier frame 410 form a shielding frame in the final product, and therefore the materials used for conductive layer 450 and mold barrier frame 410 should be consistent with the desired application. In one embodiment, conductive layer 450 comprises copper or multiple layers of copper and stainless steel. Figure 4E Provided in Figure 4C A subsequent stage of fabrication follows in which the resist is removed to expose the top surface signal pads on the device die 405 .

[0068] In an alternative embodiment, the conductive layer 450 can be formed on the surface of the encapsulation material 435 using electroplating or conductive inkjet coating rather than sputtering. For example, after the encapsulant is formed, a seed layer can be sputtered over the entire surface of the semiconductor device package, including the area where the top surface signal pads 415 are placed. Subsequently, the area incorporating the die pads can be covered with a resist material, and then the remaining surface of the semiconductor device package can be electroplated with a conductive material (e.g., copper). The resist can then be removed from the top surface signal pad area, and the seed layer can be etched back to the signal pads, exposing the top surface signal pads. This can produce Figure 4E A structure similar to that of the structure wherein the top surface signal pad 415 may be used as Figure 4F Additionally, thicker conductive layers can be formed in this way, which can then aid in shielding at lower frequencies.

[0069] Figure 4F Shown in Figure 4E The semiconductor device package 400 is then fabricated at a subsequent stage. Vertical interconnects 455 are formed vertically from the top surface signal pads 415, rising above the top surface of the conductive layer 450. The vertical interconnects may be formed using a variety of additive manufacturing techniques, including, for example, wire bonding, 3D printing, and the like. Figure 4F 4. In the example depicted, the wire bonds continue through the vertical path to connect to a point on conductive layer 450. Vertical interconnects 455 are formed so that the conductive structure is in a region directly above the corresponding top surface signal pad at least to the surface level of conductive layer 450. While wire bonds are used in the example depicted, in alternative embodiments, other techniques may be used to form the vertical portion of the interconnect above the top surface signal pad, and embodiments of the present invention are not limited to wire bonds but may encompass a variety of techniques for providing a continuous conductive structure formed on and above the top surface signal pad.

[0070] Figure 4G Shown in Figure 4F The semiconductor device package 400 is then fabricated at a subsequent stage of fabrication. Sealing material 460 is formed in the area of ​​the exposed vertical interconnects and over the surface of the conductive layer 450. Sealing material 460 may be applied using a needle-type dispensing mechanism 465. Depending on the application, sealing material 460 may include, for example, a potting material such as epoxy, thermoset plastic, or silicone rubber. Sealing material 460 may be the same as or different from sealing material 435, but generally may have low-loss RF properties because sealing material 460 contacts the vertical RF connectors.

[0071] Figure 4H Shown in Figure 4G The semiconductor device package 400 is shown in a subsequent manufacturing stage. The strip of semiconductor package is back-ground to remove a portion of encapsulation material 460, a portion of vertical interconnects 455, and a top portion of conductive layer 450. In some embodiments, it may be necessary to remove a portion of encapsulation material 435 to reduce the overall thickness of the semiconductor device package. Back-grounding forms a top major surface of the package with exposed portions of vertical interconnects 455 and conductive layer 450. The exposed portions of vertical interconnects 455 are enclosed in encapsulation material 460, which is in turn bounded by conductive layer 450 and mold barrier frame 410.

[0072] Figure 4I Shown in Figure 4H FIG4 is a semiconductor device package 400 at a manufacturing stage after the manufacturing stage of FIG4 . As shown, an antenna feed line 470 and a waveguide contact 480 are formed on the top surface of the semiconductor device package 400. The antenna feed line 470 is formed on the sealing material 460 and is in conductive contact with the exposed portion of the vertical interconnect 455, while the waveguide contact 480 is formed to contact the exposed portion of the conductive layer 450. In one embodiment, the antenna feed line and the waveguide contact are formed by sputtering a seed layer on the top surface of the semiconductor device package 400. A dry film resist can be applied to the seed layer and patterned for the antenna feed line traces and the waveguide contact. The heat sink traces and waveguide contacts can be electroplated, and then the resist is removed and the seed layer is etched to remove the exposed seed layer. Alternatively, the antenna feed line traces and the waveguide contact can be formed using electroplating or a conductive inkjet / spray coating method.

[0073] Once formed, the conductive material of vertical interconnect 455 provides a path for the RF signal provided by top surface signal pad 415 to antenna feed 470. Additionally, the material of conductive layer 450 provides a shielding frame to isolate the vertical RF interconnect. A waveguide can then be attached to the top surface of semiconductor device package 400 in the area of ​​the antenna feed and coupled to the waveguide contact pads. A conductive adhesive film can be used to attach the waveguide. Additionally, the waveguide can include a spacing transformer to move the waveguide associated with the antenna feed further apart than the spacing of the antenna feed on the semiconductor device package.

[0074] Figures 5A-5D is a set of simplified block diagrams illustrating an alternative process flow for forming a high frequency RF semiconductor package 500 including vertical interconnects along with package-level electromagnetic (EM) shielding according to one embodiment of the present invention. Figure 5A Shown is approximately Figure 4H The semiconductor device package 500 at this stage of manufacture is shown in FIG. The semiconductor package 500 at this stage differs from the semiconductor package 400 at a similar stage in that it includes package through-holes 510 drilled through the encapsulation material 435 to provide a conductive path from the top surface of the semiconductor package 500 to the contacts on the lead frame. Figure 4C The package through hole 510 is formed at a point (after the film assisted molding step shown in FIG).

[0075] Figure 5B Shielding layer 520 is shown formed on the surface of semiconductor device package 500. Shielding layer 520 can be formed by, for example, Figure 4D The conductive material is formed by the sputtering process used to form the conductive layer 450. In one embodiment, the shielding layer 520 may include copper or multiple layers of copper and stainless steel, or other conductive materials suitable for the application. As shown, the conductive layer 520 is in electrical contact with the conductive layer 450 and the package through-hole 510.

[0076] exist Figure 5C 4, a portion of shield layer 520 is removed from an area surrounding and above an antenna feed line contact formed by vertical interconnects 455 coupled to a top surface signal pad of semiconductor device die 405. This material removal can be performed using techniques known in the art, including, for example, coating a dry film resist material over the shield layer containing the opening in the antenna feed area and then etching the shield layer material from the areas not protected by the resist.

[0077] Figure 5D The semiconductor device package 500 is shown after forming a heat sink trace 530 at the surface of the encapsulation material 450 that contacts the vertical interconnect 455 in the antenna feed area. Figure 4IThe antenna feed trace 530 may be formed by sputtering a seed layer, applying a resist patterned for the heat sink trace, electroplating the heat sink trace, removing the resist, and etching the seed layer. The shielding layer 520 may provide electromagnetic protection from high frequency signals in the antenna signal path or other signal paths to the circuitry within the semiconductor device package 500 beneath the shielding layer.

[0078] Figures 6A-6J is a set of simplified block diagrams illustrating an alternative process flow for forming a high frequency RF semiconductor package 600 with vertical interconnects according to one embodiment of the present invention. Figure 6A A semiconductor device die 605 including top surface signal pads 615 is shown.

[0079] Figure 6B A semiconductor device die 605 is shown attached to a lead frame 620. Additionally, signal contact pads along the periphery of the semiconductor device die 605 are electrically coupled to leads of the lead frame 620 by wire bonds 625. Figure 6C A semiconductor device package 600 is shown at a subsequent stage of manufacturing, performing a film-assisted molding process. A mold block 630 containing a cover film is provided over the semiconductor device die / leadframe assembly. An encapsulation material 435 is then injected under heat and pressure into the area between the mold and the semiconductor device die until all of the encapsulation material is cured. As shown, the encapsulation material is formed over the entire semiconductor device die 605, including the top surface signal pads 615.

[0080] Figure 6D Shown in Figure 6C The subsequent stage of manufacturing the semiconductor device package 600 is followed by removing the mold block 630 and sputtering a seed layer 640 over the surface of the encapsulation material 635. Figure 6E A subsequent stage of fabrication is shown in which a resist 645 is applied to cover the area above the top surface signal pad 615. The surface is then plated with a conductive layer 650. The conductive layer 650 will form the shield frame in the final product, and therefore the material used for the conductive layer 650 should be consistent with the desired application. In one embodiment, the conductive layer 650 comprises copper or multiple layers of copper and stainless steel. Figure 6F Provided in Figure 6E A subsequent stage of fabrication follows in which the resist 645 is removed to expose the underlying seed layer, and the seed layer is subsequently etched to expose the encapsulant over the top surface signal pads 615 on the device die 605. Drilling can then be performed to remove the encapsulant material to expose the top surface signal pads 615. One example of a drilling method is laser drilling, which can provide high precision in the depth and area of ​​the hole 653 formed through the encapsulant 635 to the top of the semiconductor device die 605.

[0081] Figure 6G Shown in Figure 6F The semiconductor device package 600 is then fabricated at a subsequent stage. Figure 6G-6J Provided with the above Figure 4F-4I . Vertical interconnects 655 are formed vertically from the top surface signal pads 615, rising above the top surface of the conductive layer 650, and then, in the case where the vertical interconnects 655 are formed by wire bonding, are formed to connect to points on the conductive layer 650. The vertical interconnects 655 are formed so that the wire bonding is in the area directly above the corresponding top surface signal pad at least to the plane of the surface of the conductive layer 650. As Figure 4F , embodiments are not limited to forming vertical interconnects 655 by wire bonding, and may include other types of additive manufacturing techniques.

[0082] Figure 6H Shown in Figure 6G Semiconductor device package 600 is then fabricated at a subsequent stage of manufacturing. Sealing material 660 is formed in the area of ​​the exposed vertical interconnects and over the surface of conductive layer 650. Sealing material 660 may be applied using a needle-type dispensing mechanism 665. Depending on the application, sealing material 660 may include, for example, a potting material such as epoxy, thermosetting plastic, or silicone rubber. Sealing material 660 may be the same as or different from sealing material 635.

[0083] Figure 6I Shown in Figure 6H 6. The semiconductor device package 600 is shown in a subsequent manufacturing stage. The strip of semiconductor package is back-ground to remove a portion of the encapsulation material 660 and a top portion of the conductive layer 650. The back-ground process leaves the top surface of the package exposed, with vertical interconnects 655 and a portion of the conductive layer 650 exposed. The exposed portion of the vertical interconnects 655 is embedded in the encapsulation material 660, which is in turn bounded by the conductive layer 650 and the aperture 653.

[0084] Figure 6J Shown in Figure 6IThe semiconductor device package 600 is shown in a manufacturing stage after the manufacturing stage of the semiconductor device package 600. An antenna feed line 670 and a waveguide contact 680 are formed on the top surface of the semiconductor device package 600. The antenna feed line 670 is formed to be in conductive contact with the exposed portion of the vertical interconnect 655, and the waveguide contact 680 is formed on the sealing material 660 and is in conductive contact with the exposed portion of the conductive layer 650. In one embodiment, the antenna feed line and the waveguide contact are formed by sputtering a seed layer on the top surface of the semiconductor device package 600. A dry film resist can be applied to the seed layer and patterned for the antenna feed line traces and the waveguide contacts. The heat sink traces and waveguide contacts can be electroplated, and then the resist is removed and the seed layer is etched to remove the exposed seed layer. Alternatively, the antenna feed line traces and the waveguide contacts can be formed using an electroplating method.

[0085] Once formed, the conductive material of vertical interconnect 655 provides a path for the RF signal provided by top surface signal pad 615 to antenna feed 670. Additionally, the material of conductive layer 650 provides a shielding frame to isolate the vertical RF interconnect. A waveguide can then be attached to the top surface of semiconductor device package 600 in the area of ​​the antenna feed and coupled to the waveguide contact pads. A conductive adhesive film can be used to attach the waveguide. Additionally, the waveguide can include a spacing transformer to move the waveguide associated with the antenna feed further apart than the antenna feed on the semiconductor device package.

[0086] Figures 7A-7I is a set of simplified block diagrams illustrating an alternative process flow for forming a high frequency RF semiconductor package 700 with vertical interconnects according to one embodiment of the present invention. Figure 7A A semiconductor device die 705 is shown including top surface signal pads 715. Unlike previously discussed embodiments, the semiconductor device die 705 has first vertical interconnects 710 that are plated onto the top surface signal pads while the device die is still on the wafer. These first vertical interconnects can be, for example, copper pillars that rise to approximately 100 μm from the top surface of the semiconductor device die.

[0087] Figure 7B A semiconductor device die 705 is shown attached to a lead frame 720. Additionally, signal contact pads along the periphery of the semiconductor device die 705 are electrically coupled to leads of the lead frame 720 by wire bonds 725. Figure 7BAlso shown is a semiconductor device package 700 that has undergone a film-assisted molding process. A mold block 730 is provided over the semiconductor device die / leadframe assembly, contacting the first vertical interconnect 710. An encapsulant 735 is injected into the mold under heat and pressure until all of the encapsulant is cured. As shown, encapsulant 735 forms over the entire semiconductor device die 705, excluding the top of the first vertical interconnect 710. This provides a conductive path to the top surface signal pad 715.

[0088] Figure 7D Shown in Figure 7C The semiconductor device package 700 is then fabricated at a subsequent stage of manufacture. The mold block 730 is removed, and a seed layer 740 is sputtered over the surface of the encapsulation material 735 . Figure 7E A subsequent stage of fabrication is then shown, in which a resist 745 is applied to cover the area above the first vertical interconnect 710. The surface is then electroplated with a conductive layer 750. The conductive layer 750 will form the shield frame in the final product, and therefore the material used for the conductive layer 750 should be suitable for the desired application. In one embodiment, the conductive layer 750 comprises copper or multiple layers of copper and stainless steel.

[0089] Figure 7F Provided Figure 7E A subsequent stage of fabrication follows in which the resist is removed to expose the underlying seed layer, and the seed layer is subsequently etched to expose the seed layer and the encapsulant 735 in an area below the top surface of the vertical interconnect 710. A second vertical interconnect 755 can then be formed vertically from the top surface of the first vertical interconnect 710, rising above the top surface of the conductive layer 750, and then, in the case of forming the second vertical interconnect 755 by wire bonding, formed to connect to a point on the conductive layer 750. The second vertical interconnect 755 is formed so that it is planar to at least the surface of the conductive layer 750 in an area directly above the corresponding top surface signal pad. An advantage of using the first vertical interconnect 710 rather than coupling the second vertical interconnect directly to the top surface signal pad 715 is that there is no need to remove material down to the surface of the semiconductor device die 705 (e.g., as in semiconductor device package 600) or to leave a cavity for access to the top surface of the device die (e.g., as in semiconductor device package 400). However, one disadvantage of this approach is the addition of material interfaces (e.g., between the vertical interconnects and the top surface signal pads, and between the first and second vertical interconnects) that can affect the resistance of the signal path and, therefore, the performance of the device.

[0090] Figure 7G-7I Provided with the above Figure 6H-6J The manufacturing stages are similar to those shown in . Figure 7G Shown in Figure 7F Semiconductor device package 700 is then fabricated at a subsequent stage. Sealing material 760 is formed in the exposed wire bond areas and over the surface of conductive layer 750. Sealing material 760 may be applied using a needle-type dispensing mechanism 765. Depending on the application, sealing material 760 may include, for example, a potting material such as epoxy, thermosetting plastic, or silicone rubber. Sealing material 760 may be the same as or different from sealing material 735.

[0091] Figure 7H Shown in Figure 7G 7. The semiconductor device package 700 is shown in a manufacturing stage subsequent to the previous manufacturing stage. The strip of semiconductor package is back-ground to remove a portion of the encapsulation material 760 and a top portion of the conductive layer 750. The back-grounding results in a top surface of the package that exposes a second vertical interconnect 755 and a portion of the conductive layer 750. The exposed portion of the second vertical interconnect 755 is embedded in the encapsulation material 760, which is in turn bounded by the conductive layer 750.

[0092] Figure 7I Shown in Figure 7H The semiconductor device package 700 is provided at a manufacturing stage after the manufacturing stage of the semiconductor device package 700. An antenna feed line 770 and a waveguide contact 780 are formed on the top surface of the semiconductor device package 700. The antenna feed line 770 is formed on the sealing material 760 and is in contact with the exposed portion of the second vertical interconnect 755, while the waveguide contact 780 is formed to be in contact with the exposed portion of the conductive layer 750. In one embodiment, the antenna feed line and the waveguide contact are formed by sputtering a seed layer on the top surface of the semiconductor device package 700. A dry film resist may be applied to the seed layer and patterned for the antenna feed line trace and the waveguide contact. The heat sink trace and the waveguide contact may be electroplated, and then the resist may be removed and the seed layer etched to remove the exposed seed layer. Alternatively, the antenna feed line trace and the waveguide contact may be formed using an electroplating method.

[0093] Once formed, the conductive material of second vertical interconnect 755, together with the conductive material of vertical interconnect 710, forms a combined interconnect for the RF signals provided by top surface signal pad 715 to antenna feed 770. Additionally, the material of conductive layer 750 provides a shielding frame to isolate the vertical RF interconnects. A waveguide can then be attached to the top surface of semiconductor device package 700 in the area of ​​the antenna feed and coupled to the waveguide contact pads. A conductive adhesive film can be used to attach the waveguide. Additionally, the waveguide can include a spacing transformer for moving the waveguides associated with the antenna feed further apart than the spacing of the antenna feed on the semiconductor device package.

[0094] exist Figure 7A In an alternative embodiment of the structure shown in FIG, the area around the first vertical interconnect 710 may be plated, for example Figure 4A The mold barrier shown in FIG. Figures 4A-4I In the embodiment shown in FIG, the mold barrier provides an area around the first vertical interconnect where molding compound is not formed during film-assisted molding. In addition, the mold barrier can also provide a conductive path for the shielding structure to the surface of the semiconductor device die 705, thereby providing shielding over the bottom portion of the first vertical interconnect.

[0095] It should now be appreciated that a semiconductor device package has been provided, comprising: a semiconductor device die having one or more RF pads on an active major surface; an encapsulation material over and around the semiconductor device die; one or more antenna feed lines formed on a major surface of the encapsulation material; and a vertical interconnect coupling each RF signal pad to a corresponding antenna feed line. Each antenna feed line has a corresponding RF signal pad on the semiconductor device die, and at least a portion of each antenna feed line is directly over the corresponding RF signal pad. The vertical interconnect comprises a continuous conductor formed by additive manufacturing, with each continuous conductor vertically positioned through the encapsulation material.

[0096] In one aspect of the above embodiment, the semiconductor device package further includes one or more waveguide contact pads on a major surface of the encapsulant corresponding to a first antenna feed line, and a first electromagnetic shield formed in a mold compound surrounding the antenna feed line and electrically coupled to the waveguide contact pads. In another aspect, the electromagnetic shield extends to the active major surface of the semiconductor device die. In yet another aspect, the electromagnetic shield is configured to electromagnetically isolate the vertical interconnects. In yet another aspect, the semiconductor device package further includes a waveguide electrically coupled to the first waveguide contact pad, wherein the waveguide is adhesively coupled to the major surface of the encapsulant, and the waveguide is communicatively coupled to the associated antenna feed line.

[0097] In another aspect of the above embodiment, the vertical interconnect further comprises a conductive stud formed vertically on each RF signal pad, and a continuous conductor couples the conductive stud to the antenna feed line. In another aspect of the above embodiment, the semiconductor device package further comprises: a lead frame adhesively coupled to the inactive major surface of the semiconductor device die and comprising one or more leads; and one or more wire bonds electrically coupling one or more other signal pads on the active major surface of the semiconductor device die to corresponding leads of the one or more leads. In yet another aspect of the above embodiment, the continuous conductor comprises a wire bond.

[0098] Another embodiment provides a method for forming a semiconductor device package having one or more waveguide antenna feed lines formed vertically above a semiconductor device die included in the package. The method includes coupling the semiconductor device die to a package leadframe, wherein the semiconductor device die includes a first RF signal pad on an active major surface; forming a vertical interconnect from the first RF signal pad to a top major surface of the semiconductor device package; forming an encapsulant over and around the sides of the semiconductor device die and over and around the vertical interconnect; and exposing a second end of a continuous conductor at the first major surface of the semiconductor device package. The vertical interconnect includes a continuous conductor having a first end coupled to a connection point in the vertical interconnect and extending from the connection point to a height at least equal to the final thickness of the semiconductor device package, and the continuous conductor is formed above the connection point using additive manufacturing technology.

[0099] An aspect of the above embodiment further includes forming a first electromagnetic shielding structure above the semiconductor device die and around the vertical interconnects, wherein the electromagnetic shielding structure extends to a first major surface of the semiconductor device package. In another aspect, forming the encapsulant includes performing film-assisted molding to form a surface on which the first electromagnetic shielding structure is formed and a top region of the semiconductor device package, wherein the film-assisted molding is performed using a first encapsulant material. In yet another aspect, forming the first electromagnetic shielding structure further includes forming a conductive layer on a surface of the first encapsulant material. In yet another aspect, forming the conductive layer includes sputtering or electroplating.

[0100] In another further aspect, the method further comprises: exposing a connection point in the vertical interconnect if the first electromagnetic shielding structure or the first encapsulant covers the connection point; forming a continuous conductor vertically from the connection point to a height at least equal to the thickness of the semiconductor device package; and subsequently forming a wire bond to couple the wire bond to a surface of the electromagnetic shield. In yet another further aspect, exposing the second end of the continuous conductor comprises forming a second encapsulant over at least a portion of the continuous conductor and the first electromagnetic shielding structure, and grinding the second encapsulant, the first encapsulant, a portion of the continuous conductor, and a portion of the electromagnetic shielding structure to a final thickness of the semiconductor device package.

[0101] Another aspect additionally includes attaching a mold barrier to the active major surface of the semiconductor device die, wherein the mold barrier surrounds the first RF signal pad; and performing film assisted molding such that the mold barrier prevents encapsulant from forming over the first RF signal pad.

[0102] In another aspect of the above embodiment, forming the vertical interconnect includes forming a conductive pillar extending vertically from the first RF signal pad, wherein the connection point is a free end of the conductive pillar. In another aspect of the above embodiment, the connection point is the first RF signal pad. Yet another aspect of the above embodiment further includes forming one or more waveguide antenna feed lines on the top major surface of the semiconductor device package.

[0103] Because the apparatus implementing the present invention is composed, for the most part, of electronic components and circuits known to those skilled in the art, circuit details will not be explained to any greater extent than deemed necessary as shown above in order to understand and appreciate the basic concepts of the invention and so as not to obscure or distract from the teachings of the invention.

[0104] Furthermore, the use of the terms "front," "back," "top," "bottom," "above," "below," and the like, if any, in the specification and in the claims, is for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

[0105] It should be understood that the architectures depicted herein are merely exemplary, and that many other architectures that achieve the same functionality may be implemented. In an abstract, yet still explicit, sense, any arrangement of components that achieve the same functionality is in fact "associated" to achieve the desired functionality. Thus, any two components herein combined to achieve a particular functionality may be considered "associated" with each other to achieve the desired functionality, regardless of the architecture or intervening components. Similarly, any two components so associated may also be considered "operably connected" or "operably coupled" to each other to achieve the desired functionality.

[0106] Furthermore, those skilled in the art will recognize that the boundaries between the functionality of the above-described operations are illustrative only. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be dispersed into other operations. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0107] Although the present invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the appended claims. Therefore, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not intended to be construed as key, required, or essential features or elements of any or all the claims.

[0108] As used herein, the term "coupled" is not intended to be limited to a direct coupling or a mechanical coupling.

[0109] Furthermore, the terms "a" and "an," as used herein, are defined as one or more than one. Furthermore, introductory phrases such as "at least one" and "one or more" used in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing such introduced element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a." The same applies to the use of definite articles.

[0110] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A semiconductor device package, characterized in that: include: a semiconductor device die comprising one or more radio frequency (RF) pads on an active major surface; an encapsulation material over and around the semiconductor device die; one or more waveguide contact pads on the major surface of the sealing material; as well as one or more antenna feed lines formed in openings in a first electromagnetic shield and on a major surface of the encapsulation material, wherein the first electromagnetic shield is formed in a mold compound surrounding the antenna feed lines and is electrically coupled to the waveguide contact pads, the first electromagnetic shield extending above the encapsulation material; Each antenna feed line has a corresponding radio frequency (RF) pad on the semiconductor device die, and At least a portion of each antenna feed line is directly above the corresponding radio frequency (RF) pad; as well as a vertical interconnect coupling each radio frequency (RF) pad to a corresponding antenna feed line, wherein The vertical interconnect comprises a continuous conductor formed by additive manufacturing, and Each continuous conductor is disposed vertically through the sealing material.

2. The semiconductor device package according to claim 1, wherein: The electromagnetic shield extends to the active main surface of the semiconductor device die.

3. The semiconductor device package according to claim 2, wherein: The electromagnetic shield is configured to electromagnetically isolate the vertical interconnects.

4. The semiconductor device package according to claim 2, wherein: Also includes: a waveguide electrically coupled to the waveguide contact pad, wherein The waveguide is adhesively coupled to the major surface of the sealing material, and The waveguide is communicatively coupled to an associated antenna feed line.

5. The semiconductor device package according to claim 1, wherein The vertical interconnect further comprises: A conductive pillar is vertically formed on each radio frequency (RF) pad; and The continuous conductor couples the conductive post to the antenna feed line.

6. The semiconductor device package according to claim 1, wherein Also includes: a lead frame adhesively coupled to the inactive major surface of the semiconductor device die and including one or more leads; as well as One or more wire bonds electrically couple one or more other signal pads on the active major surface of the semiconductor device die to corresponding ones of the one or more leads.

7. The semiconductor device package according to claim 1, wherein: The continuous conductor includes a wire bond.

8. A method for forming a semiconductor device package having one or more waveguide antenna feed lines formed vertically above a semiconductor device die included in the package, characterized in that: The method comprises: coupling the semiconductor device die to a package lead frame, wherein the semiconductor device die includes a first radio frequency (RF) signal pad on an active major surface; A vertical interconnect is formed from the first radio frequency (RF) signal pad to the top major surface of the semiconductor device package, wherein The vertical interconnect comprises a continuous conductor having a first end coupled to the first radio frequency (RF) signal pad and extending from the first end to a height at least equal to a final thickness of the semiconductor device package, and forming the continuous conductor over the first end using an additive manufacturing technique; forming an encapsulant over and around sides of the semiconductor device die and over and around the vertical interconnects; forming a first electromagnetic shielding structure over the semiconductor device die and around the vertical interconnect, wherein the electromagnetic shielding structure extends over the encapsulant, and The first electromagnetic shielding layer has an opening above the first radio frequency (RF) signal pad, and A second end of the continuous conductor is exposed at the first major surface of the semiconductor device package.

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