Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the same are provided. The display device includes: a plurality of pixels connected to gate lines and data lines; a gate driver for supplying gate signals to the gate lines; and a data driver for supplying data signals to the data lines. The gate driver includes: a first transistor including a first active layer at a first layer; and a second transistor including a second active layer at a second layer on the first layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0101685 filed on August 20, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Aspects of the disclosed embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0003] The display device includes pixels and a driving circuit for driving the pixels. The driving circuit includes a gate driver for controlling the driving timing of the pixels in accordance with a timing control signal and a data driver for controlling the brightness of the pixels in accordance with image data.

[0004] In addition to the pixels, the driving circuit may also be provided in the display panel (for example, the driving circuit may be provided in the display panel together with the pixels), or the driving circuit may be provided outside the display panel (for example, provided outside the display panel). Summary of the Invention

[0005] One or more disclosed example embodiments relate to a display device including a gate driver and a method of manufacturing the display device.

[0006] According to a disclosed example embodiment, a display device includes: a plurality of pixels connected to gate lines and data lines; a gate driver for supplying gate signals to the gate lines; and a data driver for supplying data signals to the data lines. The gate driver includes: a first transistor including a first active layer located at a first layer; and a second transistor including a second active layer located at a second layer above the first layer.

[0007] In example embodiments, the gate lines may include scan lines and light emission control lines; and the gate driver may include a scan driver for supplying scan signals to the scan lines and a light emission control driver for supplying light emission control signals to the light emission control lines.

[0008] In example embodiments, the scan driver may include a scan stage including a second transistor; and the light emission control driver may include a light emission control stage including a first transistor.

[0009] In example embodiments, the scan driver may include a scan stage including a first transistor; and the light emission control driver may include a light emission control stage including a second transistor.

[0010] In example embodiments, the gate lines may include scan lines; the gate driver may include scan stages for sequentially supplying scan signals to the scan lines; each of the scan stages may include: an input circuit including the second transistor; and an output circuit including the first transistor.

[0011] In example embodiments, the gate lines may include light emitting control lines; the gate driver may include light emitting control stages for sequentially supplying light emitting control signals to the light emitting control lines; each of the light emitting control stages may include: an input circuit including a second transistor; and an output circuit including a first transistor.

[0012] In example embodiments, the first active layer and the second active layer may overlap each other.

[0013] In example embodiments, the first transistor and the second transistor may have different characteristics from each other.

[0014] In example embodiments, the first transistor and the second transistor may have different threshold voltages from each other.

[0015] In example embodiments, each of the first transistor and the second transistor may include a P-type transistor; and a threshold voltage of the first transistor may be greater than a threshold voltage of the second transistor.

[0016] In example embodiments, the first active layer and the second active layer may have different characteristics from each other.

[0017] In example embodiments, the first active layer may have crystallinity less than that of the second active layer.

[0018] In example embodiments, the display device may further include a display panel including a display area and a non-display area, the pixels may be provided in the display area, and the gate driver may be provided in the non-display area.

[0019] In example embodiments, each of the pixels may include a pixel transistor including a third active layer; the third active layer may have crystallinity less than that of at least one of the first and second active layers.

[0020] According to a disclosed example embodiment, a method for manufacturing a display device including a gate driver is provided. The gate driver includes a first transistor and a second transistor. The method includes: forming an active layer of the first transistor on a base layer; and forming an active layer of the second transistor on the active layer of the first transistor. The active layer of the first transistor and the active layer of the second transistor are crystallized under different conditions.

[0021] In example embodiments, when crystallizing the active layer of the first transistor, the active layer of the first transistor may be irradiated with a laser at a first pitch; and when crystallizing the active layer of the second transistor, the active layer of the second transistor may be irradiated with a laser at a second pitch.

[0022] In example embodiments, the first interval may be greater than the second interval.

[0023] In example embodiments, the active layer of the first transistor may be crystallized before the active layer of the second transistor is crystallized.

[0024] In example embodiments, the method may further include forming a pixel transistor in a display area of the display device, and an active layer of the pixel transistor may be crystallized under conditions different from crystallization conditions of at least one of the active layers of the first transistor and the second transistor.

[0025] In an example embodiment, when crystallizing the at least one active layer among the active layer of the first transistor and the active layer of the second transistor, a laser may be used to irradiate the at least one active layer among the active layer of the first transistor and the active layer of the second transistor at a first spacing; and when crystallizing the active layer of the pixel transistor, a laser may be used to irradiate the active layer of the pixel transistor at a second spacing greater than the first spacing.

[0026] According to one or more disclosed embodiments, a high-density stacked gate driver can be formed by dividing and arranging the first and second transistors constituting (e.g., included in) the gate driver into different layers. Thus, the non-display area of the display panel including the gate driver can be reduced (e.g., effectively reduced).

[0027] Furthermore, according to one or more disclosed embodiments, the crystallization conditions of transistors provided at (e.g., within or on) a display panel can be controlled for each layer or region, taking into account the characteristics used (or desired) for each transistor. Consequently, the manufacturing efficiency of the display device can be increased while improving or ensuring the operational characteristics of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art from the following detailed description of example embodiments with reference to the accompanying drawings.

[0029] Figures 1A to 1D Various examples of display devices according to disclosed embodiments are shown.

[0030] Figures 2A to 2B Various examples of display panels according to disclosed embodiments are shown.

[0031] Figures 3A to 3C Various examples of pixels according to the disclosed embodiments are shown.

[0032] Figure 4 A method for driving a pixel according to a disclosed embodiment is shown.

[0033] Figure 5 A scan driver according to a disclosed embodiment is shown.

[0034] Figure 6 A scanning stage according to a disclosed embodiment is shown.

[0035] Figure 7 A driving method of a scanning stage according to a disclosed embodiment is shown.

[0036] Figure 8 A light emission control driver according to a disclosed embodiment is shown.

[0037] Figure 9 A lighting control stage according to a disclosed embodiment is shown.

[0038] Figure 10 A driving method of the light emitting control stage according to the disclosed embodiment is shown.

[0039] Figures 11A to 11C Various examples of gate drivers according to disclosed embodiments are shown.

[0040] 12A to 12D A cross-sectional view of a gate driver according to a disclosed embodiment is shown.

[0041] Figure 13 A cross-sectional view of a gate driver according to a disclosed embodiment is shown.

[0042] Figure 14 A method of manufacturing a display device according to a disclosed embodiment is shown.

[0043] Figure 15 A method of manufacturing a display device according to a disclosed embodiment is shown. DETAILED DESCRIPTION

[0044] Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals always represent like elements. However, the present disclosure may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, like reference numerals represent like elements throughout the drawings and written description, and therefore descriptions thereof may not be repeated.

[0045] In the accompanying drawings, the relative sizes of elements, layers, and regions may be exaggerated and / or simplified for clarity. For ease of explanation, spatially relative terms such as "below," "beneath," "below," "beneath," "above," "above," and the like may be used herein to describe the relationship of one element or feature to another element or feature(s) as shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below," "beneath," or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0046] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to separate one element, component, region, layer, or part from another element, component, region, layer, or part of a region. Thus, a first element, component, region, layer, or part described below may be named a second element, component, region, layer, or part without departing from the spirit and scope of the present disclosure.

[0047] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0048] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "a (kind / person)" are intended to also include the plural forms. It will also be understood that the terms "comprises," "comprising," "having," "having" and their variations, when used in this specification, indicate the presence of the stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. When a statement such as "at least one of..." follows a column of elements, it modifies the entire column of elements without modifying the individual elements in the column.

[0049] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent variation in measured or calculated values that one of ordinary skill in the art would recognize. Furthermore, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the term "using" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively. Furthermore, the term "exemplary" is intended to indicate an example or illustration.

[0050] The description of features or aspects within each exemplary embodiment should generally be considered as available for other similar features or aspects in other exemplary embodiments. For example, each of the embodiments disclosed herein can be implemented separately or in any suitable combination with at least one of the other embodiments.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0052] Figures 1A to 1D Various examples of display devices according to the disclosed embodiments are shown. For example, Figures 1A to 1D Embodiments different from each other are shown regarding the gate lines GL and the gate driver GD for driving the gate lines GL.

[0053] Reference Figure 1A , a display device according to a disclosed embodiment includes pixels PXL disposed at (eg, in or on) a display area DA and a driving circuit DRC for driving the pixels PXL.

[0054] The display area DA includes gate lines GL, data lines DL, and pixels PXL connected to the gate lines GL and the data lines DL. As used in this disclosure, the term "connection" may refer to electrical connection and / or physical connection.

[0055] Each of the gate lines GL extends in a first direction (e.g., horizontally or in a row direction) at (e.g., within or on) the display area DA, and the gate lines GL are sequentially arranged along a second direction (e.g., vertically or in a column direction) that intersects the first direction. The gate lines GL may be connected (e.g., commonly connected) to the pixels PXL located at (e.g., within or on) each horizontal line (which may also be referred to as a "pixel row"). Depending on the embodiment, the gate lines GL may include at least one scan line S and may further include at least one (or at least one type of) other control line in addition to the scan line S.

[0056] Each of the data lines DL extends in a second direction (e.g., a vertical direction or a column direction) at the display area DA (e.g., in or on the display area DA) to intersect the gate line GL, and the data lines DL are sequentially arranged along a suitable direction (e.g., a first direction) intersecting the second direction. The data lines DL may be connected (e.g., commonly connected) to the pixels PXL located at (e.g., in or on) each vertical line (which may also be referred to as a "pixel column").

[0057] Pixels PXL are connected to gate lines GL and data lines DL to receive corresponding gate and data signals from them. For example, a pixel PXL located at the i-th horizontal line (i is a natural number greater than 0) and the j-th vertical line (j is a natural number greater than 0) may be connected to the i-th scan line Si and the j-th data line DLj to receive scan and data signals for each frame from them. In embodiments, in addition to scan lines S and data lines DL, pixels PXL may be connected to other types of signal lines (e.g., to each of an emission control line, an initialization control line, and / or a sensing control line) depending on the structure and / or driving method of the pixels PXL. The operation of the pixels PXL may be controlled by corresponding control signals supplied from the signal lines.

[0058] In addition, the pixel PXL may also receive operating power from a power source. For example, the pixel PXL may be driven by receiving a first pixel power and a second pixel power having different potentials (e.g., different power levels or voltage levels) from the power source. Furthermore, in addition to the first pixel power and the second pixel power, the pixel PXL may also selectively receive at least one other power (e.g., initialization power and / or reference power) depending on the structure and / or driving method of the pixel PXL.

[0059] Pixels PXL are operated according to a driving timing sequence by gate signals supplied from corresponding gate lines GL and emit light having a desired brightness in accordance with data signals supplied from corresponding data lines DL. For example, a pixel PXL located at the i-th horizontal line and the j-th vertical line (e.g., located in or on the i-th horizontal line and the j-th vertical line) receives a data signal from the j-th data line DLj when a scan signal is supplied from the i-th scan line Si. During the light-emission period of the corresponding frame, the pixel emits light having a desired brightness corresponding to the data signal. Consequently, an image corresponding to the data signal of each frame can be displayed in the display area DA (e.g., in or on the display area DA).

[0060] The drive circuit DRC includes a gate driver GD for driving the gate lines GL, a data driver DD for driving the data lines DL, and a timing controller TCON for controlling the gate driver GD and the data driver DD. In embodiments, the drive circuit DRC may be disposed on (e.g., within) the display panel in addition to the pixels PXL (e.g., the drive circuit DRC may be disposed on the display panel together with the pixels PXL), or the drive circuit DRC may be located outside the display panel (e.g., external to the display panel) and connected to the pixels PXL via a pad (or "pad") portion and / or a circuit board.

[0061] The gate driver GD receives a gate drive control signal GCS from the timing controller TCON and supplies a corresponding gate signal to the gate line GL in response to the gate drive control signal GCS. According to an embodiment, the gate driver GD may include at least a scan driver. Furthermore, when the gate line GL includes at least one other control line in addition to the scan line S, the gate driver GD may also optionally include at least one control line driver (e.g., a light emission control driver) for driving the control line.

[0062] The scan driver supplies a corresponding scan signal to the scan line S in response to the scan drive control signal included in the gate drive control signal GCS. For example, the scan driver may supply (e.g., sequentially supply) the scan signal to the scan line S during each frame period in response to the scan drive control signal. Therefore, the scan driver may include a plurality of scan stages. When the scan signal is supplied to the scan line S, the pixel PXL connected to the scan line S supplied with the scan signal is selected, and the selected pixel PXL receives a data signal from the data line DL.

[0063] According to an embodiment, a scan signal may be used to select pixels PXL in units of horizontal lines (e.g., one horizontal row). For example, the scan signal may have a gate-on voltage (e.g., a low voltage) at which the switching transistor of each pixel PXL connected to the corresponding data line DL may be turned on, and the scan signal may be supplied to the pixels PXL of the horizontal line corresponding to each horizontal period. The pixels PXL receiving the scan signal may be connected to the data line DL to receive the corresponding data signal during the period in which the scan signal is supplied.

[0064] The data driver DD receives a data drive control signal DCS and image data RGB from the timing controller TCON and supplies data signals to the data lines DL corresponding to the data drive control signal DCS and the image data RGB. The data signals supplied to the data lines DL are supplied to the pixels PXL selected by the corresponding scan signals. Pixels PXL receiving the data signals emit light having a desired brightness corresponding to the data signals during the light-emission period of each frame. On the other hand, when a data signal corresponding to a black grayscale (e.g., a black grayscale level, a black grayscale scale, or a black grayscale value) is supplied to a pixel PXL, the pixel PXL may remain, or substantially remain, in a non-luminous state even during the light-emission period of the corresponding frame.

[0065] The timing controller TCON receives various timing signals (e.g., vertical / horizontal synchronization signals, main clock signal, etc.) from the outside (e.g., from a host processor) and generates a gate drive control signal GCS and a data drive control signal DCS. The gate drive control signal GCS and the data drive control signal DCS are supplied to the gate driver GD and the data driver DD, respectively.

[0066] The gate drive control signal GCS may include at least a scan drive control signal. The scan drive control signal includes a first start pulse and at least one scan clock signal. The first start pulse controls the output timing of a first scan signal (e.g., a scan signal supplied to a first scan line), and the scan clock signal is used to shift (e.g., sequentially shift) the first start pulse.

[0067] The data driving control signal DCS includes a source sampling pulse, a source sampling clock, and a source output enable signal. The data driving control signal DCS controls a sampling operation of data (eg, image data).

[0068] In addition, the timing controller TCON receives input image data from the outside and rearranges the input image data to generate image data RGB. The timing controller TCON supplies the image data RGB to the data driver DD. The image data RGB supplied to the data driver DD is used to generate a data signal.

[0069] Reference Figure 1B In addition to the scan line S, the gate line GL according to the disclosed embodiment may further include a light emission control line E (e.g., the gate line GL according to the disclosed embodiment may include the light emission control line E and the scan line S). For example, in addition to the i-th scan line Si and the j-th data line DLj, a pixel PXL located at the i-th horizontal line and the j-th vertical line (e.g., in or on the i-th horizontal line and the j-th vertical line) may also be connected to the i-th light emission control line Ei. The light emission period of the pixel PXL may be controlled by the light emission control signal supplied from the i-th light emission control line Ei. For example, when a light emission control signal having a gate-off voltage (e.g., a high voltage) is supplied from the i-th light emission control line Ei, the pixel PXL may remain in or substantially remain in a non-light emitting state and may emit light having a desired brightness corresponding to the data signal during other periods (e.g., other periods when the light emission control signal is not supplied or when the light emission control signal has a gate-on voltage).

[0070] In this case, the gate driver GD may further include a light emission control driver for driving the light emission control lines E in addition to the scan driver for driving the scan lines S. In addition, the gate drive control signal GCS may further include a light emission drive control signal in addition to the scan drive control signal.

[0071] The light emission control driver supplies a corresponding light emission control signal to the light emission control line E in correspondence with the light emission drive control signal. For example, the light emission control driver may supply (e.g., sequentially supply) a light emission control signal having a gate-off voltage to the light emission control line E during each frame period in correspondence with the light emission drive control signal. Therefore, the light emission control driver may include a plurality of light emission control stages.

[0072] The light-emission control signal can be used to control the light-emission period (e.g., the light-emission timing and / or the light-emission duration) of the pixel PXL. For example, the light-emission control signal can have a gate-off voltage, at which at least one transistor located in the current path of each pixel PXL can be turned off. In this case, the pixel PXL receiving the light-emission control signal can be set to a non-light-emitting state during the period when the light-emission control signal is supplied, and can be set to a light-emitting state during other periods (e.g., during other periods when the light-emission control signal is not supplied or when the light-emission control signal has a gate-on voltage).

[0073] The light-emitting drive control signal for controlling the light-emitting control driver includes a second start pulse and at least one light-emitting clock signal. The second start pulse controls the output timing of the first light-emitting control signal (e.g., the light-emitting control signal supplied to the first light-emitting control line), and the light-emitting clock signal is used to shift (e.g., sequentially shift) the second start pulse.

[0074] Reference Figure 1C The display device according to the disclosed embodiments may include multiple gate drivers GD. For example, the display device may include two gate drivers GD disposed on sides (e.g., opposite sides) of the display area DA so as to face each other. Each gate driver GD may include a scan driver and / or a light emission control driver.

[0075] In an embodiment, the plurality of gate drivers GD may have the same or substantially the same configuration and may be connected to the ends (e.g., both ends or opposing ends) of each of the gate lines GL. In this case, each gate line GL can concurrently (e.g., simultaneously) receive gate signals from both ends of the gate line GL. For example, each scan line S can concurrently (e.g., simultaneously) receive scan signals from two scan stages connected to the respective ends of the scan line S, and each emission control line E can concurrently (e.g., simultaneously) receive emission control signals from two emission control stages connected to the respective ends of the emission control line E. In this case, even if the display device is enlarged (e.g., a large-screen display device), gate signal delay can be reduced or minimized.

[0076] In another embodiment, the gate driver GD may be connected to one end of each of the different gate lines GL. For example, the gate driver GD disposed on one side of the display area DA may be connected to some scan lines S (e.g., odd-numbered scan lines S) and / or some emission control lines E (e.g., odd-numbered emission control lines E) to drive some of the scan lines S and / or some of the emission control lines E. Furthermore, the gate driver GD disposed on the other side (e.g., the opposite side) of the display area DA may be connected to other scan lines S (e.g., even-numbered scan lines S) and / or other emission control lines E (e.g., even-numbered emission control lines E) to drive the other scan lines S and / or other emission control lines E.

[0077] Reference Figure 1D The display device according to the disclosed embodiment may include a first gate driver GD1 and a second gate driver GD2. The first gate driver GD1 and the second gate driver GD2 are disposed at different sides (e.g., opposite sides) of the display area DA (e.g., on different sides) and have different circuit configurations. The first gate driver GD1 and the second gate driver GD2 may be connected to a first gate line GL1 (e.g., a scan line S) and a second gate line GL2 (e.g., a light emission control line E), respectively.

[0078] In an embodiment, a first gate driver GD1 may be provided at (e.g., on) one side of the display area DA and may drive the first gate line GL1 in response to a first gate drive control signal GCS1 supplied from a timing controller TCON. The first gate line GL1 may include (or may be) a scan line S, and the first gate drive control signal GCS1 may include (or may be) a scan drive control signal. In this case, the first gate driver GD1 may include (e.g., or may be configured with) a scan driver including one or more scan stages connected to each scan line S. A second gate driver GD2 may be provided at (e.g., on) the other side of the display area DA (e.g., opposite the one side of the display area DA) and may drive the second gate line GL2 in response to a second gate drive control signal GCS2 supplied from the timing controller TCON. The second gate line GL2 may include (or may be) an emission control line E, and the second gate drive control signal GCS2 may include (or may be) an emission control signal E. In this case, the second gate driver GD2 may include (eg, or may be configured with) a light emitting control driver including one or more light emitting control stages connected to each light emitting control line E.

[0079] According to one or more of the above embodiments, the display device can have various suitable structures, and the method of driving the display device can be variously modified (for example, according to the structure of the display device). However, the disclosure is not limited to the above structures and / or driving methods, and in addition to any structure and / or driving method in the above embodiments, the structure and / or driving method of the display device can be variously modified to have any suitable structure and / or any suitable driving method as will be understood by those skilled in the art.

[0080] Figure 2A and Figure 2B Various examples of the display panel PNL according to the disclosed embodiment are shown. For example, Figure 2A and Figure 2B Different embodiments of the display panel PNL are shown. The display panel PNL may include Figures 1A to 1D Specifically, Figure 2A and Figure 2B Various embodiments of a display panel PNL including a gate driver GD are shown.

[0081] Reference Figure 2A and Figure 2B According to the disclosed embodiment, the display panel PNL includes: a base layer BSL including a display area DA and a non-display area NDA; a pixel PXL, which is arranged at the display area DA of the base layer BSL (for example, in the display area DA or on the display area DA); a gate driver GD, which is arranged at the non-display area NDA of the base layer BSL (for example, in the non-display area NDA or on the non-display area NDA) and is located around the pixel PXL (for example, adjacent to the pixel PXL). In an embodiment, the display area DA can be arranged at the center area (or central area) of the display panel PNL (for example, in the center area or on the center area), and the non-display area NDA can be arranged outside the display panel PNL to surround the display area DA (for example, around the periphery of the display area DA). However, according to an embodiment, the position, size, etc. of the display area DA can be changed from Figure 2A and Figure 2B The positions, sizes, etc. shown in the drawings may be modified in various ways.

[0082] The base layer BSL may constitute the base member of the display panel PNL. The base layer BSL may include (or may be) a rigid substrate or rigid film, or a flexible substrate or flexible film, but its material and / or physical properties are not particularly limited. For example, the base layer BSL may include (or may be) a rigid substrate formed of glass or tempered glass, a flexible substrate (or flexible film) including plastic or metal materials, or an insulating film including at least one layer, but its material and / or physical properties are not limited thereto.

[0083] In addition, the base layer BSL may be transparent or substantially transparent, but the disclosure is not limited thereto. For example, the base layer BSL may be a transparent base member, a translucent base member, an opaque base member, or a reflective base member.

[0084] A plurality of pixels PXL may be disposed in the display area DA (e.g., in or on the display area DA). For example, the plurality of pixels PXL may be arranged (e.g., regularly) in the display area DA (e.g., in or on the display area DA) according to a stripe array structure or a pentile array structure. However, the arrangement structure of the pixels PXL is not limited thereto, and the pixels PXL may be arranged in the display area DA (e.g., in or on the display area DA) according to various suitable structures (e.g., arrangement structures) and / or methods. The display area DA constitutes a screen (e.g., a display screen) on or on which an image is displayed.

[0085] Various lines (e.g., signal lines, power lines, etc.) and / or internal circuits connected to the pixels PXL in the display area DA may be provided in the non-display area NDA (e.g., in or on the non-display area NDA). For example, at least one gate driver GD and various power lines and / or signal lines may be provided in the non-display area NDA (e.g., in or on the non-display area NDA).

[0086] In an embodiment, the display panel PNL may be as follows Figure 2A As shown in FIG, the display panel PNL includes a single gate driver GD disposed at one side (eg, left or right) of the display area DA (eg, on one side of the display area DA). In another embodiment, the display panel PNL may be configured as follows: Figure 2B As shown in FIG, a plurality of gate drivers GD are provided at both sides (eg, left and right sides) of the display area DA (eg, on both sides of the display area DA). Figure 2B As shown in , the plurality of gate drivers GD may be disposed at opposite sides of the display area DA. According to an embodiment, the plurality of gate drivers GD may be disposed to face each other with the display area DA interposed therebetween, and may have the same or substantially the same circuit configuration as each other or may have different circuit configurations from each other.

[0087] Figures 3A to 3C Various examples of pixels PXL according to the disclosed embodiments are shown. For example, Figures 3A to 3C Different embodiments of the pixel PXL are shown. The pixel PXL may be arranged in Figures 1A to 2B Any one of the display areas DA shown in FIG. Figures 1A to 2B In any one of the display areas DA shown in Figures 1A to 2B on any one of the display areas DA shown in FIG).

[0088] According to an embodiment, Figures 3A to 3C Different embodiments of pixels PXL that may be included in a light-emitting display device are disclosed. However, the disclosure is not limited to light-emitting display devices, and the pixel PXL may be a pixel included in any suitable display device having various suitable structures and / or various suitable driving methods, as known to those skilled in the art.

[0089] Figures 3A to 3C An arbitrary pixel (e.g., example pixel or representative pixel) PXL disposed at (e.g., in or on) the i-th horizontal line and the j-th vertical line of the display area DA is shown, and other pixels PXL disposed at (e.g., in or on) the display area DA may have the same Figures 3A to 3C The structures of the pixels PXL shown in any one of the drawings are the same or substantially the same (e.g., or similar) in structure. For example, in an embodiment, the pixels PXL provided at the display area DA (e.g., in the display area DA or on the display area DA) may have the same or substantially the same structure as each other, or at least some of the pixels PXL provided at the display area DA (e.g., in the display area DA or on the display area DA) may have different structures from each other. Figures 3A to 3C , the pixel PXL can be connected to the i-th scan line Si and the j-th data line DLj, and according to various embodiments, the pixel PXL can also be selectively connected to at least one of the i-th emission control line Ei, the i-th initialization control line GIi, the i-th sensing control line SCLi, and / or the j-th sensing line SENj. For convenience of description, the "i-th scan line Si", "j-th data line DLj", "i-th emission control line Ei", "i-th initialization control line GIi", "i-th sensing control line SCLi", and "j-th sensing line SENj" may be referred to as "scan line Si", "data line DLj", "emission control line Ei", "initialization control line GIi", "sensing control line SCLi", and "sensing line SENj", respectively.

[0090] Reference Figure 3A According to the disclosed embodiment, the pixel PXL includes a light-emitting element EL and a pixel circuit PXC for driving the light-emitting element EL. According to the embodiment, the light-emitting element EL may be connected between the pixel circuit PXC and a second pixel power source (e.g., a second pixel power source) ELVSS, but the location of the light-emitting element EL is not limited thereto. For example, in another embodiment, the light-emitting element EL may be connected between a first pixel power source (e.g., a first pixel power source) ELVDD and the pixel circuit PXC.

[0091] The light-emitting element EL is connected between a first pixel power ELVDD and a second pixel power ELVSS in a forward direction (e.g., in a forward biased direction). For example, the anode electrode of the light-emitting element EL may be connected to the first pixel power ELVDD via the pixel circuit PXC, and the cathode electrode of the light-emitting element EL may be connected to the second pixel power ELVSS. The first pixel power ELVDD and the second pixel power ELVSS may have a potential difference (e.g., a difference in power level or voltage level) that enables the light-emitting element EL to emit light (e.g., allows the light-emitting element EL to emit light). For example, the first pixel power ELVDD may be a high-potential pixel power, and the second pixel power ELVSS may be a low-potential pixel power having a potential lower than the first pixel power ELVDD by at least the threshold voltage of the light-emitting element EL.

[0092] The pixel circuit PXC is connected to the scan line Si, the light emission control line Ei, and the data line DLj. The pixel circuit PXC includes a first pixel transistor TP1, a second pixel transistor TP2, a third pixel transistor TP3, and a storage capacitor Cst.

[0093] For convenience, in the description Figure 3A In the embodiment of the present invention, the first pixel transistor TP1, the second pixel transistor TP2, and the third pixel transistor TP3 may be referred to as "the first transistor TP1, the second transistor TP2, and the third transistor TP3," respectively. In addition, when referring to a specific (or particular) transistor from among the first transistor TP1, the second transistor TP2, and the third transistor TP3, the specific transistor may be appropriately referred to as "the first transistor TP1," "the second transistor TP2," or "the third transistor TP3." On the other hand, when arbitrarily referring to at least one of the first transistor TP1, the second transistor TP2, and the third transistor TP3, or when referring to at least two (or each) of the first transistor TP1, the second transistor TP2, and the third transistor TP3 collectively, the at least one of the first transistor TP1, the second transistor TP2, and the third transistor TP3, or the aggregate of the first transistor TP1, the second transistor TP2, and the third transistor TP3 may be appropriately referred to as "the pixel transistor TP" or "the plurality of pixel transistors TP."

[0094] The first transistor TP1 is connected between the first pixel power source ELVDD and the light-emitting element EL. For example, the first electrode (e.g., source electrode) of the first transistor TP1 can be connected to the first pixel power source ELVDD, and the second electrode (e.g., drain electrode) of the first transistor TP1 can be connected to the anode electrode of the light-emitting element EL via the third transistor TP3. Furthermore, the gate electrode of the first transistor TP1 is connected to the first node N1. The first transistor TP1 controls the drive current flowing from the first pixel power source ELVDD to the second pixel power source ELVSS via the third transistor TP3 and the light-emitting element EL in response to the voltage at the first node N1. In other words, the first transistor TP1 can be the drive transistor of the pixel PXL.

[0095] The second transistor TP2 is connected between the data line DLj and the first node N1. For example, a first electrode (e.g., a source electrode) of the second transistor TP2 may be connected to the data line DLj, and a second electrode (e.g., a drain electrode) of the second transistor TP2 may be connected to the first node N1. Furthermore, a gate electrode of the second transistor TP2 is connected to the scan line Si. The second transistor TP2 is turned on when a scan signal having a gate-on voltage (e.g., a low voltage) is supplied to the scan line Si, thereby transmitting a data signal supplied from the data line DLj to the first node N1.

[0096] The third transistor TP3 is connected between the first transistor TP1 and the light-emitting element EL. For example, a first electrode (e.g., source electrode) of the third transistor TP3 may be connected to the second electrode of the first transistor TP1, and a second electrode (e.g., drain electrode) of the third transistor TP3 may be connected to the anode electrode of the light-emitting element EL. The gate electrode of the third transistor TP3 is connected to the light-emission control line Ei. The third transistor TP3 is turned off when a light-emission control signal having a gate-off voltage (e.g., a high voltage) is supplied to the light-emission control line Ei, and is turned on in other situations (e.g., when the supply of the light-emission control signal is stopped and / or the voltage of the light-emission control line Ei is maintained at or substantially maintained at the gate-on voltage).

[0097] When the third transistor TP3 is turned off, the connection between the first transistor TP1 and the light-emitting element EL is disconnected (e.g., cut off). Therefore, the pixel PXL does not emit light because the current path in the pixel PXL is blocked. On the other hand, when the third transistor TP3 is turned on, the first transistor TP1 and the light-emitting element EL are connected to each other. Therefore, a current path through which a driving current can flow is formed in the pixel PXL, and the pixel PXL is set to a state in which the pixel PXL can emit light (e.g., a light-emitting state).

[0098] The storage capacitor Cst is connected between the first pixel power ELVDD and the first node N1 and charges (eg, stores) a voltage corresponding to the voltage of the first node N1 (eg, a voltage corresponding to the data signal).

[0099] Although the pixel transistor TP is Figure 3A 1 is shown as a P-type transistor, but the disclosure is not limited thereto. For example, in another embodiment, at least one pixel transistor TP may be an N-type transistor. In this case, the gate-on voltage for turning on the at least one pixel transistor TP (e.g., an N-type transistor) may be a high voltage. Furthermore, when the first transistor TP1 is a P-type transistor, the pixel PXL may emit light at a higher brightness when a data signal having a lower voltage is supplied, and when the first transistor TP1 is an N-type transistor, the pixel PXL may emit light at a higher brightness when a data signal having a higher voltage is supplied.

[0100] However, disclosure is not limited to Figure 3A The structure of the pixel PXL is shown in FIG. 1 , and various modifications may be made to the structure of the pixel PXL according to the embodiment. For example, the structure of the pixel circuit PXC may be as follows: Figure 3B Examples or Figure 3C In addition, the pixel circuit PXC may be configured according to various suitable pixel circuits having various suitable structures and / or various suitable driving methods known to those skilled in the art.

[0101] Reference Figure 3B According to the disclosed embodiment, the pixel circuit PXC is connected to the scan line Si, the data line DLj, the sensing control line SCLi, and the sensing line SENj. The pixel circuit PXC includes a first pixel transistor TP1', a second pixel transistor TP2', a third pixel transistor TP3', and a storage capacitor Cst'. However, the disclosure is not limited thereto. In another embodiment, the sensing line SENj may be omitted, and the characteristics of each pixel PXL may be detected via the data line DLj.

[0102] For convenience, in the description Figure 3BIn the embodiment of the present invention, the first pixel transistor TP1', the second pixel transistor TP2' and the third pixel transistor TP3' may be referred to as "the first transistor TP1', the second transistor TP2' and the third transistor TP3'", respectively. In addition, when referring to a specific (or particular) transistor from among the first transistor TP1', the second transistor TP2' and the third transistor TP3', the specific transistor may be appropriately referred to as "the first transistor TP1'", "the second transistor TP2'" or "the third transistor TP3'". On the other hand, when arbitrarily referring to at least one of the first transistor TP1', the second transistor TP2' and the third transistor TP3', or when referring to at least two (or each) of the first transistor TP1', the second transistor TP2' and the third transistor TP3' collectively, the at least one of the first transistor TP1', the second transistor TP2' and the third transistor TP3' or the aggregate of the first transistor TP1', the second transistor TP2' and the third transistor TP3' may be appropriately referred to as "the pixel transistor TP'" or "the plurality of pixel transistors TP'". In addition, in describing Figure 3B When implementing the embodiment, you may not repeat Figure 3A In the present embodiment, each pixel transistor TP' may be an N-type transistor, but the disclosure is not limited thereto.

[0103] The first transistor TP1' may be a driving transistor for the pixel PXL and is connected between the first pixel power ELVDD and the light-emitting element EL to control the driving current of the pixel PXL in accordance with the voltage of the first node N1. In this case, the gate electrode of the first transistor TP1' may be connected to the first node N1. In an embodiment, when the first transistor TP1' is an N-type transistor, the first electrode of the first transistor TP1' connected to the first pixel power ELVDD may be a drain electrode, and the second electrode of the first transistor TP1' connected to the light-emitting element EL may be a source electrode. In this case, the storage capacitor Cst' may be connected between the first node N1 and the second electrode of the first transistor TP1'.

[0104] The second transistor TP2' is connected between the data line DLj and the first node N1. The second transistor TP2' is turned on when a scan signal having a gate-on voltage (e.g., a high voltage) is supplied from the scan line Si to transmit the data signal supplied from the data line DLj to the first node N1. Therefore, the gate electrode of the second transistor TP2' can be connected to the scan line Si.

[0105] The third transistor TP3' is connected between the second electrode of the first transistor TP1' and the sensing line SENj. On the other hand, when the sensing line SENj is omitted and the characteristics of each pixel PXL are detected through the data line DLj, the third transistor TP3' may be connected between the second electrode of the first transistor TP1' and the data line DLj.

[0106] A gate electrode of the third transistor TP3′ is connected to the sensing control line SCLi. The third transistor TP3′ is turned on by a sensing control signal having a gate-on voltage (e.g., a high voltage) supplied to the sensing control line SCLi during a sensing period (e.g., a predetermined sensing period) to connect the sensing line SENj and the first transistor TP1′ to each other.

[0107] According to embodiments, a sensing period may include (or may be) a period for extracting characteristics (e.g., the threshold voltage of the first transistor TP1′) of each of the pixels PXL disposed in the display area DA (e.g., in or on the display area DA). During the sensing period, the first transistor TP1′ may be turned on by supplying a suitable reference voltage (e.g., a predetermined reference voltage) to the first node N1 via the data line DLj and the second transistor TP2′, which can turn on the first transistor TP1′. Alternatively, the first transistor TP1′ may be turned on by connecting each pixel PXL to a current source, etc. Furthermore, the first transistor TP1′ may be connected to the sensing line SENj by supplying a sensing control signal having a gate-on voltage to the sensing control line SCLi, thereby turning on the third transistor TP3′. A sensing signal is then obtained from each pixel PXL via the sensing line SENj, and characteristics of each pixel PXL, including the threshold voltage of the first transistor TP1′, etc., may be detected using (e.g., utilizing) the sensing signal.

[0108] The characteristics detected from the pixels PXL during each sensing period may be used to convert image data so that characteristic deviations between the pixels PXL disposed at (eg, in or on) the display area DA may be compensated. Figure 3B The display device of the pixel PXL of the embodiment may detect characteristics from each pixel PXL and may improve image quality by applying an external compensation method that changes data (eg, image data) corresponding to the characteristics.

[0109] Reference Figure 3CAccording to the disclosed embodiment, the pixel circuit PXC is connected to the scan line Si, the data line DLj, the emission control line Ei, and the initialization control line GIi. The pixel circuit PXC includes a first pixel transistor TP1, a second pixel transistor TP2", a third pixel transistor TP3", a fourth pixel transistor TP4, a fifth pixel transistor TP5, a sixth pixel transistor TP6, a seventh pixel transistor TP7, and a storage capacitor Cst.

[0110] For convenience, in the description Figure 3C In the embodiment of the present invention, the first pixel transistor TP1, the second pixel transistor TP2", the third pixel transistor TP3", the fourth pixel transistor TP4, the fifth pixel transistor TP5, the sixth pixel transistor TP6 and the seventh pixel transistor TP7 can be respectively referred to as "the first transistor TP1, the second transistor TP2", the third transistor TP3", the fourth transistor TP4, the fifth transistor TP5, the sixth transistor TP6 and the seventh transistor TP7". In addition, when referring to a specific (or particular) transistor among the first transistor TP1, the second transistor TP2", the third transistor TP3", the fourth transistor TP4, the fifth transistor TP5, the sixth transistor TP6 or the seventh transistor TP7, the specific transistor can be appropriately referred to as "the first transistor TP1, the second transistor TP2", the third transistor TP3", the fourth transistor TP4, the fifth transistor TP5, the sixth transistor TP6 or the seventh transistor TP7". On the other hand, when at least one of the first transistor TP1, the second transistor TP2", the third transistor TP3", the fourth transistor TP4, the fifth transistor TP5, the sixth transistor TP6 and the seventh transistor TP7 is arbitrarily referred to, or when at least two (or each) of the first transistor TP1, the second transistor TP2", the third transistor TP3", the fourth transistor TP4, the fifth transistor TP5, the sixth transistor TP6 and the seventh transistor TP7 are collectively referred to, the at least one of the first transistor TP1, the second transistor TP2", the third transistor TP3", the fourth transistor TP4, the fifth transistor TP5, the sixth transistor TP6 and the seventh transistor TP7 or the aggregate of the first transistor TP1, the second transistor TP2", the third transistor TP3", the fourth transistor TP4, the fifth transistor TP5, the sixth transistor TP6 and the seventh transistor TP7 may be appropriately referred to as "pixel transistor TP" or "multiple pixel transistors TP". In addition, in describing Figure 3C In the embodiment, it is not necessary to repeat the above embodiment (for example, Figure 3A According to an embodiment, each pixel transistor TP″ may be a P-type transistor, but the disclosure is not limited thereto.

[0111] A first electrode of the first transistor TP1 can be connected to the first pixel power ELVDD via the fifth transistor TP5, and a second electrode of the first transistor TP1 can be connected to the anode electrode of the light-emitting element EL via the sixth transistor TP6. Furthermore, a gate electrode of the first transistor TP1 is connected to a first node N1. The first transistor TP1 controls a driving current flowing from the first pixel power ELVDD to the second pixel power ELVSS via the light-emitting element EL in response to the voltage of the first node N1.

[0112] A first electrode of the second transistor TP2″ is connected to the data line DLj, and a second electrode of the second transistor TP2″ is connected to the first electrode of the first transistor TP1. A second electrode of the second transistor TP2″ is connected to the first node N1 via the first transistor TP1 and the third transistor TP3″. In addition, a gate electrode of the second transistor TP2″ is connected to the scan line Si. The second transistor TP2″ is turned on when a scan signal having a gate-on voltage is supplied to the scan line Si to connect the data line DLj and the first electrode of the first transistor TP1 to each other. Therefore, when the second transistor TP2" is turned on, the data signal from the data line DLj can be transmitted to the first electrode of the first transistor TP1. In addition, during the period in which the second transistor TP2" is turned on by the scan signal, the first transistor TP1 is turned on in the form of a diode connection through the third transistor TP3". In other words, during the period in which the second transistor TP2" is turned on, the third transistor TP3" can also be turned on to diode-connect the first transistor TP1. Therefore, the data signal from the data line DLj can be transmitted to the first node N1 via the second transistor TP2", the first transistor TP1 and the third transistor TP3". Then, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor TP1.

[0113] The third transistor TP3″ is connected between the first transistor TP1 and the first node N1. In addition, the gate electrode of the third transistor TP3″ is connected to the scan line Si. The third transistor TP3″ is turned on when a scan signal having a gate-on voltage is supplied to the scan line Si to connect the second electrode of the first transistor TP1 and the first node N1 to each other. Therefore, when the third transistor TP3″ is turned on, the first transistor TP1 is connected in a diode form (for example, the first transistor TP1 is diode-connected).

[0114] The fourth transistor TP4 is connected between the first node N1 and initialization power (e.g., initialization power supply) Vint. Furthermore, a gate electrode of the fourth transistor TP4 is connected to an initialization control line GIi. The fourth transistor TP4 is turned on when an initialization control signal having a gate-on voltage is supplied to the initialization control line GIi, thereby connecting the first node N1 to the initialization power Vint.

[0115] In an embodiment, the initialization control line GIi may include (or may be) one of the preceding scan lines. For example, the initialization control line GIi may be the (i-1)th scan line Si-1. In this case, the fourth transistor TP4 turns on when a scan signal having a gate-on voltage is supplied to the (i-1)th scan line Si-1, thereby initializing the voltage of the first node N1 to the voltage of the initialization power Vint. On the other hand, the initialization control line GIi is not limited to any of the preceding scan lines, and the initialization control line GIi may be modified in various ways depending on the embodiment. For example, in another embodiment, another control line driven separately from the scan line S may be formed at the display area DA (e.g., in or on the display area DA) and used as the initialization control line GIi.

[0116] According to an embodiment, the voltage of the initialization power Vint can be set to be less than or equal to the voltage of the data signal. For example, the voltage of the initialization power Vint can be set to be less than or equal to the lowest voltage of the data signal. Therefore, when the voltage of the first node N1 is initialized to the voltage of the initialization power Vint before the data signal of the current frame is transmitted to each pixel PXL, the first transistor TP1 can be diode-connected in the forward direction (e.g., forward biased direction) during the period of supplying the scan signal of the current frame, regardless of the data signal of the previous frame. Therefore, during the period of supplying the scan signal of each frame, the data signal can be stably transmitted to the first node N1 of each of the pixels PXL selected by the scan signal.

[0117] The fifth transistor TP5 is connected between the first pixel power source ELVDD and the first transistor TP1. Furthermore, a gate electrode of the fifth transistor TP5 is connected to the emission control line Ei. The fifth transistor TP5 is turned off when a light emission control signal having a gate-off voltage is supplied to the light emission control line Ei, and is turned on otherwise (e.g., when no light emission control signal is supplied or when a light emission control signal having a gate-on voltage is supplied).

[0118] The sixth transistor TP6 is connected between the first transistor TP1 and the light-emitting element EL. Furthermore, a gate electrode of the sixth transistor TP6 is connected to the light-emission control line Ei. The sixth transistor TP6 is turned off when a light-emission control signal having a gate-off voltage is supplied to the light-emission control line Ei, and is turned on otherwise (for example, when no light-emission control signal is supplied or when a light-emission control signal having a gate-on voltage is supplied).

[0119] In other words, the fifth transistor TP5 and the sixth transistor TP6 can be turned on or off concurrently (e.g., simultaneously) with each other by the light emission control signal. When the fifth transistor TP5 and the sixth transistor TP6 are turned on, a current path through which a driving current can flow is formed in the pixel PXL. On the other hand, when the fifth transistor TP5 and the sixth transistor TP6 are turned off, the current path is blocked (e.g., disconnected), and the pixel PXL does not emit light.

[0120] The seventh transistor TP7 is connected between the initialization power Vint and the anode electrode of the light-emitting element EL. Furthermore, the gate electrode of the seventh transistor TP7 is connected to the scan line Si. The seventh transistor TP7 is turned on when a scan signal having a gate-on voltage is supplied to the scan line Si, thereby initializing the anode voltage of the light-emitting element EL to the voltage of the initialization power Vint. Consequently, each pixel PXL can exhibit uniform or substantially uniform luminance characteristics during the light-emitting period of each frame, regardless of the luminance of the previous frame.

[0121] Although Figure 3C Although an embodiment is shown in which the gate electrode of the seventh transistor TP7 is connected to the scan line Si, the disclosure is not limited thereto. For example, in another embodiment, the gate electrode of the seventh transistor TP7 may be connected to any suitable subsequent scan line (e.g., the (i+1)th scan line Si+1), or the gate electrode of the seventh transistor TP7 may be connected to another control line formed separately from the scan line S to be driven.

[0122] The storage capacitor Cst is connected between the first pixel power ELVDD and the first node N1 and charges a voltage corresponding to the data signal and the threshold voltage of the first transistor TP1.

[0123] As described above, according to one or more embodiments, the pixel PXL may include a pixel circuit PXC having various suitable structures and / or various suitable driving methods. However, the type (or structure), and / or driving method of the pixel PXL are not limited to the above-described embodiments. For example, in another disclosed embodiment, each pixel PXL may be configured for use in a passive light-emitting display device, etc. (e.g., or configured within a passive light-emitting display device, etc.). In this case, the pixel circuit PXC may be omitted, and the light-emitting element EL may be connected (e.g., directly connected) to the scan line Si, the data line DLj, the first pixel power line, the second pixel power line, other wiring, etc. Furthermore, in another disclosed embodiment, the display device may include a separate light source unit (e.g., a separate light source or a separate light source device) such as a backlight unit (e.g., a backlight source or a backlight device). In this case, the pixel (e.g., each pixel) PXL may not include the light-emitting element EL, etc.

[0124] Figure 4 The driving method of the pixel PXL according to the disclosed embodiment is shown. For example, Figure 4 FIG. 2 shows an exemplary waveform of a driving signal that may be supplied to a signal line connected to a pixel PXL to drive the pixel PXL. Figure 3C Pixel PXL.

[0125] Reference Figure 3C and Figure 4 , one frame period 1F may include a non-light emitting period NEP and a light emitting period EP. The non-light emitting period NEP of each frame period 1F may be a period during which a light emitting control signal having a gate-off voltage is supplied to the light emitting control line Ei of the pixel PXL, and a scan signal having a gate-on voltage may be sequentially supplied to the initialization control line GIi (for example, the i-1th scan line Si-1) and the scan line Si connected to the pixel PXL.

[0126] When a light emission control signal having a gate-off voltage is supplied to the light emission control line Ei, the fifth transistor TP5 and the sixth transistor TP6 are turned off. Therefore, a current path through which a driving current can flow in the pixel PXL is blocked (or disconnected), and the pixel PXL can be set to a non-light emitting state.

[0127] When an initialization control signal (eg, a previous scan signal) having a gate-on voltage is supplied to the initialization control line GIi, the fourth transistor TP4 is turned on, and thus the first node N1 is initialized to a voltage of the initialization power Vint.

[0128] After the initialization control signal, when a scan signal having a gate-on voltage is supplied to the scan line Si, each of the second transistor TP2", the third transistor TP3" and the seventh transistor TP7 is turned on. In addition, the first transistor TP1 is turned on in a diode-connected form through the third transistor TP3".

[0129] When the first transistor TP1, the second transistor TP2″, and the third transistor TP3″ are turned on, the data signal from the data line DLj can be sequentially transmitted to the first node N1 via the second transistor TP2″, the first transistor TP1, and the third transistor TP3″. At this time, a voltage corresponding to the data signal and the threshold voltage of the first transistor TP1 (for example, a voltage difference between the voltage of the data signal and the threshold voltage of the first transistor TP1) is transmitted to the first node N1, and the voltage transmitted to the first node N1 is stored in the storage capacitor Cst.

[0130] When the seventh transistor TP7 is turned on, the voltage of the initialization power Vint is transmitted to the anode electrode of the light emitting element EL. Therefore, the charge charged in the parasitic capacitor of the light emitting element EL during the previous frame period is initialized.

[0131] When the voltage of the light-emission control line Ei changes to the gate-on voltage, the non-light-emission period NEP ends, and the light-emission period EP begins immediately following (following) the non-light-emission period NEP. During the light-emission period EP, the voltage of the light-emission control line Ei remains or substantially remains at the gate-on voltage. Consequently, each of the fifth transistor TP5 and the sixth transistor TP6 turns on, forming a current path through which the drive current can flow in the pixel PXL.

[0132] During the emission period EP, the first transistor TP1 generates a driving current corresponding to the voltage of the first node N1. The driving current flows from the first pixel power ELVDD to the second pixel power ELVSS via the light emitting element EL. Therefore, the light emitting element EL emits light with a desired brightness corresponding to the driving current.

[0133] On the other hand, during the non-light-emission period NEP, during a period in which a scan signal having a gate-on voltage is supplied to the scan line Si, when a data signal corresponding to a black grayscale (e.g., a black gray level or a black grayscale) is supplied to the pixel PXL, the first transistor TP1 does not generate a driving current during the corresponding frame period 1F. In this case, even during the light-emission period EP of the corresponding frame, the pixel PXL may maintain or substantially maintain a non-light-emission state to express a black grayscale (e.g., a grayscale value, grayscale level, or grayscale corresponding to a black image).

[0134] Figure 5FIG. 4 shows a scanning driver SD according to an embodiment of the disclosure. For example, Figure 5 Shows that can be set in Figures 1A to 2B For convenience, the gate driver GD shown in FIG. Figure 5 Only four scanning stages, eg, a first scanning stage SST1 , a second scanning stage SST2 , a third scanning stage SST3 , and a fourth scanning stage SST4 , are shown, but the disclosure is not limited thereto.

[0135] Reference Figure 5 According to the disclosed embodiment, the scan driver SD includes a plurality of scan stages to supply corresponding scan signals to a plurality of scan lines S. For example, the scan driver SD may include a plurality of scan stages connected (e.g., dependently connected) to an input terminal of the first start pulse SP1 (e.g., the first input terminal 101 of the first scan stage SST1). In the following description, when at least one of the scan stages is arbitrarily referred to, or when at least two of the scan stages are collectively referred to (e.g., each of the scan stages), the at least one of the scan stages or the collection of the scan stages may be appropriately referred to as a "scanning stage SST" or "a plurality of scanning stages SST."

[0136] The scanning stage SST outputs a scanning signal to each scan line S and is driven in response to at least one scan clock signal. For example, the first scanning stage SST1, the second scanning stage SST2, the third scanning stage SST3, and the fourth scanning stage SST4 are connected to the first scan line S1, the second scan line S2, the third scan line S3, and the fourth scan line S4, respectively, and each scanning signal is generated using the first clock signal CLK1 and the second clock signal CLK2. The first scanning stage SST1, the second scanning stage SST2, the third scanning stage SST3, and the fourth scanning stage SST4 can sequentially output scanning signals (e.g., scanning signals having a gate-on voltage) to the first scan line S1, the second scan line S2, the third scan line S3, and the fourth scan line S4, respectively. Depending on the embodiment, the scanning stages SST can have the same or substantially the same circuit structure as each other.

[0137] Each of the scanning stages SST includes a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 .

[0138] The first input terminal 101 receives a first input signal. Depending on the embodiment, the first input signal may be a first start pulse SP1 or an output signal of a previous scanning stage (e.g., a scan signal of a previous stage). For example, the first scanning stage SST1 may receive the first start pulse SP1 via the first input terminal 101, and the remaining scanning stages SST may receive the output signal of the previous scanning stage via their respective first input terminals 101. For example, the second scanning stage SST2 may receive the output signal of the first scanning stage SST1, the third scanning stage SST3 may receive the output signal of the second scanning stage SST2, the fourth scanning stage SST4 may receive the output signal of the third scanning stage SST3, and so on.

[0139] The second input terminal 102 and the third input terminal 103 receive a second input signal and a third input signal, respectively. According to an embodiment, the second input signal and the third input signal of the kth (k is an odd or even number) scanning stage SSTk may be the first clock signal CLK1 and the second clock signal CLK2, respectively. Furthermore, the second input signal and the third input signal of the k+1th scanning stage SSTk+1 may be the second clock signal CLK2 and the first clock signal CLK1, respectively. For example, the kth scanning stage SSTk (e.g., an odd-numbered scanning stage SST) may receive the first clock signal CLK1 and the second clock signal CLK2 via the second input terminal 102 and the third input terminal 103, respectively, while the k+1th scanning stage SSTk+1 (e.g., an even-numbered scanning stage SST) may receive the second clock signal CLK2 and the first clock signal CLK1 via the second input terminal 102 and the third input terminal 103, respectively.

[0140] The first clock signal CLK1 and the second clock signal CLK2 may alternately have a gate-on voltage. For example, the first clock signal CLK1 and the second clock signal CLK2 may have the same or substantially the same period and non-overlapping phases. For example, the second clock signal CLK2 may be a clock signal having a half-period shift of the first clock signal CLK1.

[0141] In addition, the scanning stage SST is operated by receiving a first driving power (e.g., a first driving power supply) VDD1 and a second driving power (e.g., a second driving power supply) VSS1. The voltage of the first driving power supply VDD1 can be set to a gate-off voltage (e.g., a gate-high voltage) of a suitable level (e.g., a predetermined level), and the voltage of the second driving power supply VSS1 can be set to a gate-on voltage (e.g., a gate-low voltage) of a suitable level (e.g., a predetermined level). In this case, the voltage of the second driving power VSS1 transmitted to the output terminal 104 of each scanning stage SST can be used as a scanning signal for selecting a pixel PXL.

[0142] Figure 6 FIG. 4 shows a scanning stage SST according to a disclosed embodiment. For example, Figure 6 Shows that can be included in Figure 5 1 and 2. The scanning stages SST in the scanning driver SD are shown in FIG. 1 and FIG. 3, and the first scanning stage SST1 and the second scanning stage SST2 are shown in more detail as representatives of the scanning stages SST.

[0143] Reference Figure 6 Each scanning stage SST according to the disclosed embodiments may include an input unit (e.g., input circuit) 110, a controller 120, and an output unit (e.g., output circuit) 130 (which may also be referred to as a "buffer unit," "buffer circuit," and / or "output buffer"). The scanning stage SST generates scan signals using a first input signal, a second input signal, and a third input signal (also referred to as a "first scan drive signal," a second scan drive signal, and a third scan drive signal") supplied through a first input terminal 101, a second input terminal 102, and a third input terminal 103 (also referred to as a "first scan drive input terminal," a second scan drive input terminal, and a third scan drive input terminal, respectively). The scanning stage SST supplies the scan signals to an output terminal 104. For example, the scanning stage SST may output each scan signal using a first start pulse SP1 or an output signal of a previous scanning stage, any one of a first clock signal CLK1 and a second clock signal CLK2, and the other of the first clock signal CLK1 and the second clock signal CLK2, supplied through the first input terminal 101, the second input terminal 102, and the third input terminal 103, respectively.

[0144] In addition, the scanning stage SST receives the first driving power VDD1 and the second driving power VSS1 through the first power terminal 105 and the second power terminal 106. The scanning stage SST can control the voltage of the output terminal 104 by using the first to third input signals and the voltages of the first driving power VDD1 and the second driving power VSS1.

[0145] In more detail, the scanning stage SST may include first to eighth transistors TS1 to TS8 and first and second capacitors CS1 to CS2. Hereinafter, when arbitrarily referring to at least one of the first to eighth transistors TS1 to TS8, the at least one of the first to eighth transistors TS1 to TS8 or the aggregate of the first to eighth transistors TS1 to TS8 may be appropriately referred to as "first driver transistor TS" or "plurality of first driver transistors TS". When arbitrarily referring to at least one of the first and second capacitors CS1 and CS2, the at least one of the first and second capacitors CS1 and CS2 or the aggregate of the first and second capacitors CS1 and CS2 may be appropriately referred to as "first driver capacitor CS" or "plurality of first driver capacitors CS". For convenience, hereinafter, the circuit structure of each scanning stage SST will be described with reference to the first scanning stage SST1.

[0146] The input unit 110 controls the voltage of the third node NS3 in response to the first input signal, the second input signal, and the third input signal respectively supplied to the first input terminal 101, the second input terminal 102, and the third input terminal 103. For example, the input unit 110 may control the voltage of the third node NS3 in response to the first start pulse SP1 supplied to the first input terminal 101, the first clock signal CLK1 supplied to the second input terminal 102, and the second clock signal CLK2 supplied to the third input terminal 103. Therefore, the input unit 110 includes a first transistor TS1, a second transistor TS2, and a third transistor TS3.

[0147] The first transistor TS1 is connected between the first input terminal 101 and the third node NS3, and a gate electrode of the first transistor TS1 is connected to the second input terminal 102. The first transistor TS1 is turned on when a first clock signal CLK1 having a gate-on voltage (e.g., a low voltage) is supplied to the second input terminal 102 to connect the first input terminal 101 and the third node NS3 to each other.

[0148] The second transistor TS2 and the third transistor TS3 are connected between the third node NS3 and the first driving power VDD1. For example, the second transistor TS2 and the third transistor TS3 may be connected in series between the third node NS3 and the first driving power VDD1.

[0149] The second transistor TS2 is connected between the third transistor TS3 and the third node NS3, and a gate electrode of the second transistor TS2 is connected to the third input terminal 103. The second transistor TS2 is turned on when the second clock signal CLK2 having a gate-on voltage (e.g., a low voltage) is supplied to the third input terminal 103 to connect the third transistor TS3 and the third node NS3 to each other.

[0150] The third transistor TS3 is connected between the second transistor TS2 and the first driving power VDD1, and has a gate electrode connected to the first node NS1. The third transistor TS3 controls the connection between the second transistor TS2 and the first driving power VDD1 in accordance with the voltage of the first node NS1.

[0151] The controller 120 controls the voltage of the first node NS1 and the voltage of the second node NS2 in correspondence with the second input signal supplied to the second input terminal 102 and the voltage of the third node NS3. For example, the controller 120 may control the voltage of the first node NS1 and the second node NS2 in correspondence with the first clock signal CLK1 supplied to the second input terminal 102 and the voltage of the third node NS3. Therefore, the controller 120 includes a fourth transistor TS4, a fifth transistor TS5, and a sixth transistor TS6, and a first capacitor CS1 and a second capacitor CS2.

[0152] The fourth transistor TS4 is connected between the first node NS1 and the second input terminal 102, and has a gate electrode connected to the third node NS3. The fourth transistor TS4 controls the connection between the first node NS1 and the second input terminal 102 in accordance with the voltage of the third node NS3.

[0153] The fifth transistor TS5 is connected between the first node NS1 and the second power terminal 106, and a gate electrode of the fifth transistor TS5 is connected to the second input terminal 102. The fifth transistor TS5 is turned on when the first clock signal CLK1 having a gate-on voltage is supplied to the second input terminal 102 to connect the first node NS1 to the second power terminal 106. Therefore, when the fifth transistor TS5 is turned on, the low voltage of the second driving power VSS1 is transmitted to the first node NS1.

[0154] The sixth transistor TS6 is connected between the third node NS3 and the second node NS2, and the gate electrode of the sixth transistor TS6 is connected to the second power terminal 106. The sixth transistor TS6 is turned on by the low voltage of the second drive power VSS1 supplied to the second power terminal 106, thereby connecting the third node NS3 and the second node NS2 to each other. The width of the voltage drop (e.g., the amount of voltage drop) at the third node NS3 can be limited by the sixth transistor TS6. For example, even if the voltage of the second node NS2 drops to a voltage lower than the voltage of the second drive power VSS1, the voltage of the third node NS3 can be no lower than the voltage corresponding to the difference between the voltage of the second drive power VSS1 and the threshold voltage of the sixth transistor TS6 (e.g., the voltage obtained by subtracting the threshold voltage of the sixth transistor TS6 from the voltage of the second drive power VSS1).

[0155] The first capacitor CS1 is connected between the second node NS2 and the output terminal 104. The first capacitor CS1 is charged with a suitable voltage to turn on and / or turn off the eighth transistor TS8.

[0156] The second capacitor CS2 is connected between the first node NS1 and the first power terminal 105. The second capacitor CS2 charges the voltage applied to the first node NS1.

[0157] The output unit 130 controls the voltage supplied to the output terminal 104 in accordance with the voltages of the first node NS1 and the second node NS2. For example, the output unit 130 may apply a high voltage of the first driving power VDD1 or a low voltage of the second driving power VSS1 to the output terminal 104 in accordance with the voltages of the first node NS1 and the second node NS2. Therefore, the output unit 130 includes a seventh transistor TS7 and an eighth transistor TS8.

[0158] The seventh transistor TS7 is connected between the first power terminal 105 and the output terminal 104, and the gate electrode of the seventh transistor TS7 is connected to the first node NS1. The seventh transistor TS7 is turned on or off in response to the voltage of the first node NS1 to control the connection between the first power terminal 105 and the output terminal 104. When the seventh transistor TS7 is turned on, the high voltage of the first drive power VDD1 is transmitted to the output terminal 104. Therefore, the gate-off voltage can be output to the scan line S (e.g., the first scan line S1) connected to the output terminal 104.

[0159] The eighth transistor TS8 is connected between the output terminal 104 and the third input terminal 103, and the gate electrode of the eighth transistor TS8 is connected to the second node NS2. The eighth transistor TS8 is turned on or off in response to the voltage of the second node NS2 to control the connection between the third input terminal 103 and the output terminal 104. When the eighth transistor TS8 is turned on, the voltage of the second clock signal CLK2 is transmitted to the output terminal 104. The second clock signal CLK2 has a high voltage and a low voltage that repeat according to a certain period (e.g., a predetermined period). During the period when the second clock signal CLK2 has a low voltage while the eighth transistor TS8 is turned on, the low voltage of the second clock signal CLK2 can be transmitted to the scan line S (e.g., the first scan line S1) connected to the output terminal 104 and can be used as a scan signal.

[0160] In the second scanning stage SST2, the first, second, and third input signals supplied to the first, second, and third input terminals 101, 102, and 103 are different from the first, second, and third input signals of the first scanning stage SST1. The circuit structure and operation process of the second scanning stage SST2 may be the same or substantially the same as those of the first scanning stage SST1. For example, the second scanning stage SST2 may receive the output signal of the first scanning stage SST1 (e.g., the first scanning signal supplied to the first scanning line S1), the second clock signal CLK2, and the first clock signal CLK1 through the first, second, and third input terminals 101, 102, and 103, respectively. The second, second, and first clock signals CLK2 and CLK1 may be used to generate a scanning signal (e.g., a scanning signal supplied to the output terminal 104 of the second scanning stage SST2). The scanning signal generated by (e.g., generated in) the second scanning stage SST2 is supplied to the second scanning line S2.

[0161] The scanning stage SST may sequentially output scanning signals to the scanning lines S while operating in the above-described manner. A circuit structure and an operation process of each of the second scanning stage SST2 and the remaining scanning stages SST subsequent to the second scanning stage SST2 may be the same or substantially the same as those of the first scanning stage SST1. Therefore, a redundant description thereof may not be repeated.

[0162] However, the structure of the scanning stage SST according to the disclosed embodiment is not limited to Figure 6 For example, each scanning stage SST may be configured by a stage circuit having various suitable structures and / or various suitable driving methods as will be known to those skilled in the art.

[0163] Figure 7 The driving method of the scanning stage SST according to the disclosed embodiment is shown. For example, Figure 7 Shown Figure 5 and Figure 6 For convenience, the first scanning stage SST1 will be used as a representative example reference. Figure 7 Describe the operation process of each scanning stage SST.

[0164] Reference Figure 7, each of the first clock signal CLK1 and the second clock signal CLK2 may have a period corresponding to two horizontal periods (2H), and the first clock signal CLK1 and the second clock signal CLK2 may be supplied during different horizontal periods. For convenience, when describing this embodiment, when each of the first clock signal CLK1 and the second clock signal CLK2 has a gate-on voltage, each of the first clock signal CLK1 and the second clock signal CLK2 may be described as being "supplied". Similarly, when the first start pulse SP1 has a gate-on voltage, the first start pulse SP1 may be described as being "supplied". Because the first driver transistor TS is Figure 6 1 is shown as a P-type transistor, so hereinafter, the gate-on voltage and the gate-off voltage will be described as “low voltage” and “high voltage”, respectively, but the disclosure is not limited thereto.

[0165] According to an embodiment, the second clock signal CLK2 may be a signal shifted from the first clock signal CLK1 by half a cycle (e.g., one horizontal period 1H). In addition, the first start pulse SP1 supplied to the first input terminal 101 may be supplied synchronously with the second input signal (e.g., the first clock signal CLK1) supplied to the second input terminal 102. In other words, the first start pulse SP1 may be supplied to the first input terminal 101 concurrently (e.g., simultaneously) with the second input signal (e.g., the first clock signal CLK1) supplied to the second input terminal 102 at least once.

[0166] In an embodiment, when the first start pulse SP1 is supplied, the first input terminal 101 may be set to a low voltage of the second drive power VSS1, and when the first start pulse SP1 is not supplied, the first input terminal 101 may be set to a high voltage of the first drive power VDD1. In addition, when the first clock signal CLK1 and the second clock signal CLK2 are supplied to the second input terminal 102 and the third input terminal 103, respectively, the second input terminal 102 and the third input terminal 103 may be set to a low voltage of the second drive power VSS1, and when the first clock signal CLK1 and the second clock signal CLK2 are not supplied, the second input terminal 102 and the third input terminal 103 may be set to a high voltage of the first drive power VDD1.

[0167] In the following, reference will be made to Figure 6 and Figure 7 The operation process is described in more detail. First, a first start pulse SP1 is supplied in synchronization with the supply of the first clock signal CLK1.

[0168] When the first clock signal CLK1 is supplied, the first transistor TS1 and the fifth transistor TS5 are turned on. When the first transistor TS1 is turned on, the first input terminal 101 and the third node NS3 are electrically connected to each other. In some embodiments, because the sixth transistor TS6 can be always turned on by the second driving power VSS1, the third node NS3 is connected to the second node NS2.

[0169] When the first input terminal 101 and the third node NS3 are electrically connected to each other, the voltages of the third node NS3 and the second node NS2 are set to a low voltage by the first start pulse SP1 supplied to the first input terminal 101. When the voltages of the third node NS3 and the second node NS2 are set to a low voltage, the eighth transistor TS8 and the fourth transistor TS4 are turned on.

[0170] When the eighth transistor TS8 is turned on, the third input terminal 103 and the output terminal 104 are electrically connected to each other. Here, the third input terminal 103 is set to a high voltage (for example, based on the second clock signal CLK2 not being supplied), and thus the high voltage is output to the output terminal 104. When the fourth transistor TS4 is turned on, the second input terminal 102 and the first node NS1 are electrically connected to each other. Then, the voltage of the first clock signal CLK1 supplied to the second input terminal 102 (for example, a low voltage) is supplied to the first node NS1.

[0171] In addition, when the first clock signal CLK1 is supplied, the fifth transistor TS5 is turned on. When the fifth transistor TS5 is turned on, the low voltage of the second drive power VSS1 is supplied to the first node NS1. Here, the low voltage of the second drive power VSS1 is set to be the same as or substantially the same as (e.g., or similar to) the voltage of the first clock signal CLK1. Therefore, the first node NS1 maintains or substantially maintains (e.g., stably maintains) a low voltage.

[0172] When the first node NS1 is set to a low voltage, the third transistor TS3 and the seventh transistor TS7 are turned on. When the third transistor TS3 is turned on, the first drive power VDD1 and the second transistor TS2 are connected to each other. At this time, because the second transistor TS2 is set to an off state, even if the third transistor TS3 is turned on, the third node NS3 maintains or substantially maintains (e.g., maintains a stable) low voltage. When the seventh transistor TS7 is turned on, the high voltage of the first drive power VDD1 is supplied to the output terminal 104. Here, the voltage of the first drive power VDD1 is set to be the same as or substantially the same as the high voltage supplied to the third input terminal 103. Therefore, the output terminal 104 can maintain or substantially maintain (e.g., maintain a stable) high voltage.

[0173] Thereafter, the supply of the first start pulse SP1 and the first clock signal CLK1 is stopped (e.g., changed to a high voltage). When the supply of the first clock signal CLK1 is stopped, the first transistor TS1 and the fifth transistor TS5 are turned off. At this time, the eighth transistor TS8 and the fourth transistor TS4 remain in or substantially remain in an on state corresponding to the voltage stored in the first capacitor CS1. In other words, the second node NS2 and the third node NS3 can be maintained or substantially maintained at a low voltage by the voltage stored in the first capacitor CS1.

[0174] When the eighth transistor TS8 remains or substantially remains in the on state, the output terminal 104 remains connected to the third input terminal 103. When the fourth transistor TS4 remains or substantially remains in the on state, the first node NS1 remains or substantially remains connected to the second input terminal 102. Here, the voltage of the second input terminal 102 is set to a high voltage in response to the cessation (or change) of the supply of the first clock signal CLK1, and therefore the first node NS1 is also set to a high voltage. When the high voltage is supplied to the first node NS1, the third transistor TS3 and the seventh transistor TS7 are turned off.

[0175] Thereafter, the second clock signal CLK2 is supplied to the third input terminal 103. At this time, since the eighth transistor TS8 is set to the on state, the second clock signal CLK2 supplied to the third input terminal 103 is supplied to the output terminal 104. In this case, the output terminal 104 outputs the second clock signal CLK2 having a low voltage as a scan signal having a gate-on voltage to the first scan line S1.

[0176] When the second clock signal CLK2 is supplied to the output terminal 104, the voltage of the second node NS2 decreases to a voltage lower than the low voltage of the second driving power VSS1 due to coupling of the first capacitor CS1, and thus the eighth transistor TS8 maintains or substantially maintains (eg, stably maintains) a turned-on state.

[0177] Even when the voltage of the second node NS2 decreases, the third node NS3 can maintain or substantially maintain a voltage corresponding to (e.g., approximately) the voltage of the second driving power VSS1 (e.g., a voltage obtained by subtracting the threshold voltage of the sixth transistor TS6 from the low voltage of the second driving power VSS1).

[0178] After the scan signal is output to the first scan line S1, the supply of the second clock signal CLK2 is stopped (for example, the supply of the second clock signal CLK2 is changed to a high voltage). When the supply of the second clock signal CLK2 is stopped, the output terminal 104 outputs a high voltage. In addition, the voltage of the second node NS2 increases to a low voltage of the second driving power VSS1 in response to the high voltage of the output terminal 104.

[0179] Thereafter, the first clock signal CLK1 is supplied. When the first clock signal CLK1 is supplied, the first transistor TS1 and the fifth transistor TS5 are turned on. When the first transistor TS1 is turned on, the first input terminal 101 and the third node NS3 are connected to each other. At this time, the first start pulse SP1 is not supplied to the first input terminal 101, and therefore, the first input terminal 101 is set to a high voltage. Therefore, a high voltage is supplied to the third node NS3 and the second node NS2, and thus the eighth transistor TS8 and the fourth transistor TS4 are turned off.

[0180] When the fifth transistor TS5 is turned on, the low voltage of the second driving power VSS1 is supplied to the first node NS1, and thus the third transistor TS3 and the seventh transistor TS7 are turned on. When the seventh transistor TS7 is turned on, the high voltage of the first driving power VDD1 is supplied to the output terminal 104. Thereafter, the third transistor TS3 and the seventh transistor TS7 remain in or substantially remain in an on state corresponding to the voltage charged in the second capacitor CS2, and thus the output terminal 104 stably receives the high voltage of the first driving power VDD1.

[0181] In addition, when the second clock signal CLK2 is supplied, the second transistor TS2 is turned on. At this time, because the third transistor TS3 is set to the on state, the high voltage of the first drive power VDD1 is supplied to the third node NS3 and the second node NS2. In this case, the eighth transistor TS8 and the fourth transistor TS4 remain in or substantially remain in (e.g., stably remain in) the off state.

[0182] The second scanning stage SST2 receives the output signal of the first scanning stage SST1 (e.g., the first scanning signal supplied to the first scanning line S1) in synchronization with the second clock signal CLK2. Furthermore, the second scanning stage SST2 outputs the scanning signal to the second scanning line S2 in synchronization with the first clock signal CLK1. The scanning stage SST according to the disclosed embodiment sequentially outputs the scanning signal to the scanning lines S by repeating the above process.

[0183] Figure 8 FIG. 4 shows a light emission control driver ED according to an embodiment of the disclosure. For example, Figure 8 Shows that can be included in Figures 1A to 2BFor convenience, the embodiment of the light emission control driver ED in any one of the gate drivers GD is shown. Figure 8 Only four light emitting control stages, for example, a first light emitting control stage EST1 , a second light emitting control stage EST2 , a third light emitting control stage EST3 , and a fourth light emitting control stage EST4 are shown, but the disclosure is not limited thereto.

[0184] Reference Figure 8 According to the disclosed embodiment, the light emission control driver ED includes multiple light emission control stages to supply corresponding light emission control signals to multiple light emission control lines E. For example, the light emission control driver ED may include multiple light emission stages connected (e.g., dependently connected) to an input terminal of the second start pulse SP2 (e.g., the first input terminal 201 of the first light emission control stage EST1). In the following description, when at least one of the light emission control stages is arbitrarily referred to, or when at least two of the light emission control stages (e.g., or each of the light emission control stages) are collectively referred to, the at least one of the light emission control stages or the aggregate of the light emission control stages may be appropriately referred to as a "light emission control stage EST" or "a plurality of light emission control stages EST."

[0185] In an embodiment, the light control stages EST are connected to any one of the light control lines E and driven in response to at least one light clock signal. For example, the first light control stage EST1, the second light control stage EST2, the third light control stage EST3, and the fourth light control stage EST4 are connected to the first light control line E1, the second light control line E2, the third light control line E3, and the fourth light control line E4, respectively, and use the third clock signal CLK3 and the fourth clock signal CLK4 to generate corresponding light control signals. The first light control stage EST1, the second light control stage EST2, the third light control stage EST3, and the fourth light control stage EST4 can sequentially output light control signals (e.g., light control signals with gate-off voltages) to the first light control line E1, the second light control line E2, the third light control line E3, and the fourth light control line E4. Depending on the embodiment, the light control stages EST can have the same or substantially the same circuit structure as each other.

[0186] In another embodiment, the emission control stage EST may be connected to multiple emission control lines E to concurrently (e.g., simultaneously) supply emission control signals to the multiple emission control lines E. For example, the first emission control stage EST1 may be commonly connected to the first emission control line E1 and the second emission control line E2 via the output terminal 204 to concurrently (e.g., simultaneously) supply emission control signals to the first emission control line E1 and the second emission control line E2. In this case, the pixels PXL of the first and second horizontal lines connected to the first and second emission control lines E1 and E2 may emit light concurrently (e.g., simultaneously) or not emit light. For example, the first emission control stage EST1 may concurrently (e.g., simultaneously) supply emission control signals to the first and second emission control lines E1 and E2 so as to overlap with the initialization control signals and scan signals supplied to the first and second initialization control lines GI1 and GI2 and the first and second scan lines S1 and S2, respectively, connected to the pixels PXL of the first and second horizontal lines. In this case, the first light emitting control stage EST1 may concurrently (eg, simultaneously) drive the first light emitting control line E1 and the second light emitting control line E2 .

[0187] Similarly, the remaining light emitting control stages EST can respectively and concurrently (e.g., simultaneously) drive the plurality of light emitting control lines E. For example, the second light emitting control stage EST2 can concurrently (e.g., simultaneously) drive the third light emitting control line E3 and the fourth light emitting control line E4, the third light emitting control stage EST3 can concurrently (e.g., simultaneously) drive the fifth light emitting control line E5 and the sixth light emitting control line E6, and the fourth light emitting control stage EST4 can concurrently (e.g., simultaneously) drive the seventh light emitting control line E7 and the eighth light emitting control line E8.

[0188] As described above, when each of the light emission control stages EST drives a plurality of light emission control lines E concurrently (e.g., simultaneously), the circuit structure of the light emission control driver ED can be simplified and the area (e.g., size) of the light emission control driver ED can be reduced. However, for convenience, in describing Figure 8 Embodiments and related Figure 9 and Figure 10 When the embodiment is described, it can be assumed that each of the light emission control stages EST can supply a light emission control signal to any one or more of the light emission control lines E.

[0189] Each of the light emission control stages EST includes a first input terminal 201 , a second input terminal 202 , a third input terminal 203 , and an output terminal 204 .

[0190] The first input terminal 201 receives a first input signal. Depending on the embodiment, the first input signal may be a second start pulse SP2 or an output signal of a previous light control stage (e.g., a light control signal of the previous stage). For example, the first light control stage EST1 may receive the second start pulse SP2 via the first input terminal 201, and the remaining light control stages EST may receive the output signal of the previous light control stage via their respective first input terminals 201. For example, the second light control stage EST2 may receive the output signal of the first light control stage EST1, the third light control stage EST3 may receive the output signal of the second light control stage EST2, the fourth light control stage EST4 may receive the output signal of the third light control stage EST3, and so on.

[0191] The second input terminal 202 and the third input terminal 203 receive a second input signal and a third input signal, respectively. According to an embodiment, the second input signal and the third input signal of the kth (k is an odd or even number) light emitting control stage ESTk may be the third clock signal CLK3 and the fourth clock signal CLK4, respectively. Furthermore, the second input signal and the third input signal of the k+1th light emitting control stage ESTk+1 may be the fourth clock signal CLK4 and the third clock signal CLK3, respectively. For example, the kth light emitting control stage ESTk (e.g., an odd-numbered light emitting control stage EST) may receive the third clock signal CLK3 and the fourth clock signal CLK4 via the second input terminal 202 and the third input terminal 203, respectively, and the k+1th light emitting control stage ESTk+1 (e.g., an even-numbered light emitting control stage EST) may receive the fourth clock signal CLK4 and the third clock signal CLK3 via the second input terminal 202 and the third input terminal 203, respectively.

[0192] The third clock signal CLK3 and the fourth clock signal CLK4 may alternately have a gate-on voltage. For example, the third clock signal CLK3 and the fourth clock signal CLK4 may have the same or substantially the same period and non-overlapping phases. For example, the fourth clock signal CLK4 may be a clock signal having a form in which the third clock signal CLK3 is shifted by half a period.

[0193] In addition, the light emission control stage EST operates by receiving a third drive power (e.g., a third drive power supply) VDD2 and a fourth drive power (e.g., a fourth drive power supply) VSS2. The voltage of the third drive power VDD2 is set to a gate-off voltage (e.g., a gate-high voltage), and the fourth drive power VSS2 is set to a gate-on voltage (e.g., a gate-low voltage). In this case, the high voltage of the third drive power VDD2 transmitted to the output terminal 204 of each light emission control stage EST can be used as a light emission control signal for preventing or substantially preventing the pixel PXL from emitting light.

[0194] According to an embodiment, the high voltage of the third driving power VDD2 may be the same as or substantially the same as the high voltage of the first driving power VDD1 supplied to the scan driver SD, or may be different from the high voltage of the first driving power VDD1 supplied to the scan driver SD. Similarly, the low voltage of the fourth driving power VSS2 may be the same as or substantially the same as the low voltage of the second driving power VSS1 supplied to the scan driver SD, or may be different from the low voltage of the second driving power VSS1 supplied to the scan driver SD.

[0195] Figure 9 FIG. 1 shows a light emission control stage EST according to an embodiment disclosed. For example, Figure 9 Shows that can be included in Figure 8 1 and 2. The light emitting control stage EST in the light emitting control driver ED is shown in detail, and the first light emitting control stage EST1 and the second light emitting control stage EST2 as representatives of the light emitting control stage EST are shown in more detail.

[0196] Reference Figure 9 Each of the light emission control stages EST includes an input unit (e.g., input circuit) 210, a first control unit (e.g., first control circuit or first controller) 220, a second control unit (e.g., second control circuit or second controller) 230, and an output unit (e.g., output circuit) 240. The light emission control stage EST generates a light emission control signal using a first input signal, a second input signal, and a third input signal (which may also be referred to as a "first light emission drive input terminal, a second light emission drive input terminal, and a third light emission drive input terminal") supplied through a first input terminal 201, a second input terminal 202, and a third input terminal 203, respectively (which may also be referred to as a "first light emission drive input terminal, a second light emission drive input terminal, and a third light emission drive input terminal," respectively). The light emission control stage EST supplies the generated light emission control signal to an output terminal 204. For example, the light-emitting control stage EST can output each light-emitting control signal using the second start pulse SP2 or the output signal of the previous light-emitting control stage, any one of the third clock signal CLK3 and the fourth clock signal CLK4, and the other of the third clock signal CLK3 and the fourth clock signal CLK4 supplied through the first input terminal 201, the second input terminal 202 and the third input terminal 203 respectively.

[0197] In addition, the light emission control stage EST receives the third driving power VDD2 and the fourth driving power VSS2 through the first power terminal 205 and the second power terminal 206. The light emission control stage EST can control the voltage of the output terminal 204 using the first to third input signals and the voltages of the third driving power VDD2 and the fourth driving power VSS2.

[0198] In more detail, the light emission control stage EST may include first to tenth transistors TE1 to TE10 and first to third capacitors CE1 to CE3. Hereinafter, when any reference is made to at least one of the first to tenth transistors TE1 to TE10, or when the first to tenth transistors TE1 to TE10 are collectively referred to (e.g., or each of the first to tenth transistors TE1 to TE10), at least one of the first to tenth transistors TE1 to TE10 or the aggregate of the first to tenth transistors TE1 to TE10 may be referred to as a "second driver transistor TE" or "plurality of second driver transistors TE." When any reference is made to at least one of the first to third capacitors CE1 to CE3, or when the first to third capacitors CE1 to CE3 are collectively referred to (e.g., or each of the first to third capacitors CE1 to CE3), at least one of the first to third capacitors CE1 to CE3 or the aggregate of the first to third capacitors CE1 to CE3 may be referred to as a "second driver capacitor CE" or "plurality of second driver capacitors CE." For convenience, the circuit structure of each light emission control stage EST will be described below with reference to the first light emission control stage EST1.

[0199] The input unit 210 controls the voltage of the first node NE1 and the voltage of the second node NE2 in response to the first input signal supplied to the first input terminal 201 and the second input signal supplied to the second input terminal 202. For example, the input unit 210 of the first light emitting control stage EST1 can control the voltage of the first node NE1 and the second node NE2 in response to the second start pulse SP2 supplied to the first input terminal 201 and the third clock signal CLK3 supplied to the second input terminal 202. Therefore, the input unit 210 includes a first transistor TE1, a second transistor TE2, and a third transistor TE3.

[0200] The first transistor TE1 is connected between the first input terminal 201 and the first node NE1, and a gate electrode of the first transistor TE1 is connected to the second input terminal 202. The first transistor TE1 is turned on when a third clock signal CLK3 having a gate-on voltage (e.g., a low voltage) is supplied to the second input terminal 202 to connect the first input terminal 201 and the first node NE1 to each other.

[0201] The second transistor TE2 is connected between the second node NE2 and the second input terminal 202, and has a gate electrode connected to the first node NE1. The second transistor TE2 controls the connection between the second node NE2 and the second input terminal 202 in response to the voltage of the first node NE1.

[0202] The third transistor TE3 is connected between the second node NE2 and the fourth driving power VSS2, and a gate electrode of the third transistor TE3 is connected to the second input terminal 202. The third transistor TE3 is turned on when the third clock signal CLK3 having a gate-on voltage is supplied to the second input terminal 202 to supply the voltage of the fourth driving power VSS2 to the second node NE2.

[0203] The first controller 220 controls the voltages of the first node NE1 and the third node NE3 in accordance with the third input signal (e.g., the fourth clock signal CLK4) supplied to the third input terminal 203 and the voltage of the second node NE2. In more detail, the first controller 220 includes fourth to seventh transistors TE4 to TE7 and first and second capacitors CE1 and CE2.

[0204] The fourth transistor TE4 and the fifth transistor TE5 are connected between the first node NE1 and the third driving power VDD2. For example, the fourth transistor TE4 and the fifth transistor TE5 may be connected in series between the first node NE1 and the third driving power VDD2.

[0205] The fourth transistor TE4 is connected between the first node NE1 and the fifth transistor TE5, and a gate electrode of the fourth transistor TE4 is connected to the third input terminal 203. The fourth transistor TE4 is turned on when a fourth clock signal CLK4 having a gate-on voltage (e.g., a low voltage) is supplied to the third input terminal 203 to connect the first node NE1 and the fifth transistor TE5 to each other.

[0206] The fifth transistor TE5 is connected between the fourth transistor TE4 and the third driving power VDD2, and has a gate electrode connected to the second node NE2. The fifth transistor TE5 controls the connection between the fourth transistor TE4 and the third driving power VDD2 in accordance with the voltage of the second node NE2.

[0207] The sixth transistor TE6 is connected between the first electrode of the seventh transistor TE7 and the third input terminal 203, and the gate electrode of the sixth transistor TE6 is connected to the second node NE2. The sixth transistor TE6 controls the connection between the first electrode of the seventh transistor TE7 and the third input terminal 203 in response to the voltage of the second node NE2.

[0208] The seventh transistor TE7 is connected between the first electrode of the sixth transistor TE6 and the third node NE3, and the gate electrode of the seventh transistor TE7 is connected to the third input terminal 203. The seventh transistor TE7 is turned on when the fourth clock signal CLK4 having the gate-on voltage is supplied to the third input terminal 203 to connect the first electrode of the sixth transistor TE6 and the third node NE3 to each other.

[0209] The first capacitor CE1 is connected between the first node NE1 and the third input terminal 203 .

[0210] The second capacitor CE2 is connected between the second node NE2 and the first electrode of the seventh transistor TE7.

[0211] The second controller 230 controls the voltage of the third node NE3 corresponding to the voltage of the first node NE1. In more detail, the second controller 230 includes an eighth transistor TE8 and a third capacitor CE3.

[0212] The eighth transistor TE8 is connected between the third node NE3 and the third driving power VDD2, and has a gate electrode connected to the first node NE1. The eighth transistor TE8 controls the connection between the third node NE3 and the third driving power VDD2 in accordance with the voltage of the first node NE1.

[0213] The third capacitor CE3 is connected between the third node NE3 and the third driving power VDD2 .

[0214] The output unit 240 controls a voltage supplied to the output terminal 204 corresponding to voltages of the first node NE1 and the third node NE3. In more detail, the output unit 240 includes a ninth transistor TE9 and a tenth transistor TE10.

[0215] The ninth transistor TE9 is connected between the first power terminal 205 and the output terminal 204, and the gate electrode of the ninth transistor TE9 is connected to the third node NE3. The ninth transistor TE9 is turned on or off in response to the voltage of the third node NE3, and controls the connection between the first power terminal 205 and the output terminal 204. When the ninth transistor TE9 is turned on, the high voltage of the third drive power VDD2 is transmitted to the output terminal 204. Therefore, the high voltage of the third drive power VDD2 is supplied to the light emission control line E (e.g., the first light emission control line E1) connected to the output terminal 204. The high voltage of the third drive power VDD2 can be used as a light emission control signal with a gate-off voltage.

[0216] The tenth transistor TE10 is connected between the output terminal 204 and the second power terminal 206, and the gate electrode of the tenth transistor TE10 is connected to the first node NE1. The tenth transistor TE10 is turned on or off in response to the voltage of the first node NE1, and controls the connection between the second power terminal 206 and the output terminal 204. When the tenth transistor TE10 is turned on, the low voltage of the fourth driving power VSS2 is transmitted to the output terminal 204. Therefore, the gate-on voltage can be output to the light emission control line E (e.g., the first light emission control line E1) connected to the output terminal 204.

[0217] In the second light emission control stage EST2, the first, second, and third input signals supplied to the first, second, and third input terminals 201, 202, and 203, respectively, are different from the first, second, and third input signals of the first light emission control stage EST1. The circuit structure and operation process of the second light emission control stage EST2 may be the same or substantially the same as those of the first light emission control stage EST1. For example, the second light emission control stage EST2 may receive the output signal of the first light emission control stage EST1 (e.g., the first light emission control signal supplied to the first light emission control line E1), the fourth clock signal CLK4, and the third clock signal CLK3 through the first, second, and third input terminals 201, 202, and 203, respectively. The output signal of the first light emission control stage EST1, the fourth clock signal CLK4, and the third clock signal CLK3 may be used to generate a light emission control signal (e.g., the light emission control signal supplied to the output terminal 204 of the second light emission control stage EST2). The light emitting control signal generated by (eg, or generated in) the second light emitting control stage EST2 is supplied to the second light emitting control line E2.

[0218] The light emission control stage EST can sequentially output the light emission control signal to the light emission control line E while operating in the above-described manner. The circuit structure and operation process of each of the second light emission control stage EST2 and the remaining light emission control stages EST after the second light emission control stage EST2 may be the same or substantially the same as the circuit structure and operation process of the first light emission control stage EST1. Therefore, a redundant description thereof may not be repeated.

[0219] However, the structure of the light emission control stage EST according to the disclosed embodiment is not limited to Figure 9 For example, each light emission control stage EST may be configured by a stage circuit having various suitable structures and / or various suitable driving methods known to those skilled in the art.

[0220] Figure 10FIG. 1 shows a driving method of the light emitting control stage EST according to the disclosed embodiment. For example, Figure 10 Shown Figure 8 and Figure 9 For convenience, the first light emitting control stage EST1 will be used as a representative example for reference. Figure 10 Describe the operation process of each lighting control stage EST.

[0221] Reference Figure 10 Each of the third clock signal CLK3 and the fourth clock signal CLK4 may have a period corresponding to two horizontal periods (2H), and the third clock signal CLK3 and the fourth clock signal CLK4 may be supplied during different horizontal periods. For example, the fourth clock signal CLK4 may be a signal shifted from the third clock signal CLK3 by half a period (e.g., one horizontal period, 1H). For convenience, when describing this embodiment, the third clock signal CLK3 and the fourth clock signal CLK4 may be described as being "supplied" when each has a gate-on voltage (e.g., a low voltage). For example, when the third clock signal CLK3 and the fourth clock signal CLK4 are respectively supplied to the second input terminal 202 and the third input terminal 203, the second input terminal 202 and the third input terminal 203 can be set to the low voltage of the fourth driving power VSS2, and when the third clock signal CLK3 and the fourth clock signal CLK4 are not supplied, the second input terminal 202 and the third input terminal 203 can be set to the high voltage of the third driving power VDD2.

[0222] The second start pulse SP2 supplied to the first input terminal 201 may be supplied in synchronization with the clock signal (e.g., the third clock signal CLK3) supplied to the second input terminal 202. Furthermore, the second start pulse SP2 is set to have a width wider than that of the third clock signal CLK3. For example, the second start pulse SP2 may be supplied during four horizontal periods (4H).

[0223] The second start pulse SP2 is used to generate a light emitting control signal to turn off (e.g., temporarily block) the light emitting of the pixel PXL. Therefore, when the second start pulse SP2 has a gate-off voltage (e.g., a high voltage), the second start pulse SP2 can be described as being "supplied." For example, when the second start pulse SP2 is supplied, the first input terminal 201 can be set to the high voltage of the third driving power VDD2, and when the second start pulse SP2 is not supplied, the first input terminal 201 can be set to the low voltage of the fourth driving power VSS2. Figure 9In the embodiment, since the second driver transistor TE is shown to be formed of a P-type transistor, the gate-on voltage and the gate-off voltage will be described as “low voltage” and “high voltage”, respectively, hereinafter, but the disclosure is not limited thereto.

[0224] In the following, reference will be made to Figure 9 and Figure 10 The operation process is described in more detail. First, the third clock signal CLK3 is supplied to the second input terminal 202 within a suitable period (eg, a predetermined period) from the first time point t1. When the third clock signal CLK3 is supplied to the second input terminal 202, the first transistor TE1 and the third transistor TE3 are turned on.

[0225] When the first transistor TE1 is turned on, the first input terminal 201 and the first node NE1 are connected to each other. At this time, since the second start pulse SP2 is not supplied to the first input terminal 201, a low voltage is supplied to the first node NE1.

[0226] When the low voltage is supplied to the first node NE1 , the second transistor TE2 , the eighth transistor TE8 , and the tenth transistor TE10 are turned on.

[0227] When the eighth transistor TE8 is turned on, the high voltage of the third drive power VDD2 is supplied to the third node NE3, and thus the ninth transistor TE9 is turned off. At this time, the third capacitor CE3 is charged with a voltage corresponding to the high voltage of the third drive power VDD2. Therefore, even after the first time point t1, the ninth transistor TE9 remains or substantially remains (e.g., remains stably) in the off state.

[0228] When the tenth transistor TE10 is turned on, the low voltage of the fourth driving power VSS2 is supplied to the output terminal 204. Therefore, the light emitting control signal is not supplied to the first light emitting control line E1 at the first time point t1.

[0229] When the second transistor TE2 is turned on, the third clock signal CLK3 is supplied to the second node NE2. Furthermore, when the third transistor TE3 is turned on, the low voltage of the fourth drive power VSS2 is supplied to the second node NE2. Here, the third clock signal CLK3 can be set to the low voltage of the fourth drive power VSS2, so the second node NE2 can be stably set to the low voltage of the fourth drive power VSS2. When the voltage of the second node NE2 is set to the low voltage of the fourth drive power VSS2, the seventh transistor TE7 is set to be in an off state. Therefore, the third node NE3 maintains or substantially maintains the high voltage of the third drive power VDD2, regardless of the voltage of the second node NE2.

[0230] At the second time point t2, the supply of the third clock signal CLK3 is stopped. When the supply of the third clock signal CLK3 is stopped, the first transistor TE1 and the third transistor TE3 are turned off. At this time, the voltage of the first node NE1 is maintained or substantially maintained at a low voltage through the first capacitor CE1. Therefore, the second transistor TE2, the eighth transistor TE8, and the tenth transistor TE10 are maintained or substantially maintained in the on state.

[0231] When the second transistor TE2 is turned on, the second input terminal 202 and the second node NE2 are connected to each other. At this time, the second node NE2 is set to a high voltage.

[0232] When the eighth transistor TE8 is turned on, the high voltage of the third driving power VDD2 is supplied to the third node NE3, and thus the ninth transistor TE9 maintains or substantially maintains a turned-off state.

[0233] When the tenth transistor TE10 is turned on, the low voltage of the fourth driving power VSS2 is supplied to the output terminal 204 .

[0234] The fourth clock signal CLK4 is supplied to the third input terminal 203 at a third time point t3. When the fourth clock signal CLK4 is supplied to the third input terminal 203, the fourth transistor TE4 and the seventh transistor TE7 are turned on.

[0235] When the seventh transistor TE7 is turned on, the second capacitor CE2 and the third node NE3 are electrically connected to each other. At this time, the third node NE3 maintains or substantially maintains the high voltage of the third driving power VDD2. In addition, because the fifth transistor TE5 is set to be in the off state when the fourth transistor TE4 is turned on, the voltage of the first node NE1 does not change even if the fourth transistor TE4 is turned on.

[0236] When the fourth clock signal CLK4 is supplied to the third input terminal 203, the voltage of the first node NE1 decreases to a voltage lower than the low voltage of the fourth driving power VSS2 due to coupling of the first capacitor CE1. As described above, when the voltage of the first node NE1 decreases to a voltage lower than the voltage of the fourth driving power VSS2, the driving characteristics of the eighth transistor TE8 and the tenth transistor TE10 can be improved.

[0237] At a fourth time point t4, the second start pulse SP2 is supplied to the first input terminal 201 and the third clock signal CLK3 is supplied to the second input terminal 202. When the third clock signal CLK3 is supplied to the second input terminal 202, the first transistor TE1 and the third transistor TE3 are turned on.

[0238] When the first transistor TE1 is turned on, the first input terminal 201 and the first node NE1 are connected to each other. At this time, because the second start pulse SP2 is supplied to the first input terminal 201, a high voltage is supplied to the first node NE1. When the high voltage is supplied to the first node NE1, the second transistor TE2, the eighth transistor TE8, and the tenth transistor TE10 are turned off.

[0239] When the third transistor TE3 is turned on, the low voltage of the fourth drive power VSS2 is supplied to the second node NE2. At this time, because the fourth transistor TE4 is set to the off state, the first node NE1 maintains or substantially maintains a high voltage. Furthermore, because the seventh transistor TE7 is set to the off state, the voltage of the third node NE3 is maintained or substantially maintains a high voltage via the third capacitor CE3. Consequently, the ninth transistor TE9 remains or substantially remains in the off state.

[0240] The fourth clock signal CLK4 is supplied to the third input terminal 203 at the fifth time point t5. When the fourth clock signal CLK4 is supplied to the third input terminal 203, the fourth transistor TE4 and the seventh transistor TE7 are turned on. In addition, because the voltage of the second node NE2 is set to the low voltage of the fourth driving power VSS2, the fifth transistor TE5 and the sixth transistor TE6 are turned on.

[0241] When the sixth transistor TE6 and the seventh transistor TE7 are turned on, the fourth clock signal CLK4 is supplied to the third node NE3. When the fourth clock signal CLK4 is supplied to the third node NE3, the ninth transistor TE9 is turned on. When the ninth transistor TE9 is turned on, the high voltage of the third drive power VDD2 is supplied to the output terminal 204. The high voltage of the third drive power VDD2 supplied to the output terminal 204 is supplied to the first light emission control line E1 as a light emission control signal.

[0242] When the voltage of the fourth clock signal CLK4 is supplied to the third node NE3, the voltage of the second node NE2 decreases to a voltage lower than the low voltage of the fourth driving power VSS2 due to coupling of the second capacitor CE2, thereby improving the driving characteristics of the transistor connected to the second node NE2.

[0243] When the fourth transistor TE4 and the fifth transistor TE5 are turned on, the high voltage of the third driving power VDD2 is supplied to the first node NE1. As the high voltage of the third driving power VDD2 is supplied to the first node NE1, the tenth transistor TE10 remains or substantially remains in the off state. Therefore, the high voltage of the third driving power VDD2 can be stably supplied to the first light emission control line E1.

[0244] The third clock signal CLK3 is supplied to the second input terminal 202 at the sixth time point t6. In addition, the supply of the second start pulse SP2 is stopped at the sixth time point t6.

[0245] When the third clock signal CLK3 is supplied to the second input terminal 202 , the first transistor TE1 and the third transistor TE3 are turned on.

[0246] When the first transistor TE1 is turned on, the first node NE1 and the first input terminal 201 are electrically connected to each other. Therefore, the voltage of the first node NE1 is set to a low voltage. When the voltage of the first node NE1 is set to a low voltage, the eighth transistor TE8 and the tenth transistor TE10 are turned on.

[0247] When the eighth transistor TE8 is turned on, the high voltage of the third driving power VDD2 is supplied to the third node NE3, and thus the ninth transistor TE9 is turned off. When the tenth transistor TE10 is turned on, the low voltage of the fourth driving power VSS2 is supplied to the output terminal 204. The low voltage of the fourth driving power VSS2 supplied to the output terminal 204 is supplied to the first light emission control line E1, and thus the supply of the light emission control signal is stopped.

[0248] The second light-emission control stage EST2 receives the output signal of the first light-emission control stage EST1 (e.g., the first light-emission control signal supplied to the first light-emission control line E1) in synchronization with the fourth clock signal CLK4. In this case, the second light-emission control stage EST2 outputs the light-emission control signal to the second light-emission control line E2 in synchronization with the third clock signal CLK3. The light-emission control stage EST according to the disclosed embodiment sequentially outputs the light-emission control signal to the light-emission control line E by repeating the above process.

[0249] Figures 11A to 11C Various examples of gate drivers GD according to the disclosed embodiments are shown. For example, Figures 11A to 11C Shown Figures 1A to 2B In the description of the gate driver GD shown in FIG. Figures 11A to 11C In the embodiments, redundant descriptions of configurations and / or components that are identical or substantially identical (eg, or similar) to one or more configurations and / or components in the above-described embodiments may not be repeated.

[0250] Reference Figures 1A to 11A The gate line GL according to the disclosed embodiment may include a scan line S, and the gate driver GD for driving the gate line GL may include a scan driver SD. The scan driver SD includes a scan stage SST for supplying a scan signal to the scan line S.

[0251] According to an embodiment, in addition to the pixels PXL, the scan driver SD may also be provided at the display panel PNL (for example, the scan driver SD may be provided at the display panel PNL together with the pixels PXL) (for example, provided in or provided on the display panel PNL). For example, the scan stage SST is provided at the non-display area NDA of the display panel PNL (for example, provided in or provided on the non-display area NDA of the display panel PNL) to be adjacent to at least one side (for example, the left side and / or the right side) of the display area DA, and may be sequentially arranged along one direction (for example, a column direction, a vertical direction, or a longitudinal direction).

[0252] Reference Figure 11B According to the disclosed embodiment, the gate lines GL may include scan lines S and emission control lines E. The gate driver GD for driving the gate lines GL may include a scan driver SD and an emission control driver ED. The scan driver SD includes a scan stage SST for supplying a scan signal to the scan line S. The emission control driver ED includes an emission control stage EST for supplying an emission control signal to at least one emission control line E. For example, each emission control stage EST may supply an emission control signal to a corresponding emission control line among the emission control lines E, or to one or more corresponding emission control lines among the emission control lines E.

[0253] According to an embodiment, in addition to the scan driver SD and the pixel PXL, the light emission control driver ED may also be provided at the display panel PNL (for example, the light emission control driver ED may be provided at the display panel PNL together with the scan driver SD and the pixel PXL) (for example, provided in or on the display panel PNL). For example, the light emission control stage EST is provided at the non-display area NDA of the display panel PNL (for example, in or on the non-display area NDA) to be adjacent to at least one side (for example, the left side and / or the right side) of the display area DA, and may be sequentially arranged along one direction (for example, a column direction, a vertical direction, or a longitudinal direction).

[0254] In an embodiment, the light emission control stage EST may be disposed adjacent to the scanning stage SST. For example, in addition to the scanning stage SST, the light emission control stage EST may be disposed at any side (e.g., the left or right side) of the display area DA (e.g., the light emission control stage EST may be disposed together with the scanning stage SST at any side of the display area DA), or in addition to the scanning stage SST, the light emission control stage EST may be disposed at both sides (e.g., the left and right sides) of the display area DA (e.g., the light emission control stage EST may be disposed together with the scanning stage SST at both sides of the display area DA).

[0255] In another embodiment, the light emission control stage EST and the scanning stage SST may be disposed on different sides (e.g., the left and right sides, respectively) of the display area DA. For example, the scanning stage SST may be disposed in the non-display area NDA on the left side of the display area DA (e.g., in or on the non-display area NDA), and the light emission control stage EST may be disposed in the non-display area NDA on the right side of the display area DA (e.g., in or on the non-display area NDA).

[0256] In another embodiment, in addition to some of the scanning stages SST, some of the light-emission control stages EST may also be disposed at the non-display area NDA at one side (e.g., the left side) of the display area DA (e.g., some of the light-emission control stages EST may be disposed at the non-display area NDA at one side of the display area DA together with some of the scanning stages SST) (e.g., disposed in or on the non-display area NDA). In addition, in addition to the other remaining scanning stages SST, the other remaining light-emission control stages EST may also be disposed at the non-display area NDA at the other side (e.g., the right side or the opposite side) of the display area DA (e.g., the other remaining light-emission control stages EST may be disposed at the non-display area NDA at the other side of the display area DA together with the other remaining scanning stages SST) (e.g., disposed in or on the non-display area NDA).

[0257] In addition to the above-described embodiments, the structures (eg, arrangement structures) of the scanning stage SST and the light emission control stage EST may be variously modified according to the embodiments.

[0258] In an embodiment, the light emission control driver ED may include light emission control stages EST for concurrently (e.g., simultaneously) supplying light emission control signals to two or more light emission control lines E. For example, the light emission control driver ED may include first light emission control stages EST1 / 2 for concurrently (e.g., simultaneously) supplying light emission control signals to the first light emission control line E1 and the second light emission control line E2, and second light emission control stages EST3 / 4 for concurrently (e.g., simultaneously) supplying light emission control signals to the third light emission control line E3 and the fourth light emission control line E4. In one or more of the above embodiments, each of the light emission control drivers ED may include light emission control stages ESTi / i+1 for concurrently (e.g., simultaneously) supplying light emission control signals to the i-th light emission control line Ei and the i+1-th light emission control line Ei+1.

[0259] Reference Figure 11CAccording to the disclosed embodiment, the gate line GL may include a scan line S and a light emission control line E, and the gate driver GD may include a scan driver SD and a light emission control driver ED. In addition, the scan driver SD and the light emission control driver ED may be disposed to overlap each other.

[0260] For example, each light emission control stage EST may be stacked with at least one scanning stage SST. More specifically, at least one first driver transistor TS included in each scanning stage SST may be provided at a layer different from (e.g., in or on) that of at least one second driver transistor TE included in each light emission control stage EST, and the at least one first driver transistor TS may be stacked with the at least one second driver transistor TE.

[0261] When the scan driver SD and the light emission control driver ED are disposed to overlap each other as described above, the area occupied by the gate driver GD can be reduced. Therefore, even if the gate driver GD is disposed at the display panel PNL (e.g., in or on the display panel PNL), the non-display area NDA of the display panel PNL can be effectively reduced by reducing or minimizing the area occupied by the gate driver GD on the display panel PNL.

[0262] As in one or more of the above-described embodiments, the structure of the gate driver GD may be modified in various ways. For example, the gate driver GD may include at least a scan driver SD and may also include a light emission control driver ED according to an embodiment. Furthermore, the scan driver SD and the light emission control driver ED may or may not overlap with each other.

[0263] 12A to 12D 1 shows a cross-sectional view of a gate driver GD according to an embodiment of the disclosure. For example, 12A to 12D 1 shows a cross-sectional view of a gate driver GD according to at least one of the above-described embodiments. Figure 13 1 shows a cross-sectional view of a gate driver GD according to an embodiment of the disclosure. For example, Figure 13 Shown 12A to 12D A modified embodiment of at least one of the embodiments shown in . FIG. 12A to FIG. 13 In the embodiments, configurations and / or components that are identical or substantially identical (eg, or similar) to each other are denoted by identical or substantially identical reference numerals, and thus, redundant descriptions thereof may be simplified or may not be repeated.

[0264] according to FIG. 12A to FIG. 13The gate driver GD of one or more embodiments of the present invention may have a stacked structure including a plurality of transistors disposed at different layers (e.g., in or on different layers). For example, the gate driver GD may include a first transistor TR1 including a first active layer ACT1 disposed at a first layer (e.g., in or on the first layer) on the base layer BSL (e.g., directly above or on the buffer layer BFL), and a second transistor TR2 including a second active layer ACT2 disposed at a second layer (e.g., in or on the second layer) on the first layer (e.g., directly above or on the second insulating layer INS2).

[0265] For convenience, FIG. 12A to FIG. 13 Each of the figures shows one first transistor TR1 and one second transistor TR2. However, the gate driver GD may include multiple first transistors TR1, each including a first active layer ACT1, and multiple second transistors TR2, each including a second active layer ACT2. For example, the gate driver GD may include multiple first transistors TR1 disposed at a lower layer (e.g., in or on the lower layer) and multiple second transistors TR2 disposed at an upper layer above the first transistors TR1 (e.g., in or on the upper layer). Here, the "lower layer" and "upper layer" relatively define the positions of the first transistors TR1 and the second transistors TR2 based on their respective first active layers ACT1 and ACT2 and first and second gate electrodes.

[0266] Reference Figures 1A to 12A The gate driver GD according to the disclosed embodiment includes a scan driver SD and a light emission control driver ED stacked on each other. For example, the scan driver SD may be disposed above (eg, on) the light emission control driver ED.

[0267] The light emission control driver ED may include a light emission control stage EST including a first transistor TR1, and the scan driver SD may include a scan stage SST including a second transistor TR2. For example, each light emission control stage EST may include a plurality of second driver transistors TE, and each of the second driver transistors TE may be a first transistor TR1 including a first active layer ACT1 (e.g., having a structure identical or substantially identical to that of the first transistor TR1), the first active layer ACT1 being disposed at a first layer (e.g., in or on the first layer) on the base layer BSL. Furthermore, each scan stage SST may include a plurality of first driver transistors TS, and each of the first driver transistors TS may be a second transistor TR2 including a second active layer ACT2 (e.g., having a structure identical or substantially identical to that of the second transistor TR2), the second active layer ACT2 being disposed at a second layer (e.g., in or on the second layer) above (e.g., on) the first layer on the base layer BSL.

[0268] In more detail, according to the disclosed embodiments, the gate driver GD may include a plurality of first transistors TR1 and a plurality of second transistors TR2 disposed at different layers (e.g., in or on different layers) and a plurality of insulating layers. For example, the gate driver GD may include a buffer layer BFL, which may be stacked (e.g., sequentially disposed) on a surface (e.g., one surface) of a base layer BSL; a first active layer ACT1; a first insulating layer INS1; a first gate electrode GAT1; a second insulating layer INS2; a second active layer ACT2; a third insulating layer INS3; a second gate electrode GAT2; a fourth insulating layer INS4; a first source electrode SE1; a first drain electrode DE1; a second source electrode SE2; and a second drain electrode DE2. The gate driver GD may also optionally include at least one conductive pattern CDP.

[0269] According to an embodiment, the first transistor TR1 may include at least a first active layer ACT1 and a first gate electrode GAT1, and may optionally further include a first source electrode SE1 and a first drain electrode DE1 connected to different regions (e.g., respective source and drain regions) of the first active layer ACT1. For example, the first active layer ACT1 and the first gate electrode GAT1 may constitute (or may form) the active layer and gate electrode of the first transistor TR1, respectively. Furthermore, the first source electrode SE1 and the first drain electrode DE1 may constitute (or may form) the source and drain electrodes of the first transistor TR1, respectively.

[0270] However, according to embodiments, the first source electrode SE1 and / or the first drain electrode DE1 may be omitted, and the source electrode and / or the drain electrode of the first transistor TR1 may be integrally configured with the first active layer ACT1 (e.g., the source region and / or the drain region of the first active layer ACT1) (e.g., or may be integrally formed with the first active layer ACT1). In another example, according to embodiments, the first source electrode SE1 and / or the first drain electrode DE1 may be considered as a line (e.g., the first line LI1 and / or the second line LI2), or may be considered as an electrode of another circuit element connected to the first transistor TR1 (e.g., an electrode of at least one other transistor and / or a capacitor).

[0271] According to an embodiment, the second transistor TR2 may include at least a second active layer ACT2 and a second gate electrode GAT2, and may optionally further include a second source electrode SE2 and a second drain electrode DE2 connected to different regions (e.g., respective source and drain regions) of the second active layer ACT2. For example, the second active layer ACT2 and the second gate electrode GAT2 may constitute (or may respectively form) the active layer and the gate electrode of the second transistor TR2, respectively. Furthermore, the second source electrode SE2 and the second drain electrode DE2 may constitute (or may respectively form) the source and drain electrodes of the second transistor TR2, respectively.

[0272] However, according to embodiments, the second source electrode SE2 and / or the second drain electrode DE2 may be omitted, and the source electrode and / or the drain electrode of the second transistor TR2 may be integrally configured with the second active layer ACT2 (e.g., the source region and / or the drain region of the second active layer ACT2) (or may be integrally formed with the second active layer ACT2). In another example, according to embodiments, the second source electrode SE2 and / or the second drain electrode DE2 may be considered as a line (e.g., the third line LI3 and / or the fourth line LI4), or may be considered as an electrode of another circuit element connected to the second transistor TR2 (e.g., an electrode of at least one other transistor and / or a capacitor).

[0273] The buffer layer (BFL) can prevent or reduce the diffusion of impurities into circuit elements (e.g., into each circuit element). The buffer layer (BFL) can be composed of (or include) a single layer, but the disclosure is not limited thereto. The buffer layer (BFL) can be composed of (or include) multiple layers of at least two layers. When the buffer layer (BFL) is provided as a multilayer, each layer can be formed of the same or substantially the same material, or can be formed of different materials.

[0274] The first active layer ACT1 may be disposed on the buffer layer BFL. For example, the first active layer ACT1 may be disposed on a surface (e.g., one surface) of the base layer BSL on which (e.g., on which) the buffer layer BFL is formed. The first active layer ACT1 may include a channel region overlapping the first gate electrode GAT1, and source and drain regions located on respective sides (e.g., opposite sides) of the channel region.

[0275] According to an embodiment, the first active layer ACT1 may include (or may be) a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In addition, the channel region of the first active layer ACT1 may be an intrinsic semiconductor region into which impurities are not doped, and each of the source region and the drain region of the first active layer ACT1 may be a conductive region into which appropriate impurities (e.g., predetermined impurities) are doped.

[0276] In an embodiment, the first active layer ACT1 of the first transistor TR1 (e.g., the second driver transistor TE) constituting each light emission control stage EST (or included in each light emission control stage EST) may be formed of the same or substantially the same (e.g., similar) material. For example, the first active layer ACT1 may be formed of the same or substantially the same material including at least one of polycrystalline silicon, amorphous silicon, and an oxide semiconductor. For example, each (or all) of the first active layers ACT1 may be formed of polycrystalline silicon manufactured by a laser crystallization process. However, the present disclosure is not limited thereto. For example, in another embodiment, at least one first transistor TR1 may include a first active layer ACT1 formed of a material different from the material of the first active layer ACT1 of at least one of the remaining first transistors TR1.

[0277] In addition, in an embodiment, when the first transistor TR1 overlaps with at least one second transistor TR2, the first active layer ACT1 of the first transistor TR1 may overlap with the second active layer ACT2 of the at least one second transistor TR2. Therefore, the area of the gate driver GD can be reduced or minimized by densely arranging circuit elements constituting the gate driver GD (or included in the gate driver GD) at the non-display area NDA (e.g., in or on the non-display area NDA).

[0278] The first insulating layer INS1 may be disposed on the first active layer ACT1 to cover the first active layer ACT1. For example, the first insulating layer INS1 may include (or may be) a first gate insulating layer disposed between each first active layer ACT1 and each first gate electrode GAT1. The first insulating layer INS1 may be composed of (or may include) a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the first insulating layer INS1 may include various suitable types of organic / inorganic insulating materials known to those skilled in the art, such as silicon nitride (SiN). x ), silicon oxide (SiO x However, the structure and / or constituent material of the first insulating layer INS1 are not limited thereto.

[0279] The first gate electrode GAT1 may be disposed so as to overlap the first active layer ACT1, with the first insulating layer INS1 interposed therebetween. For example, the first gate electrode GAT1 may be disposed on the first insulating layer INS1 so as to overlap a certain region (e.g., the channel region) of the first active layer ACT1. The first gate electrode GAT1 may be composed of (or may include) a single layer or multiple layers, and may have conductivity by including at least one conductive material.

[0280] The second insulating layer INS2 may be disposed between the first transistor TR1 (e.g., multiple first transistors TR1) and the second transistor TR2 (e.g., multiple second transistors TR2). For example, the second insulating layer INS2 may be disposed on the first gate electrode GAT1 to cover the first active layer ACT1 and the first gate electrode GAT1. The second insulating layer INS2 may be composed of (or may include) a single layer or multiple layers. For example, the second insulating layer INS2 may be composed of (or may include) multiple layers including a lower insulating layer INS2_1 disposed on (e.g., directly on) the first gate electrode GAT1 and an upper insulating layer INS2_2 disposed on the lower insulating layer INS2_1.

[0281] In addition, the second insulating layer INS2 may include at least one inorganic insulating material and / or organic insulating material. For example, each of the lower insulating layer INS2_1 and the upper insulating layer INS2_2 of the second insulating layer INS2 may include various suitable types of organic / inorganic materials known to those skilled in the art, such as silicon nitride (SiN x ), silicon oxide (SiO x However, the structure and / or constituent material of the second insulating layer INS2 is not limited thereto.

[0282] In an embodiment, after forming the second insulating layer INS2, a process for planarizing the surface of the second insulating layer INS2 may be further performed by a chemical mechanical polishing process, etc. For example, after forming the lower insulating layer INS2_1 and / or the upper insulating layer INS2_2 of the second insulating layer INS2, a planarization process such as a chemical mechanical polishing process may be performed.

[0283] In addition, according to an embodiment, when the second insulating layer INS2 is formed of a multilayer including a lower insulating layer INS2_1 and an upper insulating layer INS2_2, at least one conductive pattern CDP may be further formed between the lower insulating layer INS2_1 and the upper insulating layer INS2_2. For example, at least one conductive pattern CDP may be formed between the lower insulating layer INS2_1 and the upper insulating layer INS2_2 of the second insulating layer INS2 to overlap or not overlap with at least one first transistor TR1 and / or the second transistor TR2.

[0284] In an embodiment, the conductive pattern CDP may be disposed to overlap with at least one first transistor TR1 or at least one second transistor TR2 to constitute (or form) a light-blocking pattern or an electrode (e.g., a back gate electrode) of at least one first transistor TR1 or at least one second transistor TR2. In another embodiment, the conductive pattern CDP may constitute an electrode (e.g., one electrode) of at least one first driver capacitor CS or second driver capacitor CE.

[0285] The second active layer ACT2 may be disposed on the second insulating layer INS2 . The second active layer ACT2 may include a channel region overlapping the second gate electrode GAT2 , and source and drain regions at respective sides (eg, opposite sides) of the channel region.

[0286] According to an embodiment, the second active layer ACT2 may include (or may be) a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In addition, the channel region of the second active layer ACT2 may be an intrinsic semiconductor region into which impurities are not doped, and each of the source region and the drain region of the second active layer ACT2 may be a conductive region into which appropriate impurities (e.g., predetermined impurities) are doped.

[0287] In an embodiment, the second active layer ACT2 of the second transistor TR2 (e.g., the first driver transistor TS) constituting each scanning stage SST (e.g., included in each scanning stage SST) may be formed from the same or substantially the same (e.g., similar) material as one another. For example, the second active layer ACT2 may be formed from the same or substantially the same material including at least one of polycrystalline silicon, amorphous silicon, and an oxide semiconductor. For example, each (or all) of the second active layers ACT2 may be formed from polycrystalline silicon manufactured by a laser crystallization process. However, the present disclosure is not limited thereto. For example, in another embodiment, at least one second transistor TR2 may include a second active layer ACT2 formed from a material different from the material of the second active layer ACT2 of at least one of the remaining second transistors TR2.

[0288] The third insulating layer INS3 may be disposed on the second active layer ACT2 to cover the second active layer ACT2. For example, the third insulating layer INS3 may include (or may be) a second gate insulating layer disposed between each second active layer ACT2 and each second gate electrode GAT2. The third insulating layer INS3 may be composed of (or may include) a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the third insulating layer INS3 may include various suitable organic / inorganic insulating materials known to those skilled in the art, such as silicon nitride (SiN). x ), silicon oxide (SiO x However, the structure and / or constituent material of the third insulating layer INS3 is not limited thereto.

[0289] The second gate electrode GAT2 may be disposed so as to overlap the second active layer ACT2, with the third insulating layer INS3 interposed therebetween. For example, the second gate electrode GAT2 may be disposed on the third insulating layer INS3 so as to overlap a certain region (e.g., the channel region) of the second active layer ACT2. The second gate electrode GAT2 may be composed of (or may include) a single layer or multiple layers, and may include at least one conductive material to provide electrical conductivity.

[0290] The fourth insulating layer INS4 may be provided on the second gate electrode GAT2 to cover the second active layer ACT2 and the second gate electrode GAT2 of the second transistor TR2 (e.g., the plurality of second transistors TR2). The fourth insulating layer INS4 may be composed of a single layer or multiple layers (or may include a single layer or multiple layers) and may include at least one inorganic insulating material and / or an organic insulating material. For example, the fourth insulating layer INS4 may include various suitable types of organic / inorganic insulating materials known to those skilled in the art, such as silicon nitride (SiN x ), silicon oxide (SiO x ) etc. However, the structure and / or constituent materials of the fourth insulating layer INS4 are not limited thereto. In an embodiment, after forming the fourth insulating layer INS4, a process of planarizing the surface of the fourth insulating layer INS4 may be further performed by a chemical mechanical polishing process etc.

[0291] The first and second source electrodes SE1 and SE2 and the first and second drain electrodes DE1 and DE2 may be spaced apart from each other on the fourth insulating layer INS4. The first and second source electrodes SE1 and SE2 and the first and second drain electrodes DE1 and DE2 are connected to corresponding regions of the active layers (the first and second active layers ACT1 and ACT2).

[0292] The first source electrode SE1 may be disposed on the first active layer ACT1, with the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4 interposed therebetween. The first source electrode SE1 may be connected to a region (e.g., a source region) of the first active layer ACT1 via at least one contact hole extending through (e.g., traversing) the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4. However, the disclosure is not limited thereto. According to embodiments, the first source electrode SE1 may not be formed separately from the first active layer ACT1, but may be integrally formed therewith. For example, in another disclosed embodiment, the source region of at least one first active layer ACT1 may be directly connected to an electrode of another circuit element (e.g., another transistor and / or another capacitor), or to a desired or predetermined line (e.g., first line LI1).

[0293] A first drain electrode DE1 may be disposed on the first active layer ACT1, with a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and a fourth insulating layer INS4 interposed therebetween. The first drain electrode DE1 may be connected to another region (e.g., a drain region) of the first active layer ACT1 via at least one contact hole extending through (e.g., traversing) the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3, and the fourth insulating layer INS4. However, the disclosure is not limited thereto. According to embodiments, the first drain electrode DE1 may not be formed separately from the first active layer ACT1, but may be integrally formed therewith. For example, in another disclosed embodiment, the drain region of at least one first active layer ACT1 may be directly connected to an electrode of another circuit element (e.g., another transistor and / or another capacitor), or to a desired or predetermined line (e.g., the second line LI2).

[0294] The second source electrode SE2 may be disposed on the second active layer ACT2, with the third insulating layer INS3 and the fourth insulating layer INS4 interposed therebetween. The second source electrode SE2 may be connected to a region (e.g., a source region) of the second active layer ACT2 via at least one contact hole extending through (e.g., traversing) the third insulating layer INS3 and the fourth insulating layer INS4. However, the disclosure is not limited thereto. According to embodiments, the second source electrode SE2 may not be formed separately from the second active layer ACT2, but may be integrally formed therewith. For example, in another disclosed embodiment, the source region of at least one second active layer ACT2 may be directly connected to an electrode of another circuit element (e.g., another transistor and / or another capacitor), or to a desired or predetermined line (e.g., the third line LI3).

[0295] The second drain electrode DE2 may be disposed on the second active layer ACT2, with the third insulating layer INS3 and the fourth insulating layer INS4 interposed therebetween. The second drain electrode DE2 may be connected to another region (e.g., a drain region) of the second active layer ACT2 via at least one contact hole extending through (e.g., traversing) the third insulating layer INS3 and the fourth insulating layer INS4. However, the disclosure is not limited thereto. According to embodiments, the second drain electrode DE2 may not be formed separately from the second active layer ACT2, but may be integrally formed with the second active layer ACT2. For example, in another disclosed embodiment, the drain region of at least one second active layer ACT2 may be directly connected to an electrode of another circuit element (e.g., another transistor and / or another capacitor), or to a desired or predetermined line (e.g., the fourth line LI4).

[0296] Reference Figures 1A to 12B According to the disclosed embodiment, the gate driver GD includes a scan driver SD and a light emission control driver ED stacked on each other, and the light emission control driver ED may be disposed above (e.g., on) the scan driver SD. For example, the scan driver SD may include a scan stage SST including a first transistor TR1, and the light emission control driver ED may include a light emission control stage EST including a second transistor TR2.

[0297] For example, each scanning stage SST may include a plurality of first driver transistors TS, each of which may be a first transistor TR1 (e.g., may have a structure identical or substantially identical to that of the first transistor TR1), and the first transistor TR1 may include a first active layer ACT1 disposed at a first layer (e.g., in or on the first layer) on the base layer BSL. Furthermore, each emission control stage EST may include a plurality of second driver transistors TE, each of which may be a second transistor TR2 (e.g., may have a structure identical or substantially identical to that of the second transistor TR2), and the second transistor TR2 may include a second active layer ACT2 disposed at a second layer (e.g., in or on the second layer) above the first layer (e.g., on the first layer) on the base layer BSL.

[0298] exist Figure 12A and Figure 12B In an embodiment, the gate driver GD may include a first transistor TR1 and a second transistor TR2 disposed so as to overlap each other. Furthermore, one of the first transistor TR1 and the second transistor TR2 may be one of the first driver transistor TS of the scan driver SD and the second driver transistor TE of the emission control driver ED, and the other of the first transistor TR1 and the second transistor TR2 may be the other of the first driver transistor TS and the second driver transistor TE. In other words, according to an embodiment, the scan driver SD and the emission control driver ED may be divided and disposed at different layers (e.g., in or on different layers) in the gate driver GD.

[0299] According to an embodiment, the first transistor TR1 and the second transistor TR2 may have different characteristics. For example, the first transistor TR1 and the second transistor TR2 may have different threshold voltages.

[0300] In embodiments, each of the first transistor TR1 and the second transistor TR2 may be formed as a P-type transistor, and the threshold voltage of the first transistor TR1 may be greater than the threshold voltage of the second transistor TR2. For example, after crystallizing the first active layer ACT1 to have a threshold voltage having a desired value or a desired range (e.g., a predetermined value or a predetermined range), a positive shift may occur, increasing the threshold voltage of the first active layer ACT1, due to one or more subsequent processes such as forming and crystallizing the second active layer ACT2 on the first active layer ACT1. Therefore, according to the disclosed embodiments, the stacked structure of the gate driver GD may be designed taking into account the characteristic differences between the first transistor TR1 and the second transistor TR2.

[0301] For example, each of the first driver transistor TS constituting each scanning stage SST and the second driver transistor TE constituting each emission control stage EST can be tested for operational characteristics in response to changes in threshold voltage, and the positions of the first and second driver transistors TS and TE in each layer can be determined based on (e.g., based on or dependent on) the test results. For example, assuming the test results indicate that the first driver transistor TS exhibits superior (e.g., better) operational characteristics than the second driver transistor TE for negative excursions corresponding to a threshold voltage drop, and the second driver transistor TE exhibits superior (e.g., better) operational characteristics than the first driver transistor TS for positive excursions corresponding to an increase in threshold voltage. In this case, the second driver transistor TE can be formed in a lower layer (e.g., in or on the lower layer) as a first transistor (e.g., as each first transistor) TR1, and the first driver transistor TS can be formed in an upper layer (e.g., in or on the upper layer) as a second transistor (e.g., as each second transistor) TR2.

[0302] On the other hand, when the second driver transistor TE exhibits improved (e.g., better) operating characteristics for a negative shift of the threshold voltage, and the first driver transistor TS exhibits improved (e.g., better) operating characteristics for a positive shift of the threshold voltage, the first driver transistor TS can be formed at a lower layer (e.g., formed in or formed on the lower layer) as a first transistor (e.g., as each first transistor) TR1, and the second driver transistor TE can be formed at an upper layer (e.g., formed in or formed on the upper layer) as a second transistor (e.g., as each second transistor) TR2.

[0303] In addition, taking various factors into consideration, the first driver transistor TS and the second driver transistor TE may be divided and provided at different layers from each other (e.g., in different layers from each other or on different layers from each other). As described above, when the first driver transistor TS and the second driver transistor TE are provided at different layers from each other (e.g., in different layers from each other or on different layers from each other), the characteristics of the first driver transistor TS and the characteristics of the second driver transistor TE may be independently controlled.

[0304] Reference Figures 1A to 12C The gate driver GD according to the disclosed embodiment may include at least a scan driver SD, and may be formed as a stack of first transistors TR1 having a first active layer ACT1 at a first layer (e.g., in or on the first layer) and second transistors TR2 having a second active layer ACT2 at a second layer (e.g., in or on the second layer). For example, some of the first driver transistors TS constituting each scan stage SST (e.g., included in each scan stage SST) may be formed at a lower layer (e.g., in or on the lower layer) as first transistors (e.g., as each first transistor) TR1, and other first driver transistors TS may be provided at an upper layer (e.g., in or on the upper layer) as second transistors (e.g., as each second transistor) TR2.

[0305] For example, in the composition Figure 6 The scanning level SST (for example, included in Figure 6 Among the first driver transistors TS of the scanning stage SST of the scanning driver SD, the transistors of the output unit 130 (for example, the seventh transistor TS7 and the eighth transistor TS8 of the scanning stage SST) for ensuring a high on-current and occupying a relatively large area can be formed as the first transistor TR1 of the lower layer. In addition, among the first driver transistors TS, at least some of the transistors of the input unit 110 and the controller 120 (for example, the first transistor TS1 to the sixth transistor TS6 of the scanning stage SST) for ensuring stable threshold voltage characteristics to prevent or substantially prevent malfunction of the scan driver SD can be formed as the second transistor TR2 of the upper layer.

[0306] For example, each scanning stage SST may include an input unit 110 including some of the first driver transistors TS among the second transistors TR2, a controller 120 including the other first driver transistors TS among the second transistors TR2, and an output unit 130 including the first transistors TR1. Each of the first driver capacitors CS may include at least one electrode provided at the same or substantially the same layer as (in or on the same or substantially the same layer as) some of the electrodes of the first transistors TR1 and the second transistors TR2.

[0307] Reference Figures 1A to 12D According to the disclosed embodiments, the gate driver GD may include at least a light emission control driver ED, and may be formed as a stack of first transistors TR1 having a first active layer ACT1 at a first layer (e.g., in or on the first layer) and second transistors TR2 having a second active layer ACT2 at a second layer (e.g., in or on the second layer). For example, some of the second driver transistors TE constituting each light emission control stage EST (e.g., included in each light emission control stage EST) may be formed at a lower layer (e.g., in or on the lower layer) as first transistors (e.g., as each first transistor) TR1, while the other second driver transistors TE may be provided at an upper layer (e.g., in or on the upper layer) as second transistors (e.g., as each second transistor) TR2.

[0308] For example, in the composition Figure 9 The light emission control level EST (for example, included in Figure 9 Among the second driver transistors TE of the light emission control stage EST, the transistors of the output unit 240 (for example, the ninth transistor TE9 and the tenth transistor TE10 of the light emission control stage EST) for ensuring a high on-current and occupying a relatively large area can be formed as the first transistor TR1 of the lower layer. In addition, among the second driver transistors TE, at least some of the transistors of the input unit 210, the first controller 220, and the second controller 230 (for example, the first transistor TE1 to the eighth transistor TE8 of the light emission control stage EST) for ensuring stable threshold voltage characteristics and preventing or substantially preventing malfunction of the light emission control driver ED can be formed as the second transistor TR2 of the upper layer.

[0309] For example, each light emission control stage EST may include an input unit 210 including some of the second driver transistors TE among the second transistors TR2, a first control unit 220, a second control unit 230, and an output unit 240. The input unit 210 includes some of the second driver transistors TE among the second transistors TR2, the first control unit 220 includes other of the second driver transistors TE among the second transistors TR2, the second control unit 230 includes still other of the second driver transistors TE among the second transistors TR2 that are not included in the input unit 210 and the first control unit 220, and the output unit 240 includes the first transistor TR1. Each of the second driver capacitors CE may include at least one electrode provided at the same or substantially the same layer as (in or on the same or substantially the same layer as) some of the electrodes of the first transistor TR1 and the second transistor TR2.

[0310] exist Figure 12C and Figure 12D In an embodiment, each of the scan driver SD and the light emission control driver ED may include a first transistor TR1 and a second transistor TR2 that are divided and disposed at different layers (e.g., in or on different layers). For example, considering the characteristics of each of the first driver transistors TS, the first driver transistor TS may be divided and disposed at lower and upper layers (e.g., in or on the lower and upper layers). Similarly, considering the characteristics of each of the second driver transistors TE, the second driver transistor TE may be divided and disposed at lower and upper layers (e.g., in or on the lower and upper layers).

[0311] Reference Figures 1A to 13 According to the disclosed embodiments, at least one of the first and second source electrodes SE1 and SE2 and the first and second drain electrodes DE1 and DE2 can be connected to the active layer or layers (e.g., the first active layer ACT1 and / or the second active layer ACT2) via a multi-level contact structure formed by at least one bridge pattern. For example, the first source electrode SE1 can be connected to the source region of the first active layer ACT1 via the first and second bridge patterns BRP1 and BRP2, and the first drain electrode DE1 can be connected to the drain region of the first active layer ACT1 via the third and fourth bridge patterns BRP3 and BRP4. In this case, even if the distance between the first source electrode SE1 and the first drain electrode DE1 and the first active layer ACT1 increases, the first source electrode SE1 and the first drain electrode DE1 can maintain stable connection to the first active layer ACT1.

[0312] In an embodiment, each bridge pattern may be provided at the same or substantially the same layer as any one of the first gate electrode GAT1, the second gate electrode GAT2, and the conductive pattern CDP (e.g., in the same or substantially the same layer or on the same or substantially the same layer). For example, the first bridge pattern BRP1 and the third bridge pattern BRP3 may be provided at the same or substantially the same layer as the conductive pattern CDP (e.g., in the same or substantially the same layer or on the same or substantially the same layer), and the second bridge pattern BRP2 and the fourth bridge pattern BRP4 may be provided at the same or substantially the same layer as the second gate electrode GAT2 (e.g., in the same or substantially the same layer or on the same or substantially the same layer). In this case, the bridge patterns can be formed (e.g., easily formed) within the gate driver GD without increasing the number of conductive layers constituting (or included in) the gate driver GD.

[0313] According to one or more of the above embodiments, considering the characteristics of each transistor constituting the gate driver GD (or included in the gate driver GD), the transistors constituting the gate driver GD (or included in the gate driver GD) can be divided into at least two groups and can be arranged at different layers (for example, in different layers or on different layers). Therefore, while constituting (or forming) a high-density gate driver GD with a reduced area, the operating characteristics of the gate driver GD can be improved or ensured.

[0314] Figure 14 A method for manufacturing a display device according to an embodiment of the disclosure is shown. For example, Figure 14 An embodiment of a method of crystallizing the first active layer ACT1 and the second active layer ACT2 of the stacked gate driver GD according to one or more of the above-described embodiments is shown. For convenience, Figure 14 A diagram is shown that can emphasize the characteristics of the method for controlling the crystallization conditions of the first active layer ACT1 and the second active layer ACT2, thereby Figure 14 The cross-sectional structure of the crystallization process is schematically shown in more detail in FIG.

[0315] Reference Figures 1A to 14The first active layer ACT1 and the second active layer ACT2 are disposed at different layers (e.g., in or on different layers). In this case, the first active layer ACT1 and the second active layer ACT2 can be crystallized under different conditions. For example, a display device according to a disclosed embodiment may include a gate driver GD including a first transistor TR1 and a second transistor TR2 disposed at different layers (e.g., in or on different layers). Furthermore, a method of manufacturing a display device may include forming a first active layer ACT1 for the first transistor TR1 on a base layer BSL and forming a second active layer ACT2 for the second transistor TR2 on the first active layer ACT1. The first active layer ACT1 and the second active layer ACT2 can be crystallized under different conditions. For example, when crystallizing the first active layer ACT1 and the second active layer ACT2 using a laser emitting device LID, the pitches of the lasers emitted into the first active layer ACT1 and the second active layer ACT2 can be set to be different.

[0316] According to an embodiment, crystallizing the first active layer ACT1 may include crystallizing the first active layer ACT1 by emitting a laser beam at a first pitch pt1 after forming the first active layer ACT1 on a surface of the base layer BSL on which the buffer layer BFL is formed. Crystallizing the first active layer ACT1 may be performed before forming the second active layer ACT2. In other words, the first and second active layers ACT1 and ACT2 may be sequentially crystallized in different processes.

[0317] According to an embodiment, the step of crystallizing the second active layer ACT2 may include: after forming the second active layer ACT2 on a surface of the base layer BSL on which the buffer layer BFL, the first active layer ACT1, the first insulating layer INS1, the first gate electrode GAT1, and the second insulating layer INS2 are sequentially formed, crystallizing the second active layer ACT2 by emitting laser light at a second pitch pt2. In addition, during the step of crystallizing the second active layer ACT2, the laser light may be additionally emitted to at least one region of the crystallized (e.g., previously crystallized) first active layer ACT1.

[0318] According to embodiments, the first active layer ACT1 and the second active layer ACT2 are sequentially formed and crystallized, and even after the crystallization process (e.g., the crystallization process of the first active layer ACT1 and / or the second active layer ACT2) is completed, some characteristics of the first active layer ACT1 may change due to subsequent processes. For example, the threshold voltage of the first active layer ACT1 may change (shift) due to the influence of the subsequent processes.

[0319] In an embodiment, considering the threshold voltage shift of the first active layer ACT1, a transistor that is relatively robust to threshold voltage shift may be provided at a lower layer (e.g., in or on the lower layer) as the first transistor TR1. For example, a buffer transistor provided at (e.g., in or on the output unit 130 of the scanning stage SST) (e.g., the seventh transistor TS7 and the eighth transistor TS8 of the scanning stage SST) may be provided at a lower layer (e.g., in or on the lower layer) as the first transistor TR1. In another example, a buffer transistor provided at (e.g., in or on the output unit 240 of the emission control stage EST) (e.g., the ninth transistor TE9 and the tenth transistor TE10 of the emission control stage EST) may be provided at a lower layer (e.g., in or on the lower layer) as the first transistor TR1.

[0320] In these cases, considering the characteristics used (or desired) by each of the first and second transistors TR1 and TR2, the first pitch pt1 of the laser light used to crystallize the first active layer ACT1 may be greater than the second pitch pt2 of the laser light used to crystallize the second active layer ACT2. In one embodiment, the first pitch pt1 may be approximately 20.3 μm, and the second pitch pt2 may be less than 20.3 μm, but the pitch of the laser light emitted during the crystallization process is not limited thereto. In another embodiment, considering the characteristics used (or desired) by each of the first and second transistors TR1 and TR2, the second pitch pt2 of the laser light used to crystallize the second active layer ACT2 may be greater than the first pitch pt1 of the laser light used to crystallize the first active layer ACT1. In one embodiment, the first pitch pt1 may be approximately 20.3 μm, and the second pitch pt2 may be greater than 20.3 μm, but the pitch of the laser light emitted during the crystallization process is not limited thereto.

[0321] Therefore, each first active layer ACT1 may have characteristics different from those of each second active layer ACT2. For example, the first active layer ACT1 may have a lower crystallinity than that of the second active layer ACT2.

[0322] However, the disclosure is not limited thereto. For example, as will be understood by those skilled in the art, the crystallization conditions of the first active layer ACT1 and the second active layer ACT2 and / or the crystallinity of the first active layer ACT1 and the second active layer ACT2 according to the crystallization conditions may be variously modified according to the characteristics used (or desired) in each of the first transistor TR1 and the second transistor TR2.

[0323] According to the above-described embodiment, the time used (e.g., or required) for the crystallization process of at least some of the active layers (e.g., the first active layer ACT1) can be shortened while improving or ensuring the operational characteristics of the gate driver GD. Therefore, the tact time of the display device can be reduced, and its manufacturing efficiency can be improved.

[0324] In addition, when the first transistor (e.g., each first transistor) TR1 has a relatively large area compared to the second transistor (e.g., each second transistor) TR2, the second transistor (e.g., at least one second transistor) TR2 may be formed at a region that completely overlaps (e.g., in or on a region that completely overlaps) the first transistor (e.g., any suitable one of the first transistors TR1) TR1. In this case, disconnection (e.g., disconnection between the electrode of the second transistor TR2 and the second active layer ACT2) may be prevented or substantially prevented by reducing or minimizing the step difference of the at least one second active layer ACT2.

[0325] According to one or more of the above embodiments, the crystallization conditions of the first active layer ACT1 and the second active layer ACT2 can be controlled independently of each other for each layer, taking into account the characteristics used (or desired) for each transistor constituting the gate driver GD (e.g., included in the gate driver GD). Therefore, the manufacturing efficiency of the gate driver GD can be increased while improving or ensuring the operating characteristics of the gate driver GD.

[0326] Figure 15 A method for manufacturing a display device according to an embodiment of the disclosure is shown. For example, Figure 15 An embodiment of a method of crystallizing an active layer of a display area DA and a non-display area NDA located at (e.g., in or on) a display panel PNL is shown. The display panel PNL includes pixels PXL and a gate driver GD at (e.g., in or on) the display area DA and the non-display area NDA, respectively. For convenience, Figure 15 A diagram is shown that can highlight the characteristics of the method for controlling the crystallization conditions of the active layer, thus Figure 15 The cross-sectional structure of the crystallization process is schematically shown in more detail in FIG.

[0327] Reference Figures 1A to 15The gate driver GD may include a first transistor TR1 and / or a second transistor TR2. The first transistor TR1 and / or the second transistor TR2 include a first active layer ACT1 and / or a second active layer ACT2 disposed at (e.g., in or on) a suitable layer (e.g., a predetermined layer) on the base layer BSL. The first active layer ACT1 and / or the second active layer ACT2 may be formed in (e.g., in or on) the embedded circuit region (e.g., the gate driver region) of the non-display area NDA.

[0328] In addition, each pixel PXL may include one or more pixel transistors TP (or TP' or TP"), each of which includes a corresponding third active layer ACT3. The third active layer ACT3 is provided at a suitable layer (e.g., a predetermined layer) on the base layer BSL (e.g., an upper portion of the buffer layer BFL) (e.g., in or on a suitable layer). The third active layer ACT3 of each of the pixels PXL may be formed at the display area DA (e.g., at each pixel area) (e.g., formed in or on the display area DA).

[0329] According to embodiments, the first active layer ACT1 and / or the second active layer ACT2 of the non-display area NDA and the third active layer ACT3 of the display area DA may be crystallized under conditions different from each other. For example, a method of manufacturing a display device according to a disclosed embodiment may include: forming first and second transistors TR1 and TR2, respectively, including the first and second active layers ACT1 and ACT2, in the non-display area NDA (e.g., in or on the non-display area NDA); and forming a pixel transistor TP (or TP' or TP'') including the corresponding third active layer ACT3 in the display area DA (e.g., in or on the display area DA). Furthermore, during the steps of manufacturing the display device, the third active layer ACT3 may be crystallized under conditions different from those of at least one of the first and second active layers ACT1 and ACT2.

[0330] In an embodiment, a more stable threshold voltage characteristic may be used (or desired) for the first transistor TR1 and / or the second transistor TR2 constituting (e.g., or included in) the gate driver GD, compared to the threshold voltage characteristic of the pixel transistor TP (or TP' or TP''). For example, each pixel PXL may be configured to have a threshold voltage characteristic similar to that of the pixel transistor TP (or TP' or TP''). Figure 3BThe structure of the pixel PXL shown in the embodiment of FIG. 1 is the same as or substantially the same as that of the pixel PXL, and characteristic variations of the pixel PXL can be compensated for using an external compensation method. In this case, even if threshold voltage variations (or threshold voltage variations) may occur between the driving transistors of the pixel PXL, the pixel PXL can emit light with uniform or substantially uniform brightness corresponding to each data signal by converting image data, thereby compensating for the threshold voltage variations (or threshold voltage variations).

[0331] In this case, when crystallizing at least one of the first and second active layers ACT1 and ACT2, laser light may be densely emitted to the at least one active layer at a relatively small first pitch pt1′ (e.g., approximately 20.3 μm), and when crystallizing the third active layer ACT3, laser light may be emitted to the third active layer at a second pitch pt2′ greater than the first pitch pt1′ (e.g., a pitch greater than 20.3 μm). Therefore, the third active layer (e.g., each third active layer) ACT3 may have a lower crystallinity than that of the at least one of the first and second active layers ACT1 and ACT2.

[0332] For example, the crystallization conditions of the first active layer ACT1 and / or the second active layer ACT2 and the third active layer ACT3 may be variously modified according to one or more transistor characteristics used (or desired) by the gate driver GD and the pixel PXL, respectively.

[0333] In addition, according to embodiments, the pixel transistors TP (or TP' or TP") may be formed to have a stacked structure. For example, some of the plurality of pixel transistors TP (or TP' or TP") constituting each pixel PXL (e.g., included in each pixel PXL) may be disposed at a lower layer (e.g., in or on a lower layer) to include a corresponding active layer disposed at the same or substantially the same layer as the first active layer ACT1 (e.g., in the same or substantially the same layer as the first active layer ACT1 or on the same or substantially the same layer as the first active layer ACT1), and other pixel transistors TP (or TP' or TP") may be disposed at an upper layer to include a corresponding active layer disposed at the same or substantially the same layer as the second active layer ACT2 (e.g., in the same or substantially the same layer as the second active layer ACT2 or on the same or substantially the same layer as the second active layer ACT2).

[0334] According to one or more of the above-described embodiments, the crystallization conditions of the active layers (e.g., the first active layer ACT1 and / or the second active layer ACT2 and the third active layer ACT3) formed on the display panel PNL can be independently controlled for each region, taking into account the desired (or desired) characteristics of the transistors included in the gate driver GD and the pixels PXL and / or the manufacturing efficiency of the display device. Consequently, the crystallization process time for the active layers can be shortened while improving or ensuring the desired (or desired) operating characteristics of each of the gate driver GD and the pixels PXL. For example, when crystallizing the third active layer ACT3 of the display area DA, the crystallization process time for the third active layer ACT3 can be shortened by emitting laser light at a larger pitch. Consequently, the takt time of the display device can be reduced, and its manufacturing efficiency can be improved. For example, as the display device is scaled up, the time required to crystallize the third active layer ACT3 of the pixel transistor TP (or TP' or TP'') in the display area DA can be reduced (e.g., significantly shortened) by using one or more of the above-described methods.

[0335] According to the display devices and methods of manufacturing the same according to the various disclosed embodiments described above, the first transistors TR1 and second transistors TR2 that constitute the gate driver GD (e.g., included in the gate driver GD) are divided and disposed at different layers (e.g., in or on different layers). This improves space utilization efficiency and allows for a high-density stacking of the gate drivers GD. Consequently, even if the gate driver GD is disposed at the display panel PNL (e.g., in or on the display panel PNL), the area occupied by the gate driver GD can be reduced, effectively reducing the non-display area NDA of the display panel PNL.

[0336] Furthermore, according to the display device and method of manufacturing the display device according to various disclosed embodiments, each of the first and second transistors TR1 and TR2 can be constructed by dividing the transistors of the gate driver GD into different layers, taking into account the characteristics used (or desired) by each of the transistors (e.g., the first driver transistor TS and / or the second driver transistor TE) that constitute (e.g., are included in) the gate driver GD. Furthermore, by providing the active layers of the first and second transistors TR1 and TR2 (e.g., the first and second active layers ACT1 and ACT2, respectively) at different layers (e.g., in or on different layers), the crystallization conditions of the first and second active layers ACT1 and ACT2 can be controlled for each layer. Therefore, while forming the first and second transistors TR1 and TR2 to meet the characteristics used (or desired) by the gate driver GD, the manufacturing efficiency of the display device can be improved.

[0337] Furthermore, according to the display device and method of manufacturing the same according to the disclosed embodiments, the active layer can be crystallized under different conditions for each region of the display panel PNL, taking into account the characteristics used (or desired) for each of the first and second transistors TR1 and TR2 that constitute (or are included in) the gate driver GD, and the pixel transistor TP (or TP' or TP''). For example, the active layer (e.g., the third active layer ACT3) of the pixel transistor TP (or TP' or TP'') can be crystallized under conditions that differ from those of at least one of the active layers of the first and second transistors TR1 and TR2 (e.g., the first active layer ACT1 and / or the second active layer ACT2). Consequently, the manufacturing efficiency of the display device can be improved while improving or securing the operational characteristics of the display device.

[0338] Although one or more example embodiments of the present invention have been described with reference to the drawings, it should be understood that the example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Therefore, it will be understood by those skilled in the art that various modifications in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the claims and their equivalents.

Claims

1. A display device, comprising: a plurality of pixels connected to gate lines and data lines; a gate driver, configured to supply a gate signal to the gate line; as well as a data driver for supplying a data signal to the data line; The gate driver includes: a first transistor including a first active layer located at a first layer and a first source electrode and a first drain electrode provided on the first active layer; a second transistor including a second active layer located at a second layer on the first layer and a second source electrode and a second drain electrode provided on the second active layer; and an insulating layer located on the second layer to cover the second active layer. wherein the first active layer and the second active layer are stacked on each other, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are spaced apart from each other on the insulating layer, and the first source electrode and the first drain electrode penetrate the insulating layer to be connected to a region of the first active layer that does not overlap with the second active layer, and wherein the first source electrode is connected to the 1-1 active region of the first active layer, the first drain electrode is connected to the 1-2 active region of the first active layer, the second source electrode is connected to the 2-1 active region of the second active layer, and the second drain electrode is connected to the 2-2 active region of the second active layer, and The 1-1 active region, the 1-2 active region, the 2-1 active region, and the 2-2 active region do not overlap with each other in a plan view.

2. The display device according to claim 1, wherein: The gate lines include scan lines and light emitting control lines; and The gate driver includes: a scan driver for supplying a scan signal to the scan line; and a light emission control driver for supplying a light emission control signal to the light emission control line.

3. The display device according to claim 2, wherein: The scan driver includes a scan stage including the second transistor; and The light emission control driver includes a light emission control stage including the first transistor.

4. The display device according to claim 2, wherein: The scan driver includes a scan stage including the first transistor; and The light emission control driver includes a light emission control stage including the second transistor.

5. The display device according to claim 1, wherein: The gate lines include scan lines; The gate driver includes a scanning stage for sequentially supplying scanning signals to the scanning lines; and Each of the scanning stages includes an input circuit including the second transistor; and an output circuit including the first transistor.

6. The display device according to claim 1, wherein: The gate lines include light emitting control lines; The gate driver includes a light emitting control stage for sequentially supplying light emitting control signals to the light emitting control lines; and Each of the light emission control stages includes: an input circuit including the second transistor; and an output circuit including the first transistor.

7. The display device according to claim 1, wherein The first transistor and the second transistor have different characteristics from each other.

8. The display device according to claim 7, wherein: The first transistor and the second transistor have different threshold voltages from each other.

9. The display device according to claim 8, wherein: Each of the first transistor and the second transistor comprises a P-type transistor; and A threshold voltage of the first transistor is greater than a threshold voltage of the second transistor.

10. The display device according to claim 1, wherein The first active layer and the second active layer have different characteristics from each other.

11. The display device according to claim 10, wherein: The first active layer has a crystallinity smaller than that of the second active layer.

12. The display device according to claim 1, further comprising: The display panel includes a display area and a non-display area. The pixels are arranged in the display area, and the gate driver is arranged in the non-display area.

13. The display device according to claim 12, wherein: Each of the pixels includes a pixel transistor including a third active layer; and The third active layer has crystallinity lower than that of at least one of the first active layer and the second active layer.

14. A method for manufacturing a display device including a gate driver, the gate driver including a first transistor, a second transistor, and an insulating layer, the method comprising the following steps: forming an active layer of the first transistor on a base layer; as well as forming an active layer of the second transistor on the active layer of the first transistor, wherein the active layer of the first transistor and the active layer of the second transistor are crystallized under conditions different from each other, The first transistor further includes a first source electrode and a first drain electrode disposed on the active layer of the first transistor, and the second transistor further includes a second source electrode and a second drain electrode disposed on the active layer of the second transistor. wherein the insulating layer covers the active layer of the second transistor, and wherein the active layer of the first transistor and the active layer of the second transistor overlap each other, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are spaced apart from each other on the insulating layer, and the first source electrode and the first drain electrode penetrate the insulating layer to be connected to a region of the active layer of the first transistor that does not overlap with the active layer of the second transistor, wherein the first source electrode is connected to the 1-1 active region of the active layer of the first transistor, the first drain electrode is connected to the 1-2 active region of the active layer of the first transistor, the second source electrode is connected to the 2-1 active region of the active layer of the second transistor, and the second drain electrode is connected to the 2-2 active region of the active layer of the second transistor, and The 1-1 active region, the 1-2 active region, the 2-1 active region, and the 2-2 active region do not overlap with each other in a plan view.

15. The method according to claim 14, wherein: irradiating the active layer of the first transistor with a laser at a first pitch when crystallizing the active layer of the first transistor; and When crystallizing the active layer of the second transistor, the active layer of the second transistor is irradiated with the laser at a second pitch.

16. The method according to claim 15, wherein The first distance is greater than the second distance.

17. The method according to claim 14, wherein: The active layer of the first transistor is crystallized before the active layer of the second transistor is crystallized.

18. The method according to claim 14, further comprising the steps of: forming pixel transistors in a display area of the display device, The active layer of the pixel transistor is crystallized under a condition different from a crystallization condition of at least one of the active layer of the first transistor and the active layer of the second transistor.

19. The method according to claim 18, wherein: irradiating the at least one active layer among the active layer of the first transistor and the active layer of the second transistor with a laser at a first distance when crystallizing the at least one active layer among the active layer of the first transistor and the active layer of the second transistor; and When crystallizing the active layer of the pixel transistor, the active layer of the pixel transistor is irradiated with the laser at a second pitch greater than the first pitch.

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