parameter monitoring circuit, duty cycle correction circuit, and impedance calibration circuit

Abstract

A parameter monitoring circuit, a duty cycle correction circuit, and an impedance calibration circuit are provided. The parameter monitoring circuit includes a code generation circuit configured to generate a first code to which a first offset is applied and a second code to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by applying the first code and the second code, respectively, to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error of the current parameter based on the first comparison result and the second comparison result.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0113036, filed on September 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] At least some example embodiments of the present invention are conceived to relate to parameter monitoring circuits, duty cycle correction circuits, and impedance calibration circuits, and more particularly, to parameter monitoring circuits for detecting parameter errors, duty cycle correction circuits for detecting duty cycle errors in clock signals, and impedance calibration circuits for detecting impedance errors. Background Art

[0004] In various devices, parameters required for device operation are set to desired values ​​by adjusting or correcting the parameters based on a code. For example, a duty cycle correction circuit adjusts the duty cycle of a clock signal based on a code to achieve a desired target duty cycle, and an impedance calibration circuit or a ZQ calibration circuit forms a desired impedance value based on a code.

[0005] When the value of a parameter differs significantly from the desired value, it is necessary to detect the difference and retrain the code. When the value of a parameter differs significantly from the desired value, it is called parameter error, and a method is needed to determine the error condition of the parameter. Summary of the Invention

[0006] At least some example embodiments of the inventive concepts provide a method and apparatus for detecting parameter errors without requiring separate monitoring devices in a parameter monitoring circuit, a duty cycle correction circuit, and an impedance calibration circuit.

[0007] According to at least some example embodiments of the present inventive concepts, a parameter monitoring circuit includes: a code generation circuit configured to generate a first code to which a first offset is applied and a second code to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by applying the first code and the second code to a current parameter, respectively; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter based on the first comparison result and the second comparison result.

[0008] According to at least some example embodiments of the inventive concept, there is provided a duty cycle correction circuit including a code generation circuit configured to generate a first code to which a first offset is applied and a second code to which a second offset is applied; a duty cycle adjustment circuit configured to generate a first clock signal by correcting a duty cycle of a current clock signal using the first code and generate a second clock signal by correcting the duty cycle of the current clock signal using the second code; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between a first duty cycle of the first clock signal and a target duty cycle value, and the second comparison result indicating a comparison result between a second duty cycle of the second clock signal and the target duty cycle value; and a duty cycle error detection circuit configured to detect a duty cycle error of the current clock signal based on the first comparison result and the second comparison result.

[0009] According to at least some example embodiments of the inventive concept, there is provided an impedance calibration circuit including a first code generation circuit configured to generate a first pull-up code to which a first offset is applied and a second pull-up code to which a second offset is applied; a first pull-up driver configured to form a first impedance by using the first pull-up code and form a second impedance by using the second pull-up code; an impedance pin connected to the first pull-up driver and an external impedance; a first comparator circuit configured to generate a pull-up comparison result based on a voltage of the impedance pin and a reference voltage value; and an impedance error detection circuit configured to detect an impedance error based on a first pull-up comparison result and a second pull-up comparison result, the first pull-up comparison result being generated based on the first impedance formed by the first pull-up driver, and the second pull-up comparison result being generated based on the second impedance formed by the first pull-up driver. BRIEF DESCRIPTION OF DRAWINGS

[0010] Example embodiments of the inventive concept will become more fully understood from the detailed description given herein below, and the accompanying drawings, which are given by way of illustration and are not intended to be limiting of the inventive concept. The drawings are to be regarded as being schematic representations and elements in the drawings are not necessarily shown to scale.

[0011] Figure 1 A parameter monitoring circuit according to at least one example embodiment of the inventive concept is illustrated;

[0012] Figure 2 A flowchart of a parameter monitoring method of a parameter monitoring circuit according to at least one example embodiment of the inventive concept is illustrated;

[0013] Figure 3AA conceptual diagram showing a case where an offset is applied to a normal parameter according to at least one example embodiment of the inventive concept;

[0014] Figure 3B A conceptual diagram showing a case where an offset is applied to a parameter having a positive error according to at least one example embodiment of the inventive concept;

[0015] Figure 3C A conceptual diagram showing a case where an offset is applied to a parameter having a negative error according to at least one example embodiment of the inventive concept;

[0016] Figure 4 A comparator circuit according to at least one example embodiment of the inventive concept;

[0017] Figure 5 A parameter error detection circuit according to at least one example embodiment of the inventive concept;

[0018] Figure 6 A flowchart of an error detection method of a parameter error detection circuit according to at least one example embodiment of the inventive concept;

[0019] Figure 7 A flowchart of a parameter monitoring method of a parameter monitoring circuit according to at least one example embodiment of the inventive concept;

[0020] Figure 8 A duty cycle correction circuit according to at least one example embodiment of the inventive concept;

[0021] Figure 9 A duty cycle correction circuit according to at least one example embodiment of the inventive concept;

[0022] Figure 10 A conceptual diagram showing a case where an offset is applied in a duty cycle correction circuit according to at least one example embodiment of the inventive concept;

[0023] Figure 11 A flowchart of a duty cycle error detection method of a duty cycle correction circuit according to at least one example embodiment of the inventive concept;

[0024] Figure 12 An impedance calibration circuit according to at least one example embodiment of the inventive concept; and

[0025] Figure 13 A flowchart of an impedance error detection method of an impedance calibration circuit according to at least one example embodiment of the inventive concept. DETAILED DESCRIPTION

[0026] Embodiments are described and shown in terms of functional blocks, units and / or modules as is conventional in the art of the inventive concept. Those skilled in the art will understand that these blocks, units and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuitry, discrete components, microprocessors, hardwired circuitry, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or similar, they can be programmed with software (e.g., microcode) to perform various functions discussed herein and can optionally be driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented by a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Further, each block, unit and / or module of an embodiment can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the inventive concept. Further, the blocks, units and / or modules of an embodiment can be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0027] Figure 1 A parameter monitoring circuit 10 according to at least one example embodiment of the inventive concept is shown. The parameter monitoring circuit 10 is a circuit for monitoring a parameter, and can be implemented in any device for managing a parameter. For example, the parameter monitoring circuit 10 can be implemented in various devices for setting a parameter to a target parameter value, or adjusting or correcting a parameter. According to at least one example embodiment of the inventive concept, the parameter monitoring circuit 10 can be implemented in a device related to a code generation based parameter. According to at least one example embodiment of the inventive concept, the parameter monitoring circuit 10 can be implemented in a duty cycle correction (DCC) circuit, and can also be implemented in an impedance calibration circuit. Reference will be made to Figures 8 to 11 Embodiments of the parameter monitoring circuit 10 implemented in a duty cycle correction circuit are described in more detail, and reference will be made to Figure 12 and Figure 13 Embodiments of the parameter monitoring circuit 10 implemented in an impedance calibration circuit are described in more detail. However, at least some example embodiments of the inventive concept are not limited to the above-described embodiments. For example, the parameter monitoring circuit 10 can be applied to various circuits or devices such as a delay locked loop (DLL) or a phase locked loop (PLL).

[0028] The parameter monitoring circuit 10 can include a code generation circuit 100, a parameter adjustment circuit 200, a comparator circuit 300 and a parameter error detection circuit 400.

[0029] The code generation circuit 100 can generate a code CODE for generating and / or correcting the parameter. In addition, the code generation circuit 100 can provide the generated code CODE to the parameter adjustment circuit 200. The code CODE can be an N-bit code (where N is a natural number equal to or greater than 1), and according to at least one example embodiment of the present inventive concept, the code CODE can be a code having a number of bits up to a power of 2. For example, the code CODE can be a multi-bit code having, for example, 1 bit, 2 bits, 4 bits, 8 bits, or 16 bits. However, at least some example embodiments of the present inventive concept do not limit the specific number of bits of the code CODE. According to at least one example embodiment of the present inventive concept, the code generation circuit 100 can generate a first code to which a first offset OS1 is applied, and generate a second code to which a second offset OS2 is applied. Here, each of the first offset OS1 and the second offset OS2 can refer to an offset with respect to a current code CODE, and can also refer to an offset for correcting the current code CODE. According to at least one example embodiment of the present inventive concept, in the parameter monitoring mode, the code generation circuit 100 can generate a first code to which a first offset OS1 is applied, and generate a second code to which a second offset OS2 is applied. The parameter monitoring mode can be set at every predetermined operation period, or can be set according to a parameter monitoring command provided from the outside of the parameter monitoring circuit 10.

[0030] According to at least some example embodiments of the present inventive concept, the first offset OS1 can have a positive value, and the second offset OS2 can have a negative value. According to at least some example embodiments of the present inventive concept, the first offset OS1 can have a negative value, and the second offset OS2 can have a positive value. According to at least one example embodiment of the present inventive concept, the first offset OS1 and the second offset OS2 can have the same magnitude. In other words, according to at least one example embodiment of the present inventive concept, the first offset OS1 can be a positive offset having a first offset amount, and the second offset OS2 can be a negative offset having the first offset amount. As used herein, the expression "applying an offset to a parameter" can mean adding the offset to a current parameter value or subtracting the offset from the current parameter value.

[0031] In the parameter monitoring mode, the code generation circuit 100 can provide the generated first code and the second code to the parameter adjustment circuit 200.

[0032] The parameter adjustment circuit 200 may generate the coded parameter P_C by using the code CODE provided from the code generation circuit 100. The parameter adjustment circuit 200 may provide the coded parameter P_C to the comparator circuit 300. According to at least some example embodiments of the inventive concepts, the parameter adjustment circuit 200 may generate the coded parameter P_C by using the code CODE. In addition, according to one embodiment, the parameter adjustment circuit 200 may generate the coded parameter P_C by applying the code CODE to the original parameter.

[0033] According to at least one example embodiment of the present inventive concepts, in parameter monitoring mode, the parameter adjustment circuit 200 may receive a first code to which a first offset OS1 is applied and a second code to which a second offset OS1 is applied. Here, the first code and the second code may be received simultaneously or sequentially over time. The parameter adjustment circuit 200 may generate a first parameter by using the first code and generate a second parameter by using the second code. For example, the parameter adjustment circuit 200 may generate the first parameter by applying the first code to the original parameter and generate the second parameter by applying the second code to the original parameter. In parameter monitoring mode, the parameter adjustment circuit 200 may provide the first parameter and the second parameter to the comparator circuit 300.

[0034] The comparator circuit 300 may generate a comparison result RES_Comp by comparing the code-applied parameter P_C with the reference parameter value P_ref. Here, according to at least one example embodiment of the inventive concept, the comparator circuit 300 may generate a comparison result RES_Comp by directly comparing the code-applied parameter P_C with the reference parameter value P_ref. For example, the comparator circuit 300 may include a comparator ( Figure 4 320 in FIG. ). However, at least some example embodiments of the present inventive concepts are not limited thereto, and the comparator circuit 300 may compare the code-applied parameter P_C with the reference parameter value P_ref using an indirect method. Furthermore, according to at least one example embodiment of the present inventive concepts, the reference parameter value P_ref may be equal to or substantially equal to a target parameter value representing a parameter value required by the circuit or device to which the parameter monitoring circuit 10 is applied. The comparator circuit 300 may provide the comparison result RES_Comp to the parameter error detection circuit 400.

[0035] According to at least one example embodiment of the present inventive concept, the reference parameter value P_ref can be determined based on an error monitoring sensitivity required for the parameter monitoring circuit 10. For example, when the parameter monitoring circuit 10 requires a high error monitoring sensitivity, the reference parameter value P_ref can be set to be small. Likewise, for example, when the parameter monitoring circuit 10 requires a low error monitoring sensitivity, the reference parameter value P_ref can be set to be large. In addition, according to at least some example embodiments of the present inventive concept, the reference parameter value P_ref can be a fixed value or a variable value.

[0036] According to at least one example embodiment of the present inventive concept, in the parameter monitoring mode, the comparator circuit 300 can receive the first parameter and the second parameter from the parameter adjustment circuit 200. As described above, although the first parameter and the second parameter can be received simultaneously, at least some example embodiments of the present inventive concept are not limited thereto, and the first parameter and the second parameter can be received sequentially over time. The comparator circuit 300 can provide a first comparison result obtained by comparing the first parameter with the reference parameter value P_ref to the parameter error detection circuit 400, and can provide a second comparison result obtained by comparing the second parameter with the reference parameter value P_ref to the parameter error detection circuit 400.

[0037] In addition, according to at least one example embodiment of the present inventive concept, the comparator circuit 300 can provide the comparison result RES_Comp to the code generation circuit 100. In other words, the comparator circuit 300 can feed back the comparison result RES_Comp to the code generation circuit 100. According to at least one example embodiment of the present inventive concept, the code generation circuit 100 can generate the code CODE based on the comparison result RES_Comp fed back. As such, the parameter monitoring circuit 10 can include a closed-loop type signal transmission path.

[0038] The parameter error detection circuit 400 can detect a parameter error based on the comparison result RES_Comp provided from the comparator circuit 300. For example, in the parameter monitoring mode, the parameter error detection circuit 400 can detect a parameter error based on the first comparison result and the second comparison result received from the comparator circuit 300. According to at least one example embodiment of the present inventive concept, in response to the fact that the first comparison result and the second comparison result have the same logic level, the parameter error detection circuit 400 can determine that such a condition is a condition in which a parameter error exists. In addition, according to at least one example embodiment of the present inventive concept, in response to the fact that the first comparison result and the second comparison result have logic levels different from each other, the parameter error detection circuit 400 can determine that such a condition is a normal condition in which a parameter error does not exist.

[0039] In this context, a parameter error can occur according to various circumstances. For example, a parameter error can occur because a parameter is not locked to a correct target value from the beginning, or a parameter error can occur because although a parameter is initially locked to a correct target value, the value of the parameter is then changed according to a change in the surrounding environment. As used herein, the expression "a parameter is locked" or "locking a parameter" can mean that a parameter is fixed to a target value.

[0040] The parameter error detection circuit 400 can output a parameter error detection signal PED according to whether a parameter error is detected. For example, when there is a parameter error, the parameter error detection circuit 400 can output the parameter error detection signal PED having a first logic level. Also, for example, when there is no parameter error, the parameter error detection circuit 400 can output the parameter error detection signal PED having a second logic level different from the first logic level. However, at least some example embodiments of the inventive concept are not limited thereto, and as another example, the parameter error detection circuit 400 can activate the parameter error detection signal PED only when there is a parameter error.

[0041] According to at least one example embodiment of the inventive concept, the parameter error detection circuit 400 can include a memory for storing the first comparison result, and a logic circuit for performing a logical operation by using the first comparison result and the second comparison result. The logic circuit can include an XOR gate circuit for performing an exclusive OR (XOR) operation by using the first comparison result and the second comparison result. This will be described in more detail with reference to Figure 5 This will be described in more detail.

[0042] According to at least one example embodiment of the inventive concept, the operating frequency of the parameter monitoring circuit 10 can be 1 GHz or more.

[0043] According to the parameter monitoring circuit 10 according to at least one example embodiment of the inventive concept, the parameter monitoring circuit 10 can sequentially generate codes to which first and second offsets OS1 and OS2 are respectively applied, and can detect a parameter error based on first and second comparison results thus obtained. Accordingly, a device in which the parameter monitoring circuit 10 is implemented can detect or monitor a parameter error without a separate monitoring device.

[0044] In particular, at least some of the code generation circuit 100, the parameter adjustment circuit 200, and the comparator circuit 300 can be pre-provided hardware resources used for other purposes in a device in which the parameter monitoring circuit 10 is implemented. Accordingly, the parameter monitoring circuit 10 can also improve the efficiency of hardware implementation by detecting a parameter error using pre-provided hardware resources.

[0045] Figure 2 A flowchart of a parameter monitoring method of a parameter monitoring circuit according to at least one example embodiment of the inventive concept is shown. The description of Figure 2 will be made with reference to Figure 1 together.

[0046] The parameter monitoring circuit 10 can generate a first parameter based on a first code to which a first offset OS1 is applied (S110). For example, the code generation circuit 100 can generate a first code to which a first offset OS1 is applied, and can provide the first code to the parameter adjustment circuit 200. The parameter adjustment circuit 200 can generate a first parameter by using the first code.

[0047] The parameter monitoring circuit 10 can generate a first comparison result by comparing the first parameter with a reference parameter value P_ref (S120). For example, the comparator circuit 300 can directly or indirectly compare the first parameter with the reference parameter value P_ref, and can generate a first comparison result. The comparator circuit 300 can provide the first comparison result to the parameter error detection circuit 400. The parameter error detection circuit 400 can store the first comparison result in a memory (or a flip-flop) inside thereof.

[0048] The parameter monitoring circuit 10 can generate a second parameter based on a second code to which a second offset OS2 is applied (S130). For example, the code generation circuit 100 can generate a second parameter based on a second code to which a second offset OS2 is applied, and can provide the second code to the parameter adjustment circuit 200. The parameter adjustment circuit 200 can generate a second parameter by using the second code.

[0049] The parameter monitoring circuit 10 can generate a second comparison result by comparing the second parameter with the reference parameter value P_ref (S140). For example, the comparator circuit 300 can directly or indirectly compare the second parameter with the reference parameter value P_ref, and can generate a second comparison result. The comparator circuit 300 can provide the second comparison result to the parameter error detection circuit 400.

[0050] The parameter monitoring circuit 10 can detect a parameter error based on the first comparison result and the second comparison result (S150). For example, the parameter error detection circuit 400 can detect a parameter error based on the first comparison result and the second comparison result temporarily stored therein. For example, the parameter error detection circuit 400 can detect a parameter error by performing an exclusive OR operation using the first comparison result and the second comparison result.

[0051] Figure 3AA conceptual diagram showing a condition in which an offset is applied to a normal parameter according to at least one example embodiment of the inventive concept is shown. Here, the term "normal parameter" refers to a case in which the value of the current parameter P_cur is equal to or substantially equal to the value of the desired target parameter value P_target. Descriptions regarding Figure 3A will be made together with reference to Figure 1 .

[0052] According to at least one example embodiment of the inventive concept, the reference parameter value P_ref can be equal to the target parameter value P_target representing a desired parameter value. In Figure 3A , a line positioned higher than the line of the reference parameter value P_ref indicates that the value of the line at that position is greater than the reference parameter value P_ref, and a line positioned lower than the line of the reference parameter value P_ref indicates that the value of the line at that position is less than the reference parameter value P_ref.

[0053] According to at least one example embodiment of the inventive concept, in the parameter monitoring mode, the code generation circuit 100 can generate a first code to which a first offset OS1 is applied, and can generate a second code to which a second offset OS2 is applied. The parameter adjustment circuit 200 can generate a first parameter P_1 based on the first code, and can generate a second parameter P_2 based on the second code. For example, the parameter adjustment circuit 200 can generate the first parameter P_1 by applying the first code to the original parameter, and can generate the second parameter P_2 by applying the second code to the original parameter. According to at least one example embodiment of the inventive concept, the first offset OS1 can have a positive value, and the second offset OS2 can have a negative value.

[0054] Reference will be made to Figure 3A , when the parameter is in a normal condition, the first parameter P_1 according to the first code to which the first offset OS1 is applied has a value greater than the reference parameter value P_ref. Also, when the parameter is in a normal condition, the second parameter P_2 according to the second code to which the second offset OS2 is applied has a value less than the reference parameter value P_ref.

[0055] Figure 3B A conceptual diagram showing a condition in which an offset is applied to a parameter having a positive error according to at least one example embodiment of the inventive concept is shown. Here, the expression "a parameter having a positive error" indicates a case in which the value of the current parameter P_cur has a positive error with respect to the reference parameter value P_ref. In particular, the expression "a parameter having a positive error" can indicate a case in which the value of the current parameter P_cur has a positive error beyond an acceptable range with respect to the reference parameter value P_ref. Descriptions regarding Figure 3B will also be made together with reference to Figure 1 .

[0056] According to at least one of the example embodiments of the inventive concept, the reference parameter value P_ref can be equal to a target parameter value P_target representing a desired parameter value. In Figure 3B In this case, a line positioned higher than the line of the reference parameter value P_ref indicates that the value of the line positioned higher has a value greater than the reference parameter value P_ref, and a line positioned lower than the line of the reference parameter value P_ref indicates that the value of the line positioned lower has a value less than the reference parameter value P_ref.

[0057] According to at least one of the example embodiments of the inventive concept, in the parameter monitoring mode, the code generation circuit 100 can generate a first code to which a first offset OS1 is applied, and can generate a second code to which a second offset OS2 is applied. The parameter adjustment circuit 200 can generate a first parameter P_1 based on the first code, and can generate a second parameter P_2 based on the second code. According to at least one of the example embodiments of the inventive concept, the first offset OS1 can have a positive value, and the second offset OS2 can have a negative value. Referring to Figure 3B When the parameter has a positive error, the first parameter P_1 according to the first code (to which the first offset OS1 is applied) has a value greater than the reference parameter value P_ref. Likewise, when the parameter has a positive error, the second parameter P_2 according to the second code (to which the second offset OS2 is applied) has a value greater than the reference parameter value P_ref. In contrast, Figure 3A The difference is that the second parameter P_2 has a value greater than the reference parameter value P_ref.

[0058] Figure 3C A conceptual diagram showing a case in which an offset is applied to a parameter having a negative error according to at least one of the example embodiments of the inventive concept is shown. Here, the expression "a parameter having a negative error" indicates a case in which the value of the current parameter P_cur has a negative error with respect to the reference parameter value P_ref. In particular, the expression "a parameter having a negative error" can indicate a case in which the value of the current parameter P_cur has a negative error exceeding an acceptable range with respect to the reference parameter value P_ref. As to Figure 3C The description of the above will also be made with reference to Figure 1 together.

[0059] According to at least one of the example embodiments of the inventive concept, the reference parameter value P_ref can be equal to a target parameter value P_target representing a desired parameter value. In Figure 3C In this case, a line positioned higher than the line of the reference parameter value P_ref indicates that the value of the line positioned higher has a value greater than the reference parameter value P_ref, and a line positioned lower than the line of the reference parameter value P_ref indicates that the value of the line positioned lower has a value less than the reference parameter value P_ref.

[0060] According to at least one of the example embodiments of the present inventive concept, in the parameter monitoring mode, the code generation circuit 100 can generate a first code to which a first offset OS1 is applied, and can generate a second code to which a second offset OS2 is applied. The parameter adjustment circuit 200 can generate a first parameter P_1 based on the first code, and can generate a second parameter P_2 based on the second code. According to at least one of the example embodiments of the present inventive concept, the first offset OS1 can have a positive value, and the second offset OS2 can have a negative value. Referring to Figure 3C When the parameter has a negative error, the first parameter P_1 according to the first code (to which the first offset OS1 is applied) has a value smaller than the reference parameter value P_ref. Likewise, when the parameter has a negative error, the second parameter P_2 according to the second code (to which the second offset OS2 is applied) has a value smaller than the reference parameter value P_ref. In contrast, Figure 3A The difference is that the value of the first parameter P_1 is smaller than the reference parameter value P_ref.

[0061] Summary Figures 3A to 3C When the current parameter P_cur is in a normal condition, the first parameter P_1 and the second parameter P_2 with respect to the reference parameter value P_ref can be in different directions from each other in terms of up and down, and when the current parameter P_cur is in an error condition, the first parameter P_1 and the second parameter P_2 with respect to the reference parameter value P_ref can be in the same direction in terms of up and down. The parameter monitoring circuit 10 can detect a parameter error by using these characteristics. This will be described in more detail with reference to the following drawings.

[0062] Figure 4 A comparator circuit 300 according to at least one of the example embodiments of the present inventive concept is illustrated. Figure 4 The comparator circuit 300 can be a component corresponding to the comparator circuit 300 of Figure 1 The comparator circuit 300 of Figure 4 The comparator circuit 300, repetitive descriptions given with respect to the comparator circuit 300 will be omitted. Figure 1

[0063] In particular, Figure 4 An embodiment of the comparator circuit 300 in which the parameter P_C to which the code is applied is directly compared with the reference parameter value P_ref is illustrated. That is, the comparator circuit 300 can include a comparator 320.

[0064] The comparator 320 can output a comparison result RES_Comp by comparing the parameter P_C to which the code is applied with the reference parameter value P_ref. Although Figure 4 ​The reference parameter value P_ref is input to the non-inverting input terminal of the comparator 320, and the coded parameter P_C is input to the inverting input terminal of the comparator 320 according to one embodiment, but at least some example embodiments of the inventive concept are not limited thereto. Rather, the coded parameter P_C can be input to the non-inverting input terminal of the comparator 320, and the reference parameter value P_ref can be input to the inverting input terminal of the comparator 320. According to at least some example embodiments of the inventive concept, the comparator 320 is a circuit configured to output a comparison result RES_Comp such that the value of the comparison result RES_Comp indicates whether the coded parameter P_C is greater than or less than the reference parameter value P_ref. For example, according to at least some example embodiments of the inventive concept, the comparator 320 can be a circuit that generates the comparison result RES_Comp as a binary value (e.g., "0" or "1") indicating whether the coded parameter P_C is greater than (e.g., "0", or optionally "1") or less than (e.g., "1", or optionally "0") the reference parameter value P_ref.

[0065] Figure 5 The parameter error detection circuit 400 according to at least one example embodiment of the inventive concept is illustrated. Figure 5 The parameter error detection circuit 400 according to Figure 1 The parameter error detection circuit 400 according to Figure 5 The parameter error detection circuit 400 according to Figure 1 The repeated description given with reference to

[0066] The parameter error detection circuit 400 can include a memory 420 and an XOR gate circuit 440.

[0067] The memory 420 can store a comparison result input from the outside of the parameter error detection circuit 400. For example, in the parameter monitoring mode, when the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2 are sequentially input in the order as described below, the memory 420 can provide the first comparison result RES_Comp_1 to the XOR gate circuit 440. The memory 420 can be implemented by using various types of volatile memories and various types of non-volatile memories, but is not limited thereto, and all components capable of temporarily storing data can be included in the memory 420. For example, the memory 420 can be implemented by a flip-flop.

[0068] According to at least one example embodiment of the inventive concept, the memory 420 can temporarily store both the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2. In this case, the memory 420 can provide both the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2 to the XOR gate circuit 440. According to at least one example embodiment of the inventive concept, the memory 420 can include a first flip-flop temporarily storing the first comparison result RES_Comp_1 and a second flip-flop temporarily storing the second comparison result RES_Comp_2.

[0069] The XOR gate circuit 440 can output the parameter error detection signal PED by performing a logical operation using the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2. For example, the XOR gate circuit 440 can output the parameter error detection signal PED by performing an exclusive-OR operation using the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2. According to at least one example embodiment of the inventive concept, the XOR gate circuit 440 can output the parameter error detection signal PED as an error correction guide signal guiding an operation of correcting a parameter error to the outside of the parameter monitoring circuit. Here, the outside of the parameter monitoring circuit can be a host of a system including the parameter monitoring circuit. The host can perform retraining of a code on a parameter in response to receiving the error correction guide signal. For example, the host can adjust the code based on the parameter error detection signal and provide the adjusted code to the code generation circuit 100, which can generate the first code and the second code based on the first offset OS1 and the second offset OS2, respectively.

[0070] For example, referring to the embodiment of FIG. 4, Figure 3A In a normal condition of the parameters, because the first parameter P_1 is greater than the reference parameter value P_ref, the first comparison result RES_Comp_1 can indicate a first logic level (as a non-limiting example, "0"), and because the second parameter P_2 is less than the reference parameter value P_ref, the second comparison result RES_Comp_2 can indicate a second logic level (as a non-limiting example, "1"). Accordingly, the XOR gate circuit 440 can output the parameter error detection signal PED indicating the second logic level (e.g., "1") by performing an exclusive-OR operation using the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2. Here, the parameter error detection signal PED indicating the second logic level can represent a normal condition.

[0071] In addition, for example, referring to the embodiment of FIG. 4, Figure 3BIn an embodiment, when a parameter has a positive error, because the first parameter P_1 is greater than the reference parameter value P_ref, the first comparison result RES_Comp_1 may indicate a first logic level (e.g., "0"). Furthermore, because the second parameter P_2 is also greater than the reference parameter value P_ref, the second comparison result RES_Comp_2 may also indicate a first logic level (e.g., "0"). Therefore, the XOR gate circuit 440 can output a parameter error detection signal PED indicating a first logic level (e.g., "0") by performing an exclusive OR operation using the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2. Here, the parameter error detection signal PED indicating a first logic level may indicate an error condition.

[0072] In addition, for example, refer to Figure 3C In this embodiment, when a parameter has a negative error, because the first parameter P_1 is less than the reference parameter value P_ref, the first comparison result RES_Comp_1 may indicate a second logic level (e.g., "1"). Furthermore, because the second parameter P_2 is also less than the reference parameter value P_ref, the second comparison result RES_Comp_2 may also indicate a second logic level (e.g., "1"). Therefore, the XOR gate circuit 440 can output a parameter error detection signal PED indicating a first logic level (e.g., "0") by performing an exclusive OR operation using the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2. Here, the parameter error detection signal PED indicating the first logic level may indicate an error condition.

[0073] Figure 6 A flow chart illustrating an error detection method of a parameter error detection circuit according to at least one example embodiment of the inventive concept is shown. Figure 6 The description will refer to Figure 5 Do it together.

[0074] The parameter error detection circuit 400 may store the first comparison result RES_Comp_1 in the memory 420 ( S220 ). For example, when the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2 are sequentially input in the order described below, the parameter error detection circuit 400 may temporarily store the first comparison result RES_Comp_1 in the memory 420 .

[0075] The parameter error detection circuit 400 can detect a parameter error by performing an XOR operation using the second comparison result RES_Comp_2 and the first comparison result RES_Comp_1 stored in the memory 420 (S240). For example, the XOR gate circuit 440 can output a parameter error detection signal PED by performing an XOR operation using the second comparison result RES_Comp_2 and the first comparison result RES_Comp_1 provided from the memory 420.

[0076] Figure 7 A flowchart of a parameter monitoring method of a parameter monitoring circuit according to at least one example embodiment of the inventive concept is shown. In particular, Figure 7 An embodiment of a method of monitoring a parameter when aiming at more accurately detecting a parameter error is shown. With reference to Figure 7 the description will be made together. Figure 1

[0077] The parameter monitoring circuit 10 can detect a parameter error by using a first offset (S310). The operation S310 can include Figure 2 the operations S110 to S150 in the method 1000, wherein the first offset OS1 can be a positive value having the first offset amount and the second offset OS2 can be a negative value having the first offset amount. In other words, the parameter monitoring circuit 10 can detect a parameter error by applying the first offset OS1 and the second offset OS2 each having an absolute value (or magnitude) of the first offset amount.

[0078] Depending on whether a parameter error is detected (S320), the next operation can be different. When a parameter error is detected, an operation S360 can be performed. Conversely, when a parameter error is not detected, an operation S330 can be performed.

[0079] In detecting a parameter error by using a first offset amount, when a parameter error is not detected, the parameter monitoring circuit 10 can detect a parameter error by using a second offset amount (S330). The operation S330 can include Figure 2 the operations S110 to S150 in the method 1000, wherein the first offset OS1 can have a positive value of the second offset amount and the second offset OS2 can have a negative value of the second offset amount. In other words, the parameter monitoring circuit 10 can re-detect a parameter error by applying the first offset OS1 and the second offset OS2 each having an absolute value (or magnitude) of the second offset amount. According to at least one example embodiment of the inventive concept, the value of the second offset amount can be smaller than the value of the first offset amount.

[0080] With reference to Figure 3A and Figure 3B ​When the detection is performed by using the smaller offset, the parameter error can be detected by using the higher sensitivity. That is, when the smaller offset is used, a smaller error occurring in the parameter can be detected.

[0081] The next operation can be different according to whether the parameter error is detected (S340). When the parameter error is detected, operation S360 can be performed. On the contrary, when the parameter error is not detected, operation S350 can be performed.

[0082] In the detection of the parameter error by using the second offset, when the parameter error is not detected, the parameter monitoring circuit 10 can determine that the parameter is in the normal condition (S350).

[0083] On the other hand, in the detection of the parameter error by using the first offset or the detection of the parameter error by using the second offset, when the parameter error is detected, the parameter monitoring circuit 10 can determine that the parameter is in the error condition (S360).

[0084] Figure 8 A duty cycle correction circuit 1000 according to at least one example embodiment of the inventive concept is illustrated. The duty cycle correction circuit 1000 can correspond to the parameter monitoring circuit 10 of Figure 1 In other words, the embodiments described with reference to Figures 1 to 7 can be equally applied to the duty cycle correction circuit 1000.

[0085] The duty cycle correction circuit 1000 can include a code generation circuit 1100, a duty cycle adjustment circuit 1200, a comparator circuit 1300, and a duty cycle error detection circuit 1400.

[0086] The code generation circuit 1100 can correspond to the code generation circuit 100 of Figure 1 That is, the code generation circuit 1100 can generate a code CODE for adjusting a duty cycle. According to at least one example embodiment of the inventive concept, in a duty cycle monitoring mode, the code generation circuit 1100 can generate a first code to which a first duty cycle offset DOS1 is applied and a second code to which a second duty cycle offset DOS2 is applied. The code generation circuit 1100 can provide the first code and the second code to the duty cycle adjustment circuit 1200.

[0087] The duty cycle adjustment circuit 1200 can correspond to the duty cycle adjustment circuit 200 of Figure 1The duty cycle adjustment circuit 1200 can adjust the duty cycle of the clock signal by using the current clock signal and the code CODE, and can generate the code-applied clock signal CLK_C. According to at least one of example embodiments of the present inventive concept, the duty cycle adjustment circuit 1200 can output the code-applied clock signal CLK_C as an output clock signal CLK_o to the outside of the duty cycle correction circuit 1000. According to at least one of example embodiments of the present inventive concept, in the duty cycle monitoring mode, the duty cycle adjustment circuit 1200 can provide the first clock signal having the duty cycle adjusted based on the first code and the second clock signal having the duty cycle adjusted based on the second code to the comparator circuit 1300.

[0088] The comparator circuit 1300 can correspond to Figure 1 The comparator circuit 1300 can compare the duty cycle of the code-applied clock signal CLK_C with a target duty cycle required. According to at least one of example embodiments of the present inventive concept, the target duty cycle can be 0.5 or 50%. The comparator circuit 1300 can compare the duty cycle of the code-applied clock signal CLK_C with the target duty cycle by an indirect method. The comparator circuit 1300 can output a result obtained by comparing the duty cycle of the code-applied clock signal CLK_C with the target duty cycle as a comparison result RES_Comp, and according to at least one of example embodiments of the present inventive concept, the comparator circuit 1300 can provide the comparison result RES_Comp to the duty cycle error detection circuit 1400 and the code generation circuit 1100. According to at least one of example embodiments of the present inventive concept, in the duty cycle monitoring mode, the comparator circuit 1300 can output a first comparison result by comparing the duty cycle of the first clock signal with the target duty cycle, and can output a second comparison result by comparing the duty cycle of the second clock signal with the target duty cycle.

[0089] The duty cycle error detection circuit 1400 can correspond to Figure 1 The duty cycle error detection circuit 1400 can detect a duty cycle error of the current clock signal by using the comparison result RES_Comp provided from the comparator circuit 1300. According to at least one of example embodiments of the present inventive concept, in the duty cycle monitoring mode, the duty cycle error detection circuit 1400 can output a duty cycle error detection signal DED by using the first comparison result and the second comparison result. To this end, the duty cycle error detection circuit 1400 can be implemented as in Figure 5

[0090] ​According to the duty cycle correction circuit 1000 according to at least one of the example embodiments of the present conception, the duty cycle correction circuit 1000 can sequentially generate codes to which first and second duty cycle offsets DOS1 and DOS2 are respectively applied, and can detect a duty cycle error of a clock signal based on first and second comparison results thus obtained. Accordingly, the duty cycle correction circuit 1000 can detect or monitor a duty cycle error of a clock signal without a separate monitoring device.

[0091] In particular, in the duty cycle correction circuit 1000, at least some of the code generation circuit 1100, the duty cycle adjustment circuit 1200, and the comparator circuit 1300 selected therefrom can be pre-provided hardware resources used for duty cycle correction in addition to duty cycle monitoring. Accordingly, the duty cycle correction circuit 1000 can also detect a duty cycle error of a clock signal by using the pre-provided hardware resources, thereby improving efficiency of hardware implementation.

[0092] In addition, according to at least one of the example embodiments of the present conception, the duty cycle correction circuit 1000 can be implemented inside various storage devices such as a non-volatile storage device. Here, the non-volatile storage device can include a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), or a combination thereof. According to at least one of the example embodiments of the present conception, the non-volatile storage device can have a structure in which one hundred or more layers are stacked. In addition, according to at least one of the example embodiments of the present conception, the non-volatile storage device can have a cell-on-peri or cell-over-peri (COP) structure. Here, the duty cycle correction circuit 1000 can detect a duty cycle error of a clock signal within a latency interval related to a data operation corresponding to a data operation command input to the storage device, thereby detecting a duty cycle error of a clock signal without an additional time interval. In other words, the duty cycle correction circuit 1000 can detect a condition in which a duty cycle error of a clock signal occurs without consuming an additional time.

[0093] Figure 9 A duty cycle correction circuit 1000 according to at least one of the example embodiments of the present conception is illustrated. Figure 9 A more detailed implementation example of the duty cycle correction circuit 1000 of Figure 8 may be illustrated.

[0094] The code generation circuit 1100 can include an up / down counter 1120 and a DCC code multiplexer (MUX) circuit 1140. The up / down counter 1120 can generate a control signal CS based on the comparison result RES_Comp. For example, the control signal CS can be a 4-bit digital code, and the up / down counter 1120 can increase or decrease the code of the control signal CS by 1 according to a logic level indicated by the comparison result RES_Comp.

[0095] The DCC code MUX circuit 1140 can generate a code CODE based on the control signal CS provided by the up / down counter 1120. To this end, the DCC code MUX circuit 1140 can be implemented by using a plurality of transistors. In the duty cycle monitoring mode, the DCC code MUX circuit 1140 can generate a first code by applying a first duty cycle offset DOS1, and can generate a second code by applying a second duty cycle offset DOS2. The DCC code MUX circuit 1140 can provide the generated code CODE to the duty cycle adjustment circuit 1200.

[0096] The comparator circuit 1300 can include a charge pump 1320 and a comparator 1340.

[0097] The charge pump 1320 can generate a first charge pump signal CPP and a second charge pump signal CPN based on an output clock signal CLK_o. According to at least one example embodiment of the inventive concept, the charge pump 1320 can receive two clock signals having different phases (the phases of the clock signals are separated by a phase splitter), and can generate the first charge pump signal CPP and the second charge pump signal CPN based on the two clock signals having different phases.

[0098] The comparator 1340 can output a comparison result RES_Comp by comparing the first charge pump signal CPP with the second charge pump signal CPN. As a result, according to at least one example embodiment of the inventive concept, when the on-time of the output clock signal CLK_o or the clock signal CLK_C to which a code is applied is longer than the off-time thereof, the comparator 1340 can output the comparison result RES_Comp having a first logic level. Also, according to at least one example embodiment of the inventive concept, when the on-time of the output clock signal CLK_o or the clock signal CLK_C to which a code is applied is shorter than the off-time thereof, the comparator 1340 can output the comparison result RES_Comp having a second logic level. That is, according to at least one example embodiment of the inventive concept, the comparator circuit 1300 can perform a function of indirectly comparing the duty cycle of the clock signal CLK_C to which a code is applied with 0.5 which is a target duty cycle. The comparator 1340 can provide the comparison result RES_Comp to the duty cycle error detection circuit 1400.

[0099] Figure 10 A conceptual diagram illustrating a condition of applying an offset in a duty cycle correction circuit according to at least one example embodiment of the inventive concept is shown. The description of Figure 10 will be made with reference to Figure 8 together.

[0100] The duty cycle correction circuit 1000 can generate a first clock signal CLK_1 by applying a first code to which a first duty cycle offset DOS1 is applied to the current clock signal CLK_cur. According to at least one example embodiment of the inventive concept, the first duty cycle offset DOS1 can have a positive offset value, in which the first duty cycle offset DOS1 can increase a duty cycle of a clock signal.

[0101] The comparator circuit 1300 can generate a first comparison result RES_Comp_1 based on the first clock signal CLK_1. For example, the comparator circuit 1300 can generate the first comparison result RES_Comp_1 by comparing a duty cycle of the first clock signal CLK_1 with a target duty cycle.

[0102] The duty cycle correction circuit 1000 can generate a second clock signal CLK_2 by applying a second code to which a second duty cycle offset DOS2 is applied to the current clock signal CLK_cur. According to at least one example embodiment of the inventive concept, the second duty cycle offset DOS2 can have a negative offset value, in which the second duty cycle offset DOS2 can decrease a duty cycle of a clock signal.

[0103] The comparator circuit 1300 can generate a second comparison result RES_Comp_2 based on the second clock signal CLK_2. For example, the comparator circuit 1300 can generate the second comparison result RES_Comp_2 by comparing a duty cycle of the second clock signal CLK_2 with a target duty cycle.

[0104] The duty cycle error detection circuit 1400 can generate a duty cycle error detection signal DED based on the first comparison result RES_Comp_1 and the second comparison result RES_Comp_2.

[0105] Figure 11 A flowchart illustrating a duty cycle error detection method of a duty cycle correction circuit according to at least one example embodiment of the inventive concept is shown. In particular, Figure 11 a flowchart when the duty cycle correction circuit is implemented inside a storage device is shown. The description of Figure 11 will be made with reference to Figure 8 together.

[0106] The duty cycle monitoring command can be input to the storage device including the duty cycle correction circuit 1000 (S420). In other words, when the duty cycle monitoring command is input to the storage device, the duty cycle correction circuit 1000 can monitor the duty cycle of the clock signal as follows. However, according to at least some example embodiments of the present inventive concept, the operation S420 can be skipped, e.g., the duty cycle monitoring operation can be performed in all data operations without input of the duty cycle monitoring command.

[0107] The data operation command can be input to the storage device including the duty cycle correction circuit 1000 (S440). The data operation command can include a data read command and a data write command. The data operation of the storage device according to the data operation command can include a latency interval. The latency interval can be determined differently according to the specification of the storage device.

[0108] According to at least one example embodiment of the present inventive concept, the duty cycle correction circuit 1000 can perform the duty cycle monitoring operation as in operation S460 for the latency interval according to the data operation.

[0109] The duty cycle correction circuit 1000 can generate a first comparison result by using a first clock signal generated based on a first code to which a first duty cycle offset DOS1 is applied (S462). For example, the code generation circuit 1100 can generate a first code to which a first duty cycle offset DOS1 is applied, the duty cycle adjustment circuit 1200 can generate a first clock signal by using the first code, and the comparator circuit 1300 can generate a first comparison result by comparing the duty cycle of the first clock signal with a target duty cycle.

[0110] The duty cycle correction circuit 1000 can generate a second comparison result by using a second clock signal generated based on a second code to which a second duty cycle offset DOS2 is applied (S464). For example, the code generation circuit 1100 can generate a second code to which a second duty cycle offset DOS2 is applied, the duty cycle adjustment circuit 1200 can generate a second clock signal by using the second code, and the comparator circuit 1300 can generate a second comparison result by comparing the duty cycle of the second clock signal with a target duty cycle.

[0111] The duty cycle correction circuit 1000 can detect a duty cycle error of the clock signal based on the first comparison result and the second comparison result (S466). For example, the duty cycle error detection circuit 1400 can detect a duty cycle error of the clock signal by performing a logical operation using the first comparison result and the second comparison result.

[0112] According to the duty cycle correction circuit 1000 according to at least one of the example embodiments of the present inventive concept, a duty cycle monitoring operation can be performed within a latency interval related to a data operation. Thus, since the duty cycle can be monitored without requiring additional time, consumption of additional time can be saved.

[0113] Figure 12 An impedance calibration circuit 2000 according to at least one of the example embodiments of the present inventive concept is illustrated. The impedance calibration circuit 2000 can correspond to a parameter monitoring circuit 10 of Figure 1 The embodiments described with reference to Figures 1 to 7 may also be equally applied to the impedance calibration circuit 2000.

[0114] The impedance calibration circuit 2000 can include a first code generation circuit 2100_1, a second code generation circuit 2100_2, a first pull-up driver 2200_1, a second pull-up driver 2200_2, a pull-down driver 2200_3, a first comparator circuit 2300_1, a second comparator circuit 2300_2, and a detection circuit 2400. The impedance calibration circuit 2000 can also include an impedance pin 2050 connected with an external reference impedance Rzq. The impedance pin 2050 can be connected to the first pull-up driver 2200_1.

[0115] The first code generation circuit 2100_1 can correspond to a code generation circuit 100 of Figure 1 . That is, the first code generation circuit 2100_1 can generate a pull-up code C_PU for adjusting an impedance. The first code generation circuit 2100_1 can provide the pull-up code C_PU to the first pull-up driver 2200_1 and the second pull-up driver 2200_2. According to at least one of the example embodiments of the present inventive concept, in a first impedance monitoring mode, the first code generation circuit 2100_1 can generate a first pull-up code to which a first offset OS1 is applied and a second pull-up code to which a second offset OS2 is applied. The first code generation circuit 2100_1 can provide the first pull-up code and the second pull-up code to the first pull-up driver 2200_1 and the second pull-up driver 2200_2. According to at least one of the example embodiments of the present inventive concept, the first offset OS1 can have a positive offset value, and the second offset OS2 can have a negative offset value. According to at least one of the example embodiments of the present inventive concept, an absolute value of the first offset OS1 can be equal to an absolute value of the second offset OS2.

[0116] The second code generation circuit 2100_2 can also correspond to a code generation circuit 100 of Figure 1the code generation circuit 100. That is, the second code generation circuit 2100_2 can generate a pull-down code C_PD for adjusting the impedance. The second code generation circuit 2100_2 can provide the pull-down code C_PD to the pull-down driver 2200_3. According to at least one example embodiment of the inventive concept, in the second impedance monitoring mode, the second code generation circuit 2100_2 can generate a third pull-down code to which a third offset OS3 is applied and a fourth pull-down code to which a fourth offset OS4 is applied. The second code generation circuit 2100_2 can provide the third pull-down code and the fourth pull-down code to the pull-down driver 2200_3. According to at least one example embodiment of the inventive concept, the third offset OS3 can have a positive offset value, and the fourth offset OS4 can have a negative offset value. According to at least one example embodiment of the inventive concept, an absolute value of the third offset OS3 can be equal to an absolute value of the fourth offset OS4. According to at least one example embodiment of the inventive concept, a value of the third offset OS3 can be equal to a value of the first offset OSI, and a value of the fourth offset OS4 can be equal to a value of the second offset OS2.

[0117] The first pull-up driver 2200_1 and the second pull-up driver 2200_2 can each correspond to Figure 1 the parameter adjustment circuit 200. The first pull-up driver 2200_1 and the second pull-up driver 2200_2 can each adjust an impedance value by using a pull-up code C_PU and can form an adjusted impedance value. According to at least one example embodiment of the inventive concept, in the first impedance monitoring mode, the first pull-up driver 2200_1 and the second pull-up driver 2200_2 can each have a first impedance value formed based on a first pull-up code and then can have a second impedance value formed based on a second pull-up code.

[0118] The pull-down driver 2200_3 can correspond to Figure 1 the parameter adjustment circuit 200. The pull-down driver 2200_3 can adjust an impedance value by using a pull-down code C_PD and can form an adjusted impedance value. According to at least one example embodiment of the inventive concept, in the second impedance monitoring mode, the pull-down driver 2200_3 can have a third impedance value formed based on a first pull-down code and then can have a fourth impedance value formed based on a second pull-down code.

[0119] The first comparator circuit (COMP 1) 2300_1 can correspond to Figure 1The first comparator circuit 2300_1 can compare the voltage of the impedance pin 2050 with a reference voltage V_ref. According to at least one example embodiment of the present inventive concept, the reference voltage V_ref can be equal to the voltage value of the impedance pin 2050 when the impedance formed by the first pull-up driver 2200_1 is consistent with the target impedance. The first comparator circuit 2300_1 can output the result of the comparison as a pull-up comparison result RES_Comp_PU, and according to at least one example embodiment of the present inventive concept, the pull-up comparison result RES_Comp_PU can be provided to the detection circuit 2400. According to at least one example embodiment of the present inventive concept, in the first impedance monitoring mode, the first comparator circuit 2300_1 can output a first pull-up comparison result by comparing the reference voltage V_ref with the voltage of the impedance pin 2050 resulting from the first pull-up driver 2200_1 forming the first impedance value, and can output a second pull-up comparison result by comparing the reference voltage V_ref with the voltage of the impedance pin 2050 resulting from the first pull-up driver 2200_1 forming the second impedance value.

[0120] The second comparator circuit (COMP 2) 2300_2 can correspond to Figure 1 a comparator circuit 300. The second comparator circuit 2300_2 can compare the reference voltage V_ref with the voltage of the first node to which the second pull-up driver 2200_2 and the pull-down driver 2200_3 are commonly connected. Although Figure 12 It is shown that the reference voltage input to the second comparator circuit 2300_2 is equal to the reference voltage input to the first comparator circuit 2300_1, but according to at least some example embodiments of the present inventive concept, different reference voltages can be input to the first comparator circuit 2300_1 and the second comparator circuit 2300_2, respectively. The second comparator circuit 2300_2 can output the comparison result as a pull-down comparison result RES_Comp_PD, and according to at least one example embodiment of the present inventive concept, the pull-down comparison result RES_Comp_PD can be provided to the detection circuit 2400. According to at least one example embodiment of the present inventive concept, in the second impedance monitoring mode, the second comparator circuit 2300_2 can output a first pull-down comparison result by comparing the reference voltage V_ref with the voltage of the first node resulting from the pull-down driver 2200_3 forming the third impedance value, and can output a second pull-down comparison result by comparing the reference voltage V_ref with the voltage of the first node resulting from the pull-down driver 2200_3 forming the fourth impedance value.

[0121] The detection circuit 2400 can correspond to Figure 1the parameter error detection circuit 400. That is, the detection circuit 2400 can detect the impedance error in the pull-up phase by using the pull-up comparison result RES_Comp_PU provided from the first comparator circuit 2300_1, and can detect the impedance error in the pull-down phase by using the pull-down comparison result RES_Comp_PD provided from the second comparator circuit 2300_2. According to at least one of example embodiments of the present inventive concept, in the first impedance monitoring mode, the detection circuit 2400 can output the impedance error detection signal ZED by using the first pull-up comparison result and the second pull-up comparison result. Also, according to at least one of example embodiments of the present inventive concept, in the second impedance monitoring mode, the detection circuit 2400 can output the impedance error detection signal ZED by using the first pull-down comparison result and the second pull-down comparison result. Here, the first impedance monitoring mode can refer to a mode for monitoring the impedance error of the first pull-up driver 2200_1 and the second pull-up driver 2200_2, and the second impedance monitoring mode can refer to a mode for monitoring the impedance error of the pull-down driver 2200_3. To this end, the detection circuit 2400 can be implemented as Figure 5

[0122] According to the impedance calibration circuit 2000 according to at least one of example embodiments of the present inventive concept, in the first impedance monitoring mode, the impedance calibration circuit 2000 can sequentially generate the pull-up codes C_PU to which the first offset OS1 and the second offset OS2 are respectively applied, and can detect the impedance error of the pull-up phase based on the first pull-up comparison result and the second pull-up comparison result thus obtained. Also, in the second impedance monitoring mode, the impedance calibration circuit 2000 can sequentially generate the pull-down codes C_PD to which the third offset OS3 and the fourth offset OS4 are respectively applied, and can detect the impedance error of the pull-down phase based on the first pull-down comparison result and the second pull-down comparison result thus obtained. Accordingly, the impedance calibration circuit 2000 can detect or monitor the impedance error without a separate monitoring device.

[0123] In particular, in the impedance calibration circuit 2000, at least some of the first code generation circuit 2100_1, the second code generation circuit 2100_2, the first pull-up driver 2200_1, the pull-down driver 2200_3, the first comparator circuit 2300_1, and the second comparator 2300_2 selected can be pre-provided hardware resources for impedance calibration in addition to impedance monitoring. Accordingly, the impedance calibration circuit 2000 can also improve the efficiency of hardware implementation by detecting the impedance error using the pre-provided hardware resources.

[0124] Figure 13 A flowchart illustrating an impedance error detection method of an impedance calibration circuit according to at least one of example embodiments of the present inventive concept is shown. With regard to​Figure 13 The description will be made with reference to Figure 12 together.

[0125] According to at least one example embodiment of the inventive concept, the operation S520 can represent a first impedance monitoring mode, and the operation S540 can represent a second impedance monitoring mode. Although Figure 13 Although it is shown that the operation S540 is performed after the operation S520, at least some example embodiments of the inventive concept are not limited thereto, and the operation S520 can be performed after the operation S540.

[0126] The impedance calibration circuit 2000 can generate a first pull-up comparison result by using a first impedance formed based on a first pull-up code to which a first offset OS1 is applied (S522). For example, the first code generation circuit 2100_1 can generate a first pull-up code to which the first offset OS1 is applied, the first pull-up driver 2200_1 can form a first impedance by using the first pull-up code, and the first comparator circuit 2300_1 can generate a first pull-up comparison result by comparing a reference voltage with a voltage of the impedance pin 2050 generated due to formation of the first impedance.

[0127] The impedance calibration circuit 2000 can generate a second pull-up comparison result by using a second impedance formed based on a second pull-up code to which a second offset OS2 is applied (S524). For example, the first code generation circuit 2100_1 can generate a second pull-up code to which the second offset OS2 is applied, the first pull-up driver 2200_1 can form a second impedance by using the second pull-up code, and the first comparator circuit 2300_1 can generate a second pull-up comparison result by comparing a reference voltage with a voltage of the impedance pin 2050 generated due to formation of the second impedance.

[0128] The impedance calibration circuit 2000 can detect an impedance error based on the first pull-up comparison result and the second pull-up comparison result (S526). For example, the detection circuit 2400 can detect an impedance error by performing a logical operation using the first pull-up comparison result and the second pull-up comparison result. In particular, the impedance calibration circuit 2000 can detect an impedance error in a pull-up phase.

[0129] The impedance calibration circuit 2000 can generate a first pull-down comparison result by using a third impedance formed based on a first pull-down code to which a third offset OS3 is applied (S542). For example, the second code generation circuit 2100_2 can generate the first pull-down code to which the third offset OS3 is applied, the pull-down driver 2200_3 can form the third impedance by using the first pull-down code, and the second comparator circuit 2300_2 can generate the first pull-down comparison result by comparing the reference voltage with the voltage of the first node resulting from the formation of the third impedance.

[0130] The impedance calibration circuit 2000 can generate a second pull-down comparison result by using a fourth impedance formed based on a second pull-down code to which a fourth offset OS4 is applied (S544). For example, the second code generation circuit 2100_2 can generate the second pull-down code to which the fourth offset OS4 is applied, the pull-down driver 2200_3 can form the fourth impedance by using the second pull-down code, and the second comparator circuit 2300_2 can generate the second pull-down comparison result by comparing the reference voltage with the voltage of the first node resulting from the formation of the fourth impedance.

[0131] The impedance calibration circuit 2000 can detect an impedance error based on the first pull-down comparison result and the second pull-down comparison result (S546). For example, the detection circuit 2400 can detect the impedance error by performing a logical operation using the first pull-down comparison result and the second pull-down comparison result. In particular, the impedance calibration circuit 2000 can detect the impedance error in the pull-down phase.

[0132] Having thus described the example embodiments of the inventive concept, it will be apparent that they can be varied in many ways. Such variations are not to be considered a departure from the spirit and scope of the example embodiments of the inventive concept, and all such modifications are intended to be included within the scope of the following claims.

Claims

1. A parameter monitoring circuit, comprising: a code generating circuit configured to generate a first code to which a first offset is applied and a second code to which a second offset is applied, wherein the first offset has a positive value and the second offset has a negative value; a parameter adjustment circuit configured to generate a first parameter and a second parameter by applying the first code and the second code to a current parameter, respectively, wherein the current parameter, the first parameter, and the second parameter are duty cycles of clock signals, or the current parameter, the first parameter, and the second parameter are impedances; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and The parameter error detection circuit is configured to detect an error in the current parameter based on the first comparison result and the second comparison result.

2. The parameter monitoring circuit according to claim 1, wherein: The first offset and the second offset have the same size.

3. The parameter monitoring circuit according to claim 1, wherein: The comparator circuit comprises: A comparator is configured to generate a comparison result by comparing the reference parameter value with a parameter to which a code provided from the parameter adjustment circuit is applied.

4. The parameter monitoring circuit according to claim 1, wherein: The parameter error detection circuit includes: a memory, configured to store the first comparison result; and The first logic circuit is configured to generate a parameter error detection signal based on the first comparison result and the second comparison result, wherein the first comparison result is stored in the memory.

5. The parameter monitoring circuit according to claim 4, wherein: The first logic circuit includes: An exclusive OR gate circuit is configured to perform an exclusive OR operation by using the first comparison result and the second comparison result, and generate a result value of the exclusive OR operation as the parameter error detection signal.

6. The parameter monitoring circuit according to claim 5, wherein: The first logic circuit is further configured to output the parameter error detection signal as an error correction guide signal to the outside of the parameter monitoring circuit, where the error correction guide signal is used to guide an operation of correcting the error of the current parameter.

7. The parameter monitoring circuit according to claim 6, wherein: The code generation circuit is further configured to receive a code that has been retrained by a host external to the parameter monitoring circuit based on the error correction pilot signal.

8. The parameter monitoring circuit according to claim 1, wherein: The parameter error detection circuit is further configured to determine whether the current parameter is in a normal condition based on the first offset having a positive first offset and the second offset having a negative first offset, The code generation circuit is further configured to generate a third code to which a third offset is applied and a fourth code to which a fourth offset is applied, the third offset having a positive second offset amount and the fourth offset having a negative second offset amount, The parameter adjustment circuit is further configured to generate a third parameter and a fourth parameter by applying the third code and the fourth code to the current parameter respectively. The comparator circuit is further configured to generate a third comparison result based on the third parameter and to generate a fourth comparison result based on the fourth parameter, and The parameter error detection circuit is further configured to re-detect an error in the current parameter based on the third comparison result and the fourth comparison result.

9. The parameter monitoring circuit according to claim 1, wherein: The operating frequency of the parameter monitoring circuit is 1 GHz or greater.

10. A duty cycle correction circuit, comprising: a code generating circuit configured to generate a first code to which a first offset is applied and a second code to which a second offset is applied, wherein the first offset has a positive value and the second offset has a negative value; a duty cycle adjustment circuit configured to generate a first clock signal by correcting a duty cycle of a current clock signal using the first code, and to generate a second clock signal by correcting the duty cycle of the current clock signal using the second code; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between a first duty cycle of the first clock signal and a target duty cycle value, and the second comparison result indicating a comparison result between a second duty cycle of the second clock signal and the target duty cycle value; and The duty cycle error detection circuit is configured to detect a duty cycle error of the current clock signal based on the first comparison result and the second comparison result.

11. The duty cycle correction circuit according to claim 10, wherein: The first offset and the second offset have the same size.

12. The duty cycle correction circuit according to claim 10, wherein: The comparator circuit comprises: a charge pump configured to generate a first charge pump signal and a second charge pump signal by performing a charge pump operation based on a clock signal having a duty ratio adjusted and provided from the duty ratio adjustment circuit; and The comparator is configured to output a comparison result by comparing the first charge pump signal with the second charge pump signal.

13. The duty cycle correction circuit according to claim 10, wherein: The duty cycle error detection circuit comprises: a memory, configured to store the first comparison result; and A logic circuit is configured to generate a duty ratio error detection signal by performing an exclusive OR operation using the first comparison result and the second comparison result.

14. The duty cycle correction circuit according to claim 10, wherein: In response to a duty cycle monitoring command input from outside the duty cycle correction circuit, the code generation circuit generates the first code to which the first offset is applied, and after generating the first code, generates the second code to which the second offset is applied.

15. The duty cycle correction circuit according to claim 10, wherein: The duty cycle correction circuit is arranged in a nonvolatile memory device, and The code generation circuit is further configured such that, after a data operation command is input to the nonvolatile memory device, the code generation circuit generates the first code and the second code within a latency interval of a data operation according to the data operation command.

16. An impedance calibration circuit, comprising: a first code generating circuit configured to generate a first pull-up code to which a first offset is applied and a second pull-up code to which a second offset is applied, wherein the first offset has a positive value and the second offset has a negative value; a first pull-up driver configured to form a first impedance by using the first pull-up code and to form a second impedance by using the second pull-up code; an impedance pin connected to the first pull-up driver and an external impedance; a first comparator circuit configured to generate a pull-up comparison result based on the voltage of the impedance pin and a reference voltage value; and An impedance error detection circuit is configured to detect an impedance error based on a first pull-up comparison result and a second pull-up comparison result, wherein the first pull-up comparison result is generated based on the first impedance formed by the first pull-up driver, and the second pull-up comparison result is generated based on the second impedance formed by the first pull-up driver.

17. The impedance calibration circuit according to claim 16, wherein: The first offset and the second offset have the same absolute value.

18. The impedance calibration circuit according to claim 16, further comprising: a second code generating circuit configured to generate a first pull-down code to which a third offset is applied and a second pull-down code to which a fourth offset is applied; a pull-down driver configured to form a third impedance by using the first pull-down code and to form a fourth impedance by using the second pull-down code; a second pull-up driver configured to form a pull-up impedance based on the pull-up code generated by the first code generating circuit; as well as a second comparator circuit configured to generate a pull-down comparison result by comparing the reference voltage value with a voltage of a node to which the pull-down driver and the second pull-up driver are commonly connected; Wherein, the impedance error detection circuit is further configured to detect an impedance error based on a first pull-down comparison result and a second pull-down comparison result, wherein the first pull-down comparison result is generated based on the third impedance formed by the pull-down driver, and the second pull-down comparison result is generated based on the fourth impedance formed by the pull-down driver.

Images