Display device

Abstract

A display device can include a substrate, a pixel, a first common voltage line, an external common voltage trunk, a first external common voltage line, and a second external common voltage line. The substrate can include a display area and a non-display area. The pixel can be disposed on the display area. The first common voltage line can be at least partially disposed on the display area. The external common voltage trunk can be disposed on the non-display area, can be electrically connected to the pixel through the first common voltage line, and can include a recess. The first external common voltage line can protrude from the external common voltage trunk. The second external common voltage line can protrude from the external common voltage trunk. The recess can be disposed between the second external common voltage line and the first common voltage line.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0114735, filed on September 18, 2019, in the Korean Intellectual Property Office; the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] TECHNICAL FIELD BACKGROUND

[0004] A display device can display an image. Present display devices can include light emitting diode display devices.

[0005] Light emitting diode display devices do not require a separate light source, and thus, can have minimized thickness and weight. Advantages of light emitting diode display devices can further include low power consumption, high brightness, and / or high response speed.

[0006] Generally, a light emitting diode display device includes a substrate, thin film transistors disposed on the substrate, insulating layers disposed between wires connected to the thin film transistors, and light emitting elements connected to the thin film transistors, respectively. For example, the light emitting elements can be organic light emitting elements.

[0007] A display device can include a display area and a non-display area. As the non-display area is minimized, the density of a current flowing in the non-display area can be significantly high. Thus, a lot of heat can be generated in the non-display area.

[0008] This Background section is intended to provide a background to the embodiments of the application that are further described below. The Background section can include information that is not prior art to the application in the country to which this application pertains and that is not known to be the prior art by virtue of being known in other countries. SUMMARY

[0009] Embodiments can relate to a display device in which undesired heat generation of a wire in a non-display area is prevented or mitigated.

[0010] A display device according to an embodiment includes the following elements: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a first common voltage line connected to a plurality of pixels disposed in the display area and one end of the external common voltage line, wherein the other end of the external common voltage line is branched into a first external common voltage line and a second external common voltage line, and includes a recess disposed between the second external common voltage line and the first common voltage line.

[0011] The first, second, and first common voltage lines can be disposed parallel to the second direction, and the groove can be disposed parallel to a first direction perpendicular to the second direction.

[0012] In the first common voltage line, a number of the first common voltage lines connected to the first external common voltage line can be greater than a number of the first common voltage lines connected to the second external common voltage line.

[0013] The display apparatus can further include an external initialization voltage line disposed between the external common voltage line and the display area and disposed parallel to the second direction.

[0014] The external common voltage line can include first and second ends facing each other, the first and second ends can be disposed at the same side of the display area, the display apparatus can further include an external driving voltage line disposed between the first and second ends, and the external driving voltage line and each of the pixels disposed in the display area can be connected through the driving voltage line.

[0015] The external common voltage line can be disposed to surround four sides of the display area.

[0016] A portion of the plurality of pixels can overlap the first common voltage line, and the portion of the pixels connected to the first common voltage line can not overlap the driving voltage line.

[0017] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0018] The first common voltage line can be disposed between the plurality of pixels and can be disposed parallel to the driving voltage line connected to each of the plurality of pixels.

[0019] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0020] At least one of the external common sub-voltage lines in the external common voltage line can be disposed parallel to one side of the display area, and another of the external common sub-voltage lines in the external common voltage line can be disposed parallel to another side facing the one side.

[0021] A portion of the plurality of pixels can overlap the first common voltage line, and the portion of the pixels overlapping the first common voltage line can not overlap the driving voltage line.

[0022] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0023] The first common voltage line can be disposed between the plurality of pixels and can be disposed parallel to the driving voltage line connected to each of the plurality of pixels.

[0024] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0025] The display apparatus according to another embodiment includes a substrate including a display area and a non-display area, an external common voltage line disposed in the non-display area, and a first common voltage line connected to a plurality of pixels disposed in the display area and one end of the external common voltage line, wherein the external common voltage line includes a first external common voltage line and a second external common voltage line separated via an opening therebetween.

[0026] The first external common voltage line, the second external common voltage line, and the first common voltage line can be disposed parallel to the second direction, and the opening can be disposed parallel to the second direction.

[0027] The opening can further include an area parallel to a first direction perpendicular to the second direction.

[0028] In the first common voltage line, a number of the first common voltage lines connected to the first external common voltage line can be greater than a number of the first common voltage lines connected to the second external common voltage line.

[0029] The display apparatus can further include an external initialization voltage line disposed between the external common voltage line and the display area and parallel to the second direction.

[0030] The external common voltage line can include a first end and a second end facing each other, the first end and the second end can be disposed at the same side of the display area, an external driving voltage line can be disposed between the first end and the second end, and the external driving voltage line and each of the pixels disposed in the display area can be connected through the driving voltage line.

[0031] The external common voltage line can be disposed to surround four sides of the display area.

[0032] A portion of the plurality of pixels can overlap the first common voltage line, and the portion of the plurality of pixels overlapping the first common voltage line can not overlap the driving voltage line.

[0033] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0034] The first common voltage line can be disposed between the plurality of pixels and parallel to the driving voltage line connected to each of the plurality of pixels.

[0035] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0036] At least one outer common sub-voltage line of the outer common voltage lines can be disposed parallel to one side of the display area, and another outer common sub-voltage line of the outer common voltage lines can be disposed parallel to another side facing the one side.

[0037] A portion of the plurality of pixels can overlap the first common voltage line, and the portion of the plurality of pixels overlapping the first common voltage line can not overlap the driving voltage line.

[0038] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0039] The first common voltage line can be disposed between the plurality of pixels and parallel to the driving voltage line connected to each of the plurality of pixels.

[0040] The display apparatus can further include a second common voltage line connected to the first common voltage line and crossing the first common voltage line.

[0041] Embodiments can relate to a display apparatus. The display apparatus can include a substrate, pixels, a first common voltage line, an outer common voltage trunk, a first outer common voltage line, and a second outer common voltage line. The substrate can include a display area and a non-display area. The pixels can be disposed on the display area. The first common voltage line can be disposed at least partially on the display area. The outer common voltage trunk can be disposed on the non-display area, can be electrically connected to the pixels through the first common voltage line, and can include a recess. The first outer common voltage line can protrude from the outer common voltage trunk. The second outer common voltage line can protrude from the outer common voltage trunk. The recess can be disposed between the second outer common voltage line and the first common voltage line.

[0042] A longitudinal direction of the second outer common voltage line can be perpendicular to a longitudinal direction of the recess.

[0043] A shortest electrical path between the first common voltage line and the first outer common voltage line can be shorter than a shortest electrical path between the first common voltage line and the second outer common voltage line.

[0044] The display apparatus can include an outer initialization voltage line disposed between the outer common voltage trunk and the display area and electrically connected to at least some of the pixels.

[0045] The display device can include the following elements: a driving voltage line disposed at least partially on the display area; and an external driving voltage trunk line disposed on the non-display area, disposed between a first end of the external common voltage trunk line and a second end of the external common voltage trunk line, electrically insulated from the external common voltage trunk line, and electrically connected to at least some of the pixels through the driving voltage line.

[0046] The external common voltage trunk line can include a first portion, a second portion, a third portion, a fourth portion, and a fifth portion. The first portion can be opposite the second portion in a first direction. The third portion can be opposite each of the fourth portion and the fifth portion in a second direction different from the first direction. The display area can be disposed between the first portion and the second portion in the first direction. The display area can be disposed between the third portion and each of the fourth portion and the fifth portion in the second direction.

[0047] Some of the pixels overlap the first common voltage line and do not overlap the driving voltage line.

[0048] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0049] The first common voltage line can be disposed between a first subset of the pixels and a second subset of the pixels. A longitudinal direction of the first common voltage line can be parallel to a longitudinal direction of the driving voltage line.

[0050] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0051] The external common voltage trunk line can include a first portion and a second portion. The second portion can be opposite the first portion. Two opposite sides of the display area can be disposed between the first portion of the external common voltage trunk line and the second portion of the external common voltage trunk line.

[0052] Some of the pixels overlap the first common voltage line and do not overlap the driving voltage line.

[0053] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0054] The first common voltage line can be disposed between a first subset of the pixels and a second subset of the pixels. A longitudinal direction of the first common voltage line can be parallel to a longitudinal direction of the driving voltage line.

[0055] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0056] Embodiments can relate to a display apparatus. The display apparatus can include the following elements: a substrate including a display area and a non-display area; pixels disposed on the display area; a first common voltage line disposed at least partially on the display area; a first external common voltage trunk configured to transmit a common voltage, disposed on the non-display area, and electrically connected to at least a first subset of the pixels through the first common voltage line; a second external common voltage trunk spaced apart from the first external common voltage trunk in at least a first direction, configured to transmit a common voltage, and disposed on the non-display area; a first external common voltage line protruding from the first external common voltage trunk in a second direction and disposed on the non-display area, wherein the second direction can be different from the first direction; and a second external common voltage line protruding from the second external common voltage trunk and disposed on the non-display area.

[0057] Each of a longitudinal direction of the first external common voltage line, a longitudinal direction of the second external common voltage line, and a longitudinal direction of the first common voltage line can be perpendicular to the first direction.

[0058] A first side of the first external common voltage trunk can be opposite a first side of the second external common voltage trunk in the first direction. A second side of the first external common voltage trunk can be opposite a second side of the second external common voltage trunk in the second direction.

[0059] A total number of the common voltage lines directly connected to the first external common voltage trunk can be greater than a total number of the common voltage lines directly connected to the second external common voltage trunk.

[0060] The display apparatus can include an external initialization voltage line disposed between the second external common voltage trunk and the display area and electrically connected to at least some of the pixels.

[0061] The display apparatus can include the following elements: a third external common voltage trunk spaced apart from the first external common voltage trunk in the first direction, wherein the first external common voltage trunk can be disposed between the second external common voltage trunk and the third external common voltage trunk; a drive voltage line disposed at least partially on the display area; and an external drive voltage trunk disposed on the non-display area, disposed between the first external common voltage trunk and the third external common voltage trunk, electrically insulated from each of the first external common voltage trunk and the third external common voltage trunk, and electrically connected to at least some of the pixels through the drive voltage line.

[0062] The display area can be disposed between a first portion of the second external common voltage trunk and a second portion of the second external common voltage trunk.

[0063] Some of the pixels overlap the first common voltage line and do not overlap the driving voltage line.

[0064] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0065] The first common voltage line can be disposed between the first subset of pixels and the second subset of pixels. A longitudinal direction of the first common voltage line can be parallel to a longitudinal direction of the driving voltage line.

[0066] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0067] At least one edge of the first external common voltage line can be parallel to a side of the display area, and can be disposed in the second direction between an edge of the second external common voltage trunk line and the side of the display area.

[0068] Some of the pixels overlap the first common voltage line and do not overlap the driving voltage line.

[0069] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0070] The first common voltage line can be disposed between the first subset of pixels and the second subset of pixels. A longitudinal direction of the first common voltage line can be parallel to a longitudinal direction of the driving voltage line.

[0071] The display device can include a second common voltage line electrically connected to and crossing the first common voltage line.

[0072] According to an embodiment, in the display device, heat generated in a wire disposed in the non-display area can be minimized and / or effectively dissipated. BRIEF DESCRIPTION OF DRAWINGS

[0073] Figure 1 is a view (e.g., a plan view) illustrating a display device according to an embodiment.

[0074] Figure 2 is a view illustrating a flow of current in a display device according to an embodiment.

[0075] Figure 3 is a view schematically illustrating a flow of current in a display device according to an embodiment.

[0076] Figure 4 is a view illustrating a location in a display device according to an embodiment that is the same as Area A of Figure 1 is a view illustrating a location in a display device according to an embodiment that is the same as Area A of

[0077] Figure 5 is a view showing the same position as the area A in the display device according to the embodiment. Figure 1

[0078] Figure 6 is a view (e.g., plan view) showing a display device according to the embodiment including an external common voltage line, an external drive voltage line, and an external initialization voltage line.

[0079] Figure 7 is a view showing a display device according to the embodiment.

[0080] Figure 8 is a view showing a display device according to the embodiment.

[0081] Figure 9 is a view showing a display device according to the embodiment.

[0082] Figure 10 is a view showing a display device according to the embodiment.

[0083] Figure 11 is a view showing a display device according to the embodiment.

[0084] Figure 12 is a view (e.g., plan view) showing a display area in a display device according to the embodiment.

[0085] Figure 13 is a view showing a display area in a display device according to the embodiment.

[0086] Figure 14 is a view showing a display area in a display device according to the embodiment.

[0087] Figure 15 is a view showing a display area in a display device according to the embodiment.

[0088] Figure 16 is a view (e.g., plan view) schematically showing a structure of a drive voltage connection line, a drive voltage line, and a first common voltage line in a display area.

[0089] Figure 17 is a view schematically showing a structure of a drive voltage connection line, a drive voltage line, a first common voltage line, and a second common voltage line within a display area in a display device according to the embodiment.

[0090] Figure 18 is a view schematically showing a structure of a drive voltage connection line, a drive voltage line, and a first common voltage line within a display area in a display device according to the embodiment. ​

[0091] Figure 19 FIG. 13 is a view schematically showing a structure of a driving voltage connection line, a driving voltage line, a first common voltage line, and a second common voltage line within a display area in a display device according to an embodiment.

[0092] Figure 20 FIG. 14 is an equivalent circuit diagram of one pixel of an emissive display device according to an embodiment.

[0093] Figure 21 FIG. 15 is a layout diagram of one pixel area of an organic light emitting device according to an embodiment.

[0094] Figure 22 FIG. 16 is a cross-sectional view taken along line XXII-XXII' in FIG. 15 according to an embodiment. Figure 21

[0095] Figure 23 FIG. 17 is a layout diagram of a pixel area of a display device according to an embodiment. DETAILED DESCRIPTION

[0096] Embodiments are described with reference to the drawings. The described embodiments can be modified in various ways.

[0097] The same or similar elements can be denoted by the same reference numerals.

[0098] In the drawings, the size of elements can be exaggerated for clarity.

[0099] Although the terms "first," "second," and the like can be used to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. A first element could be termed a second element without departing from the teachings of one or more embodiments. An element described as "first" can be termed a "second" without departing from the teachings of one or more embodiments. The terms "first," "second," and the like can be used to distinguish different categories or groups of elements. The terms "first," "second," and the like can be used to describe different categories or groups of elements without necessarily indicating a particular order or sequence. The terms "first," "second," and the like can be used to describe different categories or groups of elements without necessarily indicating a particular order or sequence.

[0100] When a first element is referred to as being "on" a second element, the first element can be directly on the second element or one or more intervening elements can be present between the first element and the second element. When a first element is referred to as being "directly on" a second element, there are no intervening elements (other than environmental elements such as air) present between the first element and the second element.

[0101] The words "comprise," "comprising," "contain," "containing," "have," "having," "include," "including," or "possess," can include the stated elements but not exclude any other elements unless explicitly described otherwise.​

[0102] The term "external common voltage line" can mean "external common voltage trunk line". The term "connect" can mean "electrically connect". The term "insulate" can mean "electrically insulate" or "electrically isolate". The term "recess" can mean "opening" or "hole". The term "opening" can mean "gap". The term "the same as" can mean "substantially the same as", "substantially the same as" or "similar to".

[0103] Figure 1 is a view showing a display device 1000 according to an embodiment. Referring to Figure 1 , the display device 1000 includes a display area DA and a non-display area NDA. A substrate (e.g., the substrate 110 shown in Figure 22 ) of the display device 1000 can include a display area and a non-display area corresponding to the display area DA and the non-display area NDA, respectively.

[0104] Referring to Figure 1 , the external common voltage line 7410 can substantially surround the display area DA. The external common voltage line 7410 is connected to the first common voltage line 741a and the second common voltage line 741b provided in the display area DA. The external common voltage line 7410 applies a common voltage ELVSS (shown in Figure 20 ) in the display area DA.

[0105] In Figure 1 , for ease of description, only some of the first common voltage lines 741a and some of the second common voltage lines 741b are shown, but the first common voltage lines 741a and the second common voltage lines 741b can form a grid over the entire display area DA. In an embodiment, the first common voltage line 741a or the second common voltage line 741b can be provided in the display area DA, but not both.

[0106] Each first common voltage line 741a can be longitudinal in the second direction DR2, and each second common voltage line 741b can be longitudinal in the first direction DR1. The third direction DR3 is perpendicular to a plane formed by the first direction DR1 and the second direction DR2.

[0107] In Figure 1 , for clarity, a portion labeled A is enlarged and shown separately. Referring to Figure 1 , on one edge of the display device 1000, the external common voltage line 7410 is directly connected to the first external common voltage line 7410a and the second external common voltage line 7410b. As Figure 1As shown in FIG. 10B, the external common voltage line 7410 can be directly connected to the first external common voltage line 7410a and the second external common voltage line 7410b on one edge of the pad portion connected to the display device 1000.

[0108] Referring to Figure 1 Part B, the external common voltage line 7410 includes a recess 7410c. Referring to Figure 2 , the recess 7410c can be longitudinal in a direction parallel to the second common voltage line 741b, i.e., in the first direction DR1.

[0109] The recess 7410c is disposed between the plurality of first common voltage lines 741a and the second external common voltage line 7410b, such that the electrical path is elongated between the plurality of first common voltage lines 741a and the second external common voltage line 7410b.

[0110] Therefore, it is possible to prevent or mitigate a potential heat generation problem due to excessive current flowing to the second external common voltage line 7410b at the same time. Advantageously, it is possible to obtain satisfactory reliability and / or durability of the display device 1000.

[0111] Figure 1 is a view showing the flow of current in the display device 1000 according to an embodiment. In the display device 1000, the external common voltage line 7410 does not include Figure 2 the recess shown in FIG. 10B. The flow of current in the display device 1000 shown in Figure 2 is shown by arrows. In Figure 2 , the thickness of the arrows indicates the amount of current, and the location where significant heat is generated is indicated by C.

[0112] Referring to Figure 1 , near the second external common voltage line 7410b, the current flowing from the external common voltage line 7410 (disposed in the non-display area NDA) and the current flowing from the first common voltage line 741a (at least partially disposed in the display area DA) are collected. As for the first external common voltage line 7410a, since the current flowing from the external common voltage line 7410 flows out to the second external common voltage line 7410b, only the current flowing from the common voltage line 741a is collected.

[0113] Therefore, the current accumulated toward the second external common voltage line 7410b is more than the current accumulated toward the first external common voltage line 7410a, and thus, heat generation near the second external common voltage line 7410b is more significant.

[0114] Referring to Figure 3 and Figure 3by providing a recess 7410c between the second external common voltage line 7410b and the plurality of first common voltage lines 741a, the current of the first common voltage line 741a can not significantly flow to the second external common voltage line 7410b, but can flow to the first external common voltage line 7410a. Thus, excessive heat generation can be prevented or mitigated.

[0115] Figure 3 is a view illustrating a flow of current in a display device according to an embodiment. Comparing Figure 2 and Figure 3 In the embodiment of Figure 2 the amount of current flowing to the second external common voltage line 7410b is significantly less than in the embodiment of Figure 3 Thus, according to the embodiment of Figure 4 excessive heat generation of the external common voltage line 7410 can be effectively prevented or mitigated.

[0116] Figure 1 is a view illustrating a location in a display device according to an embodiment that is the same as area A of Figure 4 Referring to Figure 4 In the display device, the first external common voltage line 7410a and the second external common voltage line 7410b are separate, and / or are directly connected to separate trunks, respectively.

[0117] Referring to Figure 4 The opening 7410d can separate the first external common voltage line 7410a from the second external common voltage line 7410b. The opening 7410d includes an edge parallel to the first direction DR1, and includes an edge parallel to the second direction DR2.

[0118] Referring to Figure 5 The current of the first common voltage line 741a is transmitted to the first external common voltage line 7410a, and is not transmitted to the second external common voltage line 7410b. Thus, near the second external common voltage line 7410b, undesirable heat generation can be prevented or mitigated.

[0119] Figure 1 is a view illustrating a location in a display device according to an embodiment that is the same as area A of Figure 5

[0120] Referring to Figure 1 ​, the first external common voltage line 7410a and the second external common voltage line 7410b are completely separated from each other via an opening 7410d, which can have opposite edges each parallel to the second direction DR2. Accordingly, the amount of current flowing into the first external common voltage line 7410a and the amount of current flowing into the second external common voltage line 7410b can be properly controlled to prevent excessive heat generation. Even though the first external common voltage line 7410a and the second external common voltage line 7410b are separated from each other, as shown in Figure 5

[0121] Referring to Figure 6 , the total number of the first common voltage lines 741a directly connected to the first external common voltage line 7410a can or can not be equal to the total number of the first common voltage lines 741a directly connected to the second external common voltage line 7410b. The number of the first common voltage lines 741a directly connected to the first external common voltage line 7410a can be significantly greater than the number of the first common voltage lines 741a directly connected to the second external common voltage line 7410b. In an embodiment, no first common voltage line 741a can be directly connected to the second external common voltage line 7410b, and some first common voltage lines 741a can be directly connected to the first external common voltage line 7410a only. The number of the first common voltage lines 741a directly connected to the first external common voltage line 7410a and the number of the first common voltage lines 741a directly connected to the second external common voltage line 7410b can be properly selected to minimize heat at the second external common voltage line 7410b.

[0122] Figure 6 is a view showing a display device 1000 including an external common voltage line 7410, an external drive voltage line 1720, and an external initialization voltage line 1270 according to an embodiment. In Figure 6 , only some of the wirings are shown for ease of illustration.

[0123] Referring to Figure 1 , in a non-display area NDA outside the display area DA, the external common voltage line 7410 can substantially surround the display area DA. The external drive voltage line 1720 can be disposed between opposite portions of the external common voltage line 7410.

[0124] ​The first and second external common voltage lines 7410a and 7410b can protrude from the external common voltage line 7410, and a groove 7410c can be provided between the first and second external common voltage lines 7410a and 7410b. The external common voltage line 7410 can be connected to the first and second common voltage lines (similar to the second common voltage line 741b shown in FIG. 17B) extending to the display area DA. In the display area DA, the first common voltage line 741a can be longitudinal in the second direction DR2, and the second common voltage line can be longitudinal in the first direction DR1. Figure 6

[0125] The external drive voltage line 1720 can be provided between opposite ends of the external common voltage line 7410. The external drive voltage line 1720 can be provided in a space between opposite portions of the external common voltage line 7410. The external drive voltage line 1720 transmits the drive voltage ELVDD to the display area DA.

[0126] The external drive voltage line 1720 is directly connected to the drive voltage line 172, which can be at least partially provided in the display area DA. The drive voltage line 172 can be longitudinal in the second direction DR2. Referring to Figure 12 Figure 6 , the drive voltage connection line 172c can be longitudinal in the first direction DR1 and can be at least partially provided in the display area DA. The drive voltage connection line 172c can cross the drive voltage line 172 to uniformly transmit the drive voltage in the display area DA. The drive voltage line 172 and the drive voltage connection line 172c form a mesh in the display area DA and are connected to each other, so that the pixels not directly connected to the drive voltage line 172 can also receive the drive voltage ELVDD.

[0127] The external initialization voltage line 1270 is provided between the external common voltage line 7410 and the display area DA. The external initialization voltage line 1270 is directly connected to the initialization voltage line 127, which can be at least partially provided in the display area DA and can transmit the initialization voltage to the display area DA. The initialization voltage line 127 can be longitudinal in the first direction DR1.

[0128] Although not shown in Figure 6 , the second common voltage line longitudinal in the first direction DR1 can be at least partially provided in the display area DA. The number and position of the wirings / lines shown in Figure 6 may be configured according to embodiments.

[0129] Although not shown in Figure 7 ​​Only portions of the first common voltage line 741a are shown, but the first common voltage line 741a can be connected to portions of the external common voltage line 7410 provided at opposite sides of the display area DA. The drive voltage line 172 can also extend in the second direction DR2 from one edge of the display area DA to the other edge of the display area DA. In an embodiment, the external initialization voltage line 1270 can be provided at two or more sides of the display area DA. The initialization voltage line 127 can extend in the first direction DR1 from one edge of the display area DA to the other edge of the display area DA.

[0130] Figure 7 is a view showing a display device according to an embodiment. Referring to Figure 8 , the first external common voltage line 7410a and the second external common voltage line 7410b are separated by a gap / opening. There is no first common voltage line 741a that can be directly connected to the second external common voltage line 7410b.

[0131] The first external common voltage line 7410a and the second external common voltage line 7410b are separated via an opening 7410d, which can have opposite edges parallel to the first direction DR1 and can have opposite edges parallel to the second direction DR2. The current of the first common voltage line 741a is transmitted to the first external common voltage line 7410a. Thus, the current is not concentrated in the second external common voltage line 7410b, and excessive heat generation can be prevented. The first external common voltage line 7410a and the second external common voltage line 7410b can be electrically connected to each other by the second common voltage line 741b provided in the display area DA, so the common voltage transmitted by the first external common voltage line 7410a is equal to the common voltage transmitted by the second external common voltage line 7410b.

[0132] Figure 8 is a view showing a display device according to an embodiment. Referring to Figure 8 , the first external common voltage line 7410a and the second external common voltage line 7410b are separated. Referring to Figure 7 , the opening 7410d can have opposite edges that are longitudinal in the second direction DR2. The operation and effects are similar to those in the embodiment of Figure 9 .

[0133] Figure 9 is a view showing a display device according to an embodiment. Referring to Figure 9 , the external common voltage line 7410 is provided at opposite sides of the display area DA.

[0134] The display area DA can not be provided between the external common voltage lines 7410 in the first direction DR1. Referring toFigure 10 The external common voltage line 7410 can include a first external common sub-voltage line 7410_S1 and a second external common sub-voltage line 7410_S2.

[0135] The first external common sub-voltage line 7410_S1 and the second external common sub-voltage line 7410_S2 can be electrically connected through a first common voltage line 741a, which can be disposed at least partially in the display area DA. Accordingly, the common voltage ELVSS can be substantially uniformly provided over the display area DA. Since no external common voltage line is disposed at the left and right sides of the display area DA, the left and right non-display areas NDA can be minimized.

[0136] Figure 10 is a view illustrating a display apparatus according to an embodiment. Referring to Figure 9 The first external common sub-voltage line 7410_S1 and the second external common sub-voltage line 7410_S2 are disposed at opposite sides of the display area DA. The second external common sub-voltage line 7410_S2 is spaced apart in the first direction DR1 and in the second direction DR2. The effect of the separation of the external common voltage line 7410 is the same as or similar to the effect described with reference to Figure 11 .

[0137] Figure 11 is a view illustrating a display apparatus according to an embodiment. Referring to Figure 9 The first external common sub-voltage line 7410_S1 and the second external common sub-voltage line 7410_S2 are disposed at opposite sides of the display area DA. The second external common sub-voltage line 7410_S2 is spaced apart in the first direction DR1. The effect of the separation of the external common voltage line 7410 is the same as or similar to the effect described with reference to Figures 12 to 15 .

[0138] One or more structures of the display area DA described with reference to one or more drawings in Figures 6 to 11 may be applicable to the display area DA described with reference to one or more drawings in Figure 12 .

[0139] Figure 12 is a view illustrating a display area DA in a display apparatus according to an embodiment. Referring to Figures 9 to 11 One of the drive voltage lines 172 connected to the plurality of pixels PX1, PX2, and PX3 is replaced with a first common voltage line 741a. Accordingly, the external common voltage line 7410 disposed via the display area DA in the second direction DR2 can be connected. When the separated external common voltage line 7410 is disposed at opposite sides of the display area DA, as Figures 6 to 8As shown in FIG. 7A, the first common voltage line 741a can be electrically connected to the separate external common voltage line 7410. Referring to FIG. 7B, Figure 12 Even if the external common voltage line 7410 is electrically connected in the non-display area NDA, the common voltage is transmitted to the first common voltage line 741a inside the display area DA, so that the common voltage can be uniformly provided in the display area DA.

[0140] Referring to FIG. 7B, Figure 13 The drive voltage connection line 172c can cross the drive voltage line 172. The drive voltage connection line 172c can be electrically connected to the drive voltage line 172 at the crossing point. Accordingly, the drive voltage transmitted to the drive voltage line 172 can be transmitted to the adjacent pixel. The drive voltage connection line 172c can be disposed on a different layer from the drive voltage line 172.

[0141] Figure 13 is a view illustrating a display area DA in a display device according to an embodiment. Except that a second common voltage line 741b is further included, Figure 12 The display area DA according to an embodiment of Figure 13 is the same as the embodiment of The first common voltage line 741a can be disposed parallel to the second direction DR2, and the second common voltage line 741b can be disposed parallel to the first direction DR1.

[0142] Figure 14 The display device according to an embodiment of

[0143] Figure 14 is a view illustrating a display area DA in a display device according to an embodiment. Referring to FIG. 8B, Figure 12 The display device is different from the display device of Figure 15 in that the structure (and / or material) of the first common voltage line 741a can be substantially different from the structure (and / or material) of each of the drive voltage lines 172 connected to the pixels PX1, PX2, and PX3. The first common voltage line 741a can be formed without removing any existing drive voltage line 172.

[0144] Figure 15 is a view illustrating a display area DA in a display device according to an embodiment. Except that the first common voltage line 741a is additionally formed without removing the drive voltage line 172 in the display area DA, Figure 13 is the same as the display device of Figures 12 to 15The display device according to the embodiment is the same as the display device 1.

[0145] In Figure 16 , the drive voltage connection line 172c, the drive voltage line 172, and the first common voltage line 741a can be provided directly on different material layers, respectively. The drive voltage connection line 172c and the drive voltage line 172 are provided on different layers, but are connected to each other by a contact hole, so that the drive voltage can be transmitted uniformly.

[0146] Figure 16 is a view schematically showing the structure of the drive voltage connection line 172c, the drive voltage line 172, and the first common voltage line 741a in the display region. In Figure 16 , the pixels PX1, PX2, and PX3 are labeled to distinguish the pixels to which the lines are connected.

[0147] Referring to Figure 16 , the drive voltage connection line 172c, the drive voltage line 172, and the first common voltage line 741a are located on different layers, respectively. For example, the drive voltage connection line 172c can be provided between the substrate and the drive voltage line 172; the drive voltage connection line 172c and the drive voltage line 172 can be provided between the substrate and the first common voltage line 741a. In the embodiment, the drive voltage line 172 and the first common voltage line 741a can be provided directly on the same layer.

[0148] Referring to Figure 17 , the width of the drive voltage connection line 172c overlapping the first common voltage line 741a can be narrower than the width of the drive voltage connection line 172c overlapping the drive voltage line 172. Thus, the risk of the first common voltage line 741a and the drive voltage connection line 172c shorting to each other can be reduced. The drive voltage connection line 172c and the drive voltage line 172 are connected to each other by a contact hole 28.

[0149] Figure 18 is a view schematically showing the structure of the drive voltage connection line 172c, the drive voltage line 172, the first common voltage line 741a, and the second common voltage line 741b in the display region in the display device according to the embodiment. The first common voltage line 741a is connected to the second common voltage line 741b.

[0150] The first common voltage line 741a and the second common voltage line 741b can be provided on the same layer, and can be connected directly to each other. The common voltage lines 741a and 741b can form a mesh. The common voltage lines 741a and 741b can be separated and insulated from the drive voltage line 172 by an intermediate insulating layer. The drive voltage line 172 can be provided closer to the substrate than the common voltage lines 741a and 741b.

[0151] Figure 18 is a view schematically showing a structure of a drive voltage connection line 172c, a drive voltage line 172, and a first common voltage line 741a within a display region in a display device according to an embodiment. Referring to Figure 19 , the first common voltage line 741a is disposed outside the pixels PX1, PX2, and PX3. The first common voltage line 741a is disposed without removing the existing drive voltage line 172. Each drive voltage line 172 is connected to the pixel PX1, PX2, or PX3, and the first common voltage line 741a is disposed between two pixel groups each including the pixels PX1, PX2, and PX3. The first common voltage line 741a can be disposed directly on the same layer as the drive voltage line 172.

[0152] Figure 20 is a view schematically showing a structure of a drive voltage connection line 172c, a drive voltage line 172, and a first common voltage line 741a within a display region in a display device according to an embodiment. The common voltage line includes the first common voltage line 741a and a second common voltage line 741b.

[0153] The first common voltage line 741a and the second common voltage line 741b can be disposed on the same layer and can be directly connected to each other. The display device can include a mesh structure in which the first common voltage line 741a crosses the second common voltage line 741b. The common voltage lines 741a and 741b can be separated and insulated from the drive voltage line 172 by an intermediate insulating layer. The drive voltage line 172 can be disposed closer to the substrate than the common voltage lines 741a and 741b.

[0154] Figure 20 is an equivalent circuit diagram of one pixel of an emissive display device according to an embodiment.

[0155] Referring to Figure 20 , the pixel PX of the emissive display device includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light emitting diode LED connected to several signal lines 127, 151, 152, 153, 158, 171, 172, and 741.

[0156] The emissive display device includes a display region in which an image is displayed, and the pixels PX are arranged in various forms in the display region.

[0157] The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, a switching transistor connected to the scan line 151 (i.e., including a second transistor T2 and a third transistor T3), and the remaining transistors are transistors required for operating the light emitting diode LED (hereinafter, referred to as compensation transistors). The compensation transistors T4, T5, T6, and T7 can include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0158] The plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 can include the scan line 151, the previous scan line 152, the emission control line 153, the bypass control line 158, the data line 171, the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741. The bypass control line 158 can be a part of the previous scan line 152, or can be electrically connected to the previous scan line 152.

[0159] The scan line 151 is connected to a gate driver, and transmits a scan signal Sn to the second transistor T2 and the third transistor T3. The previous scan line 152 is connected to a gate driver, and transmits a previous scan signal Sn-1 applied to a pixel PX located at a previous stage to the fourth transistor T4. The emission control line 153 is connected to an emission controller, and transmits an emission control signal EM that controls a time of emitting light of the light emitting diode LED to the fifth transistor T5 and the sixth transistor T6. The bypass control line 158 transmits a bypass signal GB to the seventh transistor T7.

[0160] The data line 171 is a wiring for transmitting a data voltage Dm generated by a data driver, and the brightness of the light emitting diode LED (also referred to as a light emitting element) varies according to the data voltage Dm. The driving voltage line 172 applies a driving voltage ELVDD. The initialization voltage line 127 transmits an initialization voltage Vint that initializes the driving transistor T1. The common voltage line 741 applies a common voltage ELVSS. The voltages applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 can be applied with a constant voltage, respectively.

[0161] The driving transistor T1 serves to adjust the size of a current output according to the applied data voltage Dm. The output driving current I dapplied to the light emitting diode LED to adjust the brightness of the light emitting diode LED according to the data voltage Dm. To this end, the first electrode S1 of the driving transistor T1 can allow the driving voltage ELVDD to be applied. The first electrode S1 is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2 to receive the data voltage Dm. The second electrode D1 (output electrode) of the driving transistor T1 can output a driving current I d is changed.

[0162] The second transistor T2 receives the data voltage Dm into the pixel PX. The gate electrode G2 is connected to the scan line 151, and the first electrode S2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is delivered to the first electrode S1 of the driving transistor T1.

[0163] The third transistor T3 transmits the compensation voltage (Dm + Vth) from the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst, where Vth is the threshold voltage of the driving transistor T1, which is not shown in Figure 20 The third transistor T3 transmits the compensation voltage (Dm + Vth) from the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst, where Vth is the threshold voltage of the driving transistor T1, which is not shown in

[0164] A fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 is connected to the previous scan line 152, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the previous scan signal Sn-1 received via the previous scan line 152. Therefore, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint has a low voltage value, thus being the voltage that turns on the driving transistor T1.

[0165] The fifth transistor T5 is used to transmit the drive voltage ELVDD to the drive transistor T1. Its gate electrode G5 is connected to the light-emitting control line 153, and its first electrode S5 is connected to the drive voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the drive transistor T1.

[0166] The sixth transistor T6 is used to drive the current I output from the driving transistor T1. d The signal is transmitted to the light-emitting diode (LED). The gate electrode G6 is connected to the light-emitting control line 153, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the LED.

[0167] If the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light-emitting control signal EM transmitted through the light-emitting control line 153 and the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, then the driving transistor T1 outputs a driving current I according to the voltage of the gate electrode G1 of the driving transistor T1 (i.e., the voltage of the second storage electrode E2 of the storage capacitor Cst). d The output drive current I d The current is transmitted to the light-emitting diode (LED) via the sixth transistor T6. When the current I... led When water flows through a light-emitting diode (LED), the LED emits light.

[0168] The seventh transistor T7 functions to initialize the anode of the light emitting diode LED. The gate electrode G7 is connected to the bypass control line 158, the first electrode S7 is connected to the anode of the light emitting diode LED, and the second electrode D7 is connected to the initialization voltage line 127. The bypass control line 158 can be connected to the previous scan line 152, and a bypass signal GB is applied with the same timing signal as the previous scan signal Sn-1. The bypass control line 158 can transmit a signal separate from the previous scan signal Sn-1 without being connected to the previous scan line 152. When the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode of the light emitting diode LED and is initialized.

[0169] The first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. Accordingly, the second storage electrode E2 determines the voltage of the gate electrode G1 of the driving transistor T1, and receives the data voltage Dm through the second electrode D3 of the third transistor T3 or the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0170] On the other hand, the anode of the light emitting diode LED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7, and the cathode is connected to the common voltage line 741 that transmits the common voltage ELVSS.

[0171] In Figure 21 In an embodiment, the pixel circuit includes seven transistors (T1 to T7) and one capacitor Cst. The number of transistors, the number of capacitors, and their connections can be configured according to embodiments.

[0172] Figure 22 is a layout view of one pixel region of an organic light emitting device according to an embodiment, and Figure 21 is a cross-sectional view taken along line XXII-XXII' in Figure 21

[0173] Referring to Figure 21 , the emissive display device includes a scan line 151 extending along a first direction D1 and transmitting a scan signal Sn, a previous scan line 152 transmitting a previous scan signal Sn-1, an emission control line 153 transmitting an emission control signal EM, and an initialization voltage line 127 transmitting an initialization voltage Vint. A bypass signal GB is transmitted through the previous scan line 152.

[0174] ​The emission display device includes a data line 171 extending in a second direction DR2 intersecting the first direction DR1 and transmitting a data voltage Dm, and a first common voltage line 741a transmitting a common voltage ELVSS. Figure 22 and Figure 21 The first pixel PX1 described in Embodiment 1 is the first pixel PX1 in which the drive voltage line 172 is replaced with the first common voltage line 741a. Figure 22 and Figure 21 The first pixel PX1 of Embodiment 1 is an embodiment in which the drive voltage line 172 connected to the pixel is replaced with the first common voltage line 741a. In Figure 21 In the second pixel PX2 shown in Embodiment 2, the drive voltage line 172 is not replaced with the first common voltage line 741a, and the existing drive voltage line 172 is provided. Hereinafter, the first pixel PX1 is described in comparison with the second pixel PX2.

[0175] The emission display device includes a drive transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting diode LED.

[0176] Each channel of the drive transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is provided in an elongated semiconductor layer 130. In addition, at least a part of the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 is provided in the semiconductor layer 130. The semiconductor layer 130 (a portion in which a shadow is added in FIG. 8) can be formed to be curved into various shapes. The semiconductor layer 130 can include a polycrystalline semiconductor such as polysilicon or an oxide semiconductor. Figure 20

[0177] The semiconductor layer 130 includes a channel doped with an n-type impurity or a p-type impurity and a first doped region and a second doped region whose doped concentration is higher than that of the channel. The first doped region and the second doped region correspond to the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7, respectively. One of the first doped region and the second doped region can be a source region, and the other doped region can be a drain region. Also, in the semiconductor layer 130, regions between the first electrodes and the second electrodes of different transistors from each other can be doped so that the two transistors can be electrically connected to each other.

[0178] ​Each channel of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 overlaps with each gate electrode of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7, and is provided between each first electrode and each second electrode of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7. The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 can have substantially the same stacked structure. Hereinafter, the driving transistor T1 is described in detail, and the remaining transistors T2, T3, T4, T5, T6, and T7 are briefly described.

[0179] The driving transistor T1 includes a channel, a first gate electrode 155, a first electrode S1, and a second electrode D1. The channel of the driving transistor T1 is between the first electrode S1 and the second electrode D1, and overlaps with the first gate electrode 155 in a plan view. The channel is bent to form a longer channel length in a confined area. As the channel length increases, a driving range of a gate voltage Vg applied to the first gate electrode 155 of the driving transistor T1 becomes wider, and a driving current I d increases constantly according to the gate voltage Vg. Accordingly, the gray scale of light emitted from the light emitting diode LED can be more precisely controlled by changing the size of the gate voltage Vg, and the display quality of the emission display device can be improved. In addition, since the channel does not extend in one direction but extends in various directions, there is an advantage in which the directional influence is eliminated in the manufacturing process, thereby reducing the influence of process dispersion. Accordingly, it is possible to prevent the deterioration of image quality such as unevenness defects (for example, a luminance difference occurs depending on a pixel even if the same data voltage Dm is applied) that can be caused by the characteristic difference of the driving transistor T1 depending on the area of the display device due to process dispersion. The shape of such a channel can be changed without being limited to the illustrated Ω type.

[0180] The first gate electrode 155 overlaps with the channel in a plan. The first electrode S1 and the second electrode D1 are located on respective sides of the channel. An extension portion of the storage line 126 is insulated from the first gate electrode 155, and is provided above the first gate electrode 155. The extension portion of the storage line 126 overlaps with the gate electrode 155 via a second gate insulating layer interposed therebetween in a plan, thereby constituting a storage capacitor Cst. The extension portion of the storage line 126 is a first storage electrode (E1) of the storage capacitor Cst, and the first gate electrode 155 is a second storage electrode (E2). Figure 20 Figure 21 ​(E2). An extension of the storage line 126 has an opening 56, such that the first gate electrode 155 is connected to the first data connection member 71. Within the opening 56, the upper surface of the first gate electrode 155 and the first data connection member 71 are electrically connected through a contact hole 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0181] The gate electrode of the second transistor T2 can be part of the scan line 151. The data line 171 contacts the first electrode S2 of the second transistor T2 through the contact hole 62. The first electrode S2 and the second electrode D2 can be disposed on the semiconductor layer 130.

[0182] The third transistor T3 can be composed of two adjacent transistors. Figure 21 Within pixel PX, the two portions of the third transistor T3, bent relative to semiconductor layer 130, are located on the left and bottom sides. These two portions respectively function as the third transistor T3, and have a structure in which the first electrode S3 of one portion of the third transistor T3 is connected to the second electrode D3 of the other portion of the third transistor T3. The gate electrodes of the two transistors T3 can be a portion of scan line 151 or a portion protruding upwards from scan line 151. This structure can be referred to as a dual-gate structure and can be used to block leakage current. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through contact hole 63.

[0183] The fourth transistor T4 consists of two fourth transistors T4, which are formed at the intersection of the previous scan line 152 and the semiconductor layer 130. The gate electrode of the fourth transistor T4 may be a portion of the previous scan line 152. A portion of the first electrode S4 of the fourth transistor T4 is connected to the second electrode D4 of the other portion of the fourth transistor T4. This structure can be referred to as a dual-gate structure and can be used to block leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through a contact hole 65, and the first data connection member 71 is connected to the second electrode D4 of the fourth transistor T4 through a contact hole 63.

[0184] In this way, by using a dual-gate structure as the third transistor T3 and the fourth transistor T4, leakage current can be effectively prevented by blocking the electron movement path of the channel in the off state.

[0185] The gate electrode of the fifth transistor T5 can be part of the light emission control line 153. The drive voltage connection line 172c is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 77, and the second electrode D5 is connected to the first electrode S1 of the drive transistor T1 through the semiconductor layer 130.

[0186] Since the drive voltage line 172 connected to the pixel is replaced with the first common voltage line 741a, the first pixel PX1 receives the drive voltage ELVDD from the adjacent pixel PX2 through the drive voltage connection line 172c connected to the drive voltage line 172 of the adjacent pixel PX2.

[0187] However, in the second pixel PX2, the drive voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 67, and the second electrode D5 is connected to the first electrode S1 of the drive transistor T1 through the semiconductor layer 130.

[0188] The gate electrode of the sixth transistor T6 can be part of the light emission control line 153. The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69, and the first electrode S6 is connected to the second electrode D1 of the drive transistor T1 through the semiconductor layer 130.

[0189] The gate electrode of the seventh transistor T7 can be part of the previous scan line 152. The first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6, and the second electrode D7 is connected to the first electrode S4 of the fourth transistor T4.

[0190] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 overlapping with the second gate insulating layer 142 interposed therebetween. The second storage electrode E2 can correspond to the gate electrode 155 of the drive transistor T1, and the first storage electrode E1 can be an extension of the storage line 126. The second gate insulating layer 142 becomes a dielectric material, and the capacitance is determined by the voltage between the first storage electrode E1 and the second storage electrode E2 and the charge stored in the storage capacitor Cst. By using the first gate electrode 155 as the second storage electrode E2, it is possible to secure a space for forming the storage capacitor Cst in a space narrowed by the channel of the drive transistor T1 occupying a large area in the pixel.

[0191] The first storage electrode E1 of the storage capacitor Cst receives the drive voltage through the drive voltage connection line 172c. Accordingly, the storage capacitor Cst stores a charge corresponding to the difference between the drive voltage ELVDD transmitted to the first storage electrode E1 through the drive voltage connection line 172c and the gate voltage Vg of the gate electrode 155.

[0192] However, the drive voltage line 172 is connected to the first storage electrode E1 of the storage capacitor Cst through the contact hole 68. Thus, the storage capacitor Cst stores a charge corresponding to a difference between the drive voltage ELVDD transmitted to the first storage electrode E1 through the drive voltage line 172 and the gate voltage Vg of the gate electrode 155.

[0193] The second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64. The first electrode is connected to the third data connection member 73 through the contact hole 81. The first electrode can be a pixel electrode.

[0194] A parasitic capacitor control pattern 79 can be provided between the double gate electrodes of the third transistor T3. There is a parasitic capacitor in the pixel. If a voltage applied to the parasitic capacitor changes, the image quality characteristics can change. In Figure 22 In the first pixel PX1, the first common voltage line 741a is provided instead of the drive voltage line 172 so that the drive voltage line 172 and the parasitic capacitor control pattern 79 are not connected, whereas in the second pixel PX2, the parasitic capacitor control pattern 79 is connected to the drive voltage line 172 through the contact hole 66. Thus, by applying the drive voltage ELVDD having a constant DC voltage to the parasitic capacitor, it is possible to prevent the image quality characteristics from changing. The parasitic capacitor control pattern 79 can be provided in a region different from the region shown, and a voltage other than the drive voltage ELVDD can be applied.

[0195] One end of the first data connection member 71 is connected to the gate electrode 155 through the contact hole 61, and the other end is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the contact hole 63.

[0196] One end of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the other end is connected to the initialization voltage line 127 through the contact hole 64.

[0197] The third data connection member 73 is connected to the second electrode of the sixth transistor T6 through the contact hole 69.

[0198] Referring to Figure 21 and Figure 22 A cross-sectional structure of an emission display device according to an embodiment is described.

[0199] The emission display device includes a first substrate 110.

[0200] The first substrate 110 can include a plastic layer and a barrier layer. The plastic layer and the barrier layer can be alternately stacked.

[0201] The plastic layer can include one selected from a group including polyether sulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), poly(arylene ether sulfone), and a combination of some of these materials.

[0202] The barrier layer can include at least one of silicon oxide, silicon nitride, and aluminum oxide, and can include any inorganic material without being limited thereto.

[0203] A buffer layer 112 is provided on the first substrate 110. The buffer layer 112 can include an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide, or an organic insulating material such as polyimide acryl.

[0204] A semiconductor layer 130 including channels of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, and first and second electrodes is provided on the buffer layer 112.

[0205] A first gate insulating layer 141 covering the semiconductor layer 130 is provided on the semiconductor layer 130. A first gate conductor including a first gate electrode 155, a scan line 151, a previous scan line 152, and a light emission control line 153 is provided on the first gate insulating layer 141.

[0206] A second gate insulating layer 142 covering the first gate conductor is provided on the first gate conductor. The first gate insulating layer 141 and the second gate insulating layer 142 can include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide, or an organic insulating material.

[0207] A second gate conductor including a storage line 126, an initialization voltage line 127, and a parasitic capacitor control pattern 79 is provided on the second gate insulating layer 142.

[0208] An interlayer insulating layer 160 covering the second gate conductor is provided on the second gate conductor. The interlayer insulating layer 160 can include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide, or can include an organic insulating material.

[0209] A data conductor including a data line 171, a driving voltage line 172, a driving voltage connection line 172c, a first data connection member 71, a second data connection member 72, and a third data connection member 73 is provided on the interlayer insulating layer 160. The first data connection member 71 can be connected to the first gate electrode 155 through a contact hole 61.

[0210] A passivation layer 180 covering the data conductor is provided on the data conductor. The passivation layer 180 can be a planarization layer, and can include an organic insulating material or an inorganic insulating material.

[0211] A first electrode 191 is provided on the passivation layer 180. The first electrode 191 is connected to the third data connection member 73 through the contact hole 81 formed in the passivation layer 180.

[0212] A partition 350 is formed on the passivation layer 180 and the first electrode 191. The partition 350 has an opening 351 overlapping the first electrode 191. An emission layer 370 is provided on the opening 351. A second electrode 270 is provided on the emission layer 370 and the partition 350. The first electrode 191, the emission layer 370, and the second electrode 270 form a light emitting element LED. The first electrode 191 can be a pixel electrode, and the second electrode 270 can be a common electrode.

[0213] According to an embodiment, the pixel electrode can be an anode as a hole injection electrode, and the common electrode can be a cathode as an electron injection electrode. Conversely, the pixel electrode can be a cathode and the common electrode can be an anode. When holes and electrons are injected from the pixel electrode and the common electrode into the emission layer, respectively, excitons in which the injected holes and electrons are combined emit light when they transition from an excited state to a ground state.

[0214] An encapsulation layer 400 protecting the light emitting element LED is provided on the second electrode 270. According to an embodiment, the encapsulation layer 400 can be in contact with the second electrode 270 as shown in FIG. 1B, or can be spaced apart from the second electrode 270. Figure 23

[0215] The encapsulation layer 400 can be a thin film encapsulation layer in which an inorganic film and an organic film are stacked, and can include three layers composed of an inorganic film, an organic film, and an inorganic film. According to an embodiment, a cover layer and a functional layer can be located between the second electrode 270 and the encapsulation layer 400.

[0216] Figure 23 is a layout diagram of a pixel region of a display device according to an embodiment. Referring to Figure 21 , the display device includes a plurality of signal lines 127, 151, 152, 153, 171, 172, and 741a. The plurality of signal lines 127, 151, 152, 153, 171, 172, and 741a can include a scan line 151, a previous scan line 152, and a light emission control line 153 provided in a first direction DR1, and a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741a provided in a second direction DR2.

[0217] ​The display device includes a driver transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst.

[0218] Each channel of the driver transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 extends and is provided in the semiconductor layer 130. At least a part of the first and second electrodes of the plurality of transistors T1, T2, T3, T4, T5, and T6 is provided in the semiconductor layer 130.

[0219] The signal lines and the semiconductor layer are connected through the plurality of contact holes 82, 83, 84, 85, 86, 87, and 88.

[0220] The structure of the transistors and the signal lines can be similar to the structure shown in Figure 23 .

[0221] Referring to Figure 21 , the first common voltage line 741a is provided outside the regions of the pixels PX1, PX2, and PX3. That is, in the display device of the embodiment of ​ , the drive voltage lines 172 of some of the pixels PX1 are replaced with the first common voltage line 741a, and the pixels PX1 receive the drive voltage from the adjacent pixels through the drive voltage connection lines 172c.

[0222] The separate first common voltage line 741a is provided outside the regions of the pixels PX1, PX2, and PX3. Thus, the first common voltage line 741a can be provided without removing the existing drive voltage lines 172 of the pixels PX1, PX2, and PX3.

[0223] Although example embodiments have been described, the actual embodiments are not limited to the disclosed embodiments. The actual embodiments cover various modifications and equivalent arrangements within the scope of the disclosure.

Claims

1. A display device, wherein, The display device includes: a substrate including a display area and a non-display area; pixels disposed on the display area for displaying an image; a first common voltage line disposed at least partially on the display area and connected to the pixels, and the first common voltage line is parallel to a second direction; an external common voltage trunk disposed on the non-display area and surrounding the display area, the external common voltage trunk is electrically connected to the pixels through the first common voltage line to apply a common voltage; a first external common voltage line protruding from a portion of the external common voltage trunk and located on the non-display area, the first external common voltage line collects current from the first common voltage line; and a second external common voltage line protruding from the portion of the external common voltage trunk and located on the non-display area, the second external common voltage line collects current from the external common voltage trunk and the first common voltage line, wherein the external common voltage trunk includes a groove disposed between the second external common voltage line and the first common voltage line and extending in a plane along a first direction perpendicular to the second direction, so that the shortest electrical path between the first common voltage line and the first external common voltage line is shorter than the shortest electrical path between the first common voltage line and the second external common voltage line, to reduce the current collected by the second external common voltage line from the first common voltage line.

2. The display device according to claim 1, wherein The longitudinal direction of the second external common voltage line is perpendicular to the longitudinal direction of the groove.

3. The display device according to claim 1, wherein The display device further includes: an external initialization voltage line disposed between the external common voltage trunk and the display area and electrically connected to at least some of the pixels.

4. The display device according to claim 1, wherein The display device further includes: a drive voltage line disposed at least partially on the display area; and an external drive voltage trunk disposed on the non-display area, disposed between a first end of the external common voltage trunk and a second end of the external common voltage trunk, electrically insulated from the external common voltage trunk, and electrically connected to at least some of the pixels through the drive voltage line.

5. A display device, wherein, The display device includes: a substrate including a display area and a non-display area; pixels disposed on the display area for displaying an image; a first common voltage line disposed at least partially on the display area and connected to the pixels, and the first common voltage line is parallel to a second direction; a first external common voltage trunk disposed on the non-display area and surrounding the display area, the first external common voltage trunk is electrically connected to at least a first subset of the pixels through the first common voltage line to apply a common voltage; a second external common voltage trunk spaced apart from the first external common voltage trunk in at least the first direction via an opening and disposed on the non-display region, wherein the first external common voltage trunk and the second external common voltage trunk are connected to each other in the display region by a second common voltage line disposed in the display region, and wherein a common voltage transmitted through the second external common voltage trunk is equal to the common voltage transmitted through the first external common voltage trunk when the display device is in operation; a first external common voltage line protruding from a portion of the first external common voltage trunk in the second direction and disposed on the non-display region, wherein the second direction is different from the first direction; and a second external common voltage line protruding from the second external common voltage trunk and disposed on the non-display region, wherein a total number of the first common voltage lines directly connected to the first external common voltage trunk is greater than a total number of the first common voltage lines directly connected to the second external common voltage trunk, or none of the first common voltage lines is directly connected to the second external common voltage trunk.

6. The display device of claim 5, wherein, Each of a longitudinal direction of the first external common voltage line, a longitudinal direction of the second external common voltage line, and a longitudinal direction of the first common voltage line is perpendicular to the first direction.

7. The display device according to claim 5, wherein A first side of the first external common voltage trunk opposes a first side of the second external common voltage trunk in the first direction, and wherein a second side of the first external common voltage trunk opposes a second side of the second external common voltage trunk in the second direction.

8. The display device according to claim 5, wherein The display device further includes an external initialization voltage line disposed between the second external common voltage trunk and the display region and electrically connected to at least some of the pixels.

Images