Nonvolatile memory device and method for reading the same

Abstract

A nonvolatile memory device includes: a nonvolatile memory cell including a first cell transistor and a second cell transistor, the first cell transistor and the second cell transistor being electrically coupled to a bit line in parallel and being configured to have a first physical size and a second physical size, respectively; a cell transistor selector coupled between the nonvolatile memory cell and a ground voltage terminal to control an electrical connection between the first cell transistor and the ground voltage terminal and an electrical connection between the second cell transistor and the ground voltage terminal; and a read voltage selection circuit adapted to selectively provide one of a first read voltage and a second read voltage to the bit line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0117093, filed on September 23, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate generally to nonvolatile memory devices, and more particularly, to nonvolatile memory devices having improved read operation accuracy and methods of reading the nonvolatile memory devices. Background Art

[0004] Semiconductor memory devices are generally classified as random access memory (RAM) devices or read-only memory (ROM) devices according to their data volatility. RAM devices are volatile memory devices that lose the data stored therein when their power supply is interrupted. In contrast, ROM devices are non-volatile memory devices that retain the data stored therein even when their power supply is interrupted. According to the data input method, that is, the data programming method, ROM devices can also be classified as programmable ROM (PROM) devices or mask ROM devices. PROM devices can be manufactured and sold without programming, and can be directly programmed by customers (i.e., users) after their manufacture. Mask ROM devices can be programmed using an injection mask manufactured based on the data required by the user during their manufacture, and can be subsequently provided to customers or users. PROM devices can include non-rewritable PROM (OTPROM) devices, erasable PROM (EPROM) devices, and electrically erasable PROM (EEPROM) devices. Once an OTPROM device is programmed, the data in the programmed OTPROM device cannot be changed. Therefore, after the OTPROM device is programmed, only the read operation is repeatedly performed in the OTPROM device. When a read operation of the OTPROM device is repeatedly performed, the OTPROM device may fail due to the occurrence of a read disturbance phenomenon and degradation of data retention characteristics. Summary of the invention

[0005] According to one embodiment, a nonvolatile memory device includes a nonvolatile memory cell, a cell transistor selector, and a read voltage selection circuit, the nonvolatile memory cell including a first cell transistor and a second cell transistor. The first cell transistor and the second cell transistor are electrically coupled to a bit line in parallel and are configured to have a first physical size and a second physical size, respectively. The cell transistor selector is coupled between the nonvolatile memory cell and a ground voltage terminal to control the electrical connection between the first cell transistor and the ground voltage terminal and the electrical connection between the second cell transistor and the ground voltage terminal. The read voltage selection circuit is adapted to selectively provide one of the first read voltage and the second read voltage to the bit line.

[0006] According to another embodiment, a nonvolatile memory device includes a nonvolatile memory cell array, a cell transistor selector, and a read voltage selection circuit. The nonvolatile memory cell array is configured to include first to M-th selection gate lines parallel to rows spaced apart from each other in a column direction, first to N-th bit lines spaced apart from each other in a row direction and crossing the first to M-th selection gate lines, and a plurality of nonvolatile memory cells located at respective intersections between the first to M-th selection gate lines and the first to N-th bit lines. Each of the plurality of nonvolatile memory cells includes: a first cell transistor having a first physical size and a second cell transistor having a second physical size, the first cell transistor and the second cell transistor being electrically coupled in parallel to a corresponding bit line among the first to N-th bit lines; and a selection transistor coupled to one of the first to M-th selection gate lines to control an electrical connection between the corresponding bit line and the first cell transistor and the second cell transistor. The cell transistor selector is coupled between the ground voltage terminal and the nonvolatile memory cell to control the electrical connection between the ground voltage terminal and the first cell transistor and the electrical connection between the ground voltage terminal and the second cell transistor. The read voltage selection circuit is adapted to selectively provide one of the first read voltage and the second read voltage to a bit line selected from the first bit line to the Nth bit line to perform a read operation of a nonvolatile memory cell coupled to the selected bit line.

[0007] According to another embodiment, a nonvolatile memory device includes a nonvolatile memory cell array, a cell transistor selector, and a read voltage selection circuit. The nonvolatile memory cell includes a first cell transistor having a first ratio of a first channel width to a first channel length and a second cell transistor having a second ratio of a second channel width to a second channel length, wherein the first ratio is different from the second ratio. The cell transistor selector is adapted to electrically connect and disconnect the first cell transistor and the second cell transistor to a ground voltage terminal. The read voltage selection circuit is adapted to perform a read operation of the first cell transistor and the second cell transistor selected by the cell transistor selector to determine whether the nonvolatile memory cell has a programmed state or an initialized state according to whether the first cell transistor and the second cell transistor are turned on or off.

[0008] According to another embodiment, a method for reading a nonvolatile memory device is provided, the nonvolatile memory device includes a nonvolatile memory cell, and the nonvolatile memory cell is configured to include a first cell transistor having a first current driving force and a second cell transistor having a second current driving force greater than the first current driving force, the first cell transistor and the second cell transistor being electrically coupled to a bit line in parallel. The method includes: performing a first read operation of the first cell transistor using a first read voltage; determining that the nonvolatile memory cell has an initialization state if the first cell transistor is turned off during the first read operation and performing a second read operation of the first cell transistor using a second read voltage greater than the first read voltage if the first cell transistor is turned on during the first read operation; performing a read operation of the second cell transistor using a second read voltage if the first cell transistor is turned off during the second read operation; and determining that the nonvolatile memory cell has an initialization state if the second cell transistor is turned off during the read operation of the second cell transistor and determining that the nonvolatile memory cell has a programmed state if the second cell transistor is turned on during the read operation of the second cell transistor.

[0009] These and other features and advantages of the present disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawings, the same reference numerals in different drawings represent the same or functionally similar elements. The accompanying drawings, together with the detailed description below, are incorporated into the specification and constitute a part of the specification. The accompanying drawings are used to further illustrate the embodiments of the concepts including the claimed content, and to describe various principles and advantages of these embodiments.

[0011] Figure 1 The configuration of a nonvolatile memory device according to various embodiments of the present disclosure is shown.

[0012] Figure 2 is a layout diagram showing a first cell transistor and a second cell transistor included in a nonvolatile memory device according to various embodiments of the present disclosure.

[0013] Figure 3 is a circuit diagram showing a configuration of a read voltage selection circuit included in a nonvolatile memory device according to various embodiments of the present disclosure.

[0014] Figure 4 It is shown in Figure 3 An equivalent circuit diagram of a read voltage selection circuit when a first load transistor of the read voltage selection circuit is selectively turned on.

[0015] Figure 5 It is shown in Figure 3 An equivalent circuit diagram of a read voltage selection circuit when the second load transistor of the read voltage selection circuit is selectively turned on.

[0016] Figure 6 It is shown in Figure 3 An equivalent circuit diagram of a read voltage selection circuit when the third load transistor of the read voltage selection circuit is selectively turned on.

[0017] Figure 7 is an equivalent circuit diagram illustrating a nonvolatile memory cell array of a nonvolatile memory device according to various embodiments of the present disclosure.

[0018] Figure 8 A programming operation of a nonvolatile memory device according to various embodiments of the present disclosure is illustrated.

[0019] Fig. 9 is a merged graph showing distribution of first and second cell transistors with respect to cell current to present cell current variations of the first and second cell transistors according to read disturbance and retention degradation according to various embodiments of the present disclosure.

[0020] Fig.10 , Fig.11 and Fig.12 is a flowchart illustrating a read operation of a nonvolatile memory device according to various embodiments of the present disclosure.

[0021] Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 More specifically, Figures 10 to 12 Steps of flow chart. DETAILED DESCRIPTION

[0022] For the description of the following embodiments, it will be understood that the terms "first" and "second" are intended to identify elements, rather than to define the elements themselves or to imply a specific order or hierarchy. In addition, when an element is referred to as being "above," "on," "above," "below," or "below" another element, the relative positional relationship is indicated, regardless of the presence or absence of an intervening element. Therefore, terms such as "above," "above," "above," "below," "below," and the like used herein are only used for the purpose of describing specific embodiments, and are not intended to limit the scope of the present disclosure. In addition, when an element is referred to as being "connected" or "coupled" to another element, the element may be directly electrically or mechanically connected or coupled to the other element without an intervening element, or may be indirectly electrically or mechanically connected or coupled to the other element through an intervening element.

[0023] Various embodiments of the present disclosure are directed to a nonvolatile memory device having improved read operation accuracy and a method of reading the nonvolatile memory device.

[0024] Figure 1 1 shows a configuration of a nonvolatile memory device 100 according to various embodiments of the present disclosure. Figure 1 , the nonvolatile memory device 100 may be configured to include a nonvolatile memory cell 110, a cell transistor selector 120, a programming switch 130, a read switch 140, a read voltage selection circuit 150, a sense amplifier circuit 160, and a control circuit 170. In the present embodiment, the nonvolatile memory cell 110 may be an OTP memory cell. The nonvolatile memory cell 110 may be configured to include a first cell transistor 111, a second cell transistor 112, and a selection transistor 113. In one embodiment, the first cell transistor 111 may include a first PMOS transistor PM1 having a first floating gate, and the second cell transistor 112 may include a second PMOS transistor PM2 having a second floating gate. The first floating gate and the second floating gate may be electrically isolated or insulated from each other. The selection transistor 113 may include a third PMOS transistor PM3. The first cell transistor 111 and the second cell transistor 112 may have different physical sizes from each other, which means that the current driving force of the first cell transistor 111 is different from the current driving force of the second cell transistor 112. In this embodiment, the term "physical size" may indicate a ratio of a channel width to a channel length of a MOS transistor. In one embodiment, the physical size of the second unit transistor 112 may be greater than the physical size of the first unit transistor 111. Therefore, the current driving force of the second unit transistor 112 may be greater than the current driving force of the first unit transistor 111.

[0025] A source terminal of the first cell transistor 111, a source terminal of the second cell transistor 112, and a drain terminal of the selection transistor 113 may be coupled to the first node NODE1. A source terminal of the selection transistor 113 may be coupled to a second node NODE2 of the bit line BL. A selection gate voltage VG_SG may be applied to a gate terminal of the selection transistor 113. A drain terminal of the first cell transistor 111 may be coupled to a drain terminal of a first switch transistor 121 included in the cell transistor selector 120. A drain terminal of the second cell transistor 112 may be coupled to a drain terminal of a second switch transistor 122 included in the cell transistor selector 120.

[0026] Before the first cell transistor 111 and the second cell transistor 112 are not programmed by the programming operation, the first cell transistor 111 and the second cell transistor 112 may have an initialization state, and after the programming operation of the first cell transistor 111 and the second cell transistor 112 is performed, the first cell transistor 111 and the second cell transistor 112 may have a programming state. In one embodiment, the initialization state of the first cell transistor 111 and the second cell transistor 112 may indicate a state in which the first cell transistor 111 and the second cell transistor 112 are electrically turned off. Conversely, the programming state of the first cell transistor 111 and the second cell transistor 112 may indicate a state in which the first cell transistor 111 and the second cell transistor 112 are electrically turned on. In this embodiment, the first cell transistor 111 and the second cell transistor 112 may be programmed simultaneously. If a read voltage is applied to the nonvolatile memory cell 110 having an initialization state during a read operation, a cell current smaller than a cell current corresponding to the read voltage may flow through the first cell transistor 111 and the second cell transistor 112 having an initialization state. In contrast, if a read voltage is applied to the nonvolatile memory cell 110 having a programmed state during a read operation, a cell current greater than a cell current corresponding to the read voltage may flow through the first and second cell transistors 111 and 112 having the programmed state.

[0027] The cell transistor selector 120 may be coupled between the nonvolatile memory cell 110 and the ground voltage terminal, and may be operated to electrically connect or disconnect the first cell transistor 111 and the second cell transistor 112 to the ground voltage terminal. In one embodiment, the cell transistor selector 120 may be configured to include the first switch transistor 121 and the second switch transistor 122 mentioned above. The first switch transistor 121 may include a first NMOS transistor NM1, and the second switch transistor 122 may include a second NMOS transistor NM2. The drain terminal of the first switch transistor 121 may be coupled to the drain terminal of the first cell transistor 111. The source terminal of the first switch transistor 121 may be coupled to the ground voltage terminal. The first switch gate voltage VG_CTS1 may be applied to the gate terminal of the first switch transistor 121. The drain terminal of the second switch transistor 122 may be coupled to the drain terminal of the second cell transistor 112. The source terminal of the second switch transistor 122 may be coupled to the ground voltage terminal. The second switch gate voltage VG_CTS2 may be applied to the gate terminal of the second switch transistor 122.

[0028] The first cell transistor 111 may be electrically connected or disconnected from the ground voltage terminal according to the magnitude of the first switch gate voltage VG_CTS1. In one embodiment, if the first switch gate voltage VG_CTS1 having a high level is applied to the gate terminal of the first switch transistor 121, the first switch transistor 121 may be turned on to electrically connect the first cell transistor 111 of the nonvolatile memory cell 110 to the ground voltage terminal. On the contrary, if the first switch gate voltage VG_CTS1 having a low level is applied to the gate terminal of the first switch transistor 121, the first switch transistor 121 may be turned off to electrically disconnect the first cell transistor 111 of the nonvolatile memory cell 110 from the ground voltage terminal. Similarly, if the second switch gate voltage VG_CTS2 having a high level is applied to the gate terminal of the second switch transistor 122, the second switch transistor 122 may be turned on to electrically connect the second cell transistor 112 of the nonvolatile memory cell 110 to the ground voltage terminal. In contrast, if the second switching gate voltage VG_CTS2 having a low level is applied to the gate terminal of the second switching transistor 122 , the second switching transistor 122 may be turned off to electrically disconnect the second cell transistor 112 of the nonvolatile memory cell 110 from the ground voltage terminal.

[0029] The programming switch 130 may be coupled between a programming voltage supply line 181 for providing a programming voltage Vprogram and a second node NODE2 of a bit line BL. The programming switch 130 may include a programming switch transistor 131. In the present embodiment, the programming switch transistor 131 may be used as a switch transistor for applying the programming voltage Vprogram to the second node NODE2 during a programming operation, and the load resistance value of the programming switch transistor 131 will be ignored hereinafter. In one embodiment, the programming switch transistor 131 may include a fourth PMOS transistor PM4. The source terminal of the programming switch transistor 131 may be coupled to the programming voltage supply line 181. The drain terminal of the programming switch transistor 131 may be coupled to the second node NODE2 of the bit line BL. The programming gate voltage Vprogram_b may be applied to the gate terminal of the programming switch transistor 131.

[0030] The read switch 140 may be coupled between the second node NODE2 of the bit line BL and the third node NODE3 of the bit line BL. The third node NODE3 of the bit line BL may be coupled to the output line of the read voltage selection circuit 150, which is used to generate various read voltages, such as the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3. The read switch 140 may include a read switch transistor 141. In the present embodiment, the read switch transistor 141 may be used as a switch transistor for applying a read voltage selected from the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 to the second node NODE2 of the bit line BL during a read operation, and the load resistance value of the read switch transistor 141 will be ignored hereinafter. In one embodiment, the read switch transistor 141 may include a fifth PMOS transistor PM5. The source terminal of the read switch transistor 141 may be coupled to the third node NODE3 of the bit line BL, i.e., the output line of the read voltage selection circuit 150. A drain terminal of the read switch transistor 141 may be coupled to a second node NODE2 of the bit line BL A read gate voltage Vread_b may be applied to a gate terminal of the read switch transistor 141 .

[0031] The read voltage selection circuit 150 may be coupled between a read voltage supply line 182 for providing a read voltage Vread and a third node NODE3 of the bit line BL. The read voltage selection circuit 150 may receive a read voltage selection control signal CS_Vread. The read voltage selection circuit 150 may selectively output one of the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 in response to the read voltage selection control signal CS_Vread. The voltage levels of the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 may be lower than the voltage level of the read voltage Vread provided by the read voltage supply line 182. The first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3 may have different voltage levels. In one embodiment, the first read voltage Vread1 may have the lowest voltage level among the voltage levels of the first read voltage Vread1, the second read voltage Vread2, and the third read voltage Vread3. The voltage level of the second read voltage Vread2 may be higher than the voltage level of the first read voltage Vread1. The third read voltage Vread3 may have the highest voltage level among the voltage levels of the first read voltage Vread1 , the second read voltage Vread2 , and the third read voltage Vread3 .

[0032] The first read voltage Vread1 and the second read voltage Vread2 may be used during the read operation of the nonvolatile memory cell 110. Specifically, the read operation of the first cell transistor 111 having a relatively small current driving force may be performed for the first time using the first read voltage Vread1 having a relatively low voltage level. If the state of the nonvolatile memory cell 110 is affected by read disturbance or retention degradation after the read operation of the first cell transistor 111 (i.e., the read disturbance or retention degradation of the first cell transistor 111 is suspected after the read operation of the first cell transistor 111), the read operation of the first cell transistor 111 may be performed again using the second read voltage Vread2 having a relatively high voltage level. If the state of the nonvolatile memory cell 110 is still affected by read disturbance or retention degradation even after the second read operation of the first cell transistor 111, the read operation of the second cell transistor 112 having a relatively large current driving force may be performed using the second read voltage Vread2 having a relatively high voltage level. In the present disclosure, read disturbance may be defined as a phenomenon in which a cell current of a cell transistor having an initialized state increases due to the use of a high read voltage or an increase in the frequency of a read operation. In addition, retention degradation may be defined as a phenomenon in which a cell current of a cell transistor having a programmed state decreases due to the loss of electrons stored in the gate (i.e., floating gate) of the programmed cell transistor when the temperature rises.

[0033] In addition, the third read voltage Vread3 can be used to verify the programming state of the nonvolatile memory cell 110 after the nonvolatile memory cell 110 is programmed by the programming operation. That is, the programming operation of the nonvolatile memory cell 110 can be performed so that both the cell current of the first cell transistor 111 and the cell current of the second cell transistor 112 are greater than the cell current corresponding to the third read voltage Vread3. Therefore, after performing the programming operation, a programming verification operation can be performed to verify whether the first cell transistor 111 and the second cell transistor 112 of the nonvolatile memory cell 110 are properly programmed. The programming verification operation can be implemented by performing a read operation on each of the first cell transistor 111 and the second cell transistor 112 using the third read voltage Vread3 to determine whether a cell current greater than the current corresponding to the third read voltage Vread3 flows through each of the first cell transistor 111 and the second cell transistor 112.

[0034] The sense amplifier circuit 160 may receive the node voltage of the third node NODE3 of the bit line BL as a sense input voltage during a read operation of the non-volatile memory cell 110. In one embodiment, the sense amplifier circuit 160 may be implemented using a CMOS inverter. For example, the sense amplifier circuit 160 may be configured to include a pull-up PMOS transistor coupled between a power supply voltage terminal and an output line of the sense amplifier circuit 160 and a pull-down NMOS transistor coupled between the output line of the sense amplifier circuit 160 and a ground voltage terminal. The node voltage of the third node NODE3 of the bit line BL may be applied to both the gate terminal of the pull-up PMOS transistor and the gate terminal of the pull-down NMOS transistor. In one embodiment, when the non-volatile memory cell 110 has an initialized state, the sense amplifier circuit 160 may output a low level signal, such as a ground voltage, as a first sense output signal SA_OUT1. On the contrary, when the non-volatile memory cell 110 has a programmed state, the sense amplifier circuit 160 may output a high level signal, such as a power supply voltage, as a first sense output signal SA_OUT1. The first sensing output signal SA_OUT1 output from the sense amplification circuit 160 may be input to the control circuit 170 .

[0035] The control circuit 170 may generate various gate voltages and control signals applied to the gate terminals of the respective transistors to perform a programming operation and a reading operation of the nonvolatile memory cell 110. In one embodiment, the control circuit 170 may generate a selection gate voltage VG_SG applied to the gate terminal of the selection transistor 113 included in the nonvolatile memory cell 110. The control circuit 170 may generate a first switch gate voltage VG_CTS1 applied to the gate terminal of the first switch transistor 121 included in the cell transistor selector 120. The control circuit 170 may generate a second switch gate voltage VG_CTS2 applied to the gate terminal of the second switch transistor 122 included in the cell transistor selector 120. The control circuit 170 may generate a programming gate voltage Vprogram_b applied to the gate terminal of the program switch transistor 131 included in the program switch 130 to perform a programming operation of the nonvolatile memory cell 110. The control circuit 170 may generate a read gate voltage Vread_b applied to a gate terminal of a read switch transistor 141 included in the read switch 140 and a read voltage selection control signal CS_Vread input to the read voltage selection circuit 150 to perform a read operation of the nonvolatile memory cell 110 .

[0036] During a read operation of the nonvolatile memory cell 110, the control circuit 170 may generate various gate voltages and a read voltage selection control signal CS_Vread according to the level of the selected read voltage output from the read voltage selection circuit 150 and the level of the first sense output signal SA_OUT1 output from the sense amplifier circuit 160. If the read operation of the nonvolatile memory cell 110 is terminated, the control circuit 170 may output a second sense output signal SA_OUT2. In one embodiment, when the nonvolatile memory cell 110 has an initialized state, the control circuit 170 may output a low level signal as the second sense output signal SA_OUT2. Conversely, when the nonvolatile memory cell 110 has a programmed state, the control circuit 170 may output a high level signal as the second sense output signal SA_OUT2.

[0037] Figure 2 It is shown Figure 1 FIG. 1 is a layout diagram of a first cell transistor 111, a second cell transistor 112, and a selection transistor 113 included in a nonvolatile memory device 100. Figure 2 As shown in the figure, the first cell transistor 111, the second cell transistor 112 and the selection transistor 113 can share an active area 201 defined in a semiconductor substrate (not shown) with each other. Although not shown in the figure, the active area 201 can be set in an N-type well formed in the semiconductor substrate. The first cell transistor 111 can be set in the first area of ​​the active area 201. The second cell transistor 112 can be set in the second area of ​​the active area 201. The selection transistor 113 can be set in the third area of ​​the active area 201. The first floating gate FG1 corresponding to the floating gate of the first cell transistor 111 can be set to intersect with the first area of ​​the active area 201 and along the channel width direction (i.e. Figure 2 Therefore, the first impurity region 211 and the third impurity region 213 may be disposed in the first region of the active region 201 and extend along the channel length direction (i.e., Figure 2 The second impurity region 212 and the third impurity region 213 may be disposed in the second region of the active region 201 and may be separated from each other by the second floating gate FG1 in the horizontal direction in the channel length direction. The second floating gate FG2 corresponding to the floating gate of the second cell transistor 112 may be disposed to intersect the second region of the active region 201 and extend in the channel width direction. Therefore, the second impurity region 212 and the third impurity region 213 may be disposed in the second region of the active region 201 and may be separated from each other by the second floating gate FG2 in the channel length direction.

[0038] The selection gate SG corresponding to the gate terminal of the selection transistor 113 may be disposed to intersect the third region of the active region 201 and extend in the channel width direction. Therefore, the fourth impurity region 214 and the third impurity region 213 may be disposed in the third region of the active region 201 and separated from each other in the channel length direction by the selection gate SG. The first cell transistor 111, the second cell transistor 112, and the selection transistor 113 may share the third impurity region 213 with each other. As shown in FIG. Figure 1 As described, if the first cell transistor 111, the second cell transistor 112, and the selection transistor 113 are all implemented using PMOS transistors, the first impurity region 211, the second impurity region 212, the third impurity region 213, and the fourth impurity region 214 may be P-type impurity regions.

[0039] The first impurity region 211 may correspond to a drain region of the first cell transistor 111. The second impurity region 212 may correspond to a drain region of the second cell transistor 112. Figure 2 Although not shown in the figure, the first impurity region 211 and the second impurity region 212 may be electrically coupled to the drain region of the first switch transistor 121 and the drain region of the second switch transistor 122, respectively. The third impurity region 213 may correspond to the source region of the first cell transistor 111, the source region of the second cell transistor 112, and the drain region of the selection transistor 113. The fourth impurity region 214 may correspond to the source region of the selection transistor 113.

[0040] The portion of the active region 201 overlapping the first floating gate FG1 may be used as a first channel region corresponding to the channel region of the first cell transistor 111. The portion of the active region 201 overlapping the second floating gate FG2 may be used as a second channel region corresponding to the channel region of the second cell transistor 112. The first channel length CL1 corresponding to the channel length of the first channel region of the first cell transistor 111 may be substantially equal to the second channel length CL2 corresponding to the channel length of the second channel region of the second cell transistor 112. That is, there is no difference in current driving force between the first cell transistor 111 and the second cell transistor 112 in terms of channel length. However, the second channel width CW2 corresponding to the channel width of the second channel region of the second cell transistor 112 may be greater than the first channel width CW1 corresponding to the channel width of the first channel region of the first cell transistor 111. Therefore, due to the difference between the first channel width CW1 and the second channel width CW2, the current driving force of the second cell transistor 112 may be actually greater than the current driving force of the first cell transistor 111. That is, since the first and second channel lengths CL1 and CL2 are equal to each other and the second channel width CW2 is greater than the first channel width CW1 , the current driving force of the second cell transistor 112 may be greater than that of the first cell transistor 111 .

[0041] Figure 3 It is shown Figure 1 1 is a circuit diagram of a configuration of a read voltage selection circuit 150 included in a nonvolatile memory device 100. Figures 4 to 6 is an equivalent circuit diagram showing an example in which the read voltage selection circuit 150 outputs a first read voltage Vread1, a second read voltage Vread2, and a third read voltage Vread3, respectively. Figure 3 As shown in , the read voltage selection circuit 150 may be configured to include a first load transistor 151, a second load transistor 152, and a third load transistor 153. In one embodiment, the first load transistor 151 may include a sixth PMOS transistor PM6, and the second load transistor 152 may include a seventh PMOS transistor PM7. In addition, the third load transistor 153 may include an eighth PMOS transistor PM8.

[0042] The first load transistor 151, the second load transistor 152, and the third load transistor 153 can be used as a load resistor and a switch. The first load transistor 151, the second load transistor 152, and the third load transistor 153 can have different physical sizes, such as different channel ratios, each channel ratio being defined as the ratio of channel width to channel length. Therefore, the first load transistor 151, the second load transistor 152, and the third load transistor 153 can have different load resistance values. In one embodiment, the first load transistor 151 can have the highest load resistance value among the load resistance values ​​of the first load transistor 151, the second load transistor 152, and the third load transistor 153. The load resistance value of the second load transistor 152 can be lower than the load resistance value of the first load transistor 151. The third load transistor 153 can have the lowest load resistance value among the load resistance values ​​of the first load transistor 151, the second load transistor 152, and the third load transistor 153. In one embodiment, when the first load transistor 151, the second load transistor 152, and the third load transistor 153 have the same channel length, the third load transistor 153 may have the widest channel width among the first load transistor 151, the second load transistor 152, and the third load transistor 153, and the first load transistor 151 may have the narrowest channel width among the first load transistor 151, the second load transistor 152, and the third load transistor 153. In one embodiment, when the first load transistor 151, the second load transistor 152, and the third load transistor 153 have the same channel width, the third load transistor 153 may have the shortest channel length among the first load transistor 151, the second load transistor 152, and the third load transistor 153, and the first load transistor 151 may have the longest channel length among the first load transistor 151, the second load transistor 152, and the third load transistor 153.

[0043] All source terminals of the first load transistor 151, the second load transistor 152, and the third load transistor 153 can be coupled to a read voltage supply line 182 that provides a read voltage Vread. All drain terminals of the first load transistor 151, the second load transistor 152, and the third load transistor 153 can be coupled to an output line of the read voltage selection circuit 150, i.e., a third node NODE3 of the bit line BL. A first gate voltage VG1 can be applied to the gate terminal of the first load transistor 151. A second gate voltage VG2 can be applied to the gate terminal of the second load transistor 152. A third gate voltage VG3 can be applied to the gate terminal of the third load transistor 153. The first gate voltage VG1, the second gate voltage VG2, and the third gate voltage VG3 can constitute a read voltage selection control signal ( Figure 1 CS_Vread).

[0044] Figure 4 1 shows an equivalent circuit diagram of the read voltage selection circuit 150 when the first load transistor 151 is selectively turned on. If the first gate voltage VG1 having a low level is applied to the gate terminal of the first load transistor 151, the first load transistor 151 may be turned on. Figure 4 As shown in , the first load transistor 151 can be used as a first load resistor 151R having a first equivalent resistance value R1 when turned on. In addition, a second gate voltage VG2 and a third gate voltage VG3 having a high level can be applied to the gate terminals of the second load transistor 152 and the third load transistor 153, respectively. Therefore, the second load transistor 152 and the third load transistor 153 can be turned off and become an open circuit. In this case, since a current flows through the first load resistor 151R under the bias condition when the read voltage Vread is applied to the read voltage supply line 182, a voltage drop across the first load resistor 151R occurs. Therefore, a first read voltage Vread1 can be induced at the third node NODE3 of the bit line BL through the output line of the read voltage selection circuit 150. The first read voltage Vread1 can have a magnitude corresponding to a voltage obtained by subtracting the voltage drop across the first load resistor 151R from the read voltage Vread.

[0045] Figure 5 1 shows an equivalent circuit diagram of the read voltage selection circuit 150 when the second load transistor 152 is selectively turned on. If the second gate voltage VG2 having a low level is applied to the gate terminal of the second load transistor 152, the second load transistor 152 may be turned on. Figure 5As shown in , the second load transistor 152 can be used as a second load resistor 152R having a second equivalent resistance value R2 when turned on. In addition, a first gate voltage VG1 and a third gate voltage VG3 having a high level can be applied to the gate terminals of the first load transistor 151 and the third load transistor 153, respectively. Therefore, the first load transistor 151 and the third load transistor 153 can be cut off and become an open circuit. In this case, since a current flows through the second load resistor 152R under the bias condition when the read voltage Vread is applied to the read voltage supply line 182, a voltage drop across the second load resistor 152R will occur. Therefore, a second read voltage Vread2 can be induced at the third node NODE3 of the bit line BL through the output line of the read voltage selection circuit 150. The second read voltage Vread2 can have a magnitude corresponding to a voltage obtained by subtracting the voltage drop across the second load resistor 152R from the read voltage Vread. Since the second equivalent resistance value R2 of the second load transistor 152 is smaller than the first equivalent resistance value R1 of the first load transistor 151 , the second read voltage Vread2 may be higher than the first read voltage Vread1 .

[0046] Figure 6 1 shows an equivalent circuit diagram of the read voltage selection circuit 150 when the third load transistor 153 is selectively turned on. Figure 1 As described above, the third load transistor 153 is selectively turned on after the programming operation to perform the programming verification operation. If the third gate voltage VG3 having a low level is applied to the gate terminal of the third load transistor 153, the third load transistor 153 may be turned on. Figure 6As shown in , the third load transistor 153 can be used as a third load resistor 153R having a third equivalent resistance value R3 when turned on. Furthermore, the first gate voltage VG1 and the second gate voltage VG2 having a high level can be applied to the gate terminals of the first load transistor 151 and the second load transistor 152, respectively. Therefore, the first load transistor 151 and the second load transistor 152 can be turned off to become an open circuit. In this case, since the current flows through the third load resistor 153R under the bias condition that the read voltage Vread is applied to the read voltage supply line 182, a voltage drop across the third load resistor 153R will occur. Therefore, the third read voltage Vread3 can be induced at the third node NODE3 of the bit line BL by reading the output line of the voltage selection circuit 150. The third read voltage Vread3 can have a magnitude corresponding to the voltage obtained by subtracting the voltage drop across the third load resistor 153R from the read voltage Vread. Since the third equivalent resistance value R3 of the third load transistor 153 is smaller than the second equivalent resistance value R2 of the second load transistor 152 , the third read voltage Vread3 may be higher than the second read voltage Vread2 .

[0047] Figure 7 is an equivalent circuit diagram showing a nonvolatile memory cell array in a nonvolatile memory device according to each embodiment of the present disclosure. Figure 7 , the nonvolatile memory cell array may be configured to include a plurality of nonvolatile memory cells and a cell transistor selector 120, such as the first to (M×N)th nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN. Figure 7 , but a nonvolatile memory device according to one embodiment may include a nonvolatile memory cell array, a programming switch ( Figure 1 130), read switch ( Figure 1 140), read voltage selection circuit ( Figure 1 150), sensing amplifier circuit ( Figure 1 160) and control circuit ( Figure 1 170). The first to (M×N)th nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN may be located at intersections between a plurality of bit lines spaced apart from each other and arranged in a row direction (e.g., a first to Nth bit line BL-0, ..., and BL-(N-1)) and a plurality of selection gate lines spaced apart from each other and arranged in a column direction (e.g., a first to Mth selection gate line SG-0, ..., and SG-(M-1)).

[0048] Each of the first to (M×N)th nonvolatile memory cells 110-11, . . . , 110-1N, . . . , 110-M1, . . . , and 110-MN may have a reference Figure 1 The nonvolatile memory cell 110 described above has the same construction as that of the nonvolatile memory cell 110. That is, each of the first to (M×N)th nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN may include a first cell transistor 111, a second cell transistor 112, and a selection transistor 113. The first cell transistor 111, the second cell transistor 112, and the selection transistor 113 may include a first PMOS transistor PM1, a second PMOS transistor PM2, and a third PMOS transistor PM3, respectively. A source terminal of the selection transistor 113 of each of the first to (M×N)th nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN may be coupled to any corresponding bit line among the bit lines BL-0, ..., and BL-(N-1), and a drain terminal of the selection transistor 113 may be coupled to source terminals of both the first cell transistor 111 and the second cell transistor 112. A drain terminal of the first cell transistor 111 may be coupled to a drain terminal of the first switch transistor 121. A drain terminal of the second cell transistor 112 may be coupled to a drain terminal of the second switch transistor 122.

[0049] The nonvolatile memory cells arranged in the same row may share the same selection gate line with each other. For example, the nonvolatile memory cells 110-11, ... and 110-1N arranged in the first row may share the first selection gate line SG-0 with each other. The first selection gate line SG-0 may correspond to a gate line used as a gate terminal of a selection transistor 113 included in each of the nonvolatile memory cells 110-11, ... and 110-1N arranged in the first row. Similarly, the nonvolatile memory cells 110-M1, ... and 110-MN arranged in the Mth row may share the Mth selection gate line SG-(M-1) with each other. The Mth selection gate line SG-(M-1) may correspond to a gate line used as a gate terminal of a selection transistor 113 included in each of the nonvolatile memory cells 110-M1, ... and 110-MN arranged in the Mth row. The nonvolatile memory cells arranged in the same column may share the same bit line with each other. For example, the nonvolatile memory cells 110-11, ..., and 110-M1 arranged in the first column may share a first bit line BL-0 with each other. The first bit line BL-0 may correspond to a source line used as a source terminal of a selection transistor 113 included in each of the nonvolatile memory cells 110-11, ..., and 110-M1 arranged in the first column. Similarly, the nonvolatile memory cells 110-1N, ..., and 110-MN arranged in the Nth column may share an Nth bit line BL-(N-1) with each other. The Nth bit line BL-(N-1) may correspond to a source line used as a source terminal of a selection transistor 113 included in each of the nonvolatile memory cells 110-1N, ..., and 110-MN arranged in the Nth column.

[0050] The cell transistor selector 120 may include the first switch transistor 121 and the second switch transistor 122 as described above. In addition, the first switch transistor 121 may include a first NMOS transistor NM1, and the second switch transistor 122 may include a second NMOS transistor NM2. The drain terminal of the first switch transistor 121 may be coupled to the drain terminals of all the first cell transistors 111 included in the nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN. The source terminal of the first switch transistor 121 may be coupled to the ground voltage terminal. The drain terminal of the second switch transistor 122 may be coupled to the drain terminals of all the second cell transistors 112 included in the nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN. The source terminal of the second switch transistor 122 may be coupled to the ground voltage terminal. When the first switch transistor 121 is turned on, the drain terminals of all the first cell transistors 111 included in the nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN may be grounded. When the second switch transistor 122 is turned on, the drain terminals of all the second cell transistors 112 included in the nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN may be grounded.

[0051] Any one of the nonvolatile memory cells 110-11, ..., 110-1N, ..., 110-M1, ..., and 110-MN can be selected by a bit line voltage and a selection gate voltage to selectively perform a programming operation or a reading operation. In order to perform a programming operation of the selected nonvolatile memory cell, a bit line programming voltage may be applied to a bit line coupled to the selected nonvolatile memory cell and the remaining bit lines may be grounded. In addition, in order to perform a programming operation of the selected nonvolatile memory cell, a programming gate voltage having a low level may be applied to a selection gate line coupled to the selected nonvolatile memory cell and a gate voltage having a high level may be applied to the remaining selection gate lines. Similarly, in order to perform a reading operation of the selected nonvolatile memory cell, a bit line reading voltage may be applied to a bit line coupled to the selected nonvolatile memory cell and the remaining bit lines may be grounded. In addition, in order to perform a read operation of the selected nonvolatile memory cell, a read gate voltage having a low level may be applied to a selection gate line coupled to the selected nonvolatile memory cell and a gate voltage having a high level may be applied to the remaining selection gate lines. The programming operation and the read operation of the selected nonvolatile memory cell may be performed in accordance with Figure 1The programming operation and the reading operation of the nonvolatile memory cell 110 shown in FIG. 1 are performed in the same manner, which will be described below.

[0052] Figure 8 It is shown Figure 1 Schematic diagram of the programming operation of the nonvolatile memory device 100 shown in FIG. Figure 8 In, with Figure 1 The same reference numerals used in the drawings denote the same elements. Figure 8 , a programming operation of the nonvolatile memory cell 110 according to one embodiment may be performed so that the first cell transistor 111 and the second cell transistor 112 included in the nonvolatile memory cell 110 are programmed at the same time. In order to program the first cell transistor 111 and the second cell transistor 112 included in the nonvolatile memory cell 110, the control circuit 170 may generate a program gate voltage Vprogram_b having a low level, a read gate voltage Vread_b having a high level, a select gate voltage VG_SG having a low level, a first switch gate voltage VG_CTS1 having a high level, and a second switch gate voltage VG_CTS2 having a high level. Therefore, when the program switch transistor 131 is turned on (On), the read switch transistor 141 may be turned off (Off). In addition, the select transistor 113 of the nonvolatile memory cell 110 and the first switch transistor 121 and the second switch transistor 122 of the cell transistor selector 120 may be turned on.

[0053] Since the programming voltage Vprogram and the ground voltage are applied to the corresponding terminals of the source terminal and the drain terminal of the first cell transistor 111 under the above-mentioned bias conditions, hot carriers may be generated in the first cell transistor 111 and the hot carriers (i.e., hot electrons) may be injected into the floating gate of the first cell transistor 111. Therefore, the first cell transistor 111 may have a programmed state, that is, a channel serving as a current path is formed between the drain terminal and the source terminal of the first cell transistor 111 to turn on the first cell transistor 111. Similarly, since the programming voltage Vprogram and the ground voltage are applied to the corresponding terminals of the source terminal and the drain terminal of the second cell transistor 112 under the above-mentioned bias conditions, hot carriers may be generated in the second cell transistor 112 and the hot carriers (i.e., hot electrons) may be injected into the floating gate of the second cell transistor 112. Therefore, the second cell transistor 112 may also have a programmed state, that is, a channel serving as a current path is formed between the drain terminal and the source terminal of the second cell transistor 112 to turn on the second cell transistor 112.

[0054] As described above, the first cell transistor 111 and the second cell transistor 112 included in the nonvolatile memory cell 110 may be simultaneously programmed by a programming operation of the nonvolatile memory device 100. Furthermore, since the current driving force of the first cell transistor 111 is different from the current driving force of the second cell transistor 112, the amount of the first cell current flowing through the first cell transistor 111 during the read operation may be different from the amount of the second cell current flowing through the second cell transistor 112. However, after performing the programming operation of the nonvolatile memory cell 110, both the first cell transistor 111 and the second cell transistor 112 may have a large current driving force, so that the cell current flowing through each of the first cell transistor 111 and the second cell transistor 112 is greater than the cell current corresponding to the third read voltage Vread3. Therefore, it may be possible to perform the programming operation of the nonvolatile memory cell 110 as described above. Figure 1 As described, a program verification operation is performed using the third read voltage Vread3 to verify a program state of the nonvolatile memory cell 110. The program verification operation may be implemented by sequentially performing a read operation of the first cell transistor 111 and the second cell transistor 112 using the third read voltage Vread3.

[0055] Fig. 9 1 is a combined graph showing the distribution of the first cell transistor 111 and the second cell transistor 112 with respect to the cell current in the nonvolatile memory device 100 according to various embodiments of the present disclosure, and showing the cell current variation of the first cell transistor 111 and the second cell transistor 112 according to read disturbance and retention degradation. Fig. 9 In the figure, the horizontal axis represents the unit current. Furthermore, Fig. 9 The ordinate in the above figure represents the distribution of the first unit transistor 111, and Fig. 9 The ordinate in the lower figure represents the distribution of the second unit transistor 112. Fig. 9 , a first dotted line 301 extending in the vertical direction represents a first cell current Icell1 corresponding to a first read voltage Vread1, a second dotted line 302 extending in the vertical direction represents a second cell current Icell2 corresponding to a second read voltage Vread2, and a third dotted line 303 extending in the vertical direction represents a third cell current Icell3 corresponding to a third read voltage Vread3.

[0056] Reference Fig. 9, as indicated by reference numeral 111_I, the first cell transistor 111 having an initialized state may present a cell current that is less than the first cell current Icell1. Similarly, as indicated by reference numeral 112_I, the second cell transistor 112 having an initialized state may also present a cell current that is less than the first cell current Icell1. In addition, as indicated by reference numeral 111_I', the cell current of the first cell transistor 111 having an initialized state may increase due to a read disturbance phenomenon. Similarly, as indicated by reference numeral 112_I', the cell current of the second cell transistor 112 having an initialized state may also increase due to a read disturbance phenomenon. In this case, since the current driving force of the second cell transistor 112 is greater than the current driving force of the first cell transistor 111, when a read disturbance phenomenon occurs, the increment of the cell current of the second cell transistor 112 may be greater than the increment of the cell current of the first cell transistor 111. Therefore, when both the first cell transistor 111 and the second cell transistor 112 are degraded due to the read disturbance phenomenon, it is highly likely that the cell current of the second cell transistor 112 increases to be greater than the first cell current Icell1 rather than the cell current of the first cell transistor 111 increasing to be greater than the first cell current Icell1.

[0057] As indicated by reference numeral 111_P, the first cell transistor 111 having a programming state may present a cell current greater than the third cell current Icell3. Similarly, as indicated by reference numeral 112_P, the second cell transistor 112 having a programming state may also present a cell current greater than the third cell current Icell3. In addition, as indicated by reference numeral 111_P', the cell current of the first cell transistor 111 having a programming state may decrease due to retention degradation (i.e., degradation of data retention characteristics). Similarly, as indicated by reference numeral 112_P', the cell current of the second cell transistor 112 having a programming state may also decrease due to retention degradation. In this case, since the current driving force of the second cell transistor 112 is greater than the current driving force of the first cell transistor 111, when retention degradation occurs, the reduction in the cell current of the second cell transistor 112 may be greater than the reduction in the cell current of the first cell transistor 111. Therefore, when both the first cell transistor 111 and the second cell transistor 112 degrade due to retention degradation, it is highly likely that the cell current of the second cell transistor 112 decreases to be less than the third cell current Icell3 rather than the cell current of the first cell transistor 111 decreasing to be less than the third cell current Icell3.

[0058] Fig.10 , Fig.11 and Fig.12is a flowchart showing a read operation of the nonvolatile memory device 100 according to various embodiments of the present disclosure. Figures 13 to 19 More specifically, Fig.10 , Fig.11 and Fig.12 The steps of the flowchart. Figures 13 to 19 In, with Figure 1 The same reference numerals used in the nonvolatile memory cell 110 denote the same elements. According to the read operation described in the present embodiment, after the read operation of the first cell transistor 111 included in the nonvolatile memory cell 110 is performed, the read operation of the second cell transistor 112 may be additionally performed when it is suspected that the state of the nonvolatile memory cell 110 is unclear. Therefore, the frequency of the read operation of the second cell transistor 112 may be less than the frequency of the read operation of the first cell transistor 111. This means that the second cell transistor 112 may be less affected by the read disturbance phenomenon according to the frequency of the read operation than the first cell transistor 111. Therefore, when the read disturbance state of the first cell transistor 111 is suspected as a result of the read operation of the first cell transistor 111, the result of the read operation of the first cell transistor 111 may be retained without making any decision, and the read disturbance state of the first cell transistor 111 may be inferred by analogy with the read operation of the second cell transistor 112.

[0059] First, refer to Fig.10 , at step 411, a read operation of the first cell transistor 111 having a relatively small current driving force may be performed using the first read voltage Vread1 having a relatively low level. At step 412, it may be determined whether the first sensing output signal SA_OUT1 has a low level. If the first sensing output signal SA_OUT1 has a low level at step 412, the nonvolatile memory cell 110 may be regarded as having an initialized state and the control circuit 170 may output a low level signal as the second sensing output signal SA_OUT2 at step 413. On the contrary, if the first sensing output signal SA_OUT1 has a high level at step 412, the control circuit 170 may be performed. Fig.11 The second reading process shown in .

[0060] The following will refer to Fig.13 and Fig.14 Steps 411, 412 and 413 are described in more detail. Fig.13 and Fig.14As shown, the control circuit 170 can generate a program gate voltage Vprogram_b having a high level, a read gate voltage Vread_b having a low level, a select gate voltage VG_SG having a low level, a first switch gate voltage VG_CTS1 having a high level, and a second switch gate voltage VG_CTS2 having a low level to perform Fig.10 The control circuit 170 may generate a first gate voltage VG1 having a low level, a second gate voltage VG2 having a high level, and a third gate voltage VG3 having a high level and output them to the read voltage selection circuit 150. Therefore, when the read switch transistor 141 is turned on, the program switch transistor 131 may be turned off. In addition, when both the selection transistor 113 of the nonvolatile memory cell 110 and the first switch transistor 121 of the cell transistor selector 120 are turned on, the second switch transistor 122 of the cell transistor selector 120 may be turned off.

[0061] As reference Figure 3 and Figure 4 As described, the read voltage selection circuit 150 may receive a first gate voltage VG1 having a low level, a second gate voltage VG2 having a high level, and a third gate voltage VG3 having a high level to generate a first read voltage Vread1 and output it through a third node NODE3 of the bit line BL. Since the read switch transistor 141 and the selection transistor 113 are turned on, the first read voltage Vread1 may be applied to the first node NODE1 of the nonvolatile memory cell 110. Since the first switch transistor 121 is turned on, the first read voltage Vread1 may be applied between the source terminal and the drain terminal of the first cell transistor 111. On the contrary, since the second switch transistor 122 is turned off, an open circuit may be provided between the drain terminal of the second cell transistor 112 and the ground voltage terminal.

[0062] By applying the first read voltage Vread1 between the source terminal and the drain terminal of the first cell transistor 111, the third node NODE3 of the bit line BL may maintain the first read voltage Vread1 or may be grounded according to whether the first cell transistor 111 is turned off or on. When the first cell transistor 111 is turned off, the third node NODE3 of the bit line BL may maintain the first read voltage Vread1. Fig.13 As shown in FIG. 1 , when the third node NODE3 of the bit line BL maintains the first read voltage Vread1, the sense amplifier circuit 160 may output the first sense output signal SA_OUT1 having a low level. On the contrary, when the first cell transistor 111 is turned on, the third node NODE3 of the bit line BL may be grounded. Fig.14As shown in FIG. 1 , when the third node NODE3 of the bit line BL is grounded, the sense amplifier circuit 160 may output the first sense output signal SA_OUT1 having a high level. The first sense output signal SA_OUT1 output from the sense amplifier circuit 160 may be input to the control circuit 170 .

[0063] When Fig.13 When the first sensing output signal SA_OUT1 has a low level, as shown in Fig. 9 As described, the first cell transistor 111 may present a cell current that is less than the first cell current Icell1 corresponding to the first read voltage Vread1. This means that when the first read voltage Vread1 is applied to the first cell transistor 111, the first cell transistor 111 is turned off to have an initialized state. Since the change in the cell current of the first cell transistor 111 due to retention degradation is relatively small, it is unlikely that the cell current of the first cell transistor 111 having a programmed state (greater than the third cell current Icell3) is reduced to less than the first cell current Icell1 due to retention degradation. Therefore, the control circuit 170 may regard the nonvolatile memory cell 110 as having an initialized state without performing an additional read operation of the second cell transistor 112. Therefore, as described with reference to Fig.10 As described in step 413 , the control circuit 170 may generate a second sensing output signal SA_OUT2 having a low level as a result of the final read operation of the nonvolatile memory cell 110 .

[0064] On the contrary, when Fig.14 When the first sensing output signal SA_OUT1 has a high level, as shown in FIG. Fig. 9 As described, the first cell transistor 111 may present a cell current greater than the first cell current Icell1 corresponding to the first read voltage Vread1. This means that when the first read voltage Vread1 is applied to the first cell transistor 111, the first cell transistor 111 is turned on to have a programmed state. However, it may be unreasonable to infer that the non-volatile memory cell 110 has a programmed state based solely on the fact that the first cell transistor 111 is turned on at the first read voltage Vread1. The reason is that the first cell transistor 111 having an initialized state (i.e., a cut-off state) may present a cell current greater than the first cell current Icell1 due to read interference. Therefore, although the first sensing output signal SA_OUT1 has a high level at step 412, it is still necessary to verify whether the cell current of the non-volatile memory cell 110 should be attributed to a normal programming state or a read interference. In order to verify the state of the non-volatile memory cell 110, the control circuit 170 may generate a signal for a second read process instead of the second sensing output signal SA_OUT2.

[0065] Reference Fig.11 , which shows the second reading process, when Fig.10 When the level of the first sensing output signal SA_OUT1 at step 412 is not a low level (i.e., the first sensing output signal SA_OUT1 has a high level), a second read voltage Vread2 higher than the first read voltage Vread1 may be used at step 421 to perform a read operation of the first unit transistor 111. At step 422, it may be determined whether the first sensing output signal SA_OUT1 has a low level. If the first sensing output signal SA_OUT1 has a low level at step 422, a read operation of the second unit transistor 112 having a relatively large current driving force may be performed at step 423 using the second read voltage Vread2. At step 424, it may be determined whether the first sensing output signal SA_OUT1 has a low level. When the first sensing output signal SA_OUT1 has a low level at step 424, the nonvolatile memory cell 110 may be determined to have an initialized state at step 425 and the control circuit 170 may output a low level signal as the second sensing output signal SA_OUT2. In contrast, when the first sensing output signal SA_OUT1 has a high level at step 424 , the nonvolatile memory cell 110 may be determined to have a programmed state and the control circuit 170 may output a high level signal as the second sensing output signal SA_OUT2 at step 426 .

[0066] When the first sensing output signal SA_OUT1 has a high level at step 422, a read operation of the second cell transistor 112 may be performed using the second read voltage Vread2 at step 427. At step 428, it may be determined whether the first sensing output signal SA_OUT1 has a low level. When the level of the first sensing output signal SA_OUT1 is not a low level (i.e., the first sensing output signal SA_OUT1 has a high level) at step 428, the nonvolatile memory cell 110 may be determined to have a programmed state at step 426 and the control circuit 170 may output a high level signal as the second sensing output signal SA_OUT2. On the contrary, if the first sensing output signal SA_OUT1 has a low level at step 428, then as shown in FIG. Fig.12 As shown, a third read process may be performed.

[0067] like Fig.15 As shown, the control circuit 170 can generate a program gate voltage Vprogram_b having a high level, a read gate voltage Vread_b having a low level, a select gate voltage VG_SG having a low level, a first switch gate voltage VG_CTS1 having a high level, and a second switch gate voltage VG_CTS2 having a low level to perform Fig.11 Step 421. In addition, the control circuit 170 may generate a first gate voltage VG1 having a high level, a second gate voltage VG2 having a low level, and a third gate voltage VG3 having a high level and output them to the read voltage selection circuit 150. Therefore, when the read switch transistor 141 is turned on, the program switch transistor 131 may be turned off. In addition, when both the selection transistor 113 of the nonvolatile memory cell 110 and the first switch transistor 121 of the cell transistor selector 120 are turned on, the second switch transistor 122 of the cell transistor selector 120 may be turned off.

[0068] As reference Figure 5 As described, the read voltage selection circuit 150 can receive the first gate voltage VG1 having a high level, the second gate voltage VG2 having a low level, and the third gate voltage VG3 having a high level to generate a second read voltage Vread2 and output it through the third node NODE3 of the bit line BL. Figure 1 As described above, the second read voltage Vread2 may be higher than the first read voltage Vread1. Since both the read switch transistor 141 and the select transistor 113 are turned on, the second read voltage Vread2 may be applied to the first node NODE1 of the nonvolatile memory cell 110. Since the first switch transistor 121 is turned on, the second read voltage Vread2 may be applied between the source terminal and the drain terminal of the first cell transistor 111. On the contrary, since the second switch transistor 122 is turned off, an open circuit may be provided between the drain terminal of the second cell transistor 112 and the ground voltage terminal.

[0069] Although during the read operation performed using the first read voltage Vread1 (see Fig.10In step 411 of the embodiment, the first cell transistor 111 is regarded as being turned on (i.e., a programming state), but it may not be clear whether the first cell transistor 111 is a cell transistor that normally has a programming state or a cell transistor that originally has an initialization state but presents an increased cell current due to read disturbance. Therefore, in the following process, it is necessary to additionally perform a read operation of the first cell transistor 111 using a second read voltage Vread2 that is higher than the first read voltage Vread1. If a first sensing output signal SA_OUT1 having a low level is generated as a result of performing a read operation using the second read voltage Vread2, it may be indicated that the first cell transistor 111 is turned off when the second read voltage Vread2 is applied to the first cell transistor 111. This means that the cell current presented by the first cell transistor 111 is within a range between the first cell current Icell1 corresponding to the first read voltage Vread1 and the second cell current Icell2 corresponding to the second read voltage Vread2. In this case, it is highly likely that the cell current of the first cell transistor 111 that originally has an initialization state increases due to read disturbance, rather than the cell current of the first cell transistor 111 that originally has a programming state decreases due to retention degradation. In order to verify whether the cell current of the first cell transistor 111 originally having the initialized state increases due to read disturbance or the cell current of the first cell transistor 111 originally having the programmed state decreases due to retention degradation, the control circuit 170 does not generate the second sensing output signal SA_OUT2, and may perform a read operation of the second cell transistor 112 using the second read voltage Vread2 (see Fig.11 Step 423).

[0070] like Fig.16 As shown, the control circuit 170 can generate a program gate voltage Vprogram_b having a high level, a read gate voltage Vread_b having a low level, a select gate voltage VG_SG having a low level, a first switch gate voltage VG_CTS1 having a low level, and a second switch gate voltage VG_CTS2 having a high level to perform Fig.11 Step 423. In addition, the control circuit 170 may generate a first gate voltage VG1 having a high level, a second gate voltage VG2 having a low level, and a third gate voltage VG3 having a high level and output them to the read voltage selection circuit 150. Therefore, when the read switch transistor 141 is turned on, the program switch transistor 131 may be turned off. In addition, when both the selection transistor 113 of the nonvolatile memory cell 110 and the second switch transistor 122 of the cell transistor selector 120 are turned on, the first switch transistor 121 of the cell transistor selector 120 may be turned off.

[0071] As reference Figure 3 and Figure 5 As described, the read voltage selection circuit 150 may receive a first gate voltage VG1 having a high level, a second gate voltage VG2 having a low level, and a third gate voltage VG3 having a high level to generate a second read voltage Vread2 and output it through a third node NODE3 of the bit line BL. Since both the read switch transistor 141 and the select transistor 113 are turned on, the second read voltage Vread2 may be applied to the first node NODE1 of the nonvolatile memory cell 110. Since the second switch transistor 122 is turned on, the second read voltage Vread2 may be applied between the source terminal and the drain terminal of the second cell transistor 112. On the contrary, since the first switch transistor 121 is turned off, an open circuit may be provided between the drain terminal of the first cell transistor 111 and the ground voltage terminal.

[0072] As a result of the read operation of the second cell transistor 112 performed using the second read voltage Vread2, the first sense output signal SA_OUT1 may be generated to have a low level or a high level. If the first sense output signal SA_OUT1 having a low level is generated as a result of the read operation of the second cell transistor 112 performed using the second read voltage Vread2, it may be indicated that the second cell transistor 112 presents a cell current less than the second cell current Icell2 corresponding to the second read voltage Vread2. It is highly likely that the cell current of the first cell transistor 111 having an initialized state increases to be greater than the first cell current Icell1 due to read disturbance, rather than the second cell transistor 112 having a programmed state decreasing to be less than the second cell current Icell2 due to retention degradation. Therefore, the control circuit 170 may ultimately regard the nonvolatile memory cell 110 as having an initialized state to output a low level signal as the second sense output signal SA_OUT2. In addition, the first cell transistor 111 of the nonvolatile memory cell 110 may be regarded as having an increased cell current due to read disturbance.

[0073] If the first sensing output signal SA_OUT1 having a high level is generated as a result of the read operation of the second cell transistor 112 performed using the second read voltage Vread2, it may be indicated that the second cell transistor 112 presents a cell current greater than the second cell current Icell2 corresponding to the second read voltage Vread2. In this case, it is highly likely that the second cell transistor 112 having a programmed state is reduced to less than the second cell current Icell2 due to retention degradation, rather than the cell current of the first cell transistor 111 having an initialized state being increased to greater than the first cell current Icell1 due to read disturbance. Therefore, the control circuit 170 may ultimately determine the nonvolatile memory cell 110 as having a programmed state in order to output a high-level signal as the second sensing output signal SA_OUT2. In addition, the first cell transistor 111 of the nonvolatile memory cell 110 may be determined to have an increased cell current due to read disturbance.

[0074] Furthermore, if the first cell transistor 111 is turned on by a read operation of the first cell transistor 111 using the first read voltage Vread1 (see Fig.10 Step 411) and the first cell transistor 111 is turned on even by the read operation of the first cell transistor 111 using the second read voltage Vread2 (see Fig.11 Step 421), then you can execute Fig.11 Step 427. Fig.17 and Fig.18 As shown, the control circuit 170 can generate a program gate voltage Vprogram_b having a high level, a read gate voltage Vread_b having a low level, a select gate voltage VG_SG having a low level, a first switch gate voltage VG_CTS1 having a low level, and a second switch gate voltage VG_CTS2 having a high level to perform Fig.11 Step 427. In addition, the control circuit 170 may generate a first gate voltage VG1 having a high level, a second gate voltage VG2 having a low level, and a third gate voltage VG3 having a high level and output them to the read voltage selection circuit 150. Therefore, when the read switch transistor 141 is turned on, the program switch transistor 131 may be turned off. In addition, when both the selection transistor 113 of the nonvolatile memory cell 110 and the second switch transistor 122 of the cell transistor selector 120 are turned on, the first switch transistor 121 of the cell transistor selector 120 may be turned off.

[0075] As reference Figure 3 and Figure 5As described, the read voltage selection circuit 150 may receive a first gate voltage VG1 having a high level, a second gate voltage VG2 having a low level, and a third gate voltage VG3 having a high level to generate a second read voltage Vread2 and output it through a third node NODE3 of the bit line BL. Since both the read switch transistor 141 and the select transistor 113 are turned on, the second read voltage Vread2 may be applied to the first node NODE1 of the nonvolatile memory cell 110. Since the second switch transistor 122 is turned on, the second read voltage Vread2 may be applied between the source terminal and the drain terminal of the second cell transistor 112. On the contrary, since the first switch transistor 121 is turned off, an open circuit may be provided between the drain terminal of the first cell transistor 111 and the ground voltage terminal.

[0076] like Fig.17 As shown in , if a first sensing output signal SA_OUT1 having a high level is generated as a result of a read operation of the second cell transistor 112 performed using the second read voltage Vread2, it may indicate that the second cell transistor 112 presents a cell current greater than the second cell current Icell2 corresponding to the second read voltage Vread2. As a result, this may also indicate that both the cell current of the first cell transistor 111 and the cell current of the second cell transistor 112 are greater than the second cell current Icell2 corresponding to the second read voltage Vread2. It is unlikely that the cell current of the first cell transistor 111 having an initialized state increases to be greater than the second cell current Icell2 due to read interference. In addition, it is unlikely that the cell current of the second cell transistor 112 having an initialized state increases to be greater than the second cell current Icell2 due to read interference. Therefore, as shown in Fig.11 As described at step 426, the control circuit 170 may eventually determine the nonvolatile memory cell 110 as having a programmed state so as to output a high level signal as the second sensing output signal SA_OUT2. In this case, both the first cell transistor 111 and the second cell transistor 112 may be considered to be being programmed normally.

[0077] On the contrary, Fig.18As shown in , if the first sensing output signal SA_OUT1 having a low level is generated as a result of a read operation of the second cell transistor 112 performed using the second read voltage Vread2, it may indicate that the second cell transistor 112 presents a cell current that is less than the second cell current Icell2 corresponding to the second read voltage Vread2. As a result, this may also indicate that the cell current of the first cell transistor 111 is greater than the second cell current Icell2 corresponding to the second read voltage Vread2 and the cell current of the second cell transistor 112 is less than the second cell current Icell2 corresponding to the second read voltage Vread2. That is, it may indicate that the first cell transistor 111 is turned on and the second cell transistor 112 is turned off during the read operation performed using the second read voltage Vread2. This may also indicate that the cell current of the first cell transistor 111 having an initialized state increases to be greater than the second cell current Icell2 due to read interference. Alternatively, it may indicate that the cell current of the second cell transistor 112 having a programmed state decreases to be less than the second cell current Icell2 due to retention degradation. Therefore, in order to verify whether it is correct, the control circuit 170 does not generate the second sensing output signal SA_OUT2, and may perform Fig.12 The third reading process shown in .

[0078] Reference Fig.12 , which shows the third reading process, when Fig.11 When the first sensing output signal SA_OUT1 has a low level at step 428, a read operation of the second cell transistor 112 may be performed using the first read voltage Vread1 at step 431. Subsequently, it may be determined whether the first sensing output signal SA_OUT1 has a low level at step 432. When the first sensing output signal SA_OUT1 has a low level at step 432, the nonvolatile memory cell 110 may be determined to have an initialized state and the control circuit 170 may output a low level signal as the second sensing output signal SA_OUT2 at step 433. Conversely, when the first sensing output signal SA_OUT1 has a high level at step 432, the nonvolatile memory cell 110 may be determined to have a programmed state and the control circuit 170 may output a high level signal as the second sensing output signal SA_OUT2 at step 434.

[0079] The following will refer to Fig.19 Describe in more detail Fig.12 Step 431 to step 434. If Fig.11If the first sensing output signal SA_OUT1 has a low level at step 428, it may indicate that the cell current of the first cell transistor 111 is clearly greater than the second cell current Icell2 corresponding to the second read voltage Vread2 and the cell current of the second cell transistor 112 is clearly less than the second cell current Icell2 corresponding to the second read voltage Vread2. Fig.19 As shown in FIG. 1 , the control circuit 170 can generate a program gate voltage Vprogram_b having a high level, a read gate voltage Vread_b having a low level, a select gate voltage VG_SG having a low level, a first switch gate voltage VG_CTS1 having a low level, and a second switch gate voltage VG_CTS2 having a high level to perform Fig.12 Step 431. In addition, the control circuit 170 may generate a first gate voltage VG1 having a low level, a second gate voltage VG2 having a high level, and a third gate voltage VG3 having a high level and output them to the read voltage selection circuit 150. Therefore, when the read switch transistor 141 is turned on, the program switch transistor 131 may be turned off. In addition, when both the selection transistor 113 of the nonvolatile memory cell 110 and the second switch transistor 122 of the cell transistor selector 120 are turned on, the first switch transistor 121 of the cell transistor selector 120 may be turned off.

[0080] As reference Figure 3 and Figure 4 As described, the read voltage selection circuit 150 may receive a first gate voltage VG1 having a low level, a second gate voltage VG2 having a high level, and a third gate voltage VG3 having a high level to generate a first read voltage Vread1 and output it through a third node NODE3 of the bit line BL. Since both the read switch transistor 141 and the select transistor 113 are turned on, the first read voltage Vread1 may be applied to the first node NODE1 of the nonvolatile memory cell 110. Since the second switch transistor 122 is turned on, the first read voltage Vread1 may be applied between the source terminal and the drain terminal of the second cell transistor 112. On the contrary, since the first switch transistor 121 is turned off, an open circuit may be provided between the drain terminal of the first cell transistor 111 and the ground voltage terminal.

[0081] If the second cell transistor 112 is turned off when the first read voltage Vread1 is applied to the second cell transistor 112, the third node NODE3 of the bit line BL may maintain the first read voltage Vread1. Conversely, if the second cell transistor 112 is turned on when the first read voltage Vread1 is applied to the second cell transistor 112, the third node NODE3 of the bit line BL may be grounded. When the third node NODE3 of the bit line BL maintains the first read voltage Vread1, the sense amplifier circuit 160 may generate and output a first sense output signal SA_OUT1 having a low level. Conversely, when the third node NODE3 of the bit line BL is grounded, the sense amplifier circuit 160 may generate and output a first sense output signal SA_OUT1 having a high level. The first sense output signal SA_OUT1 output from the sense amplifier circuit 160 may be input to the control circuit 170. As in Fig.12 As described at step 432 , the control circuit 170 may determine whether the first sensing output signal SA_OUT1 has a low level or a high level.

[0082] When the first sensing output signal SA_OUT1 has a low level at step 432, it may indicate that the second cell transistor 112 presents a cell current less than the first cell current Icell1 corresponding to the first read voltage Vread1. This may also indicate that the cell current of the second cell transistor 112 is still less than the cell current of the first cell current Icell1 corresponding to the first read voltage Vread1 although the cell current of the first cell transistor 111 is greater than the second cell current Icell2 corresponding to the second read voltage Vread2. It is unlikely that the cell current of the second cell transistor 112 having a programmed state (i.e., a cell current having a cell current greater than the third cell current Icell3) is reduced to less than the first cell current Icell1 due to retention degradation. Therefore, in this case, the cell current of the first cell transistor 111 having an initialized state may be determined to be increased due to read disturbance. Therefore, the control circuit 170 may ultimately determine the nonvolatile memory cell 110 to have an initialized state in order to output a low-level signal as the second sensing output signal SA_OUT2. In this case, the cell current of the first cell transistor 111 may be determined to be abnormally increased due to read disturbance.

[0083] When the first sensing output signal SA_OUT1 has a high level at step 432, it may indicate that the second cell transistor 112 presents a cell current greater than the first cell current Icell1 corresponding to the first read voltage Vread1. This may also indicate that the cell current of the second cell transistor 112 is still within a range between the first cell current Icell1 corresponding to the first read voltage Vread1 and the second cell current Icell2 corresponding to the second read voltage Vread2, although the cell current of the first cell transistor 111 is greater than the second cell current Icell2 corresponding to the second read voltage Vread2. As described above, it is unlikely that the cell current of the first cell transistor 111 increases to be greater than the second cell current Icell2 due to read disturbance. Therefore, in this case, the cell current of the second cell transistor 112 having a programmed state may be determined to be reduced to a range between the first cell current Icell1 and the second cell current Icell2 due to retention degradation. Therefore, the control circuit 170 may ultimately determine the nonvolatile memory cell 110 as having a programmed state in order to output a high-level signal as the second sensing output signal SA_OUT2. In this case, the cell current of the second cell transistor 112 may be determined to decrease due to retention degradation.

[0084] The embodiments of the present disclosure have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

1. A non-volatile memory device comprising: a nonvolatile memory cell including a first cell transistor and a second cell transistor electrically coupled in parallel to a bit line and configured to have a first physical size and a second physical size, respectively; a cell transistor selector coupled between the nonvolatile memory cell and a ground voltage terminal to control an electrical connection between the first cell transistor and the ground voltage terminal and an electrical connection between the second cell transistor and the ground voltage terminal; as well as A read voltage selection circuit is adapted to selectively provide one of a first read voltage and a second read voltage to the bit line.

2. The non-volatile memory device according to claim 1, in, A first physical size of the first unit transistor corresponds to a first current driving force; as well as The second physical size of the second unit transistor corresponds to a second current driving force, and the second current driving force is greater than the first current driving force.

3. The non-volatile memory device according to claim 1, in, The first cell transistor and the second cell transistor have the same channel length; and The channel width of the second unit transistor is greater than the channel width of the first unit transistor.

4. The non-volatile memory device according to claim 1, in, The nonvolatile memory cell further includes a select transistor coupled between the bit line and the first node; as well as The first unit transistor and the second unit transistor are commonly coupled to the first node.

5. The non-volatile memory device according to claim 4, in, The first cell transistor comprises a first PMOS transistor having a floating gate; wherein the second unit transistor comprises a second PMOS transistor having a floating gate; and Wherein, the selection transistor includes a third PMOS transistor.

6. The nonvolatile memory device according to claim 5, wherein: The first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are arranged to share one active region with each other.

7. The non-volatile memory device according to claim 5, in, A source terminal of the first cell transistor and a source terminal of the second cell transistor are coupled to a drain terminal of the selection transistor; wherein a drain terminal of the first cell transistor and a drain terminal of the second cell transistor are coupled to the cell transistor selector; and Wherein, a source terminal of the selection transistor is coupled to the bit line.

8. The nonvolatile memory device according to claim 1, wherein: The cell transistor selector comprises: a first switch transistor coupled between the first cell transistor and the ground voltage terminal; and A second switch transistor is coupled between the second cell transistor and the ground voltage terminal.

9. The non-volatile memory device according to claim 8, in, The first switch transistor comprises a first NMOS transistor; and Wherein, the second switch transistor comprises a second NMOS transistor.

10. The non-volatile memory device according to claim 9, in, The first unit transistor and the second unit transistor include a first PMOS transistor and a second PMOS transistor, respectively; wherein a drain terminal of the first switch transistor is coupled to a drain terminal of the first unit transistor; wherein a drain terminal of the second switch transistor is coupled to a drain terminal of the second unit transistor; and Wherein, a source terminal of the first switch transistor and a source terminal of the second switch transistor are coupled to the ground voltage terminal.

11. The nonvolatile memory device according to claim 1, wherein: The read voltage selection circuit includes a first load transistor and a second load transistor, both of which are coupled in parallel between a read voltage supply line for providing a read voltage and the bit line.

12. The non-volatile memory device according to claim 11, in, when the first load transistor is turned on, inducing the first read voltage at the bit line; wherein when the second load transistor is turned on, the second read voltage is induced at the bit line; and The second read voltage is greater than the first read voltage.

13. The nonvolatile memory device according to claim 11, wherein: The first load transistor is configured to have a load resistance value greater than a load resistance value of the second load transistor.

14. The nonvolatile memory device according to claim 11, wherein: The read voltage selection circuit also includes a third load transistor coupled between the read voltage supply line and the bit line.

15. The non-volatile memory device according to claim 14, in, when the first load transistor is turned on, inducing the first read voltage at the bit line; wherein, when the second load transistor is turned on, the second read voltage is induced at the bit line; wherein when the third load transistor is turned on, a third read voltage is induced at the bit line; and The second read voltage is greater than the first read voltage, and the third read voltage is greater than the second read voltage.

16. The nonvolatile memory device of claim 14, wherein: The third load transistor is configured to have a load resistance value smaller than a load resistance value of the second load transistor.

17. The nonvolatile memory device of claim 1, further comprising: a program switch coupled between a program voltage supply line for supplying a program voltage and the bit line to supply the program voltage to the bit line during a program operation of the first cell transistor and the second cell transistor; as well as A read switch is coupled between an output line of the read voltage selection circuit and the bit line to provide a read voltage output from the read voltage selection circuit to the bit line during a read operation of the first cell transistor or the second cell transistor.

18. The non-volatile memory device according to claim 17, in, The programming switch includes a programming switch transistor, the programming switch transistor includes a fourth PMOS transistor; and The read switch includes a read switch transistor, and the read switch transistor includes a fifth PMOS transistor.

19. The non-volatile memory device according to claim 18, in, A source terminal and a drain terminal of the programming switch transistor are coupled to the programming voltage supply line and the bit line, respectively; and The source terminal and the drain terminal of the read switch transistor are respectively coupled to the output line of the read voltage selection circuit and the bit line.

20. The nonvolatile memory device of claim 1, further comprising a sense amplifier circuit adapted to output a low level signal or a high level signal according to a voltage level of the bit line during a read operation of the first cell transistor or the second cell transistor.

21. The nonvolatile memory device of claim 20, further comprising a control circuit adapted to control the read voltage selection circuit so that the read voltage selection circuit selectively outputs one of the first read voltage and the second read voltage during a read operation of the first cell transistor or the second cell transistor, and adapted to control the cell transistor selector so that one of the first cell transistor and the second cell transistor is selected.

22. The nonvolatile memory device of claim 21 , further comprising a program switch transistor coupled between a program voltage supply line for supplying a program voltage and the bit line to supply the program voltage to the bit line during a program operation of the first cell transistor and the second cell transistor, in, The control circuit controls the cell transistor selector to electrically connect both the first cell transistor and the second cell transistor to a ground voltage terminal during a programming operation of the first cell transistor and the second cell transistor, and controls the programming switch transistor to provide the programming voltage to the bit line during a programming operation of the first cell transistor and the second cell transistor.

23. The nonvolatile memory device of claim 22, further comprising a read switch coupled between an output line of the read voltage selection circuit and the bit line to provide a read voltage output from the read voltage selection circuit to the bit line during a read operation of the first cell transistor or the second cell transistor, in, After the programming operation of the first cell transistor and the second cell transistor, the control circuit controls the read voltage selection circuit so that the read voltage selection circuit outputs a third read voltage greater than the second read voltage to the bit line, and controls the read switch so that the programming verification operations of the first cell transistor and the second cell transistor are sequentially performed using the third read voltage.

24. The nonvolatile memory device of claim 21 , further comprising a read switch coupled between an output line of the read voltage selection circuit and the bit line to provide a read voltage output from the read voltage selection circuit to the bit line during a read operation of the first cell transistor or the second cell transistor, in, The control circuit controls the cell transistor selector, the read voltage selection circuit, and the read switch to perform a first read operation of the first cell transistor using the first read voltage, to perform a second read operation of the first cell transistor using the second read voltage when the state of the first cell transistor is affected by read disturbance or retention degradation through the first read operation, and to perform a third read operation of the second cell transistor using the second read voltage when the state of the first cell transistor is affected by read disturbance or retention degradation through the second read operation.

25. A memory device comprising: a nonvolatile memory cell comprising a first cell transistor having a first ratio of a first channel width to a first channel length and a second cell transistor having a second ratio of a second channel width to a second channel length, wherein the first ratio is different from the second ratio; a cell transistor selector adapted to electrically connect and disconnect the first cell transistor and the second cell transistor to a ground voltage terminal; A read voltage selection circuit is adapted to perform a read operation of the first cell transistor and the second cell transistor selected by the cell transistor selector to determine whether the nonvolatile memory cell has a programmed state or an initialized state according to whether the first cell transistor and the second cell transistor are turned on or off.

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