Linear switching circuit and method

Abstract

Linear switching circuits and methods are disclosed. A system includes an output terminal and a linear switching circuit coupled to the output terminal. The linear switching circuit includes a first power field effect transistor (FET) having a first channel width, a control terminal, a first current terminal, and a second current terminal coupled to the output terminal. The linear switching circuit also includes a second power FET having a second channel width less than the first channel width, a control terminal, a first current terminal coupled to the first current terminal of the first power FET, and a second current terminal coupled to the output terminal. The system also includes a control circuit coupled to the control terminal of the first power FET and the control terminal of the second power FET. The control circuit detects a saturation condition of a drain-source voltage (V DS ) and controls the first and second power FETs accordingly.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 903,494, filed September 20, 2019, the entire contents of which are incorporated herein by reference. Background Technology

[0003] The rapid development of electronic devices and integrated circuit (IC) technology has led to the commercialization of IC products. With the development of new electronic devices and the advancement of IC technology, new IC products are being commercialized. Many IC products use power field-effect transistors (FETs), and as IC technology continues to miniaturize, the safe operating area (SOA) of power FETs is becoming increasingly limited. Summary of the Invention

[0004] According to at least one example of this disclosure, a system includes an output terminal and a linear switching circuit coupled to the output terminal. The linear switching circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switching circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also includes control circuitry coupled to the control terminals of the first and second power FETs. The control circuitry is configured to: detect the drain-source voltage (Vd) associated with the first power FET. DS ) Saturation state; in response to the detection of V DS In saturation condition, the first drive signal is adjusted to the control terminal of the first power FET to reduce the current through the first power FET; and in response to detecting V DS In saturation condition, the second drive signal is adjusted to the control terminal of the second power FET to increase the current through the second power FET.

[0005] According to at least one example of this disclosure, an integrated circuit (IC) includes a first power FET in a linear switching circuit. The monolithic IC also includes a second power FET connected in parallel with the first power FET in the linear switching circuit, wherein the second power FET is smaller than the first power FET in terms of channel width. The monolithic IC also includes control circuitry coupled to the first and second power FETs, wherein the control circuitry is configured to respond to detection of a drain-source voltage (Vd) associated with the first FET. DS In the saturation state, the gate drive signal of the second power FET is increased and the gate drive signal of the first power FET is decreased.

[0006] According to at least one example of this disclosure, a circuit includes: an input voltage (VIN) terminal; an output voltage (VOUT) terminal; and a first power field-effect transistor (FET). The first power FET includes: a first channel width; a control terminal; a first current terminal and a second current terminal, wherein the second current terminal is coupled to the VOUT terminal. The circuit also includes a second power FET, which includes: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the VOUT terminal. The circuit further includes control circuitry, which includes: a sensing circuit; and a gate drive circuitry coupled to the sensing circuitry and to the control terminals of the first and second power FETs. Attached Figure Description

[0007] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0008] Figure 1 This is a block diagram illustrating a system according to an example embodiment;

[0009] Figure 2 This is a graph illustrating the drain current density according to an example embodiment. The drain current density is the gate-to-source voltage (Vd) of a field-effect transistor (FET) for different power levels. GS The function;

[0010] Figure 3 This is illustrated according to an example embodiment as the on-resistance (R) for a power FET. SP A graph of the temperature compensation point (TCP) of the function.

[0011] Figure 4 This is a schematic diagram illustrating a system according to an example embodiment;

[0012] Figure 5 This is a graph illustrating the signals of a linear switching circuit representing a soft-start failure scenario, according to an example embodiment.

[0013] Figure 6 This is a schematic diagram illustrating another system according to an example embodiment;

[0014] Figure 7 This is a graph showing the signal of a linear switching circuit representing a current-limiting scenario as a function of time, according to an example embodiment.

[0015] Figures 8-10 This is a top view illustrating the layout of an integrated circuit (IC) assembly of a linear switching circuit according to different example embodiments; and

[0016] Figure 11 This is a flowchart illustrating a linear switching circuit control method according to an example embodiment. Detailed Implementation

[0017] This article describes a linear switching circuit topology or related system with power field-effect transistors (FETs) and saturation condition protection. To avoid thermal runaway / heat dissipation scenarios in the power FETs, the drain-source voltage (Vd) of the first or main power FET is... DS The saturation condition is monitored, and another or a lower power FET is used to replace the first power FET as needed to avoid prolonged V-saturation of the first power FET. DS Saturation conditions and / or avoidance of thermal runaway conditions in the first power FET.

[0018] When the power FET is at the gate-source voltage (V DS When operating below the temperature compensation point (TCP) saturation condition, current concentration occurs due to the positive feedback loop between current density and temperature. At a given drain current and gate-source voltage (V... DS As the temperature rises, the current concentrates in a smaller and smaller region of the power FET, thereby greatly increasing the power density of the power FET region that conducts current.

[0019] When the rate at which power density increases with temperature exceeds the rate at which heat is conducted away from the channel region, a phenomenon known as “thermal runaway” occurs, and the power FET is damaged. Due to the threshold voltage of the power FET and inhomogeneities in the thermal environment (e.g., package asymmetry), the precise region in which thermal runaway will occur in a power FET is unpredictable. In one example, a thermistor is placed at the center of the power FET, but due to extreme concentrations of current and power at different points on the IC and their distance from the thermistor, the thermistor may not be heated sufficiently to activate thermal shutdown protection.

[0020] At a specific on-resistance (R) of the power FET SP ) and vulnerability to thermal runaway (high drain current density "J D TCP under "" is in A / mm 2 There is a direct (~1 / x) tradeoff between them. For cost and size reasons, very low on-resistance (R0) is desirable for linear switching applications (e.g., hot-swappable / soft-start switches, current-limiting switches, and power multiplexers). SPPower FET technology. For example, in a Universal Serial Bus Electrical Transfer (USB-PD) device, a 30V stand-off back-to-back switch is required, with a typical total on-resistance of 6mΩ. The switch needs to be housed in a 6x6mm multi-chip module (MCM) with a large controller die. While miniaturization of the IC circuitry helps to achieve lower R... SP The size target is met, but due to the high TCP, there is a trade-off that leads to a corresponding vulnerability to thermal runaway.

[0021] In at least some of the described embodiments, the first power FET has a low on-resistance (R0). SP ), and during normal conditions (e.g., when V DS The on-state current of the linear switching circuit is defined as follows: when the load current is below the threshold, when there is no fault, and / or after the startup event has completed. The second power FET is connected in parallel with the first power FET and is smaller than the first power FET in terms of channel width (W) or W / L, where L is the channel length. The R of the first power FET is... SP In comparison, the second (smaller) power FET has a higher R0. SP And it can handle higher V DS and / or higher temperatures without thermal runaway. In operation, the second power FET is configured to respond to the V of the first power FET. DS The saturation condition is used to conduct current in the linear switching circuit. In the example embodiment, the VF of the first power FET can be detected in different ways. DS Saturation condition. Without limitation, example VDS saturation condition detection options for the first power FET include: 1) measuring the VDS of the first power FET. DS And the measured V DS 1) Compare with a threshold; 2) Measure the current (I) through the first power FET. BIG_FET ) and / or the sensed current through the associated current path (e.g., a current mirror sensing current path, which provides I BIG_FET (instructions), and I BIG_FET 3) Detect startup events; and / or 4) Detect fault conditions.

[0022] Thermal runaway of the first power FET is avoided by using a second (smaller) power FET to conduct current during the VDS saturation state of the first power FET. In one example embodiment, thermal runaway of the second power FET is also avoided by aligning a thermistor or other temperature sensor within or near the IC material layout (footprint) of the second (smaller) power FET, as the IC material layer of the second power FET is a hotspot that can ultimately lead to thermal runaway and failure of the second power FET. The precise position of the thermistor relative to the IC material layout or layer of the second power FET may vary, but the thermistor should be able to detect when thermal runaway of the second power FET is likely to occur within a threshold tolerance. Even when the second power FET is at a high voltage level (e.g., when the VDS of the first power FET is at a high voltage level), thermal runaway of the second power FET is avoided. DS When saturation is present, the device is susceptible to thermal runaway. A thermistor aligned with the second power FET can detect when the second power FET has reached a temperature indicating thermal runaway. In response to the high temperature detection at the second power FET, the second power FET is disconnected to prevent damage. Instead of dealing with unpredictable thermal runaway scenarios and / or using more complex temperature sensor arrangements, at least some of the described embodiments incorporate temperature sensing aligned with the second power FET, using a second (smaller) power FET in response to the V0 of the first (larger) power FET. DS The second power FET conducts current under saturation conditions. Because the second power FET is smaller than the first power FET, thermal runaway of the second power FET is easier to predict and / or detect. Thermal runaway of the second power FET can be detected and avoided by aligning it with a temperature sensor (part of a thermal protection circuit). For better understanding, various linear switching circuit options, thermal protection issues, and IC layout options are described using the following figures.

[0023] Figure 1 This is a block diagram illustrating system 100 according to an example embodiment. Figure 1 In this context, system 100 is an example of a hot-swappable switch, a soft-start switch, a current-limiting switch, or a power multiplexer. As shown, system 100 includes an input voltage (VIN) source 102 coupled to a linear switching circuit 104. More specifically, the linear switching circuit 104 includes an input terminal 105 configured to receive VIN from the VIN source 102. Figure 1 In the example, input terminal 105 is coupled to a first power FET 108 and a second power FET 110 connected in parallel with the first power FET 108 via an optional scaling circuit 106, wherein the second power FET 110 is smaller than the first power FET 108 in terms of W and / or W / L, such that the second power FET 110 has a higher RL. SPIn some example embodiments, optional scaling circuitry 106 scales VIN, which regulates the voltage and current at the output terminal 120 of the linear switching circuit when the first power FET 108 and / or the second power FET 110 are turned on (conducted). The linear switching circuitry 104 is capable of linearly regulating the amount of current supplied to the output terminal 120 by adjusting the drive signals 115A and 115B of the first and second power FETs 108 and 110, rather than a binary on / off state.

[0024] In one example, the amount of current supplied to output terminal 120 is a function of the load 122 coupled to output terminal 120, where load 122 can be fixed or variable. If load 122 is variable, drive signals 115A and 115B can be adjusted by monitoring the voltage and / or current at output terminal 120 of linear switching circuit 104. Figure 1 In this example, load 122 is connected in parallel with a load capacitor (CLOAD) coupled between output terminal 120 and ground 130. As shown, ground 130 is also coupled to ground terminal 128 of linear switching circuit 104. In some examples, various components and / or other components of control circuit 112 may be coupled to ground terminal 128.

[0025] In operation, the first power FET 108 and the second power FET 110 are controlled by separate drive signals 115A and 115B from the control circuit 112. As shown, the control circuit 112 includes a gate drive circuit 114 coupled to a sensing circuit 116, which is configured based on a gate drive circuit (one or more) of V DS The saturation source 113 provides one or more input signals 118 to detect the V of the first power FET 108. DS Saturation state. Example V, performed by sensing circuit 116 based on (one or more) input signals 118 (not limited to this). DS Saturation detection options include: Scenario 1) Measuring the V of the first power FET108 DS And the measured V DS Compare with a threshold; Scenario 2) Measure via the first power FET (I BIG_FET The current and / or the current through the relevant current path, and I BIG_FET Compare with a threshold; Scenario 3) detect a startup event; and / or Scenario 4) detect a fault condition (e.g., a short circuit to ground).

[0026] For scenario 1, (one or more) V DS An example of saturation source 113 is the operation of the first power FET 108 supplying power to the load 122. This is due to the R... SPLow, first power FET 108 V DS The saturation condition increases its vulnerability to thermal runaway, where the V of the first power FET 108... DS It is V DS An indicator of saturation status. Accordingly, for scenario 1, the Vsaturation of the first power FET 108 is measured. DS And compared with a threshold by sensing circuit 116. If the V of the first power FET 108 DS Above the threshold (indicating V of the first power FET 108) DS If the voltage is saturated, the sensing circuit 116 provides a control signal 119 to adjust the operation of the first power FET 108 and the second power FET 110 (e.g., reduce the conduction of the first power FET 108 and increase the conduction of the second power FET 110). In some examples of Scenario 1, the sensing circuit 116 is also responsible for timing parameters, such as the measured V of the first power FET 108. DS Has the time exceeded the threshold by more than the threshold amount?

[0027] For scenario 2, (one or more) V DS The example of saturation source 113 is again the operation of the first power FET 108 supplying power to the load 122. Due to the R of the first power FET 108... SP Low, first power FET 108 V DS The saturation condition increases its vulnerability to thermal runaway, where the current through the first power FET 108 is V. DS An indicator of saturation status. Accordingly, for scenario 2, the current through the first power FET 108 is measured and compared by the sensing circuit 116 with a threshold. If the current through the first power FET 108 is higher than the threshold (indicating the V of the first power FET 108...), the current will be measured. DS If the current through the first power FET 108 is in a saturated state, the sensing circuit 116 provides a control signal 119 to regulate the operation of the first and second power FETs 108 and 110 (e.g., reduce the conduction of the first power FET 108 and increase the conduction of the second power FET 110). In some examples of Scenario 2, the sensing circuit 116 is also responsible for timing parameters, such as whether the current through the first power FET 108 has been above a threshold for a certain amount of time.

[0028] Another scenario 2 option involves using a related current path to sense the current through the first power FET. For example, a current mirror circuit coupled to one of the current terminals of the first power FET 108 can provide a sensed current proportional to the current through the first power FET 108. This sensed current provided by the current mirror is measured by sensing circuit 116 and compared with a threshold. If the measured sensed current is higher than the threshold (indicating the V08 of the first power FET 108), the sensed current is considered. DS If the conditions are saturated, the sensing circuit 116 provides a control signal 119 to regulate the operation of the first and second power FETs 108 and 110 (e.g., reduce the conduction of the first power FET 108 and increase the conduction of the second power FET 110). In some examples of this scenario 2 option, the sensing circuit 116 is also responsible for timing parameters, such as whether the sensed current provided by the current mirror is above a threshold for a period of time exceeding a threshold amount.

[0029] For scenario 3, (one or more) V DS An example of saturation source 113 is the initial power-on operation of linear switching circuit 104. Due to the R of the first power FET 108... SP Low, first power FET 108 V DS The saturation condition increases its vulnerability to thermal runaway, where the signal associated with the initial power-on operation of the linear switching circuit 104 is V. DS An indicator of saturation status. Accordingly, for scenario 3, sensing circuit 116 detects one or more signals associated with the initial power-on operation of linear switching circuit 104. In response to detecting one or more signals associated with the initial power-on operation of linear switching circuit 104, sensing circuit 116 provides control signal 119 to regulate the operation of first and second power FETs 108 and 110 (e.g., reducing conduction of first power FET 108 and increasing conduction of second power FET 110). In some examples of scenario 3, sensing circuit 116 is also responsible for timing parameters, such as whether one or more signals associated with the initial power-on operation have been asserted to have exceeded a threshold time amount.

[0030] For scenario 4, an example of one or more VDS saturation source 113 is a linear switching circuit 104 under fault conditions (e.g., short-circuit to ground). Due to the R of the first power FET 108... SP Low, first power FET 108 V DS The saturation condition increases its vulnerability to thermal runaway, where the failure condition of the linear switching circuit 104 is V. DSAn indicator of saturation condition. Accordingly, for scenario 4, sensing circuit 116 monitors one or more signals associated with a fault condition of linear switching circuit 104. In one example, sensing circuit 116 detects voltage and / or current slew rate to identify a fault condition. In another example, sensing circuit 116 receives a signal from another fault sensing circuit included in linear switching circuit 104. In either case, sensing circuit 116 is configured to respond to fault condition detection by providing control signal 119 to adjust the operation of the first power FET 108 and the second power FET 110 (e.g., reducing conduction of the first power FET 108 and increasing conduction of the second power FET 110). In some examples of scenario 4, sensing circuit 116 is also responsible for timing parameters, such as whether a fault condition has exceeded a threshold time.

[0031] When the V of the first power FET 108 is detected DS In saturation, the sensing circuit 116 provides a control signal 119 to the gate drive circuit 114, thereby causing an update to the drive signals 115A and 115B, so that in response to the detection of V of the first power FET 108... DS In saturation, the second power FET 110 conducts more current, while the first power FET 108 conducts less current.

[0032] exist Figure 1 In one example, the linear switching circuit 104 further includes a thermal protection circuit 117 configured to detect a thermal runaway condition of the second power FET 110. In response to detecting a thermal runaway condition of the second power FET 110, the thermal protection circuit 117 instructs the control circuit 112 to disconnect the first and second power FETs 108 and 110. In some example embodiments, the thermal protection circuit 117 includes a thermistor or other temperature sensor. When the temperature sensor indicates an over-temperature condition, the thermal protection circuit 117 asserts a control signal 124 to the control circuit 112. In response to receiving the control signal 124, the gate drive circuit 114 of the control circuit 112 disconnects the first and second power FETs 108 and 110. In summary, the first power FET 108 conducts current during normal operation of the linear switching circuit 104. When a V08 of the first power FET 108 is present... DS In the event of saturation (or related events such as startup or failure), the second power FET 110 conducts current instead of the first power FET 108, thereby preventing thermal runaway of the first power FET 108. If thermal runaway of the second power FET 110 is detected, the thermal protection circuit 117 disconnects the linear switching circuit 104 by correspondingly controlling drive signals 115A and 115B.

[0033] In some example embodiments, the first power FET 108, the second power FET 110, the control circuitry 112, and the thermal protection circuitry 117 are part of a single monolithic integrated circuit (IC). In other example embodiments, the control circuitry 112 is part of the first IC, while the first power FET 108, the second power FET 110, and the thermal protection circuitry 117 are part of a second IC. In other example embodiments, the control circuitry, the second power FET, and the temperature sensor are part of the first IC, while the first power FET is part of the second IC. Other arrangements are also possible where all ICs associated with the linear switching circuitry are in a single device (e.g., a system-on-a-chip, a multi-chip module, and / or a die-multiple module).

[0034] Figure 2 This is illustrated according to an example embodiment as V for different power field-effect transistors (FETs). GS The drain current density as a function (expressed as) The curve 200 shows the V values ​​for a 30V LDMOS (Laterally Diffused Metal-Oxide Semiconductor) power FET, a 30V DENMOS (Drain-Extended Metal-Oxide Semiconductor) power FET, and a 30V DMOS (Double-Diffused Metal-Oxide Semiconductor) power FET at different temperatures. GS Waveform. Specifically, the solid line corresponds to V at 175 degrees Celsius. GS The waveform, with the dashed line corresponding to V at 25 degrees Celsius. GS Waveforms. Furthermore, the corresponding temperature compensation points (TCPs) 202, 204, and 206 for each transistor type are shown in graph 200. Specifically, TCP 202 relates to a 30V DMOS power FET, TCP 204 to a 30V DENMOS power FET, and TCP 206 to a 30V vertical DMOS power FET. As shown in graph 200, at each of TCPs 202, 204, and 206, the drain current density of the power FET increases with temperature, indicating that at V... DS Thermal runaway under saturation conditions is possible and needs to be considered. As can be seen from graph 200, TCP increases with increasing power FET Rsp, meaning that smaller power FETs can handle high voltages better without triggering thermal runaway. In many applications, linear switching power FETs (FETs) operate well in TCP or the region where thermal runaway occurs.

[0035] Figure 3 This is an illustration of R as a power FET according to an example embodiment. SP The TCP function curve is shown in graph 300. As shown in graph 300, TCP changes with R... SPThe value decreases as the value increases, allowing TCP to be approximated as 1 / R. SP .exist Figure 1 In the described example embodiment, the first power FET 108 has a lower Ri than the second power FET 110. SP Therefore, the first power FET 108 has a higher current density (TCP) than the second power FET 110. Correspondingly, the first power FET 108 is more susceptible to thermal runaway than the second power FET 110. As temperature increases, the current density of the first power FET 108 increases more than that of the second power FET 110.

[0036] Figure 4 This is an illustration of system 400 according to an example embodiment. Figure 1 A schematic diagram of system 100 (example of system 100). Specifically, system 400 illustrates a soft-boot or hot-swappable system. As shown, system 400 includes a VIN source 402 ( Figure 1 Example of VIN source 102 in the example). System 400 also includes a first power FET 440 (labeled "BIG_FET", where Figure 4 BIG_FET 440 in the context is Figure 1 Example of the first power FET 108) and the second power FET 430 (labeled "LITTLE_FET, where Figure 4 LITTLE_FET 430 in the context is Figure 1 (Example of the second power FET 110 in the example). Figure 4 In the diagram, BIG_FET 440 and LITTLE_FET 430 are linear switching circuits 404 ( Figure 1 This is part of an example of a linear switching circuit 104. As shown, the linear switching circuit 404 includes a power supply terminal 450 coupled to a VIN source 402, wherein a first terminal of the VIN source 402 is coupled to the power supply terminal 450, and a second terminal of the VIN source 402 is coupled to a ground terminal 424. In operation, BIG_FET 440 and LITTLE_FET 430 are controlled to manage the current flowing to the output terminal 420 of the linear switching circuit 404. At the output terminal 420, the output capacitor (COUT) 456 is charged by the current flowing through BIG_FET 440 and / or LITTLE_FET 430 to provide an output voltage (VOUT) at the output terminal 420. Figure 4 In the example, VOUT supplies power to the load represented by load current source 422. As shown, COUT 456 and load current source 422 are connected in parallel between output terminal 420 and ground terminal 424.

[0037] exist Figure 4In the example, BIG_FET 440 and LITTLE_FET 430 are controlled by control circuit 409 ( Figure 1 Example of control circuit 112 in the example, wherein control circuit 409 is configured to selectively provide drive signal VG_BIG 448 to BIG_FET 440 and / or drive signal VG_LITTLE 438 to LITTLE_FET 430. Figure 4 In the example, control circuit 409 includes a first pull-up current source 412A, a second pull-up current source 412B, comparators 416 and 417, a voltage source 410, transistor M1 470, and transistor M2 480. The first and second reference voltage sources 414 and 418, and more specifically, the drive signal VG_BIG 448, is a function of the current supplied by the first pull-up current source 412A, which is powered by a voltage (VCP), provided by the voltage source 410 connected in series with the VIN source 402, such that VCP is higher than VIN. Operation of control circuit 409 involves transistor M2 480 having a first current terminal 482 (e.g., a drain terminal), a second current terminal 484 (e.g., a source terminal), and a control terminal 486 (e.g., a gate terminal), wherein the first current terminal 482 is coupled to the first pull-up current source 412A, the second current terminal 484 is coupled to ground terminal 424, and the control terminal 486 is coupled to the output terminal 465 of comparator 417. The operation of control circuit 409 also involves transistor M1 470 having a first current terminal 472 (e.g., drain terminal), a second current terminal 474 (e.g., source terminal), and a control terminal 476 (e.g., gate terminal), wherein the first current terminal 472 is coupled between the second pull-up current source 412B, the second current terminal 474 is coupled to ground terminal 424, and the control terminal 486 is coupled to the output terminal 455 of comparator 416. When transistor M2 480 is turned on by a control signal (bigFetEnz) from the output terminal 465 of comparator 417, a gate voltage (VG_BIG 448) is provided to the control terminal 446 of BIG_FET 440, wherein VG_BIG 448 is the current provided by the first pull-up current source 412A and the R of transistor M2 480. SP The function of LITTLE_FET 430. Furthermore, the drive signal VG_LITTLE 438 of LITTLE_FET 430 is a function of the current supplied by the second pull-up current source 412B powered by VCP. When transistor M1470 is turned on by the control signal (littleFetEnz) from the output terminal 455 of comparator 416, the gate voltage (VG_LITTLE) is provided to the control terminal 436 of LITTLE_FET 430, where VG_LITTLE is a function of the current supplied by the second pull-up current source 412B and the R of transistor M1470.SP The function. In Figure 4 In the middle, the first Zener diode (ZD1) 426 is located between the output terminal 420 and the control terminal 446 of the BIG_FET 440 to clamp the V of the BIG_FET 440. GS Additionally, a second Zener diode (ZD2) 428 is located between the output terminal 420 and the control terminal 436 of the LITTLE_FET 430 to clamp the V of the LITTLE_FET 430. GS .

[0038] exist Figure 4 In the example, the bigFetEnz at the output terminal 465 of comparator 417 is based on a comparison of the first reference voltage vRefSs at the INN input 462 (provided by the first reference voltage source 414) with the second reference voltage vRefSsDone at the INP input 464 (provided by the second reference voltage source 418). Furthermore, the littleFetEnz at the output terminal 455 of comparator 416 is based on a comparison of the first reference voltage vRefSs at the INN input 454 with VG_LITTLE at the INP input 452. In some example embodiments, the first reference voltage vRefSs from the first reference voltage source 414 provides an indication of when the soft-start interval begins, and the second reference voltage vRefSsDone from the second reference voltage source 418 provides an indication of when the soft-start interval ends.

[0039] During operation, LITTLE_FET 430 is turned on during the soft-start interval to conduct current to output terminal 420. Once the soft-start interval ends (when VOUT at output terminal 420 is charged), BIG_FET 440 is turned on to conduct current to output terminal 420. Because BIG_FET 440 is more susceptible to thermal runaway and more efficient than LITTLE_FET 430, the linear switching circuit 404 will prevent thermal runaway of BIG_FET 440 during the startup event and then switch from LITTLE_FET 430 to BIG_FET 440 during normal operation to improve the efficiency of the linear switching circuit 404, as the RV of BIG_FET 440 is significantly higher than that of LITTLE_FET 430. SP R below LITTLE_FET 430 SP .

[0040] If a load (e.g., load current source 422) is enabled during soft-start, current will flow through LITTLE_FET 430. In some example embodiments, LITTLE_FET 430 is optimized to have a low TCP and a thermistor aligned with it, thereby achieving reliable thermal protection. One advantage of the described system 400 is the avoidance of current sensing, which simplifies the safe operating area (SOA) protection operation of the linear switching circuit 404.

[0041] Figure 5 According to an example embodiment (e.g., Figure 4 System 400 shows a graph 500 of the signals of the linear switching circuit representing a soft-start fault scenario. In graph 500, the waveforms represented include the gate-source voltage (VGS_LITTLE_FET) of LITTLE_FET 430, the gate-source voltage (VGS_BIG_FET) of BIG_FET 440, the drain-source voltage (VDS) of BIG_FET 440, the drain current (ID_BIG_FET) of LITTLE_FET 430, and the drain current (ID_BIG FET) of BIG_FET 440 as functions of time. For graph 500, the following assumptions are made: 1) When VOUT exceeds 4V, the soft-start interval (VIN = 20V) enters the participating 1A load; 2) All load current is conducted through LITTLE_FET 430; 3) LITTLE_FET 430 is sized to have a 1A load V GS 4) The thermistor placed in the center of the LITTLE_FET430 tracks the highest FET temperature well, allowing reliable triggering of thermal shutdown protection.

[0042] As shown in graph 500, during the time corresponding to the startup event, VGS_LITTLE_FET initially increases, VDS decreases, and ID_LITTLE_FET rises. After the startup event, VDS remains low while BIG_FET 440 is turned on, causing VGS_BIG_FET to increase, ID_LITTLE_FET to decrease, and ID_BIG_FET to rise. The linear switching circuit can switch back and forth between BIG_FET 440 and LITTLE_FET 430 as needed to supply current to the output terminal (e.g., output terminal 420), where BIG_FET 440 is used for normal operation, and VGS_LITTLE_FET 430 is detected. DS LITTLE_FET 430 is used in saturation conditions.

[0043] Figure 6This is an example embodiment illustrating another system 600 ( Figure 1 A schematic diagram of system 100 (example). Specifically, system 600 corresponds to a current limiting system. As shown, system 600 includes a VIN source 602 ( Figure 1 Example of VIN source 102 in the example). System 600 also includes a first power FET 640 (labeled "BIG_FET", where Figure 6 BIG_FET640 in the text is Figure 1 Example of the first power FET 108) and the second power FET 630 (labeled "LITTLE_FET") Figure 6 LITTLE_FET 630 in the context is Figure 1 (Example of the second power FET 110 in the example). Figure 6 In this circuit, BIG_FET 640 and LITTLE_FET 630 are part of the linear switching circuit 604. Figure 1 (Example of linear switching circuit 604). As shown, linear switching circuit 604 includes a power supply terminal 650 coupled to a VIN source 602, wherein a first end of the VIN source 602 is coupled to the power supply terminal 650, and a second end of the VIN source 602 is coupled to a ground terminal 624. In operation, BIG_FET 640 and LITTLE_FET 630 are controlled to manage the current flowing to the output terminal 620 of linear switching circuit 604. At the output terminal 620, the output capacitor (COUT) 656 is charged by the current flowing through BIG_FET 640 and / or LITTLE_FET 630 to provide an output voltage (VOUT) at the output terminal 620. Figure 6 In the example, VOUT is supplied to the load represented by the variable resistor 622. As shown, COUT 656 and the variable resistor 622 are connected in parallel between the output terminal 620 and the ground terminal 624.

[0044] exist Figure 6 In the example, BIG_FET 640 and LITTLE_FET 630 are controlled by circuitry 609. Figure 1 Example of control circuit 112 in the example, wherein control circuit 609 is configured to selectively provide drive signal VG_BIG 648 to BIG_FET 440 and / or drive signal VG_LITTLE 638 to LITTLE_FET 430. Figure 6In the example, control circuit 609 includes first and second pull-up current sources 612A and 612B, transistor M3 670, transistor M4 680, comparators 614 and 618, voltage sources 610 and 616, resistors R1 and R2, transistor M5 690, and resistor R3. More specifically, the drive signal VG_BIG 648 is a function of the current supplied by the first pull-up current source 612A powered by VCP, where VCP is supplied by a voltage source 610 connected in series with source 602 VIN, such that VCP is higher than VIN. The operation of control circuit 609 also relates to a transistor M3 670 having a first current terminal 682 (e.g., drain terminal), a second current terminal 684 (e.g., source terminal), and a control terminal 686 (e.g., gate terminal), wherein the first current terminal 682 is coupled to a first pull-up current source 612A, the second current terminal 684 is coupled to a ground terminal 624, and the control terminal 686 is coupled to a control signal 619 provided by the output 665 of comparator 618. The operation of control circuit 609 also relates to a transistor M3 670 having a first current terminal 672 (e.g., drain terminal), a second current terminal 674 (e.g., source terminal), and a control terminal 676 (e.g., gate terminal), wherein the first current terminal 672 is coupled to a second pull-up current source 612B, the second current terminal 674 is coupled to a ground terminal 624, and the control terminal 676 is coupled to the control signal 619 provided by the output 665 of comparator 618.

[0045] When transistor M4 680 is turned on by control signal 619, drive signal VG_BIG 648 is provided to control terminal 646 of BIG_FET 640. Drive signal VG_BIG 648 is generated by the current supplied by the first pull-up current source 612A and the R of transistor M4 680. SP The function is as follows. Furthermore, the drive signal VG_LITTLE 638 of LITTLE_FET 630 is a function of the current supplied by the second pull-up current source 612B powered by VCP. When transistor M3 670 is turned on by control signal 619, the drive signal VG_LITTLE 638 is provided to the control terminal 636 of LITTLE_FET 630, where VG_LITTLE 638 is a function of the current supplied by the second pull-up current source 612B and the current supplied by the pull-up current source 612B of M3. SP The function. As shown in the figure, capacitor C1, coupled to control terminal 636 of LITTLE_FET 630, is used to drive signal VG_LITTLE638. In Figure 6 In this configuration, the first Zener diode (ZD3) 626 is located between the output terminal 620 and the control terminal 646 of the BIG_FET 640 to clamp the V of the BIG_FET 640. GSAdditionally, a second Zener diode (ZD4) 628 is located between the output terminal 620 and the control terminal 636 of the LITTLE_FET 630 to clamp the V of the LITTLE_FET 636. GS .

[0046] As shown in the figure, comparator 618 provides control signal 619 to transistors M3 670 and M4 680. Comparator 618 is configured to compare a sensed current signal (iSense) at INP input 662 with a reference current value (iLimRef) at INN input 664, where iLimRef is provided to voltage source 616. More specifically, iSense is generated using sense resistors R1 and R2, where comparator 614 compares the voltage drop caused by R1 with the voltage drop caused by R2. The output 655 of comparator 614 is coupled to the control terminal of transistor M5 690, causing transistor M5 690 to turn on when the current to output terminal 620 is greater than a threshold.

[0047] As shown in the figure, transistor M5 690 includes a first current terminal 692 (e.g., source terminal), a second current terminal 694 (e.g., drain terminal), and a control terminal 686 (e.g., gate terminal). When transistor M5 690 is turned on, the current flowing through transistor M5 690 generates a voltage due to resistor R3, which is coupled between the second current terminal 694 of transistor M5 690 (also coupled to the INP input 662 of comparator 618) and ground terminal 624. In summary, iSense provides V for BIG_FET 640. DS When will it be greater than V corresponding to BIG_FET 640? DS An indication of the saturation threshold. In other examples, another technique is used to determine when V is present in the BIG_FET 640. DS Saturation state.

[0048] During operation, when the current to output terminal 620 exceeds a threshold, LITTLE_FET 630 conducts current to output terminal 620. Otherwise, BIG_FET 640 conducts current to output terminal 620. To guide current into LITTLE_FET 630 during current-limited conditions, the size ratio of transistor M4 680 to transistor M3 670 is set (e.g., 5:1, where transistor M4 680 is 5 times the size of transistor M3 670) so that VG_BIG 648 is strongly pulled down at control terminal 646 of BIG_FET 640 when the loop is in regulation. When in regulation, the drain current of transistor M3 670 is equal to the pull-up current (Id). PU The pull-up current (I) of source 612BPU In such an example, transistor M4 680 is larger than transistor M3 670 (with regard to W or W / L), and BIG_FET 640 is off when under regulation.

[0049] Figure 7 According to an example embodiment (e.g., Figure 6 The system 600 shows a graph 700 of the signals of a linear switching circuit representing a current-limiting scenario as a function of time. In graph 700, the waveforms represented include VIN, VOUT, the current through LITTLE_FET 630 (I_LITTLE_FET), and the current through BIG_FET 640 (I_BIGFET). For graph 700, the assumptions include: 1) both power FETs are initially turned on; 2) the current-limiting reference (e.g., ...) is... Figure 6 The following parameters are specified: 1) iLimRef is set to 1.0A; 2) the load resistance is sloping downwards (linear with 1 / RLOAD); 3) all load current is directed to LITTLE_FET 630 upon entering the current-limiting condition; and 4) the size of LITTLE_FET 630 or the type of device selected for LITTLE_FET 630 is less affected by thermal runaway under current-limiting conditions compared to BIG_FET 640. In some examples, a thermistor is placed at the center of LITTLE_FET 630 to detect and respond to thermal runaway conditions of LITTLE_FET 630 as needed. As shown in graph 700, an increase in load (or a decrease in load resistance, resulting in a larger load current) causes I_BIG_FET to increase, and eventually causes VOUT to decrease. Once the current-limiting condition is reached, I_BIG_FET decreases (BIG_FET turns off), and I_LITTLE_FET goes high (LITTLE_FET 630 turns on).

[0050] Figures 8-10 This is a top view illustrating the IC layout of a linear switching circuit assembly according to different example embodiments. Figure 8 In the diagram, a monolithic IC arrangement 800 is indicated, wherein the monolithic IC arrangement 800 includes first power FET regions 802A and 802B (e.g., with...). Figure 1 The first power FET in the middle is 108. Figure 4 BIG_FET 440 or Figure 6 A single IC, chip, or die 801 (related to BIG_FET 640 in the diagram), and a second power FET region 804 (e.g., with BIG_FET 640 in the diagram) Figure 1 The second power FET 110 in the middle Figure 4 LITTLE_FET 430 or Figure 6(related to LITTLE_FET 630 in the text), and the thermistor 806 aligned with the second power FET region 804 (e.g., with...). Figure 1 (related to the thermal protection circuit 117 in the middle) and control circuit area 808 (e.g., with Figure 1 Related to or related to control circuit 112 in the middle. Figure 4 and Figure 6 (Related to the control circuit components in the document). Using a monolithic IC layout 800, as described herein, thermal runaway associated with the first power FET regions 802A and 802B is avoided. Furthermore, the detection of thermal runaway in the second power FET region 804 (e.g., using a thermistor 806) is relatively simple because the second power FET region 804 is smaller in size compared to the first power FET regions 802A and 802B.

[0051] exist Figure 9 In the image, a multi-chip module (MCM) arrangement 900 is represented, wherein the MCM arrangement 900 includes a control circuit 908 (e.g., with...). Figure 1 Control circuit 112 in Figure 4 Control circuit 409 or Figure 6 The first IC, chip, or die 901A is associated with the control circuit 609 in the MCM arrangement 900. The MCM arrangement 900 also includes a second IC chip or die 901B that communicates with the first IC, chip, or die 901A. As shown, the second IC, chip, or die 901B includes first power FET regions 902A and 902B (e.g., related to...). Figure 1 The first power FET in the middle is 108. Figure 4 BIG_FET 440 or Figure 6 (related to BIG_FET 640 in the text), and the second power FET region 904 (e.g., with...) Figure 1 The second power FET 110 in the middle Figure 4 LITTLE_FET 430 or Figure 6 (related to LITTLE_FET630 in the image), and the thermistor 906 aligned with the second power FET region 904 (e.g., with...). Figure 1 (Related to the thermal protection circuit 117 in the document). Using an MCM arrangement 900, as described herein, thermal runaway associated with the first power FET regions 902A and 902B is avoided. Moreover, the detection of thermal runaway in the second power FET region 904 (e.g., using a thermistor 906) is relatively simple because the second power FET region 904 is smaller in size compared to the first power FET regions 902A and 902B.

[0052] exist Figure 10In the middle, it represents another MCM arrangement 1000, wherein the MCM arrangement 1000 includes a control circuit 1008 (e.g., with...). Figure 1 Related to control circuit 112, or Figure 4 and Figure 6 The first IC, chip, or chip 1001A (related to the control circuit components in the middle), and the second power FET region 1004 (e.g., with...) Figure 1 The second power FET 110 in the middle Figure 4 LITTLE_FET430 or Figure 6 (related to LITTLE_FET 630 in the text), and the thermistor 1006 aligned with the second power FET region 1004 (e.g., with...). Figure 1 (Related to the thermal protection circuit 117 in the middle). The MCM arrangement 1000 also includes a first power FET region 1002 (e.g., with...). Figure 1 The first power FET in the middle is 108. Figure 4 BIG_FET440 or Figure 6 The second IC, chip, or die 1001B (related to BIG_FET 640 in the document) is used. An MCM arrangement 1000 is used, as described herein, to avoid thermal runaway associated with the first power FET region 1002. Furthermore, the detection of thermal runaway in the second power FET region 1004 (e.g., using a thermistor 1006) is relatively simple because the second power FET region 1004 is smaller in size compared to the first power FET region 1002. In some examples, the first power FET region 1002 is designed for low R... SP Furthermore, the second power FET region 1004 is optimized to meet thermal SOA targets.

[0053] The described embodiments provide improved VF for power FETs in linear switching circuits or related systems. DS Saturation protection. In some example implementations (e.g., linear current limiting or soft-start / hot-swap switches), two power FETs are used instead of one. The first power FET is larger and for R... SP Optimizations have been made. Using the same FET technology as the first power FET, the second power FET is smaller or biased above the TCP. Another option is to use a different FET type, with a lower TCP for the second power FET. The first power FET is fully turned on at normal low V. DS Under operating conditions, it conducts most of the load current. At high V... DSDuring startup events or fault conditions at voltage levels, the second power FET conducts current. Directing current into the second power FET provides control over where the hotspot will be located and the location of the thermal sensing diode. In the described embodiment, the hotspot is more likely to be located within the smaller second power FET, which facilitates detection using a conventional thermistor.

[0054] Figure 11 This is a flowchart illustrating a linear switching circuit control method 1100 according to an example embodiment. The linear switching circuit control method 1100 is, for example, controlled by a control circuit for a linear switching device (e.g., Figure 1 Control circuit 112 in Figure 4 Control circuit 409 or Figure 6 The control circuit 609 in the figure is used to perform this. As shown, method 1100 includes monitoring the first power FET (e.g., at block 1102) at block 1102. Figure 1 The first power FET in the middle is 108. Figure 4 BIG_FET 440 in Figure 6 V of BIG_FET640 DS Saturation condition. If V is not detected for the first power FET... DS If saturation condition is detected (decision box 1104), then method 1100 continues with the operation of box 1102. At box 1106, if V is detected by the first power FET... DS In the saturation state (determination box 1104), the first drive signal is adjusted to the control terminal of the first power FET to reduce the current flowing through the first power FET, and the signal is adjusted to the second power FET (e.g., in the linear switching circuit connected in parallel with the first power FET) (e.g., Figure 1 The second power FET110 in Figure 4 LITTLE_FET 430 in Figure 6 The second drive signal of the control terminal of LITTLE_FET 630 in the first power FET is used to increase the current flowing through the second power FET. If no thermal condition (e.g., over-temperature condition) is detected using a temperature sensor aligned with the second power FET (decision box 1108) and the V of the first power FET is... DS If the saturation condition has not yet ended (decision block 1112), method 1100 returns to decision block 1108. If a thermal condition (e.g., over-temperature condition) is detected using a temperature sensor aligned with the second power FET (decision block 1108), the second power FET is disconnected at block 1110. The first power FET can also be disconnected at block 1110. At block 1114, if no thermal condition is detected using a temperature sensor aligned with the second power FET (decision block 1108), and the V of the first power FET... DSIf the saturation condition has ended (decision box 1112), then the first drive signal to the control terminal of the first power FET is adjusted to increase the current flowing through the first power FET, and the second drive signal to the control terminal of the second power FET is adjusted to decrease the current flowing through the second power FET. Method 1100 can be repeated as needed.

[0055] Certain terms are used in this specification and claims to refer to specific system components. As those skilled in the art will understand, different parts may be referred to by different names. This document is not intended to distinguish between components that differ only in name but are not different in their respective functions or structures. In this invention and claims, the term "comprising" is used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to..."

[0056] The term "coupling" is used throughout this specification. This term can encompass a connection, communication, or signal path that achieves a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example, device A is coupled to device B via a direct connection; or in a second example, if intervening component C does not alter the functional relationship between device A and device B such that a control signal generated by device B via device A is controlled by device A, then device A is coupled to device B via intervening component C.

[0057] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once the foregoing disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art.

Claims

1. A system comprising: A first field-effect transistor (FET) has a first gate, a first drain, and a first source. The first FET includes a first channel having a first channel width. A second FET has a second gate, a second drain, and a second source. The second FET includes: a second channel having a second channel width smaller than the width of the first channel; the second drain is coupled to the first drain; and the second source is coupled to the first source. A control circuit coupled to the first gate and the second gate, wherein the control circuit is configured to: Detect the saturation status of the drain-source voltage VDS associated with the first FET; In response to detecting the VDS saturation condition, the first drive signal to the first gate is adjusted to reduce the first current through the first FET; and In response to the detection of the VDS saturation condition, the second drive signal to the second gate is adjusted to increase the second current through the second FET.

2. The system of claim 1, wherein the first FET and the second FET are components of a single integrated circuit IC.

3. The system according to claim 2, wherein the IC comprises: The first portion of the first FET; The second part of the first FET; as well as The second FET, wherein the first portion and the second portion of the first FET are located on opposite sides of the second FET.

4. The system according to claim 2, wherein the control circuit is located in the IC.

5. The system according to claim 2, wherein the IC is a first IC, and wherein the control circuit is in a second IC.

6. The system of claim 2 further includes a temperature sensor aligned with the second FET.

7. The system according to claim 1, wherein, The first FET is located in a first IC, and the control circuit and the second FET are located in a second IC.

8. The system according to claim 1, wherein the control circuit comprises: A sensing circuit configured to detect the saturation state of the VDS; as well as A gate drive circuit is configured to provide a first gate drive signal to the first FET when the VDS saturation condition is not met, and to provide a second gate drive signal to the second FET when the VDS saturation condition is met.

9. The system according to claim 1, wherein the control circuit comprises: A sensing circuit configured to detect a startup event associated with the VDS saturation state; as well as A gate drive circuit is configured to provide a first gate drive signal to the first FET when the VDS saturation condition is not met, and to provide a second gate drive signal to the second FET when the VDS saturation condition is met.

10. The system of claim 1, wherein the control circuit comprises: A sensing circuit configured to detect fault conditions associated with the VDS saturation condition; as well as A gate drive circuit is configured to provide a first gate drive signal to the first FET when the VDS saturation condition is not met, and to provide a second gate drive signal to the second FET when the VDS saturation condition is met.

11. An integrated circuit IC, comprising: A first field-effect transistor (FET) includes a first channel having a first channel width; A second FET connected in parallel with the first FET, the second FET including a second channel having a second channel width smaller than the first channel width; as well as A control circuit coupled to the first FET and the second FET, wherein the control circuit is configured to increase a first gate drive signal to the second FET and decrease a second gate drive signal to the first FET in response to detecting a saturation state of the drain-source voltage VDS associated with the first FET.

12. The IC of claim 11, wherein the IC comprises: A first region, which includes the first FET; The second region includes the control circuitry and the second FET. The first region is separated from the second region, and each part of the control circuit is located on the opposite side of the second FET.

13. The IC of claim 12, further comprising a temperature sensor aligned with the second FET.

14. The IC of claim 11, wherein the IC comprises: The first portion of the first FET; The second part of the first FET; as well as The second FET, wherein the first portion and the second portion of the first FET are located on opposite sides of the second FET.

15. The IC of claim 14, further comprising a temperature sensor aligned with the second FET.

16. A circuit comprising: A first field-effect transistor (FET) has a first gate, a first drain, and a first source, and the first FET includes a first channel having a first channel width. The second FET has a second gate, a second drain, and a second source. The second FET includes a second channel with a second width that is smaller than the width of the first channel. The second drain is coupled to the first drain and the second source is coupled to the first source. as well as Control circuit, comprising: Sensing circuit; and A gate driving circuit, coupled to the sensing circuit, the first gate, and the second gate, The gate drive circuit is configured as follows: In response to the sensing circuit detecting a saturation state of the drain-source voltage VDS of the first FET, the first drive signal to the first gate is adjusted to reduce the first current flowing through the first FET; and In response to the sensing circuit detecting VDS saturation of the first FET, the second drive signal to the second gate is adjusted to increase the second current through the second FET.

17. The circuit of claim 16, wherein the first FET and the second FET are components of a single integrated circuit IC.

18. The circuit of claim 17, wherein the IC comprises: The first portion of the first FET; The second part of the first FET; as well as The second FET, wherein the first portion and the second portion of the first FET are located on opposite sides of the second FET.

19. The circuit of claim 17, wherein the control circuit is included in the IC.

20. The circuit of claim 17, wherein the IC is a first IC, and wherein the control circuit is part of a second IC.

21. The circuit of claim 17, further comprising a temperature sensor aligned with the second FET.

22. The circuit of claim 16, wherein the sensing circuit is configured to detect a VDS saturation state or an event associated with the VDS saturation state, wherein the gate drive circuit is configured to: When the VDS saturation condition is not met, a first gate drive signal is provided to the first FET; and When the VDS saturation condition is met, a second gate drive signal is provided to the second FET.

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