Chip package, process method thereof and electronic device

Abstract

The application discloses a chip package, a manufacturing method thereof and an electronic device. The chip package comprises a patterned metal substrate plate, a chip disposed on the metal substrate plate, a first insulating layer covering the chip and the metal substrate plate, wherein a through hole is disposed in the first insulating layer to expose part of the metal substrate plate and the chip, and a patterned first conductive layer disposed on the first insulating layer and in the through hole to connect the chip to the metal substrate plate through the first conductive layer. In this way, the chip package can realize double-side heat dissipation of the chip, has a simple structure, short electrical path and heat dissipation path, excellent low resistance characteristics and heat dissipation effect, and can realize miniaturization and lightness and thinness of the chip package.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip package, its manufacturing process, and an electronic device. Background Technology

[0002] In recent years, with the application of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) power modules in almost all power industrial products, corresponding power devices have also been steadily developing towards high performance, high speed, small size and multi-chip interconnection packaging.

[0003] However, traditional wire bonding and double-sided copper interconnect processes are increasingly failing to meet the demands of power devices for high performance, high speed, small size, multi-chip interconnection, and modularity. Power semiconductor packaging technology needs to evolve towards the superior PLFO (Pane Level Fan Out) packaging technology. Summary of the Invention

[0004] This application provides a chip package, its manufacturing process, and an electronic device to solve the problem that existing chip packages cannot achieve miniaturization, thinness, and excellent electrical and heat dissipation characteristics.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a chip package, wherein the chip package includes: a patterned metal substrate; a chip disposed on the metal substrate; a first insulating layer covering the chip and the metal substrate, wherein the first insulating layer has through holes to expose portions of the metal substrate and the chip; and a patterned first conductive layer disposed on the first insulating layer and in the through holes, so that the chip is connected to the metal substrate through the first conductive layer.

[0006] In this design, a patterned second conductive layer is disposed between the overlapping portion of the first insulating layer and the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate through the first conductive layer.

[0007] A third conductive layer is provided between the overlapping part of the metal substrate and the chip, and the chip is bonded to the metal substrate through the third conductive layer.

[0008] The chip package also includes a conductive metal layer, which is disposed on the surface of the metal substrate away from the first insulating layer.

[0009] The chip package also includes a second insulating layer, which covers the first conductive layer and the partially exposed first insulating layer.

[0010] The surface area of ​​the through hole facing the metal substrate is smaller than the surface area of ​​the side away from the metal substrate.

[0011] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a chip package manufacturing method, wherein the manufacturing method includes: placing a chip on a metal substrate; forming a first insulating layer on the metal substrate on which the chip is placed to cover the chip and the metal substrate; patterning the first insulating layer to form a patterned first insulating layer, wherein the patterned first insulating layer has through holes to expose portions of the metal substrate and the chip; forming a first conductive layer on the patterned first insulating layer, and filling the through holes with the first conductive layer; patterning the first conductive layer to form a patterned first conductive layer; and patterning the metal substrate to form a patterned metal substrate, thereby connecting the chip to the patterned metal substrate through the patterned first conductive layer.

[0012] The process includes, after the step of forming a first insulating layer on a metal substrate on which the chip is disposed to cover the chip and the metal substrate, patterning the first insulating layer to form a patterned first insulating layer, and before the step of having through holes in the patterned first insulating layer to expose portions of the metal substrate and the chip, the process further includes: forming a second conductive layer on the first insulating layer; patterning the first insulating layer to form a patterned first insulating layer, wherein the step of having through holes in the patterned first insulating layer to expose portions of the metal substrate and the chip includes: patterning the first insulating layer and the second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein the patterned first insulating layer... The steps of forming a first conductive layer on a patterned first insulating layer and filling the through-holes with the first conductive layer include: forming a first conductive layer on a patterned first insulating layer and a patterned second conductive layer, and filling the through-holes with the first conductive layer; and patterning a metal substrate to form a patterned metal substrate, thereby connecting the chip to the patterned metal substrate via the patterned first conductive layer, including: patterning a metal substrate to form a patterned metal substrate, thereby connecting the chip to the patterned second conductive layer and the patterned metal substrate via the patterned first conductive layer.

[0013] The step of setting the chip on the metal substrate specifically includes: forming a third conductive layer on the metal substrate; and setting the chip on the third conductive layer.

[0014] The step of forming a patterned metal substrate to connect the chip to the patterned metal substrate via a patterned first conductive layer further includes: forming a conductive metal layer on the surface of the patterned metal substrate away from the first insulating layer.

[0015] The step of forming a patterned metal substrate to connect the chip to the patterned metal substrate via a patterned first conductive layer further includes: forming a second insulating layer on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

[0016] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide an electronic device, wherein the electronic device includes a chip package as described in any of the preceding claims.

[0017] The beneficial effects of this application are as follows: Unlike existing technologies, the chip package in this application includes: a patterned metal substrate; a chip disposed on the metal substrate; a first insulating layer covering the chip and the metal substrate, wherein through-holes are provided in the first insulating layer to expose portions of the metal substrate and the chip; and a patterned first conductive layer disposed on the first insulating layer and within the through-holes, so that the chip is connected to the metal substrate via the first conductive layer. Through the above method, the chip package in this application can achieve double-sided heat dissipation of the chip, and has a relatively simple structure with short electrical and heat dissipation paths, exhibiting excellent low-resistance characteristics and heat dissipation effect, enabling miniaturization and thinning of the chip package. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0019] Figure 1 This is a schematic diagram of the structure of the first embodiment of the chip package of this application;

[0020] Figure 2 This is a schematic diagram of the structure of the second embodiment of the chip package of this application;

[0021] Figure 3 This is a schematic diagram of the structure of the third embodiment of the chip package of this application;

[0022] Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the chip package of this application;

[0023] Figure 5 This is a schematic diagram of the structure of the fifth embodiment of the chip package of this application;

[0024] Figure 6 This is a schematic diagram of the structure of the sixth embodiment of the chip package of this application;

[0025] Figure 7a This is a flowchart illustrating the first embodiment of the chip package manufacturing method of this application;

[0026] Figures 7b-7g for Figure 7a A structural schematic diagram of one embodiment corresponding to S710-S760;

[0027] Figure 8a This is a flowchart illustrating the second embodiment of the chip package manufacturing method of this application;

[0028] Figures 8b-8f for Figure 8a A structural schematic diagram of one embodiment corresponding to S830-S870;

[0029] Figure 9a This is a flowchart illustrating the third embodiment of the chip package manufacturing method of this application;

[0030] Figures 9b-9c for Figure 9a A structural schematic diagram of one embodiment corresponding to S910-S920;

[0031] Figure 10a This is a flowchart illustrating the fourth embodiment of the chip package manufacturing method of this application;

[0032] Figure 10b for Figure 10a A schematic diagram of one embodiment corresponding to S1070;

[0033] Figure 11a This is a flowchart illustrating the fifth embodiment of the chip package manufacturing method of this application;

[0034] Figure 11b for Figure 11a A structural schematic diagram of one embodiment corresponding to S1170;

[0035] Figure 12 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation

[0036] To make the technical problems solved by this application, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0037] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0038] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the chip package of this application.

[0039] In this embodiment, the chip package includes a patterned metal substrate 11, a chip 21, a first insulating layer 31, and a patterned first conductive layer 41. The chip 21 is disposed on the metal substrate 11, and the first insulating layer 31 covers both the chip 21 and the metal substrate 11. The first insulating layer 31 has through-holes to expose portions of the metal substrate 11 and the chip 21. Furthermore, the first conductive layer 41 is disposed in the through-holes and on the first insulating layer 31, enabling the chip 21 to achieve electrical connection with the metal substrate 11 via the first conductive layer 41, ultimately forming the pins of the chip package. This results in a shorter electrical and heat dissipation path for the chip package, and excellent low-resistance characteristics and heat dissipation performance.

[0040] The first insulating layer 31 contains at least two vias, with at least one via disposed above the chip 21 and at least another via disposed on the metal substrate 11. The at least two vias are electrically connected to each other via a first conductive layer 41 covering the interior of each via. A portion of the metal substrate 11 below the at least two vias can serve as a package pin for the chip package, enabling electrical connection to external devices or other chips.

[0041] The patterning of the metal substrate 11 and the first conductive layer 41 is a corresponding setting made to adapt to the logic circuit to be implemented by the chip 21. Different chip pins correspond to different patterned electrical paths. This patterning can be completed by chemical etching or ion etching.

[0042] Optionally, the material of the metal substrate 11 can be one of copper, aluminum, gold, silver and their alloys or metal-filled organic materials, the material of the first insulating layer 31 can be one of organic insulating materials filled with silicon dioxide, silicon nitride, silicon oxynitride, circuit board materials, ink, and the material of the first conductive layer 41 is selected from one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organic materials, so that the chip 21 in the chip package can achieve double-sided heat dissipation through the metal substrate 11 and the first conductive layer 41 in the through hole, thereby having better heat dissipation characteristics.

[0043] Optionally, the surface area of ​​the through hole in the first insulating layer 31 on the side facing the metal substrate 11 can be set to be smaller than the surface area on the side away from the metal substrate 11. That is, the bottom areas on both sides of the through hole can be set to be different. At the same time, the through hole can also penetrate the metal substrate 11. In other embodiments, the bottom areas on both sides of the through hole can also be set to be the same. This application does not limit this.

[0044] Optionally, the edge portion of the first insulating layer 31 corresponding to the corresponding through hole can be a bevel with at least two different angles, or a reasonable structural style such as an arc-shaped surface or a wavy surface.

[0045] Unlike existing technologies, the chip package in this application includes: a patterned metal substrate; a chip disposed on the metal substrate; a first insulating layer covering the chip and the metal substrate, wherein the first insulating layer has through holes to expose portions of the metal substrate and the chip; and a patterned first conductive layer disposed on the first insulating layer and within the through holes, so that the chip is connected to the metal substrate through the first conductive layer. Through this method, the chip in the chip package of this application can dissipate heat through the patterned metal substrate and the patterned conductive layer with a larger heat dissipation area disposed within the through holes of the insulating layer, thereby enabling double-sided heat dissipation. This also simplifies the structure of the chip package, shortens the electrical and heat dissipation paths, resulting in excellent low-resistance characteristics and heat dissipation performance, and enabling miniaturization and thinning of the chip package.

[0046] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a second embodiment of the chip package of this application. This embodiment is similar to... Figure 1 The difference in the first embodiment of the chip package provided in this application is that the chip package further includes a patterned second conductive layer 51, wherein the second conductive layer 51 is disposed between the overlapping portion of the first insulating layer 31 and the first conductive layer 41.

[0047] In this embodiment, the second conductive layer 51 is disposed on the portion of the first insulating layer 31 where no through holes are formed. The chip 21 is connected to the second conductive layer 51 through the first conductive layer and is finally connected to the metal substrate 11.

[0048] The material used in the second conductive layer 51 is also selected from copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organic materials, and this application does not limit it.

[0049] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of the third embodiment of the chip package of this application. This embodiment is related to this application. Figure 1 The difference in the first embodiment of the chip package provided is that the chip package further includes a third conductive layer 61, wherein the third conductive layer 61 is disposed between the overlapping portion of the metal substrate 11 and the chip 21.

[0050] In this embodiment, a third conductive layer 61 is first provided on the metal substrate 11, and the chip 21 is correspondingly disposed on the third conductive layer 61. The chip 21 can achieve close adhesion with the metal substrate 11 through the third conductive layer 61.

[0051] Optionally, the third conductive layer 61 can be a conductive adhesive with adhesive properties, that is, an adhesive that has a certain conductivity after curing or drying, such as one of silver-based conductive adhesive, gold-based conductive adhesive, copper-based conductive adhesive and carbon-based conductive adhesive, or an adhesive alloy, such as copper, aluminum, gold, silver and their alloys or metal-filled organic matter. The third conductive layer 61 enables the chip 21 to be reliably connected to the metal substrate 11 and forms an effective conductive path.

[0052] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the chip package of this application. This embodiment is related to this application. Figure 1 The difference in the first embodiment of the chip package provided is that the chip package further includes a conductive metal layer 71, wherein the conductive metal layer 71 is disposed on the surface of the metal substrate 11 away from the first insulating layer 31, that is, the conductive metal layer 71 is disposed on the surface of the metal substrate 11 on the other side where the chip 21 is disposed.

[0053] In this embodiment, the conductive metal layer 71 is made of the same material as the metal substrate 11, selected from copper, aluminum, gold, silver and their alloys or metal-filled organic materials. It is a thickened stacked layer of the metal substrate 11 to ensure that the final patterned metal substrate 11 has more reliable strength, so as not to be easily bent and broken.

[0054] Please see Figure 5 , Figure 5 This is a schematic diagram of the fifth embodiment of the chip package of this application. This embodiment is related to this application. Figure 1 The difference in the first embodiment of the chip package provided is that the chip package further includes a second insulating layer 81, wherein the second insulating layer 81 covers the first conductive layer 41 and the partially exposed first insulating layer 31.

[0055] In this embodiment, the patterned first insulating layer 31 may be partially exposed and not completely covered by the first conductive layer 41. A second insulating layer 81 is further provided in the chip package to cover the first conductive layer 41 and the partially exposed first insulating layer 31, so as to effectively protect the first conductive layer 41 from being damaged by external forces, thereby preventing the logic circuits of the corresponding pins of the chip package from failing to be effectively implemented due to the action of external forces.

[0056] Please see Figure 6 , Figure 6 This is a schematic diagram of the sixth embodiment of the chip package of this application.

[0057] Optionally, in one embodiment, the chip package specifically includes: a patterned metal substrate 11, a chip 21, a first insulating layer 31, a patterned first conductive layer 41, a patterned second conductive layer 51, a third conductive layer 61, a conductive metal layer 71, and a second insulating layer 81.

[0058] In this design, a third conductive layer 61 is disposed on a patterned metal substrate 11, and a chip 21 is disposed on the third conductive layer 61. A first insulating layer 31 covers the chip 21 and the metal substrate 11, and a patterned second conductive layer 51 is further disposed on the first insulating layer 31. Through holes are provided in the first insulating layer 31 and the second conductive layer 51 to expose portions of the metal substrate 11 and the chip 21. A patterned first conductive layer 41 is disposed on the second conductive layer 51 and within the through holes, so that the chip 21 can be connected to the patterned second conductive layer 51 and the patterned metal substrate 11 through the patterned first conductive layer 41 to form the pins of the chip package. This results in the chip package having a shorter electrical path and heat dissipation path, as well as excellent low resistance characteristics and heat dissipation effect.

[0059] The conductive metal layer 71 is disposed on the surface of the metal substrate 11 away from the first insulating layer 31. The conductive metal layer 71 is a thickened stack of the metal substrate 11 to ensure that the final patterned metal substrate 11 has more reliable strength, preventing it from being easily bent or broken. The second insulating layer 81 covers the first conductive layer 41 and the partially exposed second conductive layer 51 to effectively protect the first conductive layer 41 and the second conductive layer 51 from damage by external forces, thereby preventing the logic circuits of the corresponding pins of the chip package from failing to function effectively due to external forces.

[0060] Optionally, the materials of the metal substrate 11 and the conductive metal layer 71 can be copper, aluminum, gold, silver and their alloys or metal-filled organic materials. The materials used for the first insulating layer 31 and the second insulating layer 81 can be organic insulating materials filled with silicon dioxide, silicon nitride, silicon oxynitride, circuit board materials, or inks. The materials of the first conductive layer 41 and the second conductive layer 51 are selected from copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organic materials. The third conductive layer 61 can be silver-based conductive adhesive, gold-based conductive adhesive, copper-based conductive adhesive, and carbon-based conductive adhesive, or an adhesive alloy, such as copper, aluminum, gold, silver and their alloys or metal-filled organic materials, so that the chip 21 in the chip package can achieve double-sided heat dissipation through the metal substrate 11 and the first conductive layer 41 in the through hole, thereby having better heat dissipation characteristics.

[0061] Optionally, the surface area of ​​the through hole in the first insulating layer 31 on the side facing the metal substrate 11 can be set to be smaller than the surface area on the side away from the metal substrate 11. That is, the bottom areas on both sides of the through hole can be set to be different. In other embodiments, the bottom areas on both sides of the through hole can also be set to be the same. At the same time, the through hole can also penetrate the metal substrate 11. This application does not limit this.

[0062] Optionally, the insulating material used in the second insulating layer 81 is different from the insulating material used in the first insulating layer 31, and the thermal conductivity of the insulating material used in the second insulating layer 81 is better than that of the insulating material used in the first insulating layer 31. That is, the thermal conductivity of the second insulating layer 81 is greater than that of the first insulating layer 31, so that after covering the first conductive layer 41 and the second conductive layer 51, the chip 21 can achieve better heat dissipation through the second insulating layer 81.

[0063] Optionally, a solder resist insulating layer is also provided on the side of the chip 21 away from the metal substrate 11, so that the first conductive layer 41 is only allowed to connect to the position corresponding to the pad on one side of the chip 21. Here, the pad refers to the exposed copper layer on one side of the chip 21 that needs to be soldered to achieve electrical connection with external devices, while the position on one side of the chip 21 that does not correspond to the pad is provided with a solder resist insulating layer.

[0064] Optionally, the outermost layer of the chip package, namely the conductive metal layer 71 and the outer side of the second insulating layer 81, is further provided with an insulating cover material of any reasonable color such as black, green or yellow, to make the appearance of the chip package more aesthetically pleasing.

[0065] Optionally, the edge portion of the metal substrate 11 corresponding to the corresponding groove and the remaining structure after etching can be a bevel with at least two different angles, or a reasonable structural style such as an arc surface or a wavy surface.

[0066] Optionally, there may be gaps at the location where the metal substrate 11 is connected to the first conductive layer 41, or inside the first conductive layer 41, and these gaps may be further filled with insulating resin to prevent the entry of air and / or water molecules.

[0067] Optionally, the patterned gaps on the side of the metal substrate 11 away from the chip 21 are filled with an insulating encapsulation material of any reasonable color such as black, green, or yellow to make the appearance of the chip package more aesthetically pleasing.

[0068] Optionally, the chip package has a multilayer metal substrate 11 and corresponding stacked insulating layers, and the interconnection of the multilayer metal substrate 11 is achieved through the multilayer conductive layers in the corresponding through holes.

[0069] Optionally, solder balls are also provided on the side of the metal substrate 11 or conductive metal layer 71 away from the chip 21 to achieve electrical connection with external devices.

[0070] Optionally, the side of the chip package away from the metal substrate 11 is further connected to a power module device, such as one or more of any reasonable power devices such as resistors, capacitors, and transistors, through a first conductive layer 41.

[0071] Optionally, at least two chips 21 are disposed on the side of the metal substrate 11 near the chip 21, and the at least two chips 21 can be electrically connected through the metal substrate 11 and the first conductive layer 41, or the at least two chips 21 can be independently connected without electrical connection. The specific configuration is determined by the user according to the circuit logic they need to achieve.

[0072] Based on the overall inventive concept, this application also provides a process method for manufacturing a chip package. Please refer to [link to relevant documentation]. Figures 7a-7g ,in, Figure 7a This is a flowchart illustrating the first embodiment of the chip package manufacturing method of this application. Figures 7b-7g for Figure 7a A structural schematic diagram of one embodiment corresponding to S710-S760. This embodiment includes the following steps:

[0073] S710: Chips are placed on a metal substrate.

[0074] Specifically, such as Figure 7b As shown, in one embodiment, the chip 21 is first disposed on the provided metal substrate 11.

[0075] S720: A first insulating layer is formed on a metal substrate on which the chip is disposed to cover the chip and the metal substrate.

[0076] Specifically, such as Figure 7c As shown, in one embodiment, after the chip 21 is disposed on the metal substrate 11, a first insulating layer 31 is further formed on the metal substrate 11 to completely cover the chip 21 and the metal substrate 11.

[0077] S730: Patterned first insulating layer to form a patterned first insulating layer, wherein through holes are provided in the patterned first insulating layer to expose portions of the metal substrate and the chip.

[0078] Specifically, such as Figure 7d As shown, in one embodiment, a first insulating layer 31 is formed by printing, pressing, and spraying. A plurality of through holes are further formed in the first insulating layer 31 by laser drilling or chemical etching, extending to the surface of the metal substrate 11 and the chip 21 to expose portions of the metal substrate 11 and the chip 21.

[0079] S740: A first conductive layer is formed on a patterned first insulating layer, and the via is filled with the first conductive layer.

[0080] Specifically, such as Figure 7e As shown, in one embodiment, after a through hole is provided in the patterned first insulating layer 31 and a portion of the metal substrate 11 and the chip 21 are exposed, a first conductive layer 41 is further fabricated on the first insulating layer 31 by means of printing, lamination, spraying, chemical electroplating, chemical deposition and other processing methods, and the first conductive layer 41 is filled on the surface inside the through hole to realize the corresponding connection between the chip 21 and the metal substrate 11.

[0081] S750: Pattern the first conductive layer to form a patterned first conductive layer.

[0082] Specifically, such as Figure 7f As shown, in one embodiment, the first conductive layer 41 is patterned by chemical etching or ion etching to form a patterned first conductive layer 41.

[0083] S760: Patterned metal substrate, forming a patterned metal substrate so that the chip is connected to the patterned metal substrate through a patterned first conductive layer.

[0084] Specifically, such as Figure 7g As shown, in one embodiment, after a first conductive layer 41 is formed on a patterned first insulating layer 31 covering the chip 21 and the metal substrate 11, and within a via, the first conductive layer 41 is patterned, and the metal substrate 11 is further patterned by chemical etching or ion etching to form a patterned first conductive layer 41 and a metal substrate 11. It can be understood that the chip 21 can be connected to the patterned metal substrate 11 via the patterned first conductive layer 41 within the via and on the first insulating layer 31. The patterning of the first insulating layer 31, the first conductive layer 41, and the metal substrate 11 is an adaptive setting to achieve electrical connection between the chip 21 and the metal substrate 11, and to accommodate the logic circuit to be implemented, ultimately forming the pins of the chip package.

[0085] Optionally, the material of the metal substrate 11 can be one of copper, aluminum, gold, silver and their alloys or metal-filled organic materials, the material of the first insulating layer 31 can be one of organic insulating materials filled with silicon dioxide, silicon nitride, silicon oxynitride, circuit board materials, ink, and the material of the first conductive layer 41 is selected from one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organic materials, so that the chip in the chip package can achieve double-sided heat dissipation through the metal substrate 11 and the first conductive layer 41 in the through hole, thereby having better heat dissipation characteristics.

[0086] Unlike existing technologies, the chip package manufacturing process in this application includes: placing a chip on a metal substrate; forming a first insulating layer on the metal substrate on which the chip is placed to cover the chip and the metal substrate; patterning the first insulating layer to form a patterned first insulating layer, wherein the patterned first insulating layer has through holes to expose portions of the metal substrate and the chip; forming a first conductive layer on the patterned first insulating layer, and filling the through holes with the first conductive layer; patterning the first conductive layer to form a patterned first conductive layer; and patterning the metal substrate to form a patterned metal substrate, thereby connecting the chip to the patterned metal substrate via the patterned first conductive layer. Through the above method, the chip package obtained in this application can dissipate heat through a patterned metal substrate and a patterned conductive layer with a larger heat dissipation area disposed in the through-hole of the insulating layer, thereby enabling the chip to achieve double-sided heat dissipation. The structure is relatively simple, with short electrical and heat dissipation paths, and has better low resistance characteristics and heat dissipation effect. It can realize the miniaturization and thinning of the chip package. The bidirectional manufacturing method also makes the entire process fully compatible with the PCB equipment process, thus having the characteristics of high efficiency, high batch production, and low cost.

[0087] Please see Figures 8a-8f ,in, Figure 8a This is a flowchart illustrating the second embodiment of the chip package manufacturing method of this application. Figures 8b-8f for Figure 8a The diagram shows a structural schematic of one embodiment corresponding to S830-S870. It can be understood that the chip package manufacturing process method of this embodiment... Figure 7a A detailed flowchart of a method for manufacturing a chip package includes the following steps:

[0088] in, Figure 8a The S810 and S820 in the text are respectively with Figure 7a The S710 and S720 are the same; please refer to [link / reference] for details. Figure 7a The related textual descriptions will not be repeated here. In S820, after the step of forming a first insulating layer on the metal substrate on which the chip is disposed to cover the chip and the metal substrate, the following steps are also included:

[0089] S830: A second conductive layer is formed on the first insulating layer.

[0090] Specifically, such as Figure 8bAs shown, in one embodiment, after the chip 21 is disposed on the metal substrate 11 and a first insulating layer 31 is formed on the metal substrate 11 to cover the chip 21 and the metal substrate 11, the method further includes fabricating and forming a second conductive layer 51 on the first insulating layer 31.

[0091] S840: Patterning a first insulating layer and a second conductive layer to form a patterned first insulating layer and a patterned second conductive layer, wherein through-holes are provided in the patterned first insulating layer and the patterned second conductive layer to expose portions of the metal substrate and the chip.

[0092] Specifically, such as Figure 8c As shown, in one embodiment, the first insulating layer 31 formed and covering the chip 21 and the metal substrate 11 on which the chip 21 is disposed, and the second conductive layer 51 formed on the first insulating layer 31 are patterned to obtain a patterned first insulating layer 31 and a patterned second conductive layer 51. Furthermore, multiple through holes are formed in the first insulating layer 31 and the second conductive layer 51 by laser drilling or chemical etching, and these through holes extend to the surfaces of the metal substrate 11 and the chip 21 to expose portions of the metal substrate 11 and the chip 21.

[0093] S850: A first conductive layer is formed on a patterned first insulating layer and a patterned second conductive layer, and the via is filled with the first conductive layer.

[0094] Specifically, such as Figure 8d As shown, in one embodiment, through holes are provided in the patterned first insulating layer 31 and the second conductive layer 51, exposing part of the metal substrate 11 and the chip 21. Further, a first conductive layer 41 is fabricated on the first insulating layer 31 and the second conductive layer 51, and the first conductive layer 41 is filled into the through holes formed in the first insulating layer 31 to achieve the corresponding connection between the chip 21 and the metal substrate 11.

[0095] S860: Pattern the first conductive layer to form a patterned first conductive layer.

[0096] Specifically, such as Figure 8e As shown, in one embodiment, the first conductive layer 41 is patterned by chemical etching or ion etching to form a patterned first conductive layer 41. In other embodiments, the second conductive layer 51 can also be further patterned to form a first conductive layer 41 and a second conductive layer 51 that are patterned in the vertical direction.

[0097] S870: Patterned metal substrate to form a patterned metal substrate, thereby connecting the chip to a patterned second conductive layer and the patterned metal substrate via a patterned first conductive layer.

[0098] Specifically, such as Figure 8f As shown, in one embodiment, a first conductive layer 41 is formed on a patterned first insulating layer 31 and a patterned second conductive layer 51 covering the chip 21 and the metal substrate 11, and the vias in the first insulating layer 31 are also filled with the first conductive layer 41. The first conductive layer 41 is then patterned, and the metal substrate 11 is further patterned using chemical etching or ion etching to form the patterned first conductive layer 41 and the metal substrate 11. It can be understood that the chip 21 can be connected to the patterned metal substrate 11 via the patterned first conductive layer 41 within the vias and on the first insulating layer 31 and the second conductive layer 51. The patterning of the first insulating layer 31, the second conductive layer 51, the first conductive layer 41, and the metal substrate 11 is an adaptive setting to achieve electrical connection between the chip 21 and the metal substrate 11, and to accommodate the logic circuit to be implemented, ultimately forming the pins of the chip package.

[0099] Please see Figures 9a-9c ,in, Figure 9a This is a flowchart illustrating the third embodiment of the chip package manufacturing method of this application. Figures 9b-9c for Figure 9a The diagram shows a structural schematic of one embodiment corresponding to S910-S920. It can be understood that the chip package manufacturing process method of this embodiment... Figure 7a A flowchart illustrating another detailed implementation of the manufacturing process for a chip package includes the following steps:

[0100] in, Figure 9a The S930, S940, S950, S960, and S970 in the text are respectively related to Figure 7a The S720, S730, S740, S750, and S760 are the same; please refer to [link / reference needed]. Figure 7a The related textual descriptions will not be repeated here, but the specific steps for setting the chip on the metal substrate include:

[0101] S910: A third conductive layer is formed on a metal substrate.

[0102] Specifically, such as Figure 9b As shown, in one embodiment, a third conductive layer 61 is fabricated and formed on a metal substrate 11.

[0103] S920: The chip is placed on the third conductive layer.

[0104] Specifically, such as Figure 9c As shown, in one embodiment, after a third conductive layer 61 is formed on the metal substrate 11, the chip 21 is then attached to the third conductive layer 61. The third conductive layer 61 can be a conductive adhesive with adhesive properties, that is, an adhesive that has a certain conductivity after curing or drying, such as one of silver-based conductive adhesive, gold-based conductive adhesive, copper-based conductive adhesive, and carbon-based conductive adhesive, or an adhesive alloy, such as copper, aluminum, gold, silver, and their alloys, or one of metal-filled organic materials. Therefore, by placing the chip 21 on the third conductive layer 61, the chip 21 can be more reliably connected to the metal substrate 11 to form an effective conductive path.

[0105] Please see Figures 10a-10b ,in, Figure 10a This is a flowchart illustrating the fourth embodiment of the chip package manufacturing method of this application. Figure 10b for Figure 10a A structural schematic diagram of an embodiment corresponding to S1070. This embodiment is similar to... Figure 7a A flowchart illustrating another detailed implementation of the manufacturing process for a chip package includes the following steps:

[0106] in, Figure 10a S1010, S1020, S1030, S1040, S1050 and S1060 respectively are with Figure 7a The S710, S720, S730, S740, S750, and S760 are the same; please refer to [link / reference needed]. Figure 7a The related textual descriptions will not be repeated here. After step S1060, which involves forming a patterned metal substrate to connect the chip to the patterned metal substrate via the patterned first conductive layer, the following steps are also included:

[0107] S1070: A conductive metal layer is formed on the surface of a patterned metal substrate away from the first insulating layer.

[0108] Specifically, such as Figure 10bAs shown, in one embodiment, when a first conductive layer 41 is formed on the patterned first insulating layer 31 covering the chip 21 and the metal substrate 11 and in the corresponding through holes, the first conductive layer 41 is patterned, and the metal substrate 11 is further patterned by chemical etching or ion etching to form the patterned first conductive layer 41 and the metal substrate 11. After the chip 21 is connected to the patterned metal substrate 11 through the patterned first conductive layer 41, a conductive metal layer 71 is further formed on the surface of the patterned metal substrate 11 away from the first insulating layer 31. In other embodiments, a first conductive layer 41 may be fabricated and formed on the patterned first insulating layer 31 covering the chip 21 and the metal substrate 11 and within the corresponding through holes. After patterning the first conductive layer 41, a conductive metal layer 71 may be fabricated and formed on the surface of the metal substrate 11 away from the first insulating layer 31. Then, the metal substrate 11 and the conductive metal layer 71 may be patterned to form the patterned first conductive layer 41, the metal substrate 11, and the conductive metal layer 71, so that the chip 21 is connected to the patterned metal substrate 11 through the patterned first conductive layer 41.

[0109] The conductive metal layer 71 is made of the same material as the metal substrate 11, selected from copper, aluminum, gold, silver and their alloys or metal-filled organic materials. It is a thickened stacked layer of the metal substrate 11, thereby ensuring that the finally formed patterned metal substrate 11 will not be easily bent and broken, that is, ensuring that the corresponding pins of the chip package have more reliable strength.

[0110] Please see Figures 11a-11b ,in, Figure 11a This is a flowchart illustrating the fifth embodiment of the chip package manufacturing method of this application. Figure 11b for Figure 11a A structural schematic diagram of an embodiment corresponding to S1170. This embodiment is similar to... Figure 7a A flowchart illustrating another detailed implementation of the manufacturing process for a chip package includes the following steps:

[0111] in, Figure 11a S1110, S1120, S1130, S1140, S1150 and S1160 respectively are with Figure 7a The S710, S720, S730, S740, S750, and S760 are the same; please refer to [link / reference needed]. Figure 7aThe related textual descriptions will not be repeated here. After step S1160, which is the step of forming a patterned metal substrate to connect the chip to the patterned metal substrate through the patterned first conductive layer, the following steps are also included:

[0112] S1170: A second insulating layer is formed on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

[0113] Specifically, such as Figure 11b As shown, in one embodiment, when a first conductive layer 41 is formed on the patterned first insulating layer 31 covering the chip 21 and the metal substrate 11 and in the corresponding through-hole, the first conductive layer 41 is patterned, and the metal substrate 11 is further patterned by chemical etching or ion etching to form the patterned first conductive layer 41 and the metal substrate 11. After the chip 21 is connected to the patterned metal substrate 11 through the patterned first conductive layer 41, a second insulating layer 81 is further formed on the first conductive layer 41 and the partially exposed first insulating layer 31 to cover the first conductive layer 41 and the partially exposed first insulating layer 31, so as to effectively protect the first conductive layer 41 from being damaged by external forces, thereby preventing the logic circuit of the corresponding pin of the chip package from being unable to be effectively implemented due to the action of external forces.

[0114] Based on the overall inventive concept, this application also provides an electronic device, please refer to [link to relevant documentation]. Figure 12 , Figure 12 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. The electronic device 1200 includes any of the chip packages 1210 described above.

[0115] Unlike existing technologies, the chip package in this application includes: a patterned metal substrate; a chip disposed on the metal substrate; a first insulating layer covering the chip and the metal substrate, wherein the first insulating layer has through holes to expose portions of the metal substrate and the chip; and a patterned first conductive layer disposed on the first insulating layer and within the through holes, so that the chip is connected to the metal substrate via the first conductive layer. Through this method, the chip package in this application can achieve double-sided heat dissipation of the chip, and has a relatively simple structure with short electrical and heat dissipation paths, exhibiting excellent low-resistance characteristics and heat dissipation effect, enabling miniaturization and thinning of the chip package.

[0116] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A chip package, characterized in that, The chip package includes: Patterned metal substrate; The chip is mounted on the metal substrate. A first insulating layer covers the chip and the metal substrate, wherein the first insulating layer has through holes to expose portions of the metal substrate and the chip; A patterned first conductive layer is disposed on the first insulating layer and within the via, so that the chip is connected to the metal substrate via the first conductive layer; The first insulating layer comprises at least two vias, wherein at least one via is disposed on the chip, and at least another via is disposed on the metal substrate. The at least two vias are electrically connected to each other by a first conductive layer covering the interior of each via. The portion of the metal substrate corresponding to the at least two vias constitutes a package pin, and the vias penetrate the metal substrate. The edge portion of the first insulating layer corresponding to the via has at least two bevels with different angles, or is an arc-shaped or wavy surface. There are gaps at the location where the metal substrate plate is connected to the first conductive layer, or inside the first conductive layer, and the gaps are filled with insulating resin.

2. The chip package according to claim 1, characterized in that, A patterned second conductive layer is further disposed between the overlapping portion of the first insulating layer and the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate through the first conductive layer.

3. The chip package according to claim 1, characterized in that, A third conductive layer is also provided between the overlapping portion of the metal substrate and the chip, and the chip is bonded to the metal substrate through the third conductive layer.

4. The chip package according to claim 1, characterized in that, The chip package also includes a conductive metal layer, which is disposed on the surface of the metal substrate away from the first insulating layer.

5. The chip package according to claim 1, characterized in that, The chip package also includes a second insulating layer, which covers the first conductive layer and the partially exposed first insulating layer.

6. The chip package according to claim 1, characterized in that, The surface area of ​​the through hole facing the metal substrate is smaller than the surface area of ​​the side away from the metal substrate.

7. A method for manufacturing a chip package, characterized in that, The manufacturing process includes: Chips are mounted on a metal substrate. A first insulating layer is formed on the metal substrate on which the chip is disposed to cover the chip and the metal substrate. The first insulating layer is patterned to form a patterned first insulating layer, wherein the patterned first insulating layer has through holes to expose portions of the metal substrate and the chip; A first conductive layer is formed on the patterned first insulating layer, and the through hole is filled with the first conductive layer; The first conductive layer is patterned to form a patterned first conductive layer; The metal substrate is patterned to form a patterned metal substrate, thereby connecting the chip to the patterned metal substrate via the patterned first conductive layer; wherein the number of vias in the first insulating layer includes at least two, wherein at least one via is disposed on the chip, and at least another via is correspondingly disposed on the metal substrate, and the at least two vias are electrically connected to each other by the first conductive layer covering the interior of each via; the portion of the metal substrate corresponding to the at least two vias constitutes a package pin, and the vias penetrate the metal substrate; the first insulating layer has at least two beveled edges with different angles, or is an arc-shaped surface or a wavy surface, at the edge portion corresponding to the via; there are gaps at the location where the metal substrate is connected to the first conductive layer, or inside the first conductive layer, and the gaps are filled with insulating resin.

8. The manufacturing method according to claim 7, characterized in that, After the step of forming a first insulating layer on the metal substrate on which the chip is disposed to cover the chip and the metal substrate, the step of patterning the first insulating layer to form a patterned first insulating layer, wherein the patterned first insulating layer has through holes to expose portions of the metal substrate and the chip, further includes: A second conductive layer is formed on the first insulating layer; The step of patterning the first insulating layer to form a patterned first insulating layer, wherein the patterned first insulating layer has through holes to expose portions of the metal substrate and the chip, includes: The first insulating layer and the second conductive layer are patterned to form a patterned first insulating layer and a patterned second conductive layer, wherein through holes are provided in the patterned first insulating layer and the patterned second conductive layer to expose portions of the metal substrate and the chip; The step of forming a first conductive layer on the patterned first insulating layer and filling the via with the first conductive layer includes: A first conductive layer is formed on the patterned first insulating layer and the patterned second conductive layer, and the via is filled with the first conductive layer; The step of patterning the metal substrate to form a patterned metal substrate, thereby connecting the chip to the patterned metal substrate via the patterned first conductive layer, includes: The metal substrate is patterned to form a patterned metal substrate, thereby connecting the chip to the patterned second conductive layer and the patterned metal substrate via the patterned first conductive layer.

9. The manufacturing method according to claim 7, characterized in that, The step of setting the chip on the metal substrate specifically includes: A third conductive layer is formed on the metal substrate. A chip is disposed on the third conductive layer.

10. The manufacturing method according to claim 7, characterized in that, The step of patterning the metal substrate to form a patterned metal substrate, thereby connecting the chip to the patterned metal substrate via the patterned first conductive layer, further includes: A conductive metal layer is formed on the surface of the patterned metal substrate away from the first insulating layer.

11. The manufacturing method according to claim 7, characterized in that, The step of patterning the metal substrate to form a patterned metal substrate, thereby connecting the chip to the patterned metal substrate via the patterned first conductive layer, further includes: A second insulating layer is formed on the first conductive layer and the partially exposed first insulating layer to cover the first conductive layer and the first insulating layer.

12. An electronic device comprising a chip package as described in any one of claims 1-6.

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