Semiconductor package including stacked semiconductor chips

Abstract

A semiconductor package including stacked semiconductor chips. The semiconductor package may include: a chip stack including first to Nth semiconductor chips, the first to Nth semiconductor chips being stacked in a manner offset to one side so that the edges of the first to Nth semiconductor chips on the other side are exposed, and having first to Nth chip pads respectively arranged at the edges of the other side; a bridging unit adjacent to the other side of the chip stack and spaced apart from the chip stack; kth to Nth wires extending in a vertical direction in a state where one end of the kth to Nth wires is connected to the kth to Nth chip pads among the first to Nth chip pads; first to k‑1th wires, one end of the first to k‑1th wires being connected to the first to k‑1th chip pads among the first to Nth chip pads; and an additional wire electrically connected to the first to k‑1th wires and extending in a vertical direction in a state where one end of the wires is connected to the bridging unit.

Description

Technical Field

[0001] Various embodiments relate generally to a semiconductor package, and more particularly, to a semiconductor package including a plurality of chips stacked over a substrate. Background Art

[0002] Electronic products need to process larger amounts of data while being smaller in size, so it is necessary to increase the integration of semiconductor devices used in such electronic products.

[0003] However, due to the limitation of semiconductor integration technology, only a single semiconductor chip cannot satisfy the required functions. Therefore, a semiconductor package having a plurality of semiconductor chips embedded therein is manufactured.

[0004] Although a semiconductor package includes a plurality of semiconductor chips, the semiconductor package needs to have a specified size or a size smaller than the specified size according to requirements of an application in which the semiconductor package is to be mounted. Summary of the invention

[0005] In one embodiment, a semiconductor package may include: a chip stack, the chip stack including first to Nth semiconductor chips, the first to Nth semiconductor chips being stacked in a manner offset to one side so that edges of the first to Nth semiconductor chips on the other side are exposed, and the first to Nth semiconductor chips have first to Nth chip pads respectively arranged at the edges of the other side, wherein N is a natural number equal to or greater than 2; a bridging unit, the bridging unit being adjacent to the other side of the chip stack and spaced apart from the chip stack; kth to Nth wires, the kth to Nth wires being connected at one end thereof to the first to Nth chip pads Extending in a vertical direction in a state where the kth to Nth chip pads are connected, wherein k is a natural number equal to or greater than 2 and equal to or less than N; first to k-1th wires, one end of the first to k-1th wires is connected to the first to k-1th chip pads among the first to Nth chip pads, wherein the other end of the first wire is connected to a bridging unit, and the other ends of the second wire to the k-1th wire are respectively connected to the bridging unit or the first to k-2th chip pads; and an additional wire, which is electrically connected to the first to k-1th wires and extends in a vertical direction in a state where one end thereof is connected to the bridging unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 3 , Figure 4 and Figure 5 2 is a diagram for describing a semiconductor package and a method of manufacturing the same according to an embodiment.

[0007] Figure 6 is a diagram showing the sweeping of a vertical conductive line.

[0008] Fig. 7A and Figure 7B are a cross-sectional view and a plan view showing a semiconductor package according to an embodiment.

[0009] Figure 8 A block diagram of an electronic system employing a memory card including a semiconductor package according to one embodiment is shown.

[0010] Fig. 9 A block diagram of another electronic system including a semiconductor package according to one embodiment is shown. DETAILED DESCRIPTION

[0011] Various examples and implementations of the disclosed technology are described in detail below with reference to the accompanying drawings.

[0012] Various embodiments may be directed to a semiconductor package and a method of manufacturing the same that can avoid defects and facilitate a manufacturing process.

[0013] The drawings may not necessarily be drawn to scale, and in some cases, the proportions of at least some structures in the drawings may be exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a specific example with two or more layers is presented in a multilayer structure in the drawings or the specification, the relative positional relationship of these layers or the order in which the layers are arranged as shown reflects the specific embodiment of the described or illustrated example, and different relative positional relationships or orders of arrangement of layers are also possible. In addition, the examples of the described or illustrated multilayer structures may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0014] Figures 1A to 1F , Figures 2A to 2G and Figures 3 to 5 2 is a diagram for describing a semiconductor package and a method of manufacturing the same according to an embodiment. Figure 1A , Figure 2A , Figure 2B , Figure 3 , Figure 4 and Figure 5 is a cross-sectional view, Figure 1B and Figure 2C are respectively corresponding to Figure 1A and Figure 2A / Figure 2B Floor plan. Figure 1C to Figure 1F It is shown Figure 1A and Figure 1B , and Figure 2D to Figure 2G It is shown Figure 1C to Figure 1F A diagram of a redistribution layer and wires connected to the redistribution layer.

[0015] First, the manufacturing method will be described.

[0016] Reference Figure 1A and Figure 1B , a carrier substrate 100 may be provided. The carrier substrate 100 may be a glass carrier substrate or a ceramic carrier substrate, etc. Alternatively, the carrier substrate 100 may be a wafer, and a plurality of packages may be formed on the carrier substrate 100 at the same time.

[0017] Then, the chip stack 200 and the bridge unit 300 may be formed on the first surface 101 of the carrier substrate 100 .

[0018] The chip stack 200 may include a plurality of semiconductor chips 210 , 220 , 230 , and 240 stacked in a direction perpendicular to the first surface 101 of the carrier substrate 100 . Figure 1A and Figure 1B It is shown that one chip stack 200 includes four semiconductor chips 210, 220, 230 and 240. However, the present embodiment is not limited thereto, but the number of semiconductor chips included in one chip stack 200 can be set to various values. Hereinafter, for the convenience of description, the four semiconductor chips 210, 220, 230 and 240 are respectively referred to as the first semiconductor chip 210, the second semiconductor chip 220, the third semiconductor chip 230 and the fourth semiconductor chip 240 according to the distance from the carrier substrate 100. In addition, for the convenience of description, the position relatively close to the carrier substrate 100 in the vertical direction will be referred to as the bottom / lower position, and the position relatively far from the carrier substrate 100 will be referred to as the top / upper position. For example, the first semiconductor chip 210 can be referred to as being located at the lowermost portion of the chip stack 200, and the fourth semiconductor chip 240 can be referred to as being located at the uppermost portion of the chip stack 200.

[0019] The first to fourth semiconductor chips 210, 220, 230, and 240 may include first to fourth active surfaces 216, 226, 236, and 246, and first to fourth inactive surfaces 217, 227, 237, and 247, respectively. The first to fourth active surfaces 216, 226, 236, and 246 do not face the first surface 101 of the carrier substrate 100, and the first to fourth inactive surfaces 217, 227, 237, and 247 are located at opposite sides of the first to fourth active surfaces 216, 226, 236, and 246 to face the first surface 101 of the carrier substrate 100. The first to fourth semiconductor chips 210, 220, 230, and 240 may include first to fourth chip pads 212, 222, 232, and 242 disposed at the first to fourth active surfaces 216, 226, 236, and 246, respectively. The first to fourth chip pads 212 , 222 , 232 , and 232 may be bonding pads for wire bonding.

[0020] The first to fourth semiconductor chips 210, 220, 230 and 240 may be stacked in a state of being pre-determinedly offset to one side (e.g., the right side) in the first direction. When the first to fourth semiconductor chips 210, 220, 230 and 240 are stacked in a manner offset to the one side in sequence, the other side edge of the first to third active surfaces 216, 226 and 236 of the first to third semiconductor chips 210, 220 and 230 may be exposed. The other side edge of the first to third active surfaces 216, 226 and 236 may be an edge (e.g., a left edge) on the opposite side of one side in the offset direction. Hereinafter, the exposed edges of the first to third active surfaces 216, 226 and 236 will be referred to as the exposed portions of the first to third active surfaces 216, 226 and 236, and will be represented by reference numerals 216A, 226A and 236A, respectively. The first to third chip pads 212, 222 and 232 may be disposed in exposed portions 216A, 226A and 236A of the first to third active surfaces 216, 226 and 236, respectively. That is, the first to third semiconductor chips 210, 220 and 230 may be edge pad-type semiconductor chips. Since the fourth semiconductor chip 240 is located at the uppermost portion of the chip stack 200, the entire fourth active surface 246 may be exposed. Therefore, the fourth chip pad 242 may be located at any position of the fourth active surface 246. In an embodiment, the fourth chip pad 242 may be located at a position substantially the same as the positions of the first to third chip pads 212, 222 and 232, that is, the left edge of the fourth active surface 246 of the fourth semiconductor chip 240. That is, the fourth semiconductor chip 240 may also be an edge pad-type semiconductor chip.

[0021] Figure 1A The cross-sectional view of FIG. 1 shows that each of the first to fourth chip pads 212, 222, 232, and 242 appears to be formed as one pad in a corresponding semiconductor chip among the first to fourth semiconductor chips 210, 220, 230, and 240. However, referring to FIG. Figure 1B In a plan view, a plurality of first chip pads 212 may be arranged in an exposed portion 216A of the first active surface 216 of the first semiconductor chip 210. The first chip pads may be spaced apart from each other in a second direction substantially perpendicular to the first direction and parallel to the first surface 101 of the carrier substrate 100. Figure 1B It is shown that 12 first chip pads 212 are formed in one line, but the number and arrangement of the first chip pads 212 can be modified in various ways. Similarly, a plurality of second chip pads 222 can be arranged in the exposed portion 226A of the second active surface 226, and spaced apart from each other in the second direction, and a plurality of third chip pads 232 can be arranged in the exposed portion 236A of the third active surface 236, and spaced apart from each other in the second direction. A plurality of fourth chip pads 242 can be arranged at the left edge of the fourth active surface 246, and spaced apart from each other in the second direction.

[0022] Among the plurality of chip pads included in each of the first to fourth semiconductor chips 210, 220, 230, and 240, a certain chip pad may be a signal pad to which an input / output signal is applied, and another chip pad may be a power pad to which a power supply voltage or a ground voltage is applied. In one embodiment, Figure 1B The figure shows a case where the bottommost first chip pad 212 among the plurality of first chip pads 212 is a signal pad, and the first chip pad 212 above the signal pad is a power pad. For ease of description, among the first chip pads 212, the signal pad will be referred to as the first signal pad 212A, and the power pad will be referred to as the first power pad 212B. In one embodiment, Figure 1BThe figure shows a situation where the bottommost second chip pad 222 among the plurality of second chip pads 222 is a signal pad, and the second chip pad 222 above the signal pad is a power pad. For ease of description, among the second chip pads 222, the signal pad will be referred to as the second signal pad 222A, and the power pad will be referred to as the second power pad 222B. In one embodiment, the first signal pad 212A of the first semiconductor chip 210 and the second signal pad 222A of the second semiconductor chip 220 may be formed at positions corresponding to each other, and the first power pad 212B of the first semiconductor chip 210 and the second power pad 222B of the second semiconductor chip 220 may be formed at positions corresponding to each other. However, the present embodiment is not limited thereto, and the number and position of the signal pads in each semiconductor chip and the number and position of the power pads may be modified in various ways.

[0023] The first to fourth semiconductor chips 210, 220, 230 and 240 may be the same chip. The first to fourth semiconductor chips 210, 220, 230 and 240 may be memory chips. For example, the first to fourth semiconductor chips 210, 220, 230 and 240 may be NAND flash memory chips. However, the present embodiment is not limited thereto, and each of the first to fourth semiconductor chips 210, 220, 230 and 240 may include a nonvolatile memory chip such as a phase change random access memory (PRAM) and a magnetoresistive RAM or a volatile memory chip such as a dynamic RAM (DRAM), a mobile DRAM and a static RAM (SRAM).

[0024] An adhesive layer 205 may be formed on each of the first to fourth inactive surfaces 217, 227, 237, and 247 of the first to fourth semiconductor chips 210, 220, 230, and 240. The first to fourth semiconductor chips 210, 220, 230, and 240 may be attached to the first surface 101 of the carrier substrate 100 and the first to third active surfaces 216, 226, and 236 of the first to third semiconductor chips 210, 220, and 230, respectively, through the adhesive layer 205. The adhesive layer 205 may include a dielectric adhesive material such as a die attach film (DAF).

[0025] The bridge unit 300 may be formed on the first surface 101 of the carrier substrate 100 while being spaced apart from the chip stack 200. Specifically, the bridge unit 300 may be disposed on one side close to the first to fourth chip pads 212, 222, 232, and 242 among both sides of the chip stack 200 in the first direction. This is to electrically connect some wires connected to the first to fourth chip pads 212, 222, 232, and 242 to the bridge unit 300. In one embodiment, the first to fourth semiconductor chips 210, 220, 230, and 240 of the chip stack 200 may be stacked in a rightwardly offset manner so that the first to fourth chip pads 212, 222, 232, and 242 are disposed at the left edge of the first to fourth semiconductor chips 210, 220, 230, and 240. Therefore, the bridge unit 300 may be disposed on the left side of the chip stack 200. However, in one embodiment, the first to fourth semiconductor chips 210, 220, 230, and 240 of the chip stack 200 may be stacked in a left-shifted manner such that the first to fourth chip pads 212, 222, 232, and 242 are disposed at right edges of the first to fourth semiconductor chips 210, 220, 230, and 240. In this case, the bridge unit 300 may be disposed on the right side of the chip stack 200.

[0026] The bridge unit 300 may include a body portion 310 and a redistribution layer 320 on the body portion 310 .

[0027] The body portion 310 may include a second surface 313 facing the first surface 101 of the carrier substrate 100 and a first surface 311 located on an opposite side of the second surface 313. A redistribution layer 320 may be formed on the first surface 311 of the body portion 310, and an adhesive layer 305 may be formed on the second surface 313 of the body portion 310 to attach the body portion 310 to the carrier substrate 100.

[0028] The body portion 310 may be a dummy that does not perform an electrical function and is electrically insulated from components within the package (e.g., the redistribution layer 320 and the chip stack 200, etc.). However, the body portion 310 may be used to provide a predetermined thickness to satisfy the thickness T2 required by the bridge unit 300, and may provide a predetermined area to provide an area where the redistribution layer 320 is to be formed. The body portion 310 may be a block formed of a material including, for example, but not limited to, silicon, glass, ceramic, or some combination thereof.

[0029] The redistribution layer 320 may include a plurality of redistribution pads 327 arranged in a matrix shape in a first direction and a second direction. When the redistribution pads 327 arranged in the first direction are referred to as a row of redistribution pads 327, a particular row of redistribution pads 327 may include a first redistribution pad 327A (see P1), and another row of redistribution pads 327 may include a second redistribution pad 327B (see P2). The first redistribution pad 327A may be connected to a signal pad (e.g., a first signal pad 212A and a second signal pad 222A). The row of the first redistribution pad 327A may be formed at a position corresponding to the first signal pad 212A and the second signal pad 222A. The second redistribution pad 327B may be connected to a power supply pad (e.g., a first power supply pad 212B and a second power supply pad 222B). The row of the second redistribution pad 327B may be formed at a position corresponding to the first power supply pad 212B and the second power supply pad 222B. Figure 1C to Figure 1F Such a redistribution layer 320 is described.

[0030] Figure 1C is based on Figure 1B A plan view of the redistribution layer 320 is shown in FIG. 1 , where the first row of redistribution pads 327A is shown. Figure 1D is along Figure 1C The cross-sectional view obtained by the line X1-X1', Figure 1E is based on Figure 1B The plan view of the redistribution layer 320 is shown in the row of the second redistribution pads 327B, and Figure 1F is along Figure 1E A cross-sectional view taken along line X2-X2'.

[0031] First, refer to Figure 1C and Figure 1D as well as Figure 1A and Figure 1B The redistribution layer 320 may include a first redistribution dielectric layer 321 formed on the first surface 311 of the main body portion 310, a first redistribution conductive layer 326A formed on the first redistribution dielectric layer 321, and a second redistribution dielectric layer 323 formed on the first redistribution dielectric layer 321 and the first redistribution conductive layer 326A and having an opening to expose a portion of the first redistribution conductive layer 326A.

[0032] The first redistribution dielectric layer 321 may cover the entire first surface 311 of the body portion 310 to insulate the first redistribution conductive layer 326A and the body portion 310 from each other.

[0033] The first redistribution conductive layer 326A may include a first conductive layer 326A-1 and a second conductive layer 326A-2 spaced apart from each other in the second direction. The first conductive layer 326A-1 may be a portion to be connected to the first signal pad 212A, and the second conductive layer 326A-2 may be a portion to be connected to the second signal pad 222A. Since different signal pads need to be electrically isolated from each other, the first conductive layer 326A-1 and the second conductive layer 326A-2 may be spaced apart from each other and electrically insulated from each other.

[0034] The first conductive layer 326A-1 may include a linear connection portion L1 and a first end portion E1 and a second end portion E1' in a plate shape. The connection portion L1 may have a relatively small width in a state extending in the first direction, and the first end portion E1 and the second end portion E1' may have a relatively large width in a state located at both ends of the connection portion L1. The second conductive layer 326A-2 may include a linear connection portion L2 and a first end portion E2 and a second end portion E2' in a plate shape. The linear connection portion L2 may have a relatively small width in a state extending in the first direction, and the first end portion E2 and the second end portion E2' may have a relatively large width in a state located at both ends of the connection portion L2.

[0035] The first end E1 and the second end E1' of the first conductive layer 326A-1 and the first end E2 and the second end E2' of the second conductive layer 326A-2 may respectively have surfaces overlapping with the opening of the second redistribution dielectric layer 323 to be exposed through the opening. The exposed portions of the first end E1 and the second end E1' of the first conductive layer 326A-1 and the first end E2 and the second end E2' of the second conductive layer 326A-2 exposed through the opening of the second redistribution dielectric layer 323 may constitute the above-mentioned first redistribution pad 327A. For example, the exposed portion of the first end E1 of the first conductive layer 326A-1 to be connected to the first signal pad 212A through a wire will be referred to as the first signal redistribution pad 327A-1 hereinafter. The exposed portion of the first end E2 of the second conductive layer 326A-2 to be connected to the second signal pad 222A through a wire will be referred to as the second signal redistribution pad 327A-2 hereinafter. The exposed portion of the second end portion E1' of the first conductive layer 326A-1 that can be electrically coupled to the first signal pad 212A through the connection portion L1 will be referred to as the first another signal redistribution pad 327A-3 hereinafter. The exposed portion of the second end portion E2' of the second conductive layer 326A-2 that can be electrically coupled to the second signal pad 222A through the connection portion L2 will be referred to as the second another signal redistribution pad 327A-4 hereinafter.

[0036] The first conductive layer 326A-1 may be arranged closer to one side (e.g., the top side) in the second direction than the second conductive layer 326A-2. The first end E1 and the second end E1' of the first conductive layer 326A-1 may protrude further to the other side (e.g., the bottom side) in the second direction than the connecting portion L1. The first end E2 and the second end E2' of the second conductive layer 326A-2 may protrude further to one side (e.g., the top side) in the second direction than the connecting portion L2. In addition, the first end E1 and the second end E1' of the first conductive layer 326A-1 and the first end E2 and the second end E2' of the second conductive layer 326A-2 may be arranged alternately from the right side to the left side. In this case, the first end E2 of the second conductive layer 326A-2 may be disposed between the first end E1 and the second end E1' of the first conductive layer 326A-1, and the second end E1' of the first conductive layer 326A-1 may be disposed between the first end E2 and the second end E2' of the second conductive layer 326A-2. Therefore, the first signal redistribution pad 327A-1, the second signal redistribution pad 327A-2, the first another signal redistribution pad 327A-3, and the second another signal redistribution pad 327A-4 may be located on a straight line (eg, line X1-X1') while being sequentially arranged in the right to left direction.

[0037] The second redistribution dielectric layer 323 may be formed to cover the first redistribution conductive layer 326A and the first redistribution dielectric layer 321 except for four openings respectively exposing the first and second ends E1 and E1′ of the first conductive layer 326A- 1 and the first and second ends E2 and E2′ of the second conductive layer 326A- 2 .

[0038] Next, refer to Figure 1E and Figure 1F as well as Figure 1A and Figure 1B The redistribution layer 320 may include a first redistribution dielectric layer 321, a second redistribution conductive layer 326B formed on the first redistribution dielectric layer 321, and a second redistribution dielectric layer 323 formed on the first redistribution dielectric layer 321 and the second redistribution conductive layer 326B and having an opening to expose a portion of the second redistribution conductive layer 326B.

[0039] The second redistribution conductive layer 326B may be a portion to be connected to the first power supply pad 212B and the second power supply pad 222B. The first power supply pad 212B and the second power supply pad 222B may be ground pads. Alternatively, the first power supply pad 212B and the second power supply pad 222B may be pads for providing power. The ground pads may be electrically connected to each other. In addition, the power supply pads may be electrically connected to each other. Therefore, the second redistribution conductive layer 326B may be commonly connected to the first power supply pad 212B and the second power supply pad 222B through a wire. For example, although described below, the second redistribution conductive layer 326B may be directly connected to the wire connected to the first power supply pad 212B, but not directly connected to the wire connected to the second power supply pad 222B. Since the wire connected to the second power supply pad 222B is connected to the first power supply pad 212B, the second power supply pad 222B may be connected to the second redistribution conductive layer 326B via the first power supply pad 212B.

[0040] The second redistribution conductive layer 326B may have a strip shape or a shape similar to the strip shape whose width in the first direction is greater than that in the second direction. The second redistribution conductive layer 326B may have a surface overlapping with the opening of the second redistribution dielectric layer 323 and exposed through the opening. The portion of the second redistribution conductive layer 326B exposed through the opening of the second redistribution dielectric layer 323 may constitute the above-mentioned second redistribution pad 327B. The second redistribution pad 327B may include a power redistribution pad 327B-1 and another power redistribution pad 327B-2, the power redistribution pad 327B-1 to be connected to the first power pad 212B through a wire, and the other power redistribution pad 327B-2 may be electrically coupled to the first power pad 212B through the second redistribution conductive layer 326B.

[0041] The power redistribution pad 327B-1 and the other power redistribution pad 327B-2 may be arranged sequentially from the right side toward the left side and arranged in a line (e.g., line X2-X2') on a straight line. The power redistribution pad 327B-1 and the other power redistribution pad 327B-2 may be disposed relatively close to the chip stack 200 (i.e., the right side).

[0042] Refer to Figure 1A and Figure 1B The sum of the number of rows of the first redistribution pads 327A and the number of rows of the second redistribution pads 327B may be substantially equal to the number of the first chip pads 212 arranged in the second direction and / or the number of the second chip pads 222 arranged in the second direction. Figure 1BA case is shown in which the row of second redistribution pads 327B is arranged as one row at the second position from the bottom in the second direction, and the other rows are rows of first redistribution pads 327 A. However, the relative number and layout thereof may be modified in various ways.

[0043] The thickness of the chip stack 200, i.e., the distance from the first surface 101 of the carrier substrate 100 to the top surface of the fourth semiconductor chip 240, or the distance from the bottom surface of the lowermost adhesive layer 205 to the top surface of the fourth semiconductor chip 240, may be referred to as a first thickness T1. When the adhesive layer 205 is omitted, the thickness T1 of the chip stack 200 may correspond to the distance from the bottom surface of the first semiconductor chip 210 to the top surface of the fourth semiconductor chip 240. The thickness of the bridge unit 300, i.e., the distance from the first surface 101 of the carrier substrate 100 to the top surface of the redistribution layer 320, or the distance from the bottom surface of the adhesive layer 305 to the top surface of the redistribution layer 320, may be referred to as a second thickness T2. When the adhesive layer 305 is omitted, the thickness T2 of the bridge unit 300 may correspond to the distance from the bottom surface of the body portion 310 to the top surface of the redistribution layer 320. The second thickness T2 may be equal to or less than the first thickness T1. In addition, the second thickness T2 may be greater than the total thickness of the semiconductor chips (e.g., the first semiconductor chip 210 and the second semiconductor chip 220) to be connected to the bridge unit 300. In this case, the vertical conductive lines (see FIG. 1 ) indirectly connected to the first semiconductor chip 210 and the second semiconductor chip 220 through the bridge unit 300 are Figure 2A The length of the vertical conductive lines (reference numerals 314 and 324) may be shorter than the length of the vertical conductive lines directly connected to the first semiconductor chip 210 and the second semiconductor chip 220. Therefore, the sweeping of the vertical conductive lines may be reduced.

[0044] Then, refer to FIG. 2A to FIG. 2C , first to fourth conductive lines 214 , 224 , 234 and 244 respectively connected to the first to fourth chip pads 212 , 222 , 232 and 242 , and first to third additional conductive lines 314 , 324 and 334 connected to some redistribution pads 327 of the redistribution layer 320 may be formed.

[0045] Among the first to fourth wires 214, 224, 234, and 244, the first wire 214 and the second wire 224 connected to the first chip pad 212 of the first semiconductor chip 210 and the second chip pad 222 of the second semiconductor chip 220 may be bent toward the redistribution layer 320 to be connected to the redistribution layer 320. On the other hand, the third wire 234 and the fourth wire 244 connected to the third chip pad 232 of the third semiconductor chip 230 and the fourth chip pad 242 of the fourth semiconductor chip 240 may extend in the vertical direction. In addition, the first to third additional wires 314, 324, and 334 may extend in the vertical direction.

[0046] The first wire 214 and the second wire 224 can be formed by a wire bonding process. The third wire 234 and the fourth wire 244 and the first to third additional wires 314, 324 and 334 can be formed by a vertical wire forming process. The vertical wire forming process will be described as follows. First, one end of the wire can be bonded to the chip pad by a wire bonding machine (not shown). The wire may include metals such as gold, silver, copper and platinum or their alloys that can be welded to the chip pad by ultrasonic energy and / or heat. Then, the other end of the wire can be pulled away from the chip pad in a vertical direction (e.g., from the bottom to the top) by a wire bonding machine. When the other end of the wire extends to the desired position, the other end of the wire can be cut off.

[0047] One end of the third wire 234 and the fourth wire 244 may be connected to the third chip pad 232 and the fourth chip pad 242, respectively, and the other end is located at the opposite side of the one end and is located at a higher level than the top surface of the chip stack 200 (i.e., the fourth active surface 246 of the fourth semiconductor chip 240). In one embodiment, the other ends of the third wire 234 and the fourth wire 244 may be located at the same distance from the first surface 101 of the carrier substrate 100 (i.e., the same height). However, the present embodiment is not limited thereto, and the other ends of the third wire 234 and the fourth wire 244 may be located at different heights under the premise that the other ends of the third wire 234 and the fourth wire 244 are located at a higher level than the fourth active surface 246. Since the third wire 234 and the fourth wire 244 are respectively connected to the third semiconductor chip 230 and the fourth semiconductor chip 240 formed at a relatively long distance from the carrier substrate 100, the third wire 234 and the fourth wire 244 may have a relatively small length.

[0048] The first conductive line 214 may have one end connected to the first chip pad 212 and the other end connected to the redistribution pad 327 of the redistribution layer 320. For example, the first conductive line 214 may include a first signal line 214A and a first power line 214B. The first signal line 214A may have one end connected to the first signal pad 212A of the first chip pad 212 and the other end connected to one of the first redistribution pads 327A. The first power line 214B may have one end connected to the first power pad 212B of the first chip pad 212 and the other end connected to one of the second redistribution pads 327B. The second conductive line 224 may have one end connected to the second chip pad 222 and the other end connected to the redistribution pad 327 of the redistribution layer 320 or the first chip pad 212. For example, the second conductive line 224 may include a second signal line 224A and a second power line 224B. The second signal line 224A may have one end connected to a second signal pad 222A among the second chip pads 222 and the other end connected to one of the first redistribution pads 327A. The second power line 224B may have one end connected to a second power pad 222B among the second chip pads 222 and the other end connected to a first power pad 212B of the first chip pad 212.

[0049] The first to third additional conductive lines 314, 324, and 334 may have one end connected to the redistribution pad 327 of the redistribution layer 320, and the other end located at the opposite side of the one end and located at a higher level than the top surface of the chip stack 200. In one embodiment, the other ends of the first to third additional conductive lines 314, 324, and 334 may be located at the same height as the other ends of the third conductive line 234 and the fourth conductive line 244 in a state of being located at the same height. However, the present embodiment is not limited thereto, but the other ends of the first to third additional conductive lines 314, 324, and 334 may be located at different heights on the premise that the other ends of the first to third additional conductive lines 314, 324, and 334 are located at a higher level than the fourth active surface 246. Since the first to third additional conductive lines 314, 324, and 334 are connected to the redistribution layer 320 formed at a relatively long distance from the carrier substrate 100, the first to third additional conductive lines 314, 324, and 334 may have a relatively small length.

[0050] Reference will be made to the following description Figure 2D to Figure 2G The connection relationship between the first and second conductive lines 214 and 224 and the redistribution layer 320 and between the first to third additional conductive lines 314 , 324 , and 334 and the redistribution layer 320 is described.

[0051] Figure 2D is based on Figure 2C327A in the first redistribution pad row shows a plan view of the redistribution layer 320 and the conductive lines connected to the redistribution layer 320, Figure 2E It is along Figure 2D The cross-sectional view obtained by the line X1-X1', Figure 2F is based on Figure 2C A plan view of the redistribution layer 320 and the conductive lines connected to the redistribution layer 320 is shown in FIG. Figure 2G is along Figure 2F A cross-sectional view taken along line X2-X2'.

[0052] First, refer to Figure 2D and Figure 2E as well as Figure 2A and Figure 2C As described above, the first redistribution pad 327A may include a first signal redistribution pad 327A-1, a second signal redistribution pad 327A-2, a first another signal redistribution pad 327A-3 and a second another signal redistribution pad 327A-4 arranged sequentially in a left to right direction.

[0053] The other end of the first signal line 214A connected to the first signal pad 212A may be connected to the first signal redistribution pad 327A-1. That is, the first signal line 214A may connect the first signal pad 212A and the first signal redistribution pad 327A-1 that are closest to each other in the first direction.

[0054] The other end of the second signal line 224A connected to the second signal pad 222A may be connected to the second signal redistribution pad 327A-2. That is, the second signal line 224A may be connected to the second signal pad 222A and the second signal redistribution pad 327A-2 that are close to each other in the first direction. In order to prevent a short circuit to the first signal line 214A, the second signal line 224A may be spaced apart from the first signal line 214A by a predetermined distance in the vertical direction and formed at a higher position than the first signal line 214A.

[0055] The first additional conductive line 314 may have one end connected to the first another signal redistribution pad 327A-3. The first another signal redistribution pad 327A-3 may be connected to the first signal redistribution pad 327A-1 through the first conductive layer 326A-1. As a result, a signal path passing through the first signal pad 212A, the first signal line 214A, the first conductive layer 326A-1, and the first additional conductive line 314 may be formed.

[0056] The second additional conductive line 324 may have one end connected to the second another signal redistribution pad 327A-4. The second another signal redistribution pad 327A-4 may be connected to the second signal redistribution pad 327A-2 through the second conductive layer 326A-2. As a result, a signal path passing through the second signal pad 222A, the second signal line 224A, the second conductive layer 326A-2 and the second additional conductive line 324 may be formed.

[0057] Next, refer to Figure 2F and Figure 2G as well as Figure 2B and Figure 2C As described above, the second redistribution pads 327B may include a power redistribution pad 327B- 1 and another power redistribution pad 327B- 2 sequentially arranged in a right-to-left direction.

[0058] The other end of the first power line 214B connected to the first power pad 212B may be connected to the power redistribution pad 327B-1. That is, the first power line 214B may connect the first power pad 212B and the power redistribution pad 327B-1 that are closest to each other in the first direction.

[0059] On the other hand, the other end of the second power line 224B connected to the second power pad 222B may not be directly connected to the second redistribution conductive layer 326B but may be connected to the first power pad 212B.

[0060] The third additional conductive line 334 may have one end connected to another power redistribution pad 327B-2. Another power redistribution pad 327B-2 may be connected to the power redistribution pad 327B-1 through the second redistribution conductive layer 326B. As a result, a power supply path passing through the second power pad 222B, the second power line 224B, the first power pad 212B, the first power line 214B, the second redistribution conductive layer 326B and the third additional conductive line 334 may be formed.

[0061] Refer again FIG. 2A to FIG. 2C, the wires (e.g., the third wire 234 and the fourth wire 244) among the first to fourth wires 214, 224, 234, and 244) connected to the semiconductor chip located at a relatively high level may have a relatively small length even if they extend in the vertical direction. Therefore, the occurrence of sweeping can be prevented, or the degree of sweeping may be small. However, the wires (e.g., the first wire 214 and the second wire 224) among the first to fourth wires 214, 224, 234, and 244) connected to the semiconductor chip located at a relatively low level may have a relatively large length when extended in the vertical direction. The degree of sweeping of the wires may be large. Therefore, in one embodiment, the first wire 214 and the second wire 224 may be connected to the bridging unit 300 to prevent the sweeping of the first wire 214 and the second wire 224. The following will refer to Figure 6 Describe the sweep.

[0062] Figure 6 2 is a diagram showing the sweep of the vertical wire VW.

[0063] Reference Figure 6 , the vertical wire VW may have one end E1 attached to the chip pad and another end E2 located at an opposite side of the one end E1.

[0064] The left side of the arrow shows the state immediately after the vertical wire VW is formed. As long as no external force is applied, such a vertical wire VW can maintain the state in which the vertical wire VW stands upright in the vertical direction.

[0065] The right side of the arrow shows the state after an external force (e.g., pressure caused by the flow of the molding material) is applied to the vertical wire VW during the molding process. When such pressure is applied, because one end E1 of the vertical wire VW is attached and fixed to the chip pad, the one end E1 does not move. However, since the other end E2 of the vertical wire VW is not fixed, the other end E2 moves in the direction in which the pressure is applied. Therefore, a sweeping motion in which the vertical wire VW is bent may occur. Due to the sweeping motion, the other end E2 of the vertical wire VW may be displaced to Figure 6 The other end E2 of the vertical wire VW is shown at a random position within the concentric circles. The displacement of the other end E2 of the vertical wire VW may change due to the vortex of the molding material caused by the molding material injection direction and pressure and the surrounding structure. As the length of the vertical wire VW increases, this sweeping may become severe. When the vertical wire VW sweeps, the vertical wire VW may be shorted with an adjacent vertical wire, or the connection between the vertical wire VW and the chip pad may be removed. In addition, due to the change in the position of the other end E2 of the vertical wire VW, the component to be connected to the other end E2 of the vertical wire VW (for example, the redistribution layer 600 (see Figure 6)) may be misaligned with the other end E2 of the vertical wire VW. Therefore, a connection defect may occur between the vertical wire VW and the redistribution layer.

[0066] Refer again FIG. 2A to FIG. 2C , when the wires connected to the first chip pad 212 and the second chip pad 222 are implemented as vertical wires, because the length of the wires connected to the first chip pad 212 and the second chip pad 222 is greater than the length of the wires connected to the third chip pad 232 and the fourth chip pad 242, the wires may be swept more than the wires connected to the third chip pad 232 and the fourth chip pad 242. In one embodiment, the first wire 214 and the second wire 224 may be connected to the bridge unit 300 on one side of the chip stack 200. Since one end and the other end of the first wire 214 and the second wire 224 are fixed, the sweeping may be prevented or reduced.

[0067] Since the first to third additional conductive lines 314, 324 and 334 extending in the vertical direction while being connected to the first conductive line 214 and the second conductive line 224 are formed in the bridge unit 300, the first conductive line 214 and the second conductive line 224 can be used as interconnects for transmitting signals in the vertical direction, like the third conductive line 234 and the fourth conductive line 244.

[0068] Since the first to third additional conductive lines 314, 324, and 334 are formed on the bridge unit 300 and thus have a relatively small length similar to the third conductive line 234 and the fourth conductive line 244, scanning may be prevented or reduced.

[0069] Reference Figure 3 , a molding layer 500 may be formed on the carrier substrate 100 on which the chip stack 200 , the bridge unit 300 , the first to fourth conductive lines 214 , 224 , 234 , and 244 , and the first to third additional conductive lines 314 , 324 , and 334 are formed.

[0070] The mold layer 500 may be formed to have a thickness sufficient to cover the chip stack 200 and the bridge unit 300. In one embodiment, the mold layer 500 may be formed to have a thickness sufficient to cover the third and fourth wires 234 and 244 as vertical wires and the first to third additional wires 314, 324, and 334. However, in another embodiment, the mold layer 500 may have a thickness that exposes the other ends of the third and fourth wires 234 and 244 and the first to third additional wires 314, 324, and 334, provided that the mold layer 500 covers the chip stack 200 and the bridge unit 300.

[0071] The molding layer 500 can be formed by a molding process that utilizes a molding material to fill the empty space of a molding mold (not shown) and then solidifies the molding material. When forming the molding layer 500, the pressure caused by the flow of the molding material may be applied to the first to the fourth wires 214, 224, 234 and 244 and the first to the third additional wires 314, 324 and 334. However, since the third wire 234 and the fourth wire 244 and the first to the third additional wires 314, 324 and 334 have a relatively small length, bending can be prevented and / or reduced. In addition, since the two ends of the first wire 214 and the second wire 224 are fixed, bending can be prevented or reduced.

[0072] Reference Figure 4 , a grinding process may be performed on the mold layer 500. The grinding process may include a mechanical or chemical polishing process.

[0073] Through the grinding process, the mold layer 500 may have a flat surface 501 located at a predetermined height from the first surface 101 of the carrier substrate 100. The height of the flat surface 501 may be greater than the height of the top surface of the chip stack 200. The other ends of the third and fourth conductive lines 234 and 244 and the first to third additional conductive lines 314, 324, and 334 may be exposed to the flat surface 501 in a state of being located at the same height as the flat surface 501 of the mold layer 500.

[0074] Reference Figure 5 , a package redistribution layer 600 may be formed on the flat surface 501 of the molding layer 500 .

[0075] The process of forming the package redistribution layer 600 will be described below. First, a first package redistribution dielectric layer 626 may be formed on the flat surface 501 of the mold layer 500. The first package redistribution dielectric layer 626 may be patterned to have an opening exposing the other ends of the third wire 234 and the fourth wire 244 and the other ends of the first to third additional wires 314, 324, and 334. Then, a package redistribution conductive layer 622 may be formed on the first package redistribution dielectric layer 626. The package redistribution conductive layer 622 may be buried in the opening of the first package redistribution dielectric layer 626 so as to be electrically connected to the other ends of the third wire 234 and the fourth wire 244 and the other ends of the first to third additional wires 314, 324, and 334, and patterned in various shapes. Then, a second package redistribution dielectric layer 624 may be formed on the first package redistribution dielectric layer 626 and the package redistribution conductive layer 622. The second packaging redistribution dielectric layer 624 may be patterned to have an opening exposing a portion of the packaging redistribution conductive layer 622 .

[0076] Subsequently, external connection terminals 700 may be formed on the package redistribution layer 600 to be electrically coupled to the package redistribution conductive layer 622 through the openings of the second package redistribution dielectric layer 624. In one embodiment, solder balls may be used as the external connection terminals 700. However, the present embodiment is not limited thereto, and various types of electrical connectors may be used.

[0077] Then, the carrier substrate 100 may be removed. The carrier substrate 100 may be removed at any step after the mold layer 500 is formed.

[0078] Through the above-described processes, the semiconductor package according to the embodiment can be manufactured.

[0079] Refer to Figure 5 and Figure 2C A semiconductor package according to an embodiment may include a chip stack 200, a bridge unit 300, third and fourth conductive lines 234 and 244, first and second conductive lines 214 and 224, and first to third additional conductive lines 314, 324, and 334. The chip stack 200 may include first to fourth semiconductor chips 210, 220, 230, and 240, the first to fourth semiconductor chips 210, 220, 230, and 240 having first to third chip pads 212, 222, and 232 and a fourth chip pad 242 formed at a fourth active surface 246, the first to third chip pads 212, 222, and 232 being respectively formed at the other side edge (e.g., left edge) exposed when the semiconductor chips are stacked in a manner offset to one side (e.g., right side), that is, at exposed portions 216A, 226A, and 236A of the first to third active surfaces 216, 226, and 236. The bridging unit 300 may be formed on the other side (e.g., the left side) of the chip stack 200 while being spaced apart from the chip stack 200. The third wire 234 and the fourth wire 244 may extend in a vertical direction in a state where one end thereof is connected to the third chip pad 232 and the fourth chip pad 242. The first wire 214 and the second wire 224 may have one end connected to the first chip pad 212 and the second chip pad 222, and the other end connected to the bridging unit 300 (or specifically, the redistribution layer 320). The first to third additional wires 314, 324, and 334 may extend in a vertical direction from the redistribution layer 320 in a state where they are electrically coupled to the first wire 214 and the second wire 224 through the redistribution layer 320.

[0080] The semiconductor package according to an embodiment may further include a package redistribution layer 600 and external connection terminals 700 formed on the flat surface 501 of the mold layer 500. Since the package redistribution layer 600 may be formed in a region defined by the mold layer 500, the semiconductor package according to an embodiment may be a fan-out semiconductor package.

[0081] Since components of the semiconductor package have been described when describing the manufacturing method, a detailed description thereof is omitted here.

[0082] The semiconductor package and the method of manufacturing the same which have been described so far can obtain the following effects.

[0083] First, in a semiconductor package including a plurality of stacked semiconductor chips that need to be connected to vertical wires having different lengths, the vertical wires having a relatively large length can be replaced by wires connected to a bridge unit and vertical wires extending from the bridge unit. Therefore, the length of the vertical wires in the semiconductor package can be set to a relatively small length. As a result, the sweeping of the vertical wires can be prevented and / or reduced, thereby preventing various defects.

[0084] Furthermore, the structure of the redistribution layer of the bridge unit and the layout of the conductive lines connected to the redistribution layer may be optimized to optimize the manufacturing process of the semiconductor package.

[0085] In one embodiment, it has been described that one bridge unit corresponding to one chip stack is formed. However, two or more chip stacks may share one bridge unit. Fig. 7A and 7B Describe the structure.

[0086] Fig. 7A and Figure 7B are a cross-sectional view and a plan view showing a semiconductor package according to an embodiment.

[0087] Reference Fig. 7A and Figure 7B , the first chip stack 200 , the bridge unit 300 ′, and the second chip stack 200 ′ may be disposed on the first surface 101 of the carrier substrate 100 .

[0088] The first chip stack 200 is substantially the same as the chip stack 200 of the above-described embodiment, and is therefore denoted by the same reference numerals. Therefore, the first to fourth conductive lines 214, 224, 234, and 244 connected to the first chip stack 200 are substantially the same as the first to fourth conductive lines 214, 224, 234, and 244 of the above-described embodiment, and are therefore denoted by the same reference numerals.

[0089] The second chip stack 200' may be located at an opposite side of the first chip stack 200, with the bridge unit 300' interposed between the first and second chip stacks 200 and 200'. That is, when the first chip stack 200 is located at the right side of the bridge unit 300', the second chip stack 200' may be located at the left side of the bridge unit 300'.

[0090] The second chip stack 200' may have a symmetrical structure with the first chip stack 200, and the bridge unit 300' is interposed between the first chip stack 200 and the second chip stack 200'. Therefore, the second chip stack 200' may include first to fourth semiconductor chips 210', 220', 230', and 240', which are stacked in a manner offset to the opposite side (e.g., the left side) of the first chip stack 200. The first to fourth semiconductor chips 210', 220', 230', and 240' may include first to fourth chip pads 212', 222', 232', and 242' formed at right edges of the first to fourth semiconductor chips 210', 220', 230', and 240' and exposed to the outside. The first signal pad 212A' and the first power pad 212B' of the first chip pad 212' may be respectively formed at positions corresponding to the first signal pad 212A and the first power pad 212B of the first chip pad 212, and the second signal pad 222A' and the second power pad 222B' of the second chip pad 222' may be respectively formed at positions corresponding to the second signal pad 222A and the second power pad 222B of the second chip pad 222. The first to fourth conductive lines 214', 224', 234' and 244' of the second chip stack 200' may also have a symmetrical structure with the first to fourth conductive lines 214, 224, 234 and 244 of the first chip stack 200.

[0091] The bridge unit 300' may be further extended in the first direction than the above-mentioned bridge unit 300, so that redistribution pads for connecting to the second chip stack 200', that is, connected to the first conductive line 214' and the second conductive line 224' may be further arranged. Since the first chip stack 200 and the second chip stack 200' are symmetrical to each other, the first to fourth conductive lines 214, 224, 234 and 244 of the second chip stack 200 and the right half of the redistribution layer 320' of the bridge unit 300 may have the same structure as the redistribution layer 320 of the above-mentioned embodiment, and the left half thereof may have a structure symmetrical to the right half. In other words, the right half of the redistribution pads (see P1' and P2') may have the same arrangement as the redistribution pads 327A and 327B of the above-mentioned embodiment, and the left half thereof may be arranged symmetrically to the right half. Therefore, the first to fourth conductive lines 214, 224, 234 and 244 and the first to third additional conductive lines 314, 324 and 334 connected to the right half of the redistribution pad can be formed in substantially the same manner as the first to fourth conductive lines 214, 224, 234 and 244 and the first to third additional conductive lines 314, 324 and 334 of the above-mentioned embodiment, and the first to fourth conductive lines 214', 224', 234' and 244' and the first to third additional conductive lines 314', 324' and 334' connected to the left half of the redistribution pad can be formed symmetrically with the first to fourth conductive lines 214, 224, 234 and 244 and the first to third additional conductive lines 314, 324 and 334.

[0092] The package according to the present embodiment is substantially the same as the package according to the above embodiment except that the second chip stack 200' and the wires 214' to 244' and 314' to 334' connected to the second chip stack 200' are symmetrical to the first chip stack 200 and the wires 214 to 244 and 314 to 334 connected to the first chip stack 200, and therefore, the redistribution layer 320' of the bridge unit 300' further includes pads for connection of the wires 214' to 244' and 314' to 334' arranged symmetrically with the pads to which the wires 214 to 244 and 314 to 334 are connected. Therefore, a detailed description of the individual components of the package according to the present embodiment is omitted herein.

[0093] According to an embodiment, defects of a semiconductor package may be avoided and a method for manufacturing the semiconductor package may be facilitated.

[0094] Figure 8A block diagram of an electronic system is shown, which includes a memory card 7800 using at least one of the semiconductor packages according to the embodiments. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiments.

[0095] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 to read out stored data or store data in response to a read / write request from the host 7830 .

[0096] Fig. 9 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715 that provides a path through which data moves.

[0097] In one embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to an embodiment of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0098] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0099] The electronic system 8710 may further include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0100] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0101] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution) or Wibro (Wireless Broadband Internet Access) technology.

[0102] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the following claims.

[0103] CROSS-REFERENCE TO RELATED APPLICATIONS

[0104] This application claims priority from Korean Patent Application No. 10-2019-0118014, filed on September 25, 2019, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: A chip stack, the chip stack comprising first to N-th semiconductor chips, the first to N-th semiconductor chips being stacked in sequence in a manner of being offset to one side so that edges of the first to N-th semiconductor chips on the other side are exposed, and the first to N-th semiconductor chips respectively have first to N-th chip pads disposed at the edges of the other side, wherein N is a natural number equal to or greater than 2; a bridge unit disposed adjacent to the other side of the chip stack and spaced apart from the chip stack; a kth wire to an Nth wire, the kth wire to the Nth wire extending in a vertical direction with one end thereof connected to the kth chip pad to the Nth chip pad among the first chip pad to the Nth chip pad, wherein k is a natural number equal to or greater than 2 and equal to or less than N; a first wire to a k-1th wire, one end of the first wire to the k-1th wire being connected to the first chip pad to the k-1th chip pad among the first chip pad to the Nth chip pad, wherein the other end of the first wire is connected to the bridge unit, and the other end of the second wire to the k-1th wire is connected to the bridge unit or the first chip pad to the k-2th chip pad, respectively; and an additional conductive line electrically coupled to the first to k-1th conductive lines and extending in the vertical direction with one end thereof connected to the bridge unit, The thickness of the bridge unit is greater than the total thickness of the first to k-1th semiconductor chips among the first to Nth semiconductor chips, and is equal to or less than the thickness of the chip stack.

2. The semiconductor package according to claim 1, wherein The bridging unit comprises: the main body; and A redistribution layer is located on the main body portion and is connected to the additional wire and the wires from the first wire to the k-1th wire whose other ends are connected to the bridge unit.

3. The semiconductor package according to claim 2, wherein: The body portion is electrically insulated from the redistribution layer and the chip stack.

4. The semiconductor package according to claim 2, wherein: The redistribution layer comprises: a first redistribution dielectric layer, the first redistribution dielectric layer covering the main body portion; a redistribution conductive layer on the first redistribution dielectric layer; and The second redistribution dielectric layer covers the first redistribution dielectric layer and the redistribution conductive layer and has an opening to expose a portion of the redistribution conductive layer.

5. The semiconductor package according to claim 4, wherein: The first chip pad to the k-1th chip pad are signal pads to which signals are applied, The redistribution conductive layer includes a first conductive layer to a k-1th conductive layer separated from each other, The first conductive line to the k-1th conductive line are connected to the first conductive layer to the k-1th conductive layer respectively, and The additional conductive lines include first to k-1th additional conductive lines, which are respectively connected to the first to k-1th conductive layers while being spaced apart from the first to k-1th conductive lines.

6. The semiconductor package according to claim 5, wherein: The tth conductive layer among the first conductive layer to the k-1th conductive layer includes a tth connecting portion having a relatively small width and two tth end portions having a relatively large width and located on both sides of the tth connecting portion, wherein t is a natural number equal to or greater than 1 and equal to or less than k-1, The t+1th conductive layer includes a t+1th connecting portion having a relatively small width and two t+1th end portions having a relatively large width and located at both sides of the t+1th connecting portion, and The tth conductive layer and the t+1th conductive layer are disposed such that the two tth end portions and the two t+1th end portions are alternately arranged.

7. The semiconductor package according to claim 6, wherein: The t-th wire among the first wire to the k-1-th wire and the t-th additional wire among the first additional wire to the k-1-th additional wire are connected to the two t-th ends, respectively, and The t+1th conductive line and the t+1th additional conductive line are connected to the two t+1th end portions, respectively.

8. The semiconductor package according to claim 7, wherein: The tth wire is connected to the closer one of the two tth ends, and The t+1th wire is connected to the closer one of the two t+1th ends.

9. The semiconductor package according to claim 6, wherein: The opening of the second redistribution dielectric layer overlaps the two t-th end portions and the two t+1-th end portions, respectively.

10. The semiconductor package according to claim 4, wherein The first chip pad to the k-1th chip pad are power pads to which a ground voltage or a power voltage is applied, The second wire to the k-1th wire are connected to the first chip pad to the k-2th chip pad, and The first conductive line and the additional conductive line are commonly connected to the redistribution conductive layer.

11. The semiconductor package according to claim 10, wherein: The redistribution conductive layer extends in one direction such that the other end of the first conductive line and one end of the additional conductive line are arranged to be spaced apart from each other in the one direction.

12. The semiconductor package according to claim 11, wherein The opening of the second redistribution dielectric layer overlaps the other end of the first conductive line and one end of the additional conductive line, respectively.

13. The semiconductor package according to claim 1, wherein The first to Nth semiconductor chips include the same memory chip.

14. The semiconductor package according to claim 1, further comprising a molding layer covering the chip stack, the bridging unit, the first to N-th wires, and the additional wires, and having a surface exposing the other ends of the k-th to N-th wires and the other end of the additional wires. 15 . The semiconductor package of claim 14 , further comprising a package redistribution layer formed on the one surface of the mold layer and electrically coupled to the other ends of the kth to Nth wires and the other end of the additional wire.

16. The semiconductor package according to claim 15, wherein: The package redistribution layer comprises: a first package redistribution dielectric layer, the first package redistribution dielectric layer covering the one surface of the molding layer and having an opening to expose the other end of the kth wire to the Nth wire and the other end of the additional wire; a package redistribution conductive layer formed on the first package redistribution dielectric layer and connected to the other ends of the kth wire to the Nth wire and the other end of the additional wire through the opening; and A second packaging redistribution dielectric layer covers the first packaging redistribution dielectric layer and the packaging redistribution conductive layer, and has an opening to expose a portion of the packaging redistribution conductive layer. 17 . The semiconductor package of claim 15 , further comprising external connection terminals electrically coupled to the package redistribution layer. 18 . The semiconductor package of claim 1 , further comprising an additional chip stack that shares the bridge unit with the chip stack.

19. The semiconductor package according to claim 18, wherein: The additional chip stack is disposed opposite to one side of the bridge unit adjacent to the other side of the chip stack such that the bridge unit is interposed between the chip stack and the additional chip stack.

20. The semiconductor package according to claim 18, wherein The conductive line connected to the additional chip stack has a symmetrical structure with the first to N-th conductive lines connected to the chip stack and the additional conductive line.

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