Stretchable display device

Abstract

Stretchable display device. According to one aspect of the present disclosure, a stretchable display device includes: a lower substrate, on which a display area for displaying an image and a non-display area adjacent to the display area are defined; a plurality of pixel substrates, the plurality of pixel substrates being arranged in the display area; a plurality of external substrates, the plurality of external substrates being arranged in the non-display area; a plurality of pixels, the plurality of pixels being arranged on the plurality of pixel substrates; and a plurality of gate drivers, the plurality of gate drivers being arranged on the plurality of external substrates and outputting gate voltages to the plurality of pixels. Therefore, even when the stretchable display device is stretched, the pixels can be driven normally.

Description

Technical Field

[0001] The present invention relates to a stretchable display device, and more particularly, to a stretchable display device that allows for reducing contraction of a display panel when the stretchable display device is stretched. Background Art

[0002] Display devices used for computer monitors, TVs, mobile phones, and the like include organic light emitting displays (OLEDs) that emit light by themselves, liquid crystal displays (LCDs) that require a separate light source, and the like.

[0003] Such display devices are being applied to an increasing variety of fields including not only computer monitors and TVs but also personal mobile devices, and thus, display devices that are reduced in size and weight while having a large display area are being studied.

[0004] Recently, a stretchable display device manufactured to be stretchable in a specific direction and changeable into various shapes by forming a display unit, a circuit, etc. on a flexible substrate such as plastic as a flexible material has attracted attention as a next-generation display device. Summary of the invention

[0005] An object to be achieved by the present disclosure is to provide a stretchable display device including a gate driver capable of outputting a gate voltage when the stretchable display device is stretched.

[0006] Another object to be achieved by the present disclosure is to provide a stretchable display device that can stably supply a driving voltage when the stretchable display device is stretched.

[0007] Still another object to be achieved by the present disclosure is to provide a stretchable display device which can reduce stress concentrated in a non-display area when the stretchable display device is stretched.

[0008] Still another object to be achieved by the present disclosure is to provide a stretchable display device which allows its frame area to be reduced.

[0009] The objects of the present disclosure are not limited to the objects mentioned above, and those skilled in the art can clearly understand other objects not mentioned above according to the following description.

[0010] According to one aspect of the present disclosure, a stretchable display device includes: a lower substrate, on which a display area for displaying an image and a non-display area adjacent to the display area are defined; a plurality of pixel substrates, the plurality of pixel substrates being arranged in the display area; a plurality of external substrates, the plurality of external substrates being arranged in the non-display area; a plurality of pixels, the plurality of pixels being arranged on the plurality of pixel substrates; and a plurality of gate drivers, the plurality of gate drivers being arranged on the plurality of external substrates and outputting gate voltages to the plurality of pixels. Therefore, even when the stretchable display device is stretched, the pixels can be driven normally.

[0011] According to another aspect of the present disclosure, a stretchable display device includes: a stretchable substrate, on which a display area for displaying an image and a non-display area adjacent to the display area are defined; a plurality of first rigid substrates, the plurality of first rigid substrates being arranged in the display area; a plurality of second rigid substrates, the plurality of second rigid substrates being arranged in the non-display area; a plurality of pixels, the plurality of pixels being arranged on the plurality of first rigid substrates; a plurality of gate drivers, the plurality of gate drivers being arranged on the plurality of second rigid substrates and including a plurality of transistors; and a plurality of power supply units, the plurality of power supply units being arranged on the plurality of second rigid substrates and connected to the plurality of gate drivers and the plurality of pixels. Therefore, even when the stretchable display device is stretched, the driving voltage can be supplied normally.

[0012] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0013] According to the present disclosure, a stretchable power supply unit and a gate driver may be provided, thereby driving pixels of a stretchable display device.

[0014] According to the present disclosure, the size of the bezel area can be reduced by overlapping the power supply unit with the gate driver.

[0015] According to the present disclosure, there is an effect of improving adhesion between the substrate and the frame by providing an adhesive material between the substrate and the structure.

[0016] According to the present disclosure, there is an effect of reducing stress concentrated in a non-display area by uniformly forming a connection substrate in a bent shape between external substrates.

[0017] According to the present disclosure, it is possible to stably supply a driving voltage by configuring a power supply unit in a plate shape.

[0018] The effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 is a schematic plan view of a stretchable display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 2 yes Figure 1 An enlarged plan view of the region X illustrated in FIG.

[0022] Figure 3 It is along Figure 2 A cross-sectional view taken along line III-III';

[0023] Figure 4 is a block diagram for illustrating driving of a gate driver according to an exemplary embodiment of the present disclosure;

[0024] Figure 5A and Figure 5B yes Figure 1 An enlarged plan view of the region Y illustrated in FIG.

[0025] Figure 6 It is along Figure 5A A cross-sectional view taken along line VI-VI';

[0026] Figure 7 is an enlarged plan view of a non-display area of ​​a stretchable display device according to another exemplary embodiment of the present disclosure;

[0027] Figure 8 It is along Figure 7 A cross-sectional view taken along line III-III' in FIG.

[0028] Fig. 9 It is along Figure 8 A cross-sectional view taken along line IX-IX'. DETAILED DESCRIPTION

[0029] By referring to the following together with the attached Figure 1 With the detailed description of the exemplary embodiments, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure. Therefore, the present disclosure will only be limited by the scope of the appended claims.

[0030] The shapes, sizes, ratios, angles, quantities, etc. illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessary confusion of the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0031] Even if not explicitly stated, parts are interpreted as including the general error range.

[0032] When terms such as “on,” “above,” “below,” and “beside” are used to describe the positional relationship between two components, one or more components may be disposed between the two components unless these terms are used together with the term “directly” or “exactly.”

[0033] When an element or layer is referred to as being “on” another element or layer, the other layer or other elements may be directly on the other element or be interposed therebetween.

[0034] Although the terms "first", "second", etc. are used to describe various components, these components should not be constrained by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below can be the second component.

[0035] Throughout the specification, like reference numerals generally refer to like elements.

[0036] For convenience of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0037] The features of the various embodiments of the present disclosure may be combined or coupled with each other in part or in whole, and may be interlocked and operated in various technical ways, and these embodiments may be performed independently of each other or in association with each other.

[0038] Hereinafter, a stretchable display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] <Stretchable Display Device>

[0040] A stretchable display device may refer to a display device that can display an image even if it is bent or stretched. A stretchable display device may have higher flexibility than a conventional display device. Therefore, the shape of the stretchable display device can be freely deformed due to user manipulation such as bending or stretching the stretchable display device. For example, when a user grabs the end of the stretchable display device and pulls the stretchable display device, the stretchable display device can be stretched under the action of the user's force. If the user places the stretchable display device on an uneven wall surface, the stretchable display device may be bent according to the shape of the wall surface. When the force applied by the user is removed, the stretchable display device may return to its original shape. In addition, the shape of the stretchable display device can be bent, stretched or extended to the extent or threshold at which the stretchable display device and its various components maintain their original features and functions. When the force applied by the user exceeds the threshold, the display device may break and may not return to its original shape or contracted shape.

[0041] Figure 1 is a schematic plan view of a stretchable display device according to an exemplary embodiment of the present disclosure.

[0042] Reference Figure 1 , the stretchable display device 100 includes a lower substrate 110 a , a plurality of pixel substrates 111 , a plurality of external substrates 121 , a plurality of connection substrates 120 , a COF (Chip On Film) 130 , and a printed circuit board 140 .

[0043] The lower substrate 110a is used to protect and support various components of the stretchable display device 100. The lower substrate 110a is a flexible substrate and may be formed of a bendable or stretchable insulating material. For example, the lower substrate 110a may be formed of a silicone rubber such as polydimethylsiloxane (PDMS) or an elastomer such as polyurethane (PU) and polytetrafluoroethylene (PTFE). Therefore, the lower substrate 110a may have flexibility. However, the material of the lower substrate 110a is not limited thereto.

[0044] The lower substrate 110 is a soft substrate so as to expand and contract reversibly. In addition, the elastic modulus of the lower substrate 110 can be several MPa to several hundred MPa, for example, it can be 0.7 MPa to 1 MPa. In addition, the ductile fracture rate of the lower substrate 110 can be 100% or more. Here, the ductile fracture rate refers to the extension distance when the stretched object is damaged or broken. That is, the ductile fracture rate is defined as the percentage of the length of the original object to the length of the stretched object when the object has been stretched sufficiently to be considered damaged. For example, if the length of the object is 100 cm when the object (e.g., the lower substrate 110) is not stretched, then, when the object is stretched sufficiently in length to damage or break it, the length of the object reaches 110 cm, so that the object is stretched to 110% of its original length. In this case, the ductile fracture rate of the object is 110%. Therefore, this number can also be called the ductile fracture ratio because it is the ratio of the stretched length as the numerator to the original unstretched length as the denominator when the fracture occurs.

[0045] An object is considered damaged when it no longer functions properly in a structure or circuit. For example, a wire as a conductor is considered damaged when its ability to carry current is sufficiently reduced to not function within the circuit specifications. Therefore, in some embodiments, a wire may not need to be completely disconnected to be considered damaged, and minor stresses at the connection ends, minor cracks, slight shifts in the position of the wire, or other movements that cause the wire to no longer function within its intended function will be considered a damaged wire. If an insulator is stretched sufficiently that it no longer provides the amount of insulation required by a structure or circuit, it is considered damaged. In some embodiments, damage will also include inelastic stretching where the object has been stretched sufficiently to not return to its original length and / or shape when it is no longer stretched. The thickness of the lower substrate 110a may be from 10 μm to 1 mm, but is not limited thereto.

[0046] In addition, the lower substrate 110 a may include a display area AA and a non-display area NA surrounding the display area AA.

[0047] The display area AA refers to the area where the stretchable display device 100 displays an image. In the display area AA, a light-emitting element and various driving elements for driving the light-emitting element are provided. The display area AA includes a plurality of pixels, and the pixels include a plurality of sub-pixels. The plurality of pixels are arranged in the display area AA and include a plurality of light-emitting devices. Each of the plurality of sub-pixels can be connected to various lines. For example, each of the plurality of sub-pixels can be connected to various lines such as a gate line, a data line, a high potential pixel drive voltage line, a low potential pixel drive voltage line, a reference voltage line, and the like.

[0048] The non-display area NA refers to an area adjacent to the display area AA. The non-display area NA is adjacent to the display area AA and surrounds the display area AA. In the non-display area NA, an image is not displayed, and lines and circuits may be set. For example, a plurality of pads may be set in the non-display area NA, and each pad may be connected to each of a plurality of sub-pixels set in the display area AA.

[0049] On the lower substrate 110a, a plurality of pixel substrates 111 and a plurality of external substrates 121 are disposed. The plurality of pixel substrates 111 may be disposed in the display area AA of the lower substrate 110a, and the plurality of external substrates 121 may be disposed in the non-display area NA of the lower substrate 110a. Figure 1 It is illustrated that the plurality of external substrates 121 in the non-display area NA are disposed on the upper and lower sides and the left side of the display area AA. However, the present disclosure is not limited thereto. The plurality of external substrates 121 may be disposed in any area in the non-display area NA.

[0050] The plurality of pixel substrates 111 and the plurality of external substrates 121 are rigid substrates and are independently arranged to be spaced apart from each other on the lower substrate 110a. That is, the pixel substrate 111 may be referred to as a first rigid substrate, and the external substrate 121 may be referred to as a second rigid substrate. The plurality of pixel substrates 111 and the plurality of external substrates 121 may be more rigid than the lower substrate 110a. That is, the lower substrate 110a may be more ductile than the plurality of pixel substrates 111 and the plurality of external substrates 121, and the plurality of pixel substrates 111 and the plurality of external substrates 121 may be more rigid than the lower substrate 110a.

[0051] Each of the multiple pixel substrates 111 and the multiple external substrates 121 as multiple rigid substrates can be formed of a flexible plastic material. The multiple pixel substrates 111 and the multiple external substrates 121 can be formed of, for example, polyimide (PI), polyacrylate, polyacetate, etc., but are not limited thereto. The multiple pixel substrates 111 and the multiple external substrates 121 can be formed of materials different from the above materials. In this case, the multiple pixel substrates 111 can be formed of the same material as the multiple external substrates 121, but are not limited thereto. The pixel substrate 111 can also be formed of a material different from the multiple external substrates 121.

[0052] The plurality of pixel substrates 111 and the plurality of external substrates 121 may have a modulus higher than that of the lower substrate 110a. Here, modulus refers to an elastic modulus representing the ratio of the deformation of the substrate to the stress applied to the substrate, and when the modulus is relatively high, the hardness will be relatively high. Therefore, the plurality of pixel substrates 111 and the plurality of external substrates 121 may be a plurality of rigid substrates having a higher rigidity than the lower substrate 110a. The modulus of the plurality of pixel substrates 111 and the plurality of external substrates 121 may be 1000 times or more of the modulus of the lower substrate 110a, but is not limited thereto. For example, depending on the transparency of the pixel substrate 111, the elastic modulus of the pixel substrate 111 may be 2GPa to 9GPa. More specifically, when the pixel substrate 111 is transparent, the elastic modulus is 2GPa, and when the pixel substrate 111 is opaque, the elastic modulus is 9GPa.

[0053] In some exemplary embodiments, the lower substrate 110a may be defined as including a plurality of first lower patterns and a second lower pattern. The plurality of first lower patterns may be disposed in a region of the lower substrate 110a overlapping with the plurality of pixel substrates 111 and the plurality of external substrates 121. In addition, the second lower pattern may be disposed in a region excluding a region where the plurality of pixel substrates 111 and the plurality of external substrates 121 are disposed. Otherwise, the second lower pattern may be disposed in the entire region of the stretchable display device 100.

[0054] In this case, the plurality of first lower patterns may have a modulus higher than that of the second lower pattern. For example, the plurality of first lower patterns may be formed of the same material as the plurality of pixel substrates 111. The second lower pattern may be formed of a material having a modulus lower than that of the plurality of pixel substrates 111.

[0055] COF 130 is a flexible film formed by placing various components on a ductile base film 131, and is a component for supplying signals to a plurality of sub-pixels in the display area AA. COF 130 may be bonded to a plurality of pads disposed in the non-display area NA, and data voltages, etc., may be supplied to a plurality of corresponding sub-pixels through the pads. COF 130 may supply pixel drive voltage, gate clock voltage, and gate drive voltage to a power supply unit PS and a gate driver GD in the non-display area NA. COF 130 may include a base film 131 and a driver IC 132, and may also include various components. The power supply unit PS (which may be referred to as a power supply circuit PS in this article) may include any circuit, feature, component, component of an electrical component, etc. configured to perform various operations of the power supply feature described herein. In some embodiments, the power supply unit PS may be included in a processing circuit such as a microprocessor, a microcontroller, an integrated circuit, a chip, a microchip, etc. or implemented by a processing circuit such as a microprocessor, a microcontroller, an integrated circuit, a chip, a microchip, etc.

[0056] The base film 131 is used to support the driving IC 132 of the OCF 130. The base film 131 may be formed of an insulating material. For example, the base film 131 may be formed of an insulating material having flexibility.

[0057] The driving IC 132 is configured to process data for displaying an image and a driving signal for processing the data. Figure 1 The method of mounting the driving IC 132 by the COF 130 is exemplified, but is not limited thereto. The driving IC 132 may also be mounted by a chip on glass (COG) method, a tape carrier package (TCP) method, or the like.

[0058] Figure 1 It is illustrated that one external substrate 121 is disposed in the non-display area NA on one side of the display area AA so as to correspond to a row of pixel substrates 111 disposed in the display area AA, and one COF 130 is disposed for one external substrate 121. However, the present disclosure is not limited thereto. That is, one external substrate 121 and one COF 130 may be disposed to correspond to a plurality of rows of pixel substrates 111.

[0059] In the printed circuit board 140, a control unit (or a control circuit) such as an IC chip, a circuit, etc. may be installed. In addition, in the printed circuit board 140, a memory, a processor, etc. may also be installed. The printed circuit board 140 is configured to transmit a signal for driving the light emitting element from the control unit to the light emitting element. Figure 1 2 and 3 , the use of three printed circuit boards 140 is exemplified, but the number of the printed circuit boards 140 is not limited thereto.

[0060] In the following, reference will be made to Figures 2 to 3 The stretchable display device 100 according to an exemplary embodiment of the present disclosure is described in more detail.

[0061] <Plane and cross-sectional structure>

[0062] Figure 2 yes Figure 1 An enlarged plan view of the area X illustrated in FIG. Figure 3 It is along Figure 2 A cross-sectional view taken along line III-III'.

[0063] Reference Figure 1 and Figure 2 , a plurality of pixel substrates 111 are disposed on the lower substrate 110a in the display area AA. The plurality of pixel substrates 111 are disposed on the lower substrate 110a spaced apart from each other. Figure 1 and Figure 2 As shown in FIG. 1 , a plurality of pixel substrates 111 may be disposed on the lower substrate 110 a in a matrix form, but is not limited thereto.

[0064] Reference Figure 1 and Figure 2 , a plurality of sub-pixels SPX constituting a plurality of pixels PX may be disposed in a plurality of pixel substrates 111. In addition, a gate driver GD and a power supply unit PS may be mounted on external substrates 121 located on both sides in the X-axis direction among a plurality of external substrates 121.

[0065] The gate driver GD may be formed in a gate-in-panel (GIP) manner on the external substrate 121. More specifically, one stage of the gate driver GD may be provided on each of the plurality of external substrates 121. Therefore, various circuit components constituting one stage of the gate driver GD, such as various transistors, capacitors, and wirings, may be provided on the plurality of external substrates 121.

[0066] In addition, each stage of the gate driver GD formed on the external substrate 121 may be electrically connected to each other. That is, each stage of the gate driver GD formed on the external substrate 121 is electrically connected to each other, thereby transmitting a gate voltage output from any stage to another stage connected to this stage. Figure 4 A specific driving method of the gate driver D is described.

[0067] However, the gate driver GD is not limited to being mounted in a gate in panel (GIP) manner, and the gate driver GD may be mounted in a chip on film (COF) manner.

[0068] In addition, the power supply unit PS may be formed on the external substrate 121. In other words, the power supply unit PS may be formed on the external substrate 121 adjacent to the gate driver GD.

[0069] In addition, the power supply unit PS is connected to the gate driver GD to supply a gate driving voltage and a gate clock voltage. In addition, the power supply unit PS is connected to the plurality of pixels PX to supply a pixel driving voltage to each of the plurality of pixels PX.

[0070] In addition, the corresponding power supply units PS formed on the plurality of external substrates 121 may be electrically connected to each other. That is, the plurality of power supply units PS formed on the plurality of external substrates 121 may be connected to each other through a gate power connection line and a pixel power connection line. Therefore, each of the plurality of power supply units PS may supply a gate drive voltage, a gate clock voltage, and a pixel drive voltage through a gate power connection line and a pixel power connection line.

[0071] Then, refer to FIG. 5A to FIG. 9 Describe the specific connection relationship of the power supply unit PS.

[0072] In addition, refer to Figure 1 , the size of the plurality of external substrates 121 may be larger than the size of the plurality of pixel substrates 111. Specifically, the size of each of the plurality of external substrates 121 may be larger than the size of each of the plurality of pixel substrates 111. As described above, the gate driver GD and the power supply unit PS are disposed on each of the plurality of external substrates 121. Therefore, since the area occupied by the gate driver GD and the power supply unit PS is relatively larger than the area on the pixel substrate 111 where the pixels PX are disposed, the size of each of the plurality of external substrates 121 may be larger than the size of each of the plurality of pixel substrates 111.

[0073] Reference Figure 1 and Figure 2 , a plurality of connection substrates 120 may be disposed between a plurality of pixel substrates 111 or between a plurality of external substrates 121. Otherwise, a plurality of connection substrates 120 may be disposed between a plurality of pixel substrates 111 and a plurality of external substrates 121. A plurality of connection substrates 120 are used to connect pixel substrates 111 adjacent to each other, to connect external substrates 121 adjacent to each other, or to connect pixel substrates 111 and external substrates 121 to each other. A plurality of connection substrates 120 may be formed of the same material as the pixel substrate 111 or the external substrate 121, and may be formed integrally with the pixel substrate 111 or the external substrate 121 at the same time. However, the present disclosure is not limited thereto.

[0074] Reference Figure 2 , the plurality of connection substrates 120 have a curved shape. Figure 2 As shown in , a plurality of connection substrates 120 may have a sine wave shape. However, the shape of a plurality of connection substrates 120 is not limited thereto. A plurality of connection substrates 120 may have various shapes. For example, a plurality of connection substrates 120 may extend in a zigzag manner, or a plurality of rhombus-shaped substrates may extend by being connected to each other at their vertices. Figure 2 The number and shape of the plurality of connection substrates 120 shown in FIG. 1 are provided by way of example. The number and shape of the plurality of connection substrates 120 may be different depending on the design thereof.

[0075] Reference Figure 3 , a plurality of inorganic insulating layers are disposed on the plurality of pixel substrates 111. For example, the plurality of inorganic insulating layers may include a buffer layer 112, a gate insulating layer 113, and an interlayer insulating layer 114, but is not limited thereto. Various inorganic insulating layers may be additionally disposed on the plurality of pixel substrates 111, or one or more of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114 may be omitted.

[0076] Reference Figure 3 , a buffer layer 112 is disposed on a plurality of pixel substrates 111. The buffer layer 112 is formed on the plurality of pixel substrates 111 to protect the various components of the stretchable display device 100 from being penetrated by moisture (H2O), oxygen (O2), etc. from outside the lower substrate 110a and the plurality of pixel substrates 111. The buffer layer 112 may be formed of an insulating material. For example, the buffer layer 112 may be formed of a single inorganic layer or multiple inorganic layers of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc. However, depending on the structure or characteristics of the stretchable display device 100, the buffer layer 112 may be omitted.

[0077] In this case, the buffer layer 112 may be formed only in the region overlapping with the plurality of pixel substrates 111 and the plurality of external substrates 121. As described above, the buffer layer 112 may be formed of an inorganic material. Therefore, while the stretchable display device 100 is stretched, the buffer layer 112 may be easily damaged, for example, may be easily broken. Therefore, the buffer layer 112 may not be formed in the region between the plurality of pixel substrates 111 and the plurality of external substrates 121. The buffer layer 112 may be patterned into the shape of the plurality of pixel substrates 111 and the plurality of external substrates 121, and may be formed only on the upper portions of the plurality of pixel substrates 111 and the plurality of external substrates 121. Therefore, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the buffer layer 112 is formed only in the region overlapping with the plurality of external substrates 121 and the plurality of pixel substrates 111 as rigid substrates. Therefore, even when the stretchable display device 100 is deformed such as bending or stretching, the buffer layer 112 may be prevented from being damaged.

[0078] Reference Figure 3 , a transistor 150 including a gate 151 , an active layer 152 , a source 153 and a drain 154 is formed on the buffer layer 112 .

[0079] First, refer to Figure 3 , the active layer 152 is disposed on the buffer layer 112. For example, the active layer 152 may be formed of an oxide semiconductor, or may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), an organic semiconductor, or the like.

[0080] The gate insulating layer 113 is disposed on the active layer 152. The gate insulating layer 113 serves as a layer for electrically insulating the gate electrode 151 from the active layer 152, and may be formed of an insulating material. For example, the gate insulating layer 113 may be formed of a single layer or a plurality of layers of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material, but is not limited thereto.

[0081] The gate 151 is disposed on the buffer layer 112. The gate 151 is disposed to overlap the active layer 152. The gate 151 may be formed of any of various metal materials (e.g., any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy of two or more thereof, or a multilayer thereof), but is not limited thereto.

[0082] An interlayer insulating layer 114 is disposed on the gate electrode 151. The interlayer insulating layer 114 serves to insulate the gate electrode 151 from the source electrode 153 and the drain electrode 154, and may be formed of an inorganic material like the buffer layer 112. For example, the interlayer insulating layer 114 may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx) as an inorganic material, but is not limited thereto.

[0083] The source electrode 153 and the drain electrode 154 contacting the active layer 152 are disposed on the interlayer insulating layer 114. The source electrode 153 and the drain electrode 154 are disposed on the same layer spaced apart from each other. The source electrode 153 and the drain electrode 154 may be electrically connected to the active layer 152 to contact the active layer 152. The source electrode 153 and the drain electrode 154 may be formed of one of various metal materials (e.g., any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy of two or more thereof, or a multilayer thereof).

[0084] In addition, the gate insulating layer 113 and the interlayer insulating layer 114 may be patterned and formed only in the region overlapping with the plurality of pixel substrates 111. The gate insulating layer 113 and the interlayer insulating layer 114 may also be formed of an inorganic material like the buffer layer 112. Therefore, while the stretchable display device 100 is stretched, the gate insulating layer 113 and the interlayer insulating layer 114 may be easily damaged, for example, may be easily broken. Therefore, the gate insulating layer 113 and the interlayer insulating layer 114 may not be formed in the region between the plurality of pixel substrates 111. The gate insulating layer 113 and the interlayer insulating layer 114 may be patterned into the shape of the plurality of pixel substrates 111 and formed only on the plurality of pixel substrates 111.

[0085] For ease of explanation, Figure 3 Only a driving transistor is illustrated among various transistors that can be included in the stretchable display device 100. However, a switching transistor, a capacitor, etc. may also be included in the stretchable display device. In addition, in the present disclosure, the transistor 150 is described as having a coplanar structure, but various types of transistors having a staggered structure, etc. may also be used.

[0086] Reference Figure 3 , a plurality of pads 170 are disposed on the interlayer insulating layer 114. Specifically, a gate pad 171 among the plurality of pads 170 is disposed on the interlayer insulating layer 114. The gate pad 171 is used to transmit a gate voltage to a plurality of sub-pixels SPX. The gate voltage may be transmitted from the gate pad 171 to the gate 151 through a gate line formed on the pixel substrate 111. The gate pad 171 may be formed of the same material as the source electrode 153 and the drain electrode 154, but is not limited thereto.

[0087] Reference Figure 3 , a data pad 172 among the plurality of pads 170 is disposed on the interlayer insulating layer 114. The data pad 172 is used to transmit a data voltage to the plurality of sub-pixels SPX. The data voltage may be transmitted from the data pad 172 to the source electrode 153 or the drain electrode 154 through a data line formed on the pixel substrate 111. The data pad 172 may be formed of the same material as the source electrode 153 and the drain electrode 154, but is not limited thereto.

[0088] Reference Figure 3 , a planarization layer 115 is formed on the transistor 150 and the interlayer insulating layer 114. The planarization layer 115 is used to planarize the upper portion of the transistor 150. The planarization layer 115 may be formed of a single layer or a plurality of layers and may be formed of an organic material. For example, the planarization layer 115 may be formed of an acrylic organic material, but is not limited thereto.

[0089] Reference Figure 3, the planarization layer 115 is disposed on the plurality of pixel substrates 111 to cover the upper and side surfaces of the buffer layer 112, the gate insulation layer 113, and the interlayer insulation layer 114. Therefore, the planarization layer 115 surrounds the buffer layer 112, the gate insulation layer 113, and the interlayer insulation layer 114 together with the plurality of pixel substrates 111. Specifically, the planarization layer 115 may be disposed to cover the upper and side surfaces of the interlayer insulation layer 114, the side surface of the gate insulation layer 113, the side surface of the buffer layer 112, and a portion of the upper surface of the plurality of pixel substrates 111. Therefore, the planarization layer 115 may compensate for the steps between the side surfaces of the buffer layer 112, the gate insulation layer 113, and the interlayer insulation layer 114. In addition, the planarization layer 115 may enhance the adhesion strength between the planarization layer 115 and the pixel connection line 180 disposed on the side surface of the planarization layer 115.

[0090] Reference Figure 3 , the inclination angle of the side surface of the planarization layer 115 may be smaller than the inclination angle of the side surfaces of the buffer layer 112, the gate insulation layer 113, and the interlayer insulation layer 114. For example, the side surface of the planarization layer 115 may have an inclination lower than the inclination of the side surface of the interlayer insulation layer 114, the side surface of the gate insulation layer 113, and the side surface of the buffer layer 112. Therefore, the pixel connection line 180 in contact with the side surface of the planarization layer 115 is set to have a low inclination. Therefore, when the stretchable display device 100 is stretched, the stress generated in the pixel connection line 180 can be reduced. In addition, cracks in the pixel connection line 180 or peeling of the pixel connection line 180 from the side surface of the planarization layer 115 can be suppressed.

[0091] In some embodiments, a passivation layer may be formed between the transistor 150 and the planarization layer 115. That is, the passivation layer covering the transistor 150 may be formed to protect the transistor 150 from being penetrated by moisture, oxygen, etc. The passivation layer may be formed of an inorganic material and formed of a single layer or a plurality of layers, but is not limited thereto.

[0092] Reference Figure 3 , a common line CL is disposed on the gate insulating layer 113. The common line CL is used to apply a common voltage to the plurality of sub-pixels SPX. The common line CL may be formed of the same material as the gate electrode 151 of the transistor 150, but is not limited thereto.

[0093] Reference Figure 2 and Figure 3 The pixel connection line 180 means a line electrically connecting a plurality of pixels PX disposed on the pixel substrate 111. The pixel connection line 180 is disposed on the pixel substrate 111 and the plurality of connection substrates 120.

[0094] The pixel connection line 180 includes a first pixel connection line 181 and a second pixel connection line 182. The first pixel connection line 181 and the second pixel connection line 182 are disposed between the plurality of pixel substrates 111. Specifically, the first pixel connection line 181 refers to a line extending in the X-axis direction between the plurality of pixel substrates 111 among the pixel connection lines 180. The second pixel connection line 182 refers to a line extending in the Y-axis direction between the plurality of pixel substrates 111 among the pixel connection lines 180.

[0095] The pixel connection line 180 may be formed of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo). Otherwise, the pixel connection line 180 may have a stacked structure of metal materials such as copper / molybdenum titanium (Cu / MoTi), titanium / aluminum / titanium (Ti / Al / Ti), etc., but is not limited thereto.

[0096] In a common organic light-emitting display device, various lines such as a plurality of gate lines and a plurality of data lines extend in a straight line and are arranged between a plurality of sub-pixels. In addition, a plurality of sub-pixels are connected to a single signal line. Therefore, in a common organic light-emitting display device, various lines such as a gate line, a data line, a high-potential pixel driving voltage line, and a reference voltage line extend continuously from one side of the organic light-emitting display device to the other side on a substrate.

[0097] In contrast, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, various lines such as a gate line, a data line, and a reference voltage line, which are formed in a straight line and are considered to be used in a common organic light-emitting display device, are provided only on the plurality of pixel substrates 111 and the plurality of external substrates 121. That is, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the lines formed in a straight line are provided only on the plurality of pixel substrates 111 and the plurality of external substrates 121.

[0098] In the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the pads on two adjacent pixel substrates 111 or one pixel substrate 111 and one external substrate 121 adjacent to each other may be connected by a pixel connection line 180 so as to connect the discontinuous lines on the pixel substrate 111 or the external substrate 121. That is, the pixel connection line 180 electrically connects the pads on the two adjacent pixel substrates 111 and the adjacent pixel substrates 111 and the external substrate 121. Therefore, the stretchable display device 100 according to the exemplary embodiment of the present disclosure may include a plurality of pixel connection lines 180 so as to electrically connect various lines such as a gate line, a data line, and a reference voltage line between the plurality of pixel substrates 111 and between the plurality of pixel substrates 111 and the plurality of external substrates 121. For example, the gate line may be provided on the plurality of pixel substrates 111 adjacent to each other in the X-axis direction, and the gate pads 171 may be provided at both ends of the gate line. In this case, the plurality of gate pads 171 on the plurality of pixel substrates 111 adjacent to each other in the X-axis direction may be connected to each other by the first pixel connection line 181 serving as the gate line. Therefore, the gate lines provided on the plurality of pixel substrates 111 and the first pixel connection line 181 provided on the external substrate 121 can be used as a single gate line. In addition, the lines extending in the X-axis direction (for example, the light emitting signal line, the low potential pixel driving voltage line, and the high potential pixel driving voltage line) among all the various lines that can be included in the stretchable display device 100 can also be electrically connected through the first pixel connection line 181 as described above.

[0099] Reference Figure 2 and Figure 3 , the first pixel connection line 181 can connect the pads on two pixel substrates 111 arranged side by side among the pads on the multiple pixel substrates 111 arranged adjacent to each other in the X-axis direction. The first pixel connection line 181 can be used as a gate line, a light emitting signal line, a high potential pixel driving voltage line or a low potential pixel driving voltage line, but is not limited thereto. For example, the first pixel connection line 181 can be used as a gate line and electrically connects the gate pads 171 on the two pixel substrates 111 arranged side by side in the X-axis direction. Therefore, as described above, the gate pads 171 on the multiple pixel substrates 111 arranged in the X-axis direction can be connected by the first pixel connection line 181 used as a gate line. A single gate signal can be transmitted to the gate pad 171.

[0100] Reference Figure 2, the second pixel connection line 182 can connect the pads on two pixel substrates 111 arranged side by side among the pads on the multiple pixel substrates 111 arranged adjacent to each other in the Y-axis direction. The second pixel connection line 182 can be used as a data line or a reference voltage line, but is not limited to this. For example, the second pixel connection line 182 can be used as a data line and electrically connects the data lines on the two pixel substrates 111 arranged side by side in the Y-axis direction. Therefore, as described above, the data lines on the multiple pixel substrates 111 arranged in the Y-axis direction can be connected by the multiple second pixel connection lines 182 used as data lines. A single data signal can be transmitted to the data line.

[0101] Reference Figure 1 The pixel connection line 180 may further include a line connecting the plurality of pixel substrates 111 and the pads on the plurality of external substrates 121 .

[0102] The first pixel connection line 181 contacts the upper surface and the side surface of the planarization layer 115 disposed on the pixel substrate 111, and may extend to the upper surface of the connection substrate 120. In addition, the second pixel connection line 182 contacts the upper surface and the side surface of the planarization layer 115 disposed on the pixel substrate 111, and may extend to the upper surface of the connection substrate 120. Subsequently, the arrangement of the first pixel connection line 181 and the second pixel connection line 182 and the resulting effects will be described in detail.

[0103] Reference Figure 3 The bank 116 is formed on the first connection pad 191, the second connection pad 192, the pixel connection line 180, and the planarization layer 115. The bank 116 is a member for distinguishing adjacent sub-pixels SPX from each other.

[0104] The levee 116 is arranged to cover the first connection pad 191 and a portion of the second pixel connection line 182 adjacent thereto or the second connection pad 192 and at least a portion of the first pixel connection line 181 adjacent thereto. The levee 116 may be formed of an insulating material. In addition, the levee 116 may include a black material. Since the levee 116 includes a black material, the levee 116 is used to hide the line visible through the display area AA. The levee 116 may be formed of, for example, a transparent carbon-based mixture. Specifically, the levee 116 may include carbon black, but is not limited thereto. The levee 116 may also be formed of a transparent insulating material.

[0105] Reference Figure 3, the LED 160 is disposed on the first connection pad 191 and the second connection pad 192. The LED 160 includes an n-type layer 161, an active layer 162, a p-type layer 163, an n-electrode 164, and a p-electrode 165. The LED 160 of the stretchable display device 100 according to the exemplary embodiment of the present disclosure has a flip chip structure in which the n-electrode 164 and the p-electrode 165 are formed on one surface thereof.

[0106] The n-type layer 161 may be formed by implanting n-type impurities into gallium nitride (GaN) having excellent crystallinity. The n-type layer 161 may be disposed on a separate base substrate formed of an emission material.

[0107] The active layer 162 is disposed on the n-type layer 161. The active layer 162 is a light emitting layer that emits light in the LED 160 and may be formed of a nitride semiconductor such as indium gallium nitride (InGaN). The p-type layer 163 is disposed on the active layer 162. The p-type layer 163 may be formed by injecting p-type impurities into gallium nitride (GaN).

[0108] The LED 160 according to the exemplary embodiment of the present disclosure may be manufactured by sequentially stacking an n-type layer 161, an active layer 162, and a p-type layer 163, and then etching predetermined regions of the layers to thereby form an n-electrode 164 and a p-electrode 165. In this case, the predetermined region is a space separating the n-electrode 164 and the p-electrode 165 from each other, and is etched to expose a portion of the n-type layer 161. In other words, the surface of the LED 160 on which the n-electrode 164 and the p-electrode 165 are to be disposed may not be flat, and may have different height levels.

[0109] The n-electrode 164 is disposed on the etched region, that is, on the n-type layer 161 exposed by etching. The n-electrode 164 may be formed of a conductive material. In addition, the p-electrode 165 is disposed on the non-etched region, that is, on the p-type layer 163. The p-electrode 165 may be formed of a conductive material. For example, the p-electrode 165 may be formed of the same material as the n-electrode 164.

[0110] The adhesive layer AD is disposed on the upper surfaces of the first and second connection pads 191 and 192 and between the first and second connection pads 191 and 192. Therefore, the LED 160 may be bonded to the first and second connection pads 191 and 192. In this case, the n-electrode 164 may be disposed on the second connection pad 192, and the p-electrode 165 may be disposed on the first connection pad 191.

[0111] The adhesive layer AD may be a conductive adhesive layer by dispersing conductive balls in an insulating base member. Therefore, when heat or pressure is applied to the adhesive layer AD, the conductive balls are electrically connected in a portion of the adhesive layer AD to which heat or pressure is applied, thereby having a conductive property. In addition, the region of the adhesive layer AD to which pressure is not applied may have an insulating property. For example, the n-electrode 164 is electrically connected to the second pixel connection line 182 through the adhesive layer AD, and the p-electrode 165 is electrically connected to the first pixel connection line 181 through the adhesive layer AD. That is, after the adhesive layer AD is applied to the first connection pad 191 and the second connection pad 192 by an inkjet method or the like, the LED 160 may be transferred to the adhesive layer AD. Then, the LED 160 may be pressurized and heated, thereby electrically connecting the first connection pad 191 to the p-electrode 165 and electrically connecting the second connection pad 192 to the n-electrode 164. However, other portions of the adhesive layer AD have insulating properties except for a portion of the adhesive layer AD disposed between the n-electrode 164 and the second connection pad 192 and a portion of the adhesive layer AD disposed between the p-electrode 165 and the first connection pad 191. In addition, the adhesive layer AD may be disposed on each of the first connection pad 191 and the second connection pad 192, respectively.

[0112] As described above, the stretchable display device 100 according to the exemplary embodiment of the present disclosure has a structure in which the LED 160 is provided on the lower substrate 110a provided with the transistor 150. Therefore, when the stretchable display device 100 is turned on, different voltage levels applied to each of the first connection pad 191 and the second connection pad 192 are transmitted to the n-electrode 164 and the p-electrode 165, so that the LED 160 emits light.

[0113] Reference Figure 3 , a stretchable upper substrate 110b is disposed on the bank 116, the LEDs 160 and the lower substrate 110a.

[0114] The stretchable upper substrate 110b is used to support various components disposed below the stretchable upper substrate 110b. The stretchable upper substrate 110b is a flexible substrate and may be formed of a bendable or stretchable insulating material. For example, the stretchable upper substrate 110b may be formed of a material having flexibility and may be formed of the same material as the lower substrate 110a, but is not limited thereto. Specifically, the stretchable upper substrate 110b may be formed by coating and hardening the material constituting the stretchable upper substrate 110b on the lower substrate 110a and the pixel substrate 111. Therefore, the stretchable upper substrate 110b may be disposed to contact the lower substrate 110a, the pixel substrate 111, the connecting substrate 120, and the pixel connecting line 180.

[0115] The stretchable upper substrate 110b is a flexible substrate and may be formed of a bendable or stretchable insulating material. The stretchable upper substrate 110b is a flexible substrate and may be reversibly expanded and contracted. In addition, the elastic modulus of the stretchable upper substrate 110b may be several MPa to several hundred MPa. In addition, the ductile fracture rate of the stretchable upper substrate 110b may be 100% or more. The thickness of the stretchable upper substrate 110b may be 10 μm to 1 mm, but is not limited thereto.

[0116] The stretchable upper substrate 110b may be formed of the same material as the lower substrate 110a. For example, the stretchable upper substrate 110b may be formed of a silicone rubber such as polydimethylsiloxane (PDMS) or an elastomer such as polyurethane (PU) and polytetrafluoroethylene (PTFE). Therefore, the stretchable upper substrate 110b may have flexibility. However, the material of the stretchable upper substrate 110b is not limited thereto.

[0117] In addition, despite Figure 3 Although not illustrated in the figure, a polarizing layer may be further provided on the stretchable upper substrate 110b. The polarizing layer polarizes light incident from the outside of the stretchable display device 100 and reduces reflection of external light. In addition, as an alternative to the polarizing layer, other optical films or the like may be provided on the stretchable upper substrate 110b.

[0118] In a conventional stretchable display device, a planarization layer formed of an organic insulating material does not cover the side surfaces of a plurality of inorganic insulating layers including a buffer layer, a gate insulating layer, and an interlayer insulating layer. Instead, the planarization layer is disposed on a plurality of inorganic insulating layers. Therefore, the connecting wire is disposed to contact the side surfaces of the plurality of inorganic insulating layers. However, when a patterning process (i.e., an etching process) is performed on the plurality of inorganic insulating layers, steps appear between the side surfaces of the plurality of inorganic insulating layers. That is, after the etching process, the side surfaces of the plurality of inorganic insulating layers have a relatively high inclination. Therefore, if the connecting wire is formed directly on the side surfaces of the plurality of inorganic insulating layers, the connecting wire will be short-circuited.

[0119] Therefore, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is provided to cover the side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114. Therefore, when the stretchable display device 100 is repeatedly stretched, the pixel connection line 180 can be suppressed from being peeled off from the side surfaces of the planarization layer 115 and the plurality of inorganic insulating layers. More specifically, the pixel connection line 180 formed of Cu or other low-resistance metal materials is provided on the upper surface and the side surface of the planarization layer 115 formed of an organic insulating material. Therefore, the adhesion strength of the lower portion of the pixel connection line 180 can be enhanced. Therefore, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is provided to cover the side surfaces of the plurality of inorganic insulating layers such as the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114 on the pixel substrate 111. Therefore, when the stretchable display device 100 is repeatedly stretched, the pixel connection line 180 can be suppressed from being peeled off from the planarization layer 115. Therefore, the reliability of the stretchable display device 100 can be improved. In addition, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is provided to cover the side surfaces of the plurality of inorganic insulating layers such as the buffer layer 112, the gate insulation layer 113 and the interlayer insulation layer 114 between the pixel substrate 111 and the planarization layer 115. Therefore, the planarization layer 115 can compensate for the steps between the side surfaces of the buffer layer 112, the gate insulation layer 113 and the interlayer insulation layer 114. That is, the planarization layer 115 is provided to cover the upper surface and the side surface of the buffer layer 112, the gate insulation layer 113 and the interlayer insulation layer 114. In addition, the inclination angle of the side surface of the planarization layer 115 can be smaller than the inclination angle of the side surface of the buffer layer 112, the gate insulation layer 113 and the interlayer insulation layer 114. That is, the side surface of the planarization layer 115 may have a slope that is gentler than the slopes of the side surfaces of the interlayer insulating layer 114, the side surfaces of the gate insulating layer 113, and the side surfaces of the buffer layer 112. Therefore, the pixel connection line 180 in contact with the side surface of the planarization layer 115 is provided with a gentle slope. Therefore, when the pixel connection line 180 is formed, cracks in the pixel connection line 180 can be suppressed. In addition, when the stretchable display device 100 is stretched, stress generated in the pixel connection line 180 can be reduced. In addition, rupture in the pixel connection line 180 or peeling of the pixel connection line 180 from the side surface of the planarization layer 115 can be suppressed.

[0120] In addition, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the pixel connection line 180 may have the same shape as the second substrate 120, and thus may have a sine wave shape. Therefore, compared with the case where the pixel connection line 180 has a straight line shape, the resistance of the pixel connection line 180 may be increased. Therefore, copper (Cu) with low resistance among various metal materials that can be used for the line may be used in the pixel connection line 180 to reduce the resistance of the pixel connection line 180. However, when Cu or other low-resistance metal materials are formed on the inorganic insulating layer, the adhesion strength between the metal material and the inorganic insulating layer may be problematic. That is, the adhesion strength of Cu or other low-resistance metal materials is small relative to the adhesion strength of the inorganic insulating layer. Therefore, if the pixel connection line 180 is disposed in contact with the side portions of a plurality of inorganic insulating layers such as the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114, the pixel connection line 180 may be peeled off from the side surfaces of the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114 when the stretchable display device 100 is stretched. Therefore, the reliability of the stretchable display device 100 may be reduced.

[0121] In addition, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the planarization layer 115 is disposed on a plurality of inorganic insulating layers such as the buffer layer 112, the gate insulating layer 113, and the interlayer insulating layer 114, and the transistor 150. Therefore, when the LED 160 is transferred, the components disposed under the planarization layer 115 can be protected. When the LED 160 is disposed on the stretchable display device 100, the LED 160 can be pressed from above the stretchable display device 100. In this case, the transistor 150, various circuits, and the connecting wire 180 disposed under the LED 160 may be damaged by pressure. Therefore, the planarization layer 115 is disposed on the buffer layer 112, the gate insulating layer 113, the interlayer insulating layer 114, and the transistor 150. Therefore, when the LED 160 is transferred, the stress caused by pressing can be reduced. Therefore, the damage of the transistor 150, various circuits, the connecting wire 180, etc. disposed under the planarization layer 115 can be reduced.

[0122] <Driving Method of Gate Driver>

[0123] Figure 4 is a block diagram for illustrating driving of a gate driver according to an exemplary embodiment of the present disclosure.

[0124] Reference Figure 4According to an exemplary embodiment of the present disclosure, the gate driver GD of the stretchable display device can be composed of a shift register, which includes receiving a high-potential gate drive voltage VGH and a low-potential gate drive voltage VGL and outputting the gate voltages Vout1, Vout2, Vout3 to Vout(n-1) and Vout(n) to the first to nth stages S1, S2, S3 to S(n-1) and Sn of the gate lines according to the gate clock voltage CLK.

[0125] As described above, each of the first to nth stages S1, S2, S3 to S(n-1), and Sn is independently disposed on the external substrate 121. However, the present disclosure is not limited thereto, and according to design requirements, a plurality of stages among the first to nth stages S1, S2, S3 to S(n-1), and Sn may be disposed on one external substrate 121 having an island shape.

[0126] In addition, the above-mentioned gating clock voltage CLK may include a plurality of gating clock voltages of different phases. For example, the gating clock voltage CLK may include a first gating clock voltage and a second gating clock voltage, and the phase of the first gating clock voltage is opposite to the phase of the second gating clock voltage. However, the present disclosure is not limited thereto, and the phase and quantity of the gating clock voltage CLK may be changed differently according to driving needs.

[0127] Therefore, the first stage S1 receives the gate start signal VST and outputs the first gate voltage Vout1 using the gate clock voltage CLK. Thereafter, the second stage S2 outputs the second gate voltage using the gate clock voltage CLK and the first gate voltage Vout1 output from the first stage S1. Thereafter, the third stage S3 to the nth stage Sn sequentially output the third gate voltage Vout3 to the nth gate voltage Vout(n) using the gate clock voltage CLK and the gate voltages Vout2 to Vout(n-1) output from the previous stages S2 to S(n-1).

[0128] <Gate Driver and Power Supply Unit>

[0129] Figure 5A and 5B yes Figure 1 An enlarged plan view of area Y illustrated in FIG. Figure 6 It is along Figure 5A A cross-sectional view taken along line VI-VI';

[0130] Reference Figure 5A , a gate driver GD, a power supply unit PS, and a plurality of power supply lines PSL1 to PSL7 may be formed on an external substrate 121 disposed in the non-display area NA.

[0131] Specifically, the gate driver GD is disposed at one side of the power supply unit PS in the X-axis direction. Then, the gate driver GD receives a plurality of powers from the power supply unit PS and outputs a gate voltage to the first sub-pixel connection line 181a as a gate line.

[0132] Furthermore, a plurality of power supply lines PSL1 to PSL7 extend along the X-axis and overlap with the power supply unit PS. Therefore, a plurality of power supply lines PSL1 to PSL7 are connected to the power supply unit PS through contact holes to transmit a plurality of voltages to the gate driver GD and a plurality of pixels PX. The gate power supply unit GPSa (also referred to herein as the gate power supply circuit GPSa) and the pixel power supply unit PPS (also referred to herein as the pixel power supply circuit PPS) may include any circuits, features, components, assemblies of electronic components, etc. configured to perform various operations of the gate power features and pixel power features as described herein. In some embodiments, the gate power supply unit GPSa and the pixel power supply unit PPS may be included in or implemented by a processing circuit, such as a microprocessor, a microcontroller, an integrated circuit, a chip, a microchip, etc.

[0133] In addition, the power supply unit PS may include a gate power supply unit GPSa which applies a gate clock voltage and a gate driving voltage to the gate driver GD, and a pixel power supply unit PPS which applies a pixel driving voltage to each of the plurality of pixels PX.

[0134] exist Figure 5A In the embodiment, the gate power supply unit GPSa is disposed at one side of the pixel power supply unit PPS in the X-axis direction. That is, in the X-axis direction, the pixel power supply unit PPS, the gate power supply unit GPSa, and the gate driver GD may be sequentially disposed.

[0135] The pixel power supply unit PPS applies a high potential pixel driving voltage and a low potential pixel driving voltage to each of the plurality of pixels PX disposed in the display area AA. That is, the pixel power supply unit PPS may include a first sub-pixel power supply unit PPS1 that applies a low potential pixel driving voltage to each of the plurality of pixels PX and a second sub-pixel power supply unit PPS2 that applies a high potential pixel driving voltage to each of the plurality of pixels PX. Figure 5A In the embodiment, the second sub-pixel power supply unit PPS2 is disposed at one side of the first sub-pixel power supply unit PPS1 in the X-axis direction.

[0136] In addition, the pixel power supply unit PPS is connected to the pixel power connection line PCL, and not only receives the high potential pixel driving voltage and the low potential pixel driving voltage but also supplies the high potential pixel driving voltage and the low potential pixel driving voltage to another pixel power supply unit PPS.

[0137] Another pixel power supply unit PPS as described above means a separate pixel power supply unit PPS formed on another external substrate 121 adjacent thereto.

[0138] Specifically, the first sub-pixel power supply unit PPS1 is connected to the first sub-pixel power connection line PCL1. Specifically, a plurality of first sub-pixel power connection lines PCL1 are spaced apart in the Y-axis direction. In addition, the first sub-pixel power connection line PCL1 extends in the Y-axis direction and electrically connects a plurality of first sub-pixel power supply units PPS1 spaced apart from each other. Therefore, the first sub-pixel power supply unit PPS1 may receive a low potential pixel driving voltage through the first sub-pixel power connection line PCL1, or may supply a low potential pixel driving voltage to another first sub-pixel power supply unit PPS1 through the first sub-pixel power connection line PCL1.

[0139] In addition, the second sub-pixel power supply unit PPS2 is connected to the second sub-pixel power connection line PCL2. Specifically, the plurality of second sub-pixel power supply units PPS2 are also spaced apart in the Y-axis direction. The second sub-pixel power connection line PCL2 also extends in the Y-axis direction and electrically connects the plurality of second sub-pixel power supply units PPS2. Therefore, the second sub-pixel power supply unit PPS2 can receive a high potential pixel driving voltage through the second sub-pixel power connection line PCL2, or can supply the high potential pixel driving voltage to another second sub-pixel power supply unit PPS2 through the second sub-pixel power connection line PCL2.

[0140] In this regard, the pixel power supply unit PPS is formed on the external substrate 121 which is a rigid substrate and is not stretched, and the pixel power connection line PCL is formed on the lower substrate 110 a which is a stretchable flexible substrate.

[0141] Therefore, the plurality of pixel power connection lines PCL may have a curved shape such that they are stretched. Figure 5A As illustrated in FIG. 1 , the plurality of pixel power connection lines PCL may have a sine wave shape. However, the shape of the plurality of pixel power connection lines PCL is not limited thereto. The plurality of pixel power connection lines PCL may have various shapes. For example, the plurality of pixel power connection lines PCL may extend in a zigzag manner, or a plurality of rhombus-shaped substrates may extend by being connected to each other at their vertices. Figure 5AThe number and shape of the plurality of pixel power connection lines PCL shown in FIG. 1 are provided by way of example. The number and shape of the plurality of pixel power connection lines PCL may be different according to the design thereof.

[0142] However, when the plurality of pixel power connection lines PCL have a curved shape, the entire length of the plurality of pixel power connection lines PCL increases. Therefore, the resistance of the plurality of pixel power connection lines PCL increases, thereby causing the IR of the pixel driving voltage to drop. As a result, a defect may occur that the plurality of pixels PX do not achieve the desired gradation.

[0143] Therefore, each of the pixel power supply units PPS formed on the external substrate 121 as a rigid substrate may be configured in a plate shape.

[0144] That is, the width of the plate-shaped pixel power supply unit PPS may be greater than the width of the pixel power connection line PCL. Figure 5A , four first subpixel power connection lines PCL1 may be connected to the first subpixel power supply unit PPS1. However, the number of first subpixel power connection lines PCL1 connected to the first subpixel power supply unit PPS1 is not limited thereto and may be variously modified according to design requirements.

[0145] Since the width of the plate-shaped pixel power supply unit PPS is greater than the width of the pixel power connection line PCL, the resistance of the plate-shaped pixel power supply unit PPS can be lower than the resistance of the pixel power connection line PCL. Therefore, the degree of IR drop in the pixel driving voltage can be reduced. Therefore, by configuring the pixel power supply unit PPS into a plate shape, the pixel driving voltage can reach the target voltage, so that multiple pixels PX can achieve gradual change normally.

[0146] As described above, a low potential pixel driving voltage may be charged in the first sub-pixel power supply unit PPS1 , and a high potential pixel driving voltage may be charged in the second sub-pixel power supply unit PPS2 .

[0147] In addition, the first sub-pixel power supply unit PPS1 can supply the low potential pixel driving voltage to the second sub-pixel connection line 181b as the low potential pixel driving voltage line through the first power line PSL1. Specifically, the first sub-pixel power supply unit PPS1 can be electrically connected to the first power line PSL1 through the contact hole, and the first power line PSL1 can be connected to the second sub-pixel connection line 181b. Therefore, the low potential pixel driving voltage charged in the first sub-pixel power supply unit PPS1 can be transmitted to the second sub-pixel connection line 181b and supplied to the plurality of pixels PX.

[0148] In addition, the second sub-pixel power supply unit PPS2 can supply the high potential pixel driving voltage to the third sub-pixel connection line 181c as the high potential pixel driving voltage line through the second power line PSL2. Specifically, the second sub-pixel power supply unit PPS2 can be electrically connected to the second power line PSL2 through the contact hole, and the second power line PSL2 can be connected to the third sub-pixel connection line 181c. Therefore, the high potential pixel driving voltage charged in the second sub-pixel power supply unit PPS2 can be transmitted to the third sub-pixel connection line 181c and supplied to the plurality of pixels PX.

[0149] The gate power supply unit GPSa applies a gate clock voltage, a high potential pixel driving voltage, and a low potential gate driving voltage to the gate driver GD set in the non-display area NA. That is, the gate power supply unit GPSa may include a first sub-gate power supply unit GPSa1 for applying a first gate clock voltage to the gate driver GD, a second sub-gate power supply unit GPSa2 for applying a second gate clock voltage to the gate driver GD, a third sub-gate power supply unit GPSa3 for applying a low potential gate driving voltage to the gate driver GD, and a fourth sub-gate power supply unit GPSa4 for applying a high potential gate driving voltage to multiple gate drivers GD. Figure 5A In the embodiment, the first to fourth sub-gate power supply units GPSa1 to GPSa4 may be sequentially disposed in the X-axis direction.

[0150] In addition, the gate power supply unit GPSa is connected to the gate power connection line GCL, and not only receives the gate clock voltage, the high potential gate drive voltage and the low potential gate drive voltage, but also supplies the gate clock voltage, the high potential gate drive voltage and the low potential gate drive voltage to another gate power supply unit GPSa.

[0151] The other gate power supply unit GPSa as described above is a separate gate power supply unit GPSa formed on the other external substrate 121 adjacent thereto.

[0152] Specifically, the first sub-gating power supply unit GPSa1 is connected to the first sub-gating power connection line GCL1. Specifically, a plurality of first sub-gating power supply units GPSa1 are spaced apart in the Y-axis direction, and the first sub-gating power connection line GCL1 extends in the Y-axis direction and electrically connects a plurality of first sub-gating power supply units GPSa1. Therefore, the first sub-gating power supply unit GPSa1 receives the first gating clock voltage through the first sub-gating power connection line GCL1, or supplies the first gating clock voltage to another first sub-gating power supply unit GPSa1 through the first sub-gating power connection line GCL1.

[0153] In addition, the second sub-gating power supply unit GPSa2 is connected to the second sub-gating power connection line GCL2. Specifically, the plurality of second sub-gating power supply units GPSa2 are also spaced apart in the Y-axis direction, and the second sub-gating power connection line GCL2 extends in the Y-axis direction and electrically connects the plurality of second sub-gating power supply units GPSa2. Therefore, the second sub-gating power supply unit GPSa2 receives the second gating clock voltage through the second sub-gating power connection line GCL2, or supplies the second gating clock voltage to another second sub-gating power supply unit GPSa2 through the second sub-gating power connection line GCL2.

[0154] In addition, the third sub-gating power supply unit GPSa3 is connected to the third sub-gating power connection line GCL3. Specifically, the plurality of third sub-gating power supply units GPSa3 are also spaced apart in the Y-axis direction, and the third sub-gating power connection line GCL3 extends in the Y-axis direction and electrically connects the plurality of third sub-gating power supply units GPSa3. Therefore, the third sub-gating power supply unit GPSa3 receives the low potential gating driving voltage through the third sub-gating power connection line GCL3, or supplies the low potential gating driving voltage to another third sub-gating power supply unit GPSa3 through the third sub-gating power connection line GCL3.

[0155] In addition, the fourth sub-gating power supply unit GPSa4 is connected to the fourth sub-gating power connection line GCL4. Specifically, a plurality of fourth sub-gating power supply units GPSa4 are also spaced apart in the Y-axis direction, and the fourth sub-gating power connection line GCL4 extends in the Y-axis direction and electrically connects a plurality of fourth sub-gating power supply units GPSa4. Therefore, the fourth sub-gating power supply unit GPSa4 receives a high potential gating driving voltage through the fourth sub-gating power connection line GCL4, or supplies a high potential gating driving voltage to another fourth sub-gating power supply unit GPSa4 through the fourth sub-gating power connection line GCL4.

[0156] In this regard, the gate power unit GPSa is formed on the external substrate 121 which is a rigid substrate and thus is not stretched, while the gate power connection line GCL is formed on the lower substrate 110a which is a stretchable flexible substrate.

[0157] Therefore, the plurality of gate power connection lines GCL may have a bent shape such that they are stretched. Figure 5A As illustrated in FIG. 1 , the plurality of gate power connection lines GCL may have a sine wave shape. However, the shape of the plurality of gate power connection lines GCL is not limited thereto. The plurality of gate power connection lines GCL may have various shapes. For example, the plurality of gate power connection lines PCL may extend in a zigzag manner, or a plurality of diamond-shaped substrates may extend by being connected to each other at their vertices. In addition, Figure 5AThe number and shape of the plurality of gate power connection lines GCL shown in FIG. 1 are provided by way of example. The number and shape of the plurality of gate power connection lines GCL may be different according to the design thereof.

[0158] In addition, each of the gate power supply units GPSa formed on the external substrate 121 as a rigid substrate may be configured in a plate shape.

[0159] That is, the width of the plate-shaped gate power supply unit GPSa may be greater than the width of the gate power connection line GCL. Figure 5A , four first sub gate power connection lines GCL1 may be connected to the first sub gate power supply unit GPSa1. However, the number of first sub gate power connection lines GCL1 connected to the first sub gate power supply unit GPSa1 is not limited thereto and may be variously modified according to design requirements.

[0160] Since the width of the plate-shaped gate power supply unit GPSa is greater than the width of the gate power connection line GCL, the resistance of the plate-shaped gate power supply unit GPSa can be lower than the resistance of the gate power connection line GCL. Therefore, the degree of IR drop occurring in the gate drive voltage can be reduced. Therefore, by configuring the gate power supply unit GPSa in a plate shape, the gate drive voltage can reach the target voltage.

[0161] As described above, the first selection clock voltage can be charged into the first sub-selection power supply unit GPSa1, the second selection clock voltage can be charged into the second sub-selection power supply unit GPSa2, the low potential selection drive voltage can be charged into the third sub-selection power supply unit GPSa3, and the high potential selection drive voltage can be charged into the fourth sub-selection power supply unit GPSa4.

[0162] In addition, the first sub-gating power supply unit GPSa1 can supply the first gating clock voltage to the gate driver GD through the third power line PSL3. Specifically, the first sub-gating power supply unit GPSa1 can be electrically connected to the third power line PSL3 through the contact hole, and the third power line PSL3 can be connected to the gate driver GD through the contact hole. Therefore, the first gating clock voltage charged in the first sub-gating power supply unit GPSa1 can be supplied to the gate driver GD.

[0163] In addition, the second sub-gating power supply unit GPSa2 can supply the second gating clock voltage to the gating driver GD through the fourth power line PSL4. Specifically, the second sub-gating power supply unit GPSa2 can be electrically connected to the fourth power line PSL4 through the contact hole, and the fourth power line PSL4 can be connected to the gating driver GD through the contact hole. Therefore, the second gating clock voltage charged in the second sub-gating power supply unit GPSa2 can be supplied to the gating driver GD.

[0164] In addition, the third sub-gating power supply unit GPSa3 can supply the low potential gating drive voltage to the gating driver GD through the fifth power line PSL5. Specifically, the third sub-gating power supply unit GPSa3 can be electrically connected to the fifth power line PSL5 through the contact hole, and the fifth power line PSL5 can be connected to the gating driver GD through the contact hole. Therefore, the low potential gating drive voltage charged in the third sub-gating power supply unit GPSa3 can be supplied to the gating driver GD.

[0165] In addition, the fourth sub-gating power supply unit GPSa4 can supply the fourth gating clock voltage to the gating driver GD through the sixth power line PSL6. Specifically, the fourth sub-gating power supply unit GPSa4 can be electrically connected to the sixth power line PSL6 through the contact hole, and the sixth power line PSL6 can be connected to the gating driver GD through the contact hole. Therefore, the high potential gating drive voltage charged in the fourth sub-gating power supply unit GPSa4 can be supplied to the gating driver GD.

[0166] In addition, the gate driver GD can output a gate voltage to a gate output line GOL, and apply the gate voltage to another gate driver GD of the next stage. Specifically, the gate driver GD can be electrically connected to the seventh power line PSL7 through a contact hole, and the seventh power line PSL7 can be electrically connected to the gate output line GOL. Therefore, the gate voltage output from the gate driver GD can be applied to another gate driver GD of the next stage.

[0167] Reference Figure 5A and Figure 6 , the connection substrate 120 may be disposed under the plurality of pixel power link lines PCL, the plurality of gate power link lines GCL, and the gate output lines GOL.

[0168] In addition, the connection substrate 120 may have the same shape as those of the plurality of pixel power link lines PCL, the plurality of gate power link lines GCL, and the gate output lines GOL.

[0169] Therefore, the plurality of connection substrates 120 also have a curved shape. Figure 5A As shown in , a plurality of connection substrates 120 may have a sine wave shape. However, the shape of a plurality of connection substrates 120 is not limited thereto. A plurality of connection substrates 120 may have various shapes. For example, a plurality of connection substrates 120 may extend in a zigzag manner, or a plurality of rhombus-shaped connection substrates 120 may extend by being connected to each other at their vertices.

[0170] As described above, the connection substrate 120 is disposed under the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output line GOL, so that the tensile stress received by the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output line GOL when the stretchable display device 100 is stretched can be reduced. Therefore, even if the stretchable display device 100 is repeatedly stretched, no cracks occur in the plurality of pixel power connection lines PCL, the plurality of gate power connection lines GCL, and the gate output line GOL, so that the pixel driving voltage, the gate clock voltage, and the gate driving voltage can be stably supplied.

[0171] In addition, refer to Figure 5B In some embodiments, a connection substrate may be disposed between a plurality of gate drivers GD.

[0172] That is, the connection substrate 120 may be disposed in all regions between the plurality of external substrates 121. Therefore, the connection substrate 120 may be uniformly disposed between the plurality of external substrates 121.

[0173] Therefore, the stretchable display device 100 according to the exemplary embodiment of the present disclosure can disperse the tensile stress by uniformly disposing the connection substrate 120 between the plurality of external substrates 121. As a result, cracks can be prevented from occurring during the stretching of the stretchable display device 100.

[0174] In the following, refer to Figure 6 , the stacking relationship and connection relationship between multiple power lines and the power supply unit will be described.

[0175] Reference Figure 6 , the external substrate 121 and the connection substrate are disposed on the lower substrate.

[0176] Both the external substrate 121 and the connection substrate 120 may be formed of the same material and by the same process.

[0177] That is, each of the external substrate 121 and the connection substrate may be formed of a flexible plastic material such as polyimide (PI), polyacrylate, polyacetate, etc. However, not limited thereto, each of the external substrate 121 and the connection substrate may be formed of other materials.

[0178] In addition, a buffer layer 112 may be provided on the external substrate 121. The buffer layer 112 may be formed of an insulating material, and may be composed of a single inorganic layer or a plurality of inorganic layers formed of, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), etc. However, depending on the structure or characteristics of the stretchable display device 100, the buffer layer 112 may be omitted.

[0179] A plurality of power supply lines PSL1 to PSL7 may be formed on the buffer layer 112. For example, Figure 6 As illustrated in FIG, the sixth power line PSL6 and the seventh power line PSL7 may be disposed on the buffer layer 112. The sixth power line PSL6 and the seventh power line PSL7 are disposed to be spaced apart on the same layer as the source 153 and the drain 154. In addition, the plurality of power lines PSL1 to PSL7 may be formed of the same material as the source 153 and the drain 154. That is, the plurality of power lines PSL1 to PSL7 may be formed of any of various metal materials (for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy of two or more thereof, or a multilayer thereof), but is not limited thereto.

[0180] In some embodiments, the plurality of power lines PSL1 to PSL7 may be spaced apart from the gate 151 and formed of the same material as the gate 151 .

[0181] Then, a planarization layer 115 is formed on the plurality of power supply lines PSL1 to PSL7. The planarization layer 115 planarizes the upper portion of the transistor 150. The planarization layer 115 may be composed of a single layer or a plurality of layers and may be formed of an organic material. Therefore, the planarization layer 115 may be referred to as an organic insulating layer. For example, the planarization layer 115 may be formed of an acrylic organic material, but is not limited thereto.

[0182] In addition, the gate output line GOL, the plurality of gate power connection lines GCL, and the plurality of pixel power connection lines GCL may be disposed on the connection substrate 120. For example, Figure 6 As illustrated in FIG. 1 , the fourth sub gate power link line GCL4 may be disposed on the connection substrate 120 .

[0183] In addition, the gate power supply unit GPSa and the pixel power supply unit PPS may be disposed on the planarization layer 115. Figure 6 As illustrated in FIG. 1 , the fourth sub gate power supply unit GPSa4 may be disposed on the planarization layer 115 .

[0184] In addition, the gate power supply unit GPSa and the pixel power supply unit PPS may be formed of the same material as the gate output line GOL, the plurality of gate power connection lines GCL, and the plurality of pixel power connection lines PCL, and may be electrically connected thereto. In addition, the gate power supply unit GPSa and the pixel power supply unit PPS may be electrically connected to the plurality of power supply lines PSL1 to PSL7 through contact holes.

[0185] For example, Figure 6As illustrated in FIG. 1 , the fourth sub-gating power connection line GCL4 is formed of the same material as the fourth sub-gating power supply unit GPSa4 and can be electrically connected thereto. In addition, the fourth sub-gating power supply unit GPSa4 can be electrically connected to the sixth power supply line PSL6 through a contact hole. Therefore, the high potential gating drive voltage charged in the fourth sub-gating power supply unit GPSa4 can be supplied to the gating driver GD.

[0186] As described above, in the stretchable display device 100 according to the exemplary embodiment of the present disclosure, the gate driver GD and the power supply unit PS are disposed on the external substrate 121, and the gate output line GOL, the gate power connection line GCL and the pixel power line PSL are disposed between the external substrates 121.

[0187] Therefore, each of the plurality of gate drivers GD outputs a gate voltage to the plurality of pixels PX disposed on the same line, and the plurality of power supply units PS outputs a pixel driving voltage to the plurality of pixels PX.

[0188] That is, the stretchable display device 100 according to the exemplary embodiment of the present disclosure includes the gate driver GD and the power supply unit PS, which may be stretchable, to thereby drive the plurality of pixels PX.

[0189] Hereinafter, a stretchable display device according to another exemplary embodiment of the present disclosure will be described. The stretchable display device according to another exemplary embodiment of the present disclosure is different from the stretchable display device according to the exemplary embodiment of the present disclosure only in terms of the overlapping relationship between the gate driver GD and the power supply unit PS. Moreover, the stretchable display device according to another exemplary embodiment of the present disclosure is the same as the stretchable display device according to the exemplary embodiment of the present disclosure in terms of the technical characteristics of the gate output line GOL, the gate power connection line GCL, and the pixel power supply line PSL. Therefore, the overlapping relationship between the gate driver GD and the power supply unit PS of the stretchable display device according to another embodiment of the present disclosure will be described in detail below.

[0190] <Overlap of gate driver and power supply unit>

[0191] Figure 7 is an enlarged plan view of a non-display area of ​​a stretchable display device according to another exemplary embodiment of the present disclosure. Figure 8 It is along Figure 7 A cross-sectional view taken along line VIII-VIII'. Fig. 9 It is along Figure 8 A cross-sectional view taken along line IX-IX'.

[0192] In the stretchable display device 200 according to another exemplary embodiment of the present disclosure, the power supply unit PS and the gate driver GD may overlap.

[0193] like Figure 7 As illustrated in FIG. 1 , the gate power supply unit GPSb of the power supply unit PS may overlap with the gate driver GD. In addition, the gate power supply unit GPSb may be built in the gate driver GD.

[0194] Specifically, the gate power supply unit GPSb may include a first sub-gate power supply unit GPSb1 for applying a first gate clock voltage to the gate driver GD, a second sub-gate power supply unit GPSb2 for applying a second gate clock voltage to the gate driver GD, a third sub-gate power supply unit GPSb3 for applying a low-potential gate drive voltage to the gate driver GD, and a fourth sub-gate power supply unit GPSb4 for applying a high-potential gate drive voltage to multiple gate drivers GD.

[0195] In addition, each of the first sub-gate power supply unit GPSb1, the second sub-gate power supply unit GPSb2, the third sub-gate power supply unit GPSb3 and the fourth sub-gate power supply unit GPSb4 can be formed in various ways so that they are electrically connected to the gate power connection line GCL and connected to the gate driver GD.

[0196] For this purpose, Figure 7 In the embodiment, each of the first sub gate power supply unit GPSb1, the second sub gate power supply unit GPSb2, the third sub gate power supply unit GPSb3 and the fourth sub gate power supply unit GPSb4 may be divided into a portion overlapping with the gate power connection line GCL and a portion overlapping with the gate driver GD.

[0197] For example, refer to Figure 7 and Figure 8 , the first sub-gating power supply unit GPSb1 can be electrically connected to the first sub-gating power connection line GCL1 through a plurality of contact holes on both sides thereof in the Y-axis direction. Therefore, the first sub-gating power supply unit GPSb1 receives the first gating clock voltage through the first sub-gating power connection line GCL1, or supplies the first gating clock voltage to another first sub-gating power supply unit GPSa1 through the first sub-gating power connection line GCL1.

[0198] In addition, the first sub gate power supply unit GPSb1 may be connected to the gate driver GD through a contact hole. Therefore, the first gate clock voltage charged in the first sub gate power supply unit GPSb1 may be supplied to the gate driver GD.

[0199] In the same manner, the second sub-gating power supply unit GPSb2 can be electrically connected to the second sub-gating power connection line GCL2 through a plurality of contact holes on both sides thereof in the Y-axis direction. Therefore, the second sub-gating power supply unit GPSb2 receives the second gating clock voltage through the second sub-gating power connection line GCL2, or supplies the second gating clock voltage to another second sub-gating power supply unit GPSa2 through the second sub-gating power connection line GCL2.

[0200] In addition, the second sub gate power supply unit GPSb2 may be connected to the gate driver GD through a contact hole. Therefore, the second gate clock voltage charged in the second sub gate power supply unit GPSb2 may be supplied to the gate driver GD.

[0201] In the same manner, the third sub-gating power supply unit GPSb3 can be electrically connected to the third sub-gating power connection line GCL3 through a plurality of contact holes on both sides in the Y-axis direction. Therefore, the third sub-gating power supply unit GPSb3 receives a low potential gating driving voltage through the third sub-gating power connection line GCL3, or supplies the low potential gating driving voltage to another third sub-gating power supply unit GPSa3 through the third sub-gating power connection line GCL3.

[0202] In addition, the third sub gate power supply unit GPSb3 may be connected to the gate driver GD through the contact hole. Therefore, the low potential gate driving voltage charged in the third sub gate power supply unit GPSb3 may be supplied to the gate driver GD.

[0203] In the same manner, the fourth sub-gating power supply unit GPSb4 can be electrically connected to the fourth sub-gating power connection line GCL4 through a plurality of contact holes on both sides thereof in the Y-axis direction. Therefore, the fourth sub-gating power supply unit GPSb4 receives a high potential gating driving voltage through the fourth sub-gating power connection line GCL4, or supplies the high potential gating driving voltage to another fourth sub-gating power supply unit GPSa4 through the fourth sub-gating power connection line GCL4.

[0204] In addition, the fourth sub gate power supply unit GPSb4 may be connected to the gate driver GD through the contact hole. Therefore, the high potential gate driving voltage charged in the fourth sub gate power supply unit GPSb4 may be supplied to the gate driver GD.

[0205] In addition, each of the first sub-gating power supply unit GPSb1, the second sub-gating power supply unit GPSb2, the third sub-gating power supply unit GPSb3, and the fourth sub-gating power supply unit GPSb4 may be formed of the same material as the source 153 and the drain 154. That is, each of the first sub-gating power supply unit GPSb1, the second sub-gating power supply unit GPSb2, the third sub-gating power supply unit GPSb3, and the fourth sub-gating power supply unit GPSb4 may be formed of any of various metal materials (for example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy of two or more thereof, or a multilayer thereof), but is not limited thereto.

[0206] In some embodiments, each of the first sub-gating power supply unit GPSb1, the second sub-gating power supply unit GPSb2, the third sub-gating power supply unit GPSb3, and the fourth sub-gating power supply unit GPSb4 can be disposed on the same layer as the gate 151, spaced apart from the gate 151, and can be formed of the same material as the gate 151.

[0207] As described above, the power supply unit PS and the gate driver GD may overlap each other. Therefore, the size of the non-display area NA provided with the power supply unit PS and the gate driver GD may be reduced. Therefore, in the stretchable display device 200 according to another embodiment of the present disclosure, the size of the frame area may be reduced, so that the size of the display area displaying the image may be relatively increased.

[0208] Next, refer to Figure 7 and Fig. 9 , the first sub-pixel power supply unit PPS1 can supply the low-potential pixel driving voltage to the second sub-pixel connection line 181b as the low-potential pixel driving voltage line through the contact portion CTP. The contact portion CTP may be formed on a layer different from the pixel power supply unit PPS and may overlap with the pixel power supply unit PPS. Specifically, the first sub-pixel power supply unit PPS1 may be electrically connected to the contact portion CTP through a plurality of contact holes, and the contact portion CTP may be connected to the second sub-pixel connection line 181b through another contact hole. Therefore, the low-potential pixel driving voltage charged in the first sub-pixel power supply unit PPS1 may be transmitted to the second sub-pixel connection line 181b and supplied to a plurality of pixels PX. That is, the first sub-pixel power supply unit PPS1 and the second sub-pixel connection line 181b may be connected to each other in a jumping structure through the contact portion CTP.

[0209] The contact portion CTP formed on the external substrate 121 as a rigid substrate may be configured in a plate shape. Fig. 9As shown in , the width of the plate-shaped contact portion CTP can be greater than the sum of the width of the first sub-pixel power supply unit PPS1 and the width of the second sub-pixel power supply unit PPS2. Therefore, the resistance of the plate-shaped contact portion CTP can be relatively low. Therefore, the degree of IR drop that occurs in the pixel driving voltage can be reduced. Therefore, by configuring the contact portion CTP into a plate shape, the pixel driving voltage can reach the target voltage, so that the plurality of pixels PX can achieve gradual change normally.

[0210] in addition, Figure 7 and Fig. 9 The contact portion CTP is illustrated as being formed of the same material as the source electrode 153 and the drain electrode 154 and formed on the same layer as the source electrode 153 and the drain electrode 154. However, the present disclosure is not limited thereto. The contact portion CTP may be disposed on the same layer as the gate electrode 151 and may be formed of the same material as the gate electrode 151, spaced apart from the gate electrode 151.

[0211] Exemplary embodiments of the present disclosure may also be described as follows:

[0212] According to one aspect of the present disclosure, a stretchable display device includes: a lower substrate, on which a display area for displaying an image and a non-display area adjacent to the display area are defined; a plurality of pixel substrates, the plurality of pixel substrates being arranged in the display area; a plurality of external substrates, the plurality of external substrates being arranged in the non-display area; a plurality of pixels, the plurality of pixels being arranged on the plurality of pixel substrates; and a plurality of gate drivers, the plurality of gate drivers being arranged on the plurality of external substrates and outputting gate voltages to the plurality of pixels. Therefore, even when the stretchable display device is stretched, the pixels can be driven normally.

[0213] The stretchable display device may further include a gate power supply unit which is disposed on the plurality of external substrates and supplies a gate clock voltage and a gate driving voltage to the plurality of gate drivers.

[0214] The gate power supply unit may have a plate shape.

[0215] The stretchable display device may further include a plurality of gate power connection lines disposed between the plurality of external substrates and electrically connected to the gate power supply unit.

[0216] The plurality of gate power connection lines may have a bent shape.

[0217] The stretchable display device may further include a connection substrate disposed under the plurality of gate power connection lines.

[0218] The plurality of gate drivers and the gate power supply unit may overlap each other.

[0219] The stretchable display device may further include a pixel power supply unit which is disposed on the plurality of external substrates and supplies a pixel driving voltage to each of the plurality of pixels.

[0220] The pixel power supply unit may have a plate shape.

[0221] The stretchable display device may further include a plurality of pixel power connection lines disposed between the plurality of external substrates and electrically connected to the pixel power supply unit.

[0222] The plurality of pixel power connection lines may have a bent shape.

[0223] The stretchable display device may further include a connection substrate disposed below the plurality of pixel power connection lines.

[0224] The pixel power supply unit may include a first sub-pixel power supply unit and a second sub-pixel power supply unit adjacent to the first sub-pixel power supply unit.

[0225] The first sub-pixel power supply unit may be electrically connected to the pixel connection line through a contact portion formed on a different layer from the pixel power supply unit.

[0226] The contact portion may overlap the pixel power supply unit and have a plate shape.

[0227] A width of the contact portion may be greater than a sum of a width of the first sub-pixel power supply unit and a width of the second sub-pixel power supply unit.

[0228] The plurality of gate drivers may be electrically connected to each other through a gate output line.

[0229] The stretchable display device may further include a connection substrate disposed between the plurality of gate drivers, the connection substrate having a bent shape.

[0230] According to another aspect of the present disclosure, a stretchable display device includes: a stretchable substrate, on which a display area for displaying an image and a non-display area adjacent to the display area are defined; a plurality of first rigid substrates, the plurality of first rigid substrates being arranged in the display area; a plurality of second rigid substrates, the plurality of second rigid substrates being arranged in the non-display area; a plurality of pixels, the plurality of pixels being arranged on the plurality of first rigid substrates; a plurality of gate drivers, the plurality of gate drivers being arranged on the plurality of second rigid substrates and including a plurality of transistors; and a plurality of power supply units, the plurality of power supply units being arranged on the plurality of second rigid substrates and connected to the plurality of gate drivers and the plurality of pixels. Therefore, even when the stretchable display device is stretched, the driving voltage can be supplied normally.

[0231] Each of the second rigid substrates may extend in one direction, and each of the plurality of gate drivers and each of the plurality of power supply units may be disposed adjacent to each other in the one direction.

[0232] The plurality of gate drivers are disposed more adjacent to the display area than the plurality of power supply units.

[0233] The plurality of power supply units may include a gate power supply unit that applies a gate clock voltage and a gate driving voltage to the gate driver, and a pixel power supply unit that applies a pixel driving voltage to each of the plurality of pixels.

[0234] The gate power supply unit is disposed more adjacent to the gate driver than the pixel power supply unit.

[0235] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be understood to fall within the scope of the present disclosure.

[0236] CROSS-REFERENCE TO RELATED APPLICATIONS

[0237] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0119067 filed on September 26, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. A stretchable display device, comprising: a lower substrate, on which a display area for displaying an image and a non-display area adjacent to the display area are defined; A plurality of pixel substrates, wherein the plurality of pixel substrates are arranged in the display area; a plurality of external substrates, the plurality of external substrates being disposed in the non-display area; a plurality of pixels, the plurality of pixels being arranged on the plurality of pixel substrates; a plurality of gate drivers disposed on the plurality of external substrates and outputting gate voltages to the plurality of pixels; as well as A plurality of power supply circuits are provided on the plurality of external substrates and connected to the plurality of gate drivers and the plurality of pixels.

2. The stretchable display device according to claim 1, wherein: The plurality of power supply circuits include a gate power supply circuit that is disposed on the plurality of external substrates and supplies a gate clock voltage and a gate driving voltage to the plurality of gate drivers.

3. The stretchable display device according to claim 2, wherein: The gate power supply circuit is implemented in a plate shape.

4. The stretchable display device according to claim 2, further comprising: A plurality of gate power connection lines are disposed between the plurality of external substrates and electrically connected to the gate power supply circuit.

5. The stretchable display device according to claim 4, wherein: The plurality of gate power connection lines have a bent shape.

6. The stretchable display device according to claim 4, further comprising: A connection substrate is disposed below the plurality of gate power connection lines.

7. The stretchable display device according to claim 2, wherein: The plurality of gate drivers and the gate power supply circuit overlap each other.

8. The stretchable display device according to claim 1, wherein: The plurality of power supply circuits include a pixel power supply circuit that is provided on the plurality of external substrates and supplies a pixel driving voltage to each of the plurality of pixels.

9. The stretchable display device according to claim 8, wherein: The pixel power supply circuit is implemented in a plate shape.

10. The stretchable display device according to claim 8, further comprising: A plurality of pixel power connection lines are provided between the plurality of external substrates and are electrically connected to the pixel power supply circuit.

11. The stretchable display device according to claim 10, wherein: The plurality of pixel power connection lines have a bent shape.

12. The stretchable display device according to claim 10, further comprising: A connection substrate is disposed below the plurality of pixel power connection lines.

13. The stretchable display device according to claim 8, in, The pixel power supply circuit includes a first sub-pixel power supply circuit and a second sub-pixel power supply circuit adjacent to the first sub-pixel power supply circuit. wherein the first sub-pixel power supply circuit is electrically connected to the pixel connection line through a contact portion formed on a layer different from that of the pixel power supply circuit, The contact portion overlaps with the pixel power circuit and is implemented in a plate shape.

14. The stretchable display device according to claim 13, wherein: The width of the contact portion is greater than the sum of the width of the first sub-pixel power supply circuit and the width of the second sub-pixel power supply circuit.

15. The stretchable display device according to claim 1, wherein: The plurality of gate drivers are electrically connected to each other through one or more gate output lines.

16. The stretchable display device according to claim 1, further comprising: A connection substrate is disposed between the plurality of gate drivers, the connection substrate having a bent shape.

17. A stretchable display device, comprising: A stretchable substrate, on which a display area for displaying an image and a non-display area adjacent to the display area are defined; a plurality of first rigid substrates, wherein the plurality of first rigid substrates are arranged in the display area; a plurality of second rigid substrates, wherein the plurality of second rigid substrates are disposed in the non-display area; a plurality of pixels, the plurality of pixels being disposed on the plurality of first rigid substrates; a plurality of gate drivers disposed on the plurality of second rigid substrates and comprising a plurality of transistors; as well as A plurality of power supply circuits are disposed on the plurality of second rigid substrates and connected to the plurality of gate drivers and the plurality of pixels.

18. The stretchable display device according to claim 17, in, Each of the second rigid substrates extends in one direction, and Each of the plurality of gate drivers and each of the plurality of power supply circuits are disposed adjacent to each other in the one direction.

19. The stretchable display device according to claim 18, wherein: The plurality of gate drivers are disposed more adjacent to the display area than the plurality of power supply circuits.

20. The stretchable display device according to claim 17, wherein: The plurality of power supply circuits include: a gate power supply circuit that applies a gate clock voltage and a gate drive voltage to the gate driver; and A pixel power supply circuit applies a pixel driving voltage to each of the plurality of pixels.

21. The stretchable display device according to claim 20, in, The gate power circuit is disposed more adjacent to the gate driver than the pixel power circuit.

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