Data processing method, device, system, computer-readable storage medium

Abstract

The present disclosure provides a data processing method, including: receiving an access request; determining a target object targeted by the access request based on the access request; determining an accessed state of the target object; and determining a response mode for the access request based on the accessed state; wherein, when it is determined that the response mode is the first response mode, obtaining the target object from a first storage unit; when it is determined that the response mode is the second response mode, obtaining the target object from at least a second storage unit, wherein the manner of obtaining the target object from the first storage unit is different from the manner of obtaining the target object from the second storage unit. The present disclosure also provides a data processing device, a data processing system, and a computer-readable storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and more particularly, to a data processing method, a data processing device, a data processing system, and a computer-readable storage medium. Background Art

[0002] In Internet applications, cache systems have been widely used. Through cache systems, data can be read and written quickly, thereby improving the performance of the system to a certain extent. Current cache systems include, for example, redis, memcache, etc. Most cache systems store data in slices, and when data is read or written, the data is accessed on the corresponding slice. In practical applications, especially during peak hours of data access, there are usually a large number of accesses to data, and there are even hot data that are frequently accessed.

[0003] In the process of implementing the concept of the present disclosure, the inventors found that there are at least the following problems in the prior art. When a large number of accesses are made to data in related technologies, it generally causes huge pressure on the background cache server. At the same time, since the cached data is generally stored as a byte array, most of it needs to be deserialized, resulting in a large consumption of server computing resources, thereby affecting the overall performance of the system and the user experience. Summary of the Invention

[0004] In view of this, the present disclosure provides an optimized data processing method, a data processing device, a data processing system, and a computer-readable storage medium.

[0005] One aspect of the present disclosure provides a data processing method, including: receiving an access request, determining, based on the access request, a target object targeted by the access request, determining an access status of the target object, and determining a response manner for the access request based on the access status. Wherein, when it is determined that the response manner is a first response manner, obtaining the target object from a first storage unit; when it is determined that the response manner is a second response manner, obtaining the target object from at least a second storage unit, and the manner of obtaining the target object from the first storage unit is different from the manner of obtaining the target object from the second storage unit.

[0006] According to an embodiment of the present disclosure, the target object can be accessed by multiple threads; the determining the access status of the target object includes: determining at least one target thread among the multiple threads, where the at least one target thread is a thread currently accessing the target object, and determining the access status of the target object, and the access status indicates a status in which the target object is accessed by the at least one target thread.

[0007] According to an embodiment of the present disclosure, when multiple target threads are included, the determining of the response manner for the access request includes: determining the response manner for the first target thread as the first response manner, where the first thread is the target thread that first accesses the target object among the multiple target threads, and determining the response manner for the second target thread as the second response manner, where the second thread is the target thread other than the first target thread among the multiple target threads.

[0008] According to an embodiment of the present disclosure, when one target thread is included, the determining of the response manner for the access request includes: determining the access order of the target thread accessing the target object, determining the response manner for the first access order as the first response manner, where the first access order indicates that the target thread first accesses the target object, and determining the response manner for the second access order as the second response manner, where the second access order is the access order of the target thread other than the first access order.

[0009] According to an embodiment of the present disclosure, obtaining the target object from at least the second storage unit includes: obtaining initial data from the second storage unit and performing deserialization processing on the initial data to obtain the target object.

[0010] According to an embodiment of the present disclosure, obtaining the target object from at least the second storage unit includes: determining the attribute information of the target object, based on the attribute information of the target object, dividing the target object into static data and dynamic data, obtaining the static data from the first storage unit, obtaining the dynamic data from the second storage unit, and performing deserialization processing on the dynamic data.

[0011] According to an embodiment of the present disclosure, the first storage unit includes a memory unit, and the second storage unit includes a cache unit.

[0012] Another aspect of the present disclosure provides a data processing device, including: a receiving module, a first determining module, a second determining module, and a third determining module. Among them, the receiving module receives an access request, the first determining module determines the target object targeted by the access request based on the access request, the second determining module determines the accessed state of the target object, and the third determining module determines the response manner for the access request based on the accessed state. Among them, when it is determined that the response manner is the first response manner, the target object is obtained from the first storage unit, and when it is determined that the response manner is the second response manner, the target object is obtained from at least the second storage unit, where the manner of obtaining the target object from the first storage unit is different from the manner of obtaining the target object from the second storage unit.

[0013] According to an embodiment of the present disclosure, a target object can be accessed by multiple threads; determining the accessed state of the target object includes: determining at least one target thread among the multiple threads, where the at least one target thread is a thread currently accessing the target object, and determining the accessed state of the target object, where the accessed state represents the state in which the target object is accessed by the at least one target thread.

[0014] According to an embodiment of the present disclosure, when there are multiple target threads, the third determination module includes: a first determination sub-module and a second determination sub-module. Among them, the first determination sub-module determines that the response method for the first target thread is the first response method, where the first thread is the target thread that first accesses the target object among the multiple target threads, and the second determination sub-module determines that the response method for the second target thread is the second response method, where the second thread is the target thread other than the first target thread among the multiple target threads.

[0015] According to an embodiment of the present disclosure, when there is one target thread, the third determination module includes: a third determination sub-module, a fourth determination sub-module, and a fifth determination sub-module. Among them, the third determination sub-module determines the access order of the target thread accessing the target object, the fourth determination sub-module determines that the response method for the first access order is the first response method, where the first access order represents the first time the target thread accesses the target object, and the fifth determination sub-module determines that the response method for the second access order is the second response method, where the second access order is the access order of the target thread other than the first access order.

[0016] According to an embodiment of the present disclosure, obtaining the target object from at least the second storage unit includes: obtaining initial data from the second storage unit and performing deserialization processing on the initial data to obtain the target object.

[0017] According to an embodiment of the present disclosure, obtaining the target object from at least the second storage unit includes: determining the attribute information of the target object, based on the attribute information of the target object, dividing the target object into static data and dynamic data, obtaining the static data from the first storage unit, obtaining the dynamic data from the second storage unit, and performing deserialization processing on the dynamic data.

[0018] According to an embodiment of the present disclosure, the first storage unit includes a memory unit, and the second storage unit includes a cache unit.

[0019] Another aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions that, when executed, are used to implement the method described above.

[0020] Another aspect of the present disclosure provides a computer program comprising computer-executable instructions that, when executed, are configured to implement the method as described above.

[0021] According to an embodiment of the present disclosure, it is possible to at least partially solve the problem in the related art that when a large amount of data is accessed, it generally causes a huge pressure on the background cache server. At the same time, since the cached data is generally stored as a byte array, most of it needs to be deserialized, resulting in a large consumption of server computing resources, thereby affecting the overall performance of the system and the user experience. Therefore, it is possible to achieve the technical effects of alleviating the server pressure and improving the data access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features and advantages of the present disclosure will become clearer. In the drawings:

[0023] Figure 1 Schematically shows the system architecture of a data processing method and a data processing system according to an embodiment of the present disclosure;

[0024] Figure 2 Schematically shows the flowchart of a data processing method according to an embodiment of the present disclosure;

[0025] Figure 3 Schematically shows the flowchart of determining a response mode according to an embodiment of the present disclosure;

[0026] Figure 4 Schematically shows the flowchart of determining a response mode according to another embodiment of the present disclosure;

[0027] Figure 5 Schematically shows the block diagram of a data processing apparatus according to an embodiment of the present disclosure;

[0028] Figure 6 Schematically shows the block diagram of a third determination module according to an embodiment of the present disclosure;

[0029] Figure 7 Schematically shows the block diagram of a third determination module according to another embodiment of the present disclosure; and

[0030] Figure 8 Schematically shows the block diagram of a computer system suitable for data processing according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted to have a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0034] In cases where expressions similar to "at least one of A, B, and C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but is not limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). In cases where expressions similar to "at least one of A, B, or C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include, but is not limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0035] Embodiments of the present disclosure provide a data processing method, including: receiving an access request, and based on the access request, determining a target object targeted by the access request. Then, determining the accessed state of the target object. Finally, based on the accessed state, determining a response manner for the access request. Among them, when it is determined that the response manner is the first response manner, obtaining the target object from the first storage unit, and when it is determined that the response manner is the second response manner, obtaining the target object from at least the second storage unit, where the manner of obtaining the target object from the first storage unit is different from the manner of obtaining the target object from the second storage unit.

[0036] Figure 1Schematically shows the system architecture of a data processing method and a data processing system according to an embodiment of the present disclosure. It should be noted that Figure 1 The shown is only an example of the system architecture to which the embodiments of the present disclosure can be applied, to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0037] As Figure 1 shown, the system architecture 100 according to this embodiment may include terminal devices 101, 102, 103, a network 104, and a server 105. The network 104 is used to provide a medium for communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, etc.

[0038] Users can use the terminal devices 101, 102, 103 to interact with the server 105 through the network 104 to receive or send messages, etc. Various communication client applications may be installed on the terminal devices 101, 102, 103, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social platform software, etc. (only as examples).

[0039] The terminal devices 101, 102, 103 may be various electronic devices having a display screen and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, and desktop computers, etc.

[0040] The server 105 may be a server providing various services, such as a background management server that supports websites browsed by users using the terminal devices 101, 102, 103 (only as an example). The background management server may analyze and process data such as user requests received, and feedback the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0041] It should be noted that the data processing method provided by the embodiments of the present disclosure can generally be executed by the server 105. Correspondingly, the data processing device provided by the embodiments of the present disclosure can generally be arranged in the server 105. The data processing method provided by the embodiments of the present disclosure can also be executed by a server or a server cluster different from the server 105 and capable of communicating with the terminal devices 101, 102, 103 and / or the server 105. Correspondingly, the data processing device provided by the embodiments of the present disclosure can also be arranged in a server or a server cluster different from the server 105 and capable of communicating with the terminal devices 101, 102, 103 and / or the server 105.

[0042] For example, the access requests obtained in the embodiments of the present disclosure can be stored in the terminal devices 101, 102, and 103, and the access requests are sent to the server 105 through the terminal devices 101, 102, and 103. The server 105 can determine the target object targeted by the access request based on the access request, determine the accessed state of the target object, and determine the response method for the access request based on the accessed state. Alternatively, the terminal devices 101, 102, and 103 can directly determine the target object targeted by the access request based on the access request, determine the accessed state of the target object, and determine the response method for the access request based on the accessed state. In addition, the access request can also be directly stored in the server 105, and the server 105 directly determines the target object targeted by the access request based on the access request, determines the accessed state of the target object, and determines the response method for the access request based on the accessed state.

[0043] It should be understood that Figure 1 the numbers of the terminal devices, networks, and servers in

[0044] Figure 2 are merely illustrative. According to the implementation requirements, there can be any number of terminal devices, networks, and servers.

[0045] As Figure 2 shown, the method includes operations S210 to S240.

[0046] In operation S210, an access request is received.

[0047] According to the embodiments of the present disclosure, data is generally stored in a storage system. Among them, the storage system can be, for example, a cache system or a memory system. After the storage system receives an access request from the outside, the storage system can respond to the access request and provide corresponding data.

[0048] In operation S220, based on the access request, determine the target object targeted by the access request.

[0049] In the embodiments of the present disclosure, for example, the access request has the object identifier of the target object to be accessed. After the storage system receives the access request, it can determine the target object targeted by the access request based on the object identifier.

[0050] In operation S230, determine the accessed state of the target object.

[0051] According to the embodiments of the present disclosure, for example, the target object can be accessed by multiple threads. First, determine at least one target thread among the multiple threads. Second, determine the accessed state of the target object. The accessed state represents the state in which the target object is accessed by at least one target thread.

[0052] Among them, the access status includes, for example, the number of target threads accessing the target object and the access order, etc. According to the access status, the response method for the access request can be determined.

[0053] In operation S240, based on the accessed status, determine the response method for the access request.

[0054] Among them, when it is determined that the response method is the first response method, obtain the target object from the first storage unit. When it is determined that the response method is the second response method, obtain the target object from at least the second storage unit. In other words, the second response method may include obtaining the target object from the second storage unit, or obtaining the target object from the first storage unit and the second storage unit.

[0055] According to an embodiment of the present disclosure, the first storage unit includes a memory unit, and the second storage unit includes a cache unit. According to an embodiment of the present disclosure, the method of obtaining the target object from the first storage unit is different from the method of obtaining the target object from the second storage unit.

[0056] For example, the target object can be directly obtained from the memory unit. In other words, the initial data is, for example, stored in the memory unit after being deserialized in advance.

[0057] For example, obtaining the target object from at least the second storage unit includes: obtaining the initial data from the second storage unit, and performing deserialization processing on the initial data to obtain the target object. That is, the initial data is directly stored in the cache unit. When obtaining the target object from the cache unit, it is necessary to perform deserialization processing on the initial object in the cache unit to obtain the required target object.

[0058] The present disclosure determines the response method through the accessed status of the target object. When the response method is the first response method, the target object can be directly obtained from the first storage unit without deserialization processing, which improves the data access efficiency and reduces the computing pressure on the server without deserialization processing, thereby improving the system performance of the server. When the response method is the second response method, the target object can be obtained from the second storage unit. This solution selectively obtains the target object from the first storage unit or the second storage unit through different response methods, reducing the pressure on the first storage unit or the second storage unit.

[0059] According to an embodiment of the present disclosure, the above operation S240 includes, for example, the following Figure 3 and Figure 4 description.

[0060] Figure 3 Schematically shows a flowchart of determining the response method according to an embodiment of the present disclosure.

[0061] As Figure 3 shown, when multiple target threads are included, the above operation S240 includes S241a to S242a.

[0062] In operation S241a, determine that the response method for the first target thread is the first response method, where the first target thread is the target thread that first accesses the target object among the multiple target threads.

[0063] According to an embodiment of the present disclosure, when multiple target threads access a target object, determine the target thread that first accesses as the first target thread, and obtain the target object from the memory unit.

[0064] In operation S242a, determine that the response method for the second target thread is the second response method, where the second target thread is the target thread other than the first target thread among the multiple target threads. For example, determine the target thread other than the first target thread among the multiple target threads as the second target thread, and the target object can be obtained from the cache unit. The reason why the second target thread obtains the target object from the cache unit is that the first target thread first obtains the target object from the memory unit, and the first target thread may have performed a modification operation on the target object in the memory unit. Therefore, the second target thread obtains the target object from the cache unit to ensure the accuracy of the obtained target object.

[0065] Specifically, when multiple target threads simultaneously obtain a target object, the reference count can be used to calculate the number of times the target object is referenced, which is mainly reflected at the spatial level (multiple target threads access simultaneously). For example, when each target thread among the multiple target threads performs business logic processing, add 1 to the reference count of the target object, and when the execution is completed, subtract 1 from the reference count of the target object. The object identifier and reference count of the target object can be associated and stored in the memory unit.

[0066] Among them, the reference count can reflect the current situation of the target object being accessed by the target thread. Therefore, it is possible to determine whether the current target thread is the first accessed thread through the reference count of the target object, which is convenient for determining the response method of the target thread.

[0067] Figure 4 Schematically shows a flowchart of determining a response method according to another embodiment of the present disclosure.

[0068] As Figure 4 shown, when one target thread is included, the above operation S240 may further include S241b to S242b.

[0069] In operation S241b, determine the access order of the target thread accessing the target object.

[0070] According to an embodiment of the present disclosure, when a target thread accesses a target object, the target thread may access the target object multiple times. Therefore, the access order of the target thread accessing the target object can be determined first.

[0071] In operation S242b, it is determined that the response manner for the first access order is the first response manner, and the first access order indicates that the target thread accesses the target object for the first time.

[0072] For example, when the target thread accesses the target object for the first time, the target object is obtained from the memory unit.

[0073] In operation S243b, it is determined that the response manner for the second access order is the second response manner, and the second access order is the access order of the target thread other than the first access order.

[0074] For example, when the target thread accesses subsequent times other than the first access, the target object can be obtained from the cache unit. Among them, for subsequent accesses other than the first access, the target object is obtained from the cache unit because when accessing for the first time, the target thread may have performed a modification operation on the target object in the memory unit. Therefore, for subsequent accesses other than the first access, the target object is obtained from the cache unit to ensure the accuracy of the obtained target object.

[0075] Specifically, when a target thread accesses a target object multiple times, the reference count can be used to calculate the number of times the target object is referenced, which is mainly reflected at the time level (a target thread accesses at different times). For example, when the target thread performs business logic processing each time, the reference count of the target object is incremented by 1, and when the execution of this time is completed, the reference count of the target object is decremented by 1. Among them, the object identifier and reference count of the target object can be associated and stored in the memory unit.

[0076] Among them, the reference count can reflect the number of times the target object is currently accessed by the target thread. Therefore, it can be determined whether the current access of the target thread is the first access through the reference count of the target object, which is convenient for determining the response manner according to the number of accesses of the target thread.

[0077] According to an embodiment of the present disclosure, obtaining the target object from at least the second storage unit includes: obtaining the target object from the second storage unit, or obtaining the target object from the first storage unit and the second storage unit. Specifically, it may include the following steps (1) to (4):

[0078] (1) Determine the attribute information of the target object.

[0079] According to an embodiment of the present disclosure, the target object may include multiple sub-objects, and each sub-object may have corresponding attribute information, for example.

[0080] (2) Divide the target object into static data and dynamic data based on the attribute information of the target object.

[0081] For example, divide multiple sub-objects into static data and dynamic data according to the attribute information. For example, the target object includes sub-object 1, sub-object 2, and sub-object 3. The attribute information of sub-object 1 and sub-object 2 is the first attribute information, and the first attribute information represents that sub-object 1 and sub-object 2 are style data. For example, style data is data that does not need to be modified or updated in real time. The attribute information of sub-object 3 is, for example, the second attribute information, and the second attribute information represents that sub-object 3 is data that needs to be modified or updated in real time. Therefore, sub-object 1 and sub-object 2 can be divided into static data, and sub-object 3 can be divided into dynamic data. Among them, static data can be stored in a memory unit, and dynamic data can be stored in a cache unit.

[0082] (3) Obtain static data from the first storage unit.

[0083] (4) Obtain dynamic data from the second storage unit and perform deserialization processing on the dynamic data.

[0084] According to the embodiments of the present disclosure, the target object read from the memory unit can be reset first (reset includes changing the data back to the data before modification), and then the target object can be split into static and dynamic parts according to the attribute information. The main purpose of the split is to reduce deserialization processing. Specifically, it can be determined whether deserialization of the target object is required based on the reference count of the target object. If deserialization is required, the target object can be further split into static data and dynamic data to specifically perform deserialization on the dynamic data. Since the static data does not change, the object in the memory unit can be directly read.

[0085] In the embodiments of the present disclosure, the target object can be preferentially read from the memory unit. Considering that the target object in the memory unit may change, a distributed coordination service can be used to monitor the changes of external objects to update the data in the memory unit in real time and synchronously update the data in the cache unit. In addition, the data stored in the memory unit may come from multiple system platforms, and the change mechanisms may not be unified. Therefore, the data of each data source type can be managed separately, that is, the memory unit is managed in a fine-grained manner according to the data source type.

[0086] According to the embodiments of the present disclosure, by preferentially reading the data in the memory unit, the data in the memory unit is ensured to be updated accurately and in real time. By splitting the target object into static and dynamic parts, deserialization processing is reduced, saving computing resources.

[0087] Figure 5A block diagram of a data processing device according to an embodiment of the present disclosure is schematically shown.

[0088] As Figure 5 shown, the data processing device 500 includes a receiving module 510, a first determination module 520, a second determination module 530, and a third determination module 540.

[0089] The receiving module 510 can be used to receive an access request. According to an embodiment of the present disclosure, the receiving module 510 can, for example, perform the operation S210 described above with reference to Figure 2 which will not be elaborated here.

[0090] The first determination module 520 can be used to determine a target object targeted by the access request based on the access request. According to an embodiment of the present disclosure, the first determination module 520 can, for example, perform the operation S220 described above with reference to Figure 2 which will not be elaborated here.

[0091] The second determination module 530 can be used to determine the accessed state of the target object.

[0092] According to an embodiment of the present disclosure, the target object can be accessed by multiple threads; determining the accessed state of the target object includes: determining at least one target thread among the multiple threads, where the at least one target thread is the thread currently accessing the target object, and determining the accessed state of the target object, and the accessed state indicates the state where the target object is accessed by at least one target thread.

[0093] According to an embodiment of the present disclosure, the second determination module 530 can, for example, perform the operation S230 described above with reference to Figure 2 which will not be elaborated here.

[0094] The third determination module 540 can be used to determine a response manner for the access request based on the accessed state.

[0095] According to an embodiment of the present disclosure, when it is determined that the response manner is the first response manner, the target object is obtained from the first storage unit, and when it is determined that the response manner is the second response manner, the target object is obtained at least from the second storage unit, where the manner of obtaining the target object from the first storage unit is different from the manner of obtaining the target object from the second storage unit.

[0096] According to an embodiment of the present disclosure, the third determination module 540 can, for example, perform the operation S240 described above with reference to Figure 2 which will not be elaborated here.

[0097] According to an embodiment of the present disclosure, obtaining the target object at least from the second storage unit includes: obtaining initial data from the second storage unit and performing deserialization processing on the initial data to obtain the target object.

[0098] According to an embodiment of the present disclosure, obtaining a target object from at least a second storage unit includes: determining attribute information of the target object, dividing the target object into static data and dynamic data based on the attribute information of the target object, obtaining the static data from a first storage unit, obtaining the dynamic data from the second storage unit, and performing deserialization processing on the dynamic data.

[0099] According to an embodiment of the present disclosure, the first storage unit includes a memory unit, and the second storage unit includes a cache unit.

[0100] Figure 6 A block diagram of a third determination module according to an embodiment of the present disclosure is schematically shown.

[0101] As Figure 6 shown, when multiple target threads are included, the third determination module 540 may include a first determination sub-module 541a and a second determination sub-module 542a.

[0102] The first determination sub-module 541a may be used to determine that the response manner for the first target thread is the first response manner, and the first thread is the target thread that first accesses the target object among the multiple target threads. According to an embodiment of the present disclosure, the first determination sub-module 541a may, for example, perform the operation S241a described above with reference to Figure 3 this, which will not be elaborated here.

[0103] The second determination sub-module 542a may be used to determine that the response manner for the second target thread is the second response manner, and the second thread is the target thread other than the first target thread among the multiple target threads. According to an embodiment of the present disclosure, the second determination sub-module 542a may, for example, perform the operation S242a described above with reference to Figure 3 this, which will not be elaborated here.

[0104] Figure 7 A block diagram of a third determination module according to another embodiment of the present disclosure is schematically shown.

[0105] As Figure 7 shown, when one target thread is included, the third determination module 540 may include a third determination sub-module 541b, a fourth determination sub-module 542b, and a fifth determination sub-module 543b.

[0106] The third determination sub-module 541b may be used to determine the access order of the target thread to access the target object. According to an embodiment of the present disclosure, the third determination sub-module 541b may, for example, perform the operation S241b described above with reference to Figure 4 this, which will not be elaborated here.

[0107] The fourth determination sub-module 542b may be used to determine that the response mode for the first access order is the first response mode, where the first access order indicates the first access of the target thread to the target object. According to an embodiment of the present disclosure, the fourth determination sub-module 542b may, for example, perform the operation S242b described above with reference to Figure 4 and will not be elaborated herein.

[0108] The fifth determination sub-module 543b may be used to determine that the response mode for the second access order is the second response mode, where the second access order is the access order of the target thread other than the first access order. According to an embodiment of the present disclosure, the fifth determination sub-module 543b may, for example, perform the operation S243b described above with reference to Figure 4 and will not be elaborated herein.

[0109] According to an embodiment of the present disclosure, any multiple of the modules, sub-modules, units, and sub-units, or at least part of the functions of any multiple of them, may be implemented in one module. Any one or more of the modules, sub-modules, units, and sub-units according to an embodiment of the present disclosure may be split into multiple modules for implementation. Any one or more of the modules, sub-modules, units, and sub-units according to an embodiment of the present disclosure may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or may be implemented by any other reasonable way of integrating or packaging circuits, in hardware or firmware, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in an appropriate combination of any several of them. Alternatively, one or more of the modules, sub-modules, units, and sub-units according to an embodiment of the present disclosure may be at least partially implemented as a computer program module, and when the computer program module is run, the corresponding functions may be executed.

[0110] For example, any combination of the receiving module 510, the first determination module 520, the second determination module 530, the third determination module 540, the first determination sub-module 541a, the second determination sub-module 542a, the third determination sub-module 541b, the fourth determination sub-module 542b, and the fifth determination sub-module 543b can be combined and implemented in one module, or any one of them can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the receiving module 510, the first determination module 520, the second determination module 530, the third determination module 540, the first determination sub-module 541a, the second determination sub-module 542a, the third determination sub-module 541b, the fourth determination sub-module 542b, and the fifth determination sub-module 543b can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable way of integrating or packaging circuits, etc., implemented by hardware or firmware, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in an appropriate combination of any several of them. Alternatively, at least one of the receiving module 510, the first determination module 520, the second determination module 530, the third determination module 540, the first determination sub-module 541a, the second determination sub-module 542a, the third determination sub-module 541b, the fourth determination sub-module 542b, and the fifth determination sub-module 543b can be at least partially implemented as a computer program module, and when the computer program module is run, it can execute the corresponding functions.

[0111] Figure 8 Schematically shows a block diagram of a computer system suitable for data processing according to an embodiment of the present disclosure. Figure 8 The computer system shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0112] As Figure 8As shown, the computer system 800 according to an embodiment of the present disclosure includes a processor 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage section 808 into a random access memory (RAM) 803. The processor 801 can include, for example, a general-purpose microprocessor (e.g., CPU), an instruction set processor, and / or a related chipset, and / or a dedicated microprocessor (e.g., an application-specific integrated circuit (ASIC)), and so on. The processor 801 can also include on-board memory for caching purposes. The processor 801 can include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0113] In the RAM 803, various programs and data required for the operation of the system 800 are stored. The processor 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. The processor 801 performs various operations of the method flow according to an embodiment of the present disclosure by executing the program in the ROM 802 and / or the RAM 803. It should be noted that the program can also be stored in one or more memories other than the ROM 802 and the RAM 803. The processor 801 can also perform various operations of the method flow according to an embodiment of the present disclosure by executing the program stored in the one or more memories.

[0114] According to an embodiment of the present disclosure, the system 800 can further include an input / output (I / O) interface 805, and the input / output (I / O) interface 805 is also connected to the bus 804. The system 800 can further include one or more of the following components connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed so that a computer program read from it can be installed into the storage section 808 as needed.

[0115] According to an embodiment of the present disclosure, the method flow according to the embodiment of the present disclosure can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 809, and / or installed from the removable medium 811. When the computer program is executed by the processor 801, the above functions defined in the system according to the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the above-described systems, devices, apparatuses, modules, units, etc. can be implemented by computer program modules.

[0116] The present disclosure also provides a computer-readable storage medium, which may be included in the device / device / system described in the above embodiment; or may exist separately without being assembled into the device / device / system. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present disclosure is implemented.

[0117] According to an embodiment of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium of a computer, and may include, for example, but not limited to: portable computer disks, hard disks, random access memories (RAMs), read-only memories (ROMs), erasable programmable read-only memories (EPROMs or flash memories), portable compact disk read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, device, or device.

[0118] For example, according to an embodiment of the present disclosure, the computer-readable storage medium may include the above-described ROM 802 and / or RAM 803 and / or one or more memories other than ROM 802 and RAM 803.

[0119] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that, in some alternative implementations, the functions noted in the blocks may occur in a different order than that noted in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and combinations of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0120] Those skilled in the art will appreciate that the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0121] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A data processing method, comprising: receiving an access request; based on the access request, determining a target object targeted by the access request; determining an accessed status of the target object, the accessed status including the number of target threads accessing the target object and the access order; and based on the accessed status, determining a response manner for the access request; wherein, when determining that the response manner is a first response manner, obtaining the target object from a first storage unit; when determining that the response manner is a second response manner, obtaining the target object from at least a second storage unit, wherein, the first storage unit includes a memory unit that stores initial data after deserialization processing; the second storage unit includes a cache unit that stores initial data without deserialization processing; the manner of obtaining the target object from the first storage unit is different from the manner of obtaining the target object from the second storage unit.

2. The method according to claim 1, wherein, the target object can be accessed by multiple threads; the determining the accessed status of the target object includes: determining at least one target thread among the multiple threads; and determining the accessed status of the target object, the accessed status indicating the status of the target object being accessed by the at least one target thread.

3. The method according to claim 2, wherein, when there are multiple target threads, the determining the response manner for the access request includes: determining that the response manner for a first target thread is the first response manner, the first target thread being the target thread that first accesses the target object among the multiple target threads; and determining that the response manner for a second target thread is the second response manner, the second target thread being the target thread other than the first target thread among the multiple target threads.

4. The method according to claim 2 or 3, wherein, when there is one target thread, the determining the response manner for the access request includes: determining the access order of the target thread accessing the target object; determining that the response manner for a first access order is the first response manner, the first access order indicating that the target thread first accesses the target object; and determining that the response manner for a second access order is the second response manner, the second access order being the access order of the target thread other than the first access order.

5. The method according to claim 1, wherein, the obtaining the target object from at least the second storage unit includes: obtaining initial data from the second storage unit; and performing deserialization processing on the initial data to obtain the target object.

6. The method according to claim 1, wherein, the obtaining the target object from at least the second storage unit includes: determining attribute information of the target object; based on the attribute information of the target object, dividing the target object into static data and dynamic data; obtaining the static data from the first storage unit; and Obtain the dynamic data from the second storage unit and perform deserialization processing on the dynamic data.

7. A data processing device, comprising: a receiving module that receives an access request; a first determination module that determines a target object targeted by the access request based on the access request; a second determination module that determines an accessed state of the target object, where the accessed state includes the number of target threads accessing the target object and the access order; and a third determination module that determines a response manner for the access request based on the accessed state; wherein, when it is determined that the response manner is a first response manner, obtain the target object from a first storage unit; when it is determined that the response manner is a second response manner, obtain the target object from at least a second storage unit, wherein the first storage unit includes a memory unit that stores initial data after deserialization processing; the second storage unit includes a cache unit that stores initial data without deserialization processing; the manner of obtaining the target object from the first storage unit is different from the manner of obtaining the target object from the second storage unit.

8. A data processing system, comprising: one or more processors; a memory for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing computer-executable instructions that, when executed, are used to implement the method according to any one of claims 1 to 6.

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