Scan Driver

Abstract

A scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes first to sixth transistors and a first capacitor. The first transistor is connected to a first Q node, a first scan clock line, and a first scan line. The second transistor is connected to a first scan carry line and a first Q node. The third transistor is connected to a first sense carry line and a second sense carry line. The fourth transistor is connected to a first control line and the third transistor. The fifth transistor is connected to the fourth transistor, the second control line, and the first node. The first capacitor is connected to the fifth transistor. The sixth transistor is connected to the third control line, the first node, and the first Q node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0112761, filed on September 11, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to a scan driver. Background Art

[0004] Each pixel of the display device may emit light at a brightness corresponding to a data signal input through a data line. The display device may display a frame image using a combination of the emitting pixels.

[0005] A plurality of pixels may be connected to each data line. Therefore, a scan driver for providing a scan signal to select a pixel to which a data signal is to be supplied is required. The scan driver may be configured in the form of a shift register so as to sequentially provide a scan signal of a conduction level in units of scan lines.

[0006] Depending on occasions, for example, in order to obtain mobility information or threshold voltage information of a driving transistor of a pixel, a scan driver capable of selectively supplying a scan signal of an on level only to a desired scan line is required.

[0007] When a scan line is selected for each frame to provide a scan signal to the selected scan line, it may take a relatively long time to provide the scan signal to all scan lines, that is, to obtain characteristic information of all pixels in the display device (that is, to obtain mobility information or threshold voltage information of the driving transistor).

[0008] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore may contain information that does not constitute prior art. Summary of the invention

[0009] Exemplary embodiments of the present invention provide a scan driver capable of selecting a plurality of scan lines in one frame and sequentially supplying scan signals to the selected scan lines.

[0010] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0011] The scan driver according to an exemplary embodiment of the present invention includes a plurality of scan stages. The first scan stage among the plurality of scan stages includes: a first transistor having a gate electrode connected to a first Q node, an electrode connected to a first scan clock line, and another electrode connected to the first scan line; a second transistor having a gate electrode and an electrode connected to a first scan carry line, and another electrode connected to the first Q node; a third transistor having a gate electrode connected to a first sensing carry line, and an electrode connected to a second sensing carry line; a fourth transistor having a gate electrode connected to a first control line, and an electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, an electrode connected to a second control line, and another electrode connected to the first node; a first capacitor having an electrode connected to an electrode of a fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to the third control line, an electrode connected to the first node, and another electrode connected to the first Q node.

[0012] The first scan stage may further include a seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the second control line, and the other electrode connected to the first node.

[0013] The first control signal provided through the first control line may include a plurality of pulses during one frame, and when both a pulse of the first sensing carry signal provided through the first sensing carry line and a pulse of the second sensing carry signal provided through the second sensing carry line overlap with one of the pulses of the first control signal, the second sensing carry signal may be written to the first capacitor.

[0014] The first scan stage may further include: a second capacitor having one electrode connected to the gate electrode of the first transistor and another electrode connected to the other electrode of the first transistor; an eighth transistor having a gate electrode connected to the first Q node, one electrode connected to the first sensing clock line, and another electrode connected to the first sensing line; a third capacitor having one electrode connected to the gate electrode of the eighth transistor and another electrode connected to the other electrode of the eighth transistor; and a ninth transistor having a gate electrode connected to the first Q node, one electrode connected to the first carry clock line, and another electrode connected to the first carry line.

[0015] The first scan stage may further include a tenth transistor having a gate electrode connected to the first reset carry line, one electrode connected to the first Q node, and the other electrode connected to the first power line.

[0016] The first scanning stage may further include: an eleventh transistor having a gate electrode connected to the first QB node, an electrode connected to the first Q node, and another electrode connected to the first power line; and a twelfth transistor having a gate electrode connected to the second QB node, an electrode connected to the first Q node, and another electrode connected to the first power line.

[0017] The first scan level may further include: a thirteenth transistor having a gate electrode connected to the first QB node, an electrode connected to the first carry line, and another electrode connected to the first power line; a fourteenth transistor having a gate electrode connected to the second QB node, an electrode connected to the first carry line, and another electrode connected to the first power line; a fifteenth transistor having a gate electrode connected to the first QB node, an electrode connected to the first sense line, and another electrode connected to the second power line; a sixteenth transistor having a gate electrode connected to the second QB node, an electrode connected to the first sense line, and another electrode connected to the second power line; a seventeenth transistor having a gate electrode connected to the first QB node, an electrode connected to the first scan line, and another electrode connected to the second power line; and an eighteenth transistor having a gate electrode connected to the second QB node, an electrode connected to the first scan line, and another electrode connected to the second power line.

[0018] The first scan stage may further include a nineteenth transistor having a gate electrode connected to the fourth control line, one electrode connected to the gate electrode of the fifth transistor, and the other electrode connected to the first power line.

[0019] The first scan stage may further include: a twentieth transistor having a gate electrode connected to the fourth control line, one electrode connected to the first Q node, and another electrode connected to the first power line; a twenty-first transistor having a gate electrode connected to the first Q node, one electrode connected to the first power line, and another electrode connected to the first QB node; and a twenty-second transistor having a gate electrode connected to the first scan carry line, one electrode connected to the first power line, and another electrode connected to the first QB node.

[0020] The first scan stage may further include: a twenty-third transistor having a gate electrode connected to the other electrode of the fourth transistor and an electrode connected to the first power line; and a twenty-fourth transistor having a gate electrode connected to the third control line, an electrode connected to the other electrode of the twenty-third transistor, and another electrode connected to the first QB node.

[0021] The first scan stage may further include: a twenty-fifth transistor having a gate electrode and an electrode connected to a fifth control line; and a twenty-sixth transistor having a gate electrode connected to the other electrode of the twenty-fifth transistor, one electrode connected to the fifth control line, and the other electrode connected to the first QB node.

[0022] The first scanning stage may further include: a twenty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to the third power line; and a twenty-eighth transistor having a gate electrode connected to the second Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and another electrode connected to the third power line.

[0023] The nineteenth transistor may include: a first sub-transistor having a gate electrode connected to a fourth control line and one electrode connected to another electrode of the fourth transistor; and a second sub-transistor having a gate electrode connected to the fourth control line, one electrode connected to another electrode of the first sub-transistor, and another electrode connected to the first power line. The first scanning stage may further include: a twenty-ninth transistor having a gate electrode connected to another electrode of the fourth transistor, one electrode connected to one electrode of the fourth transistor, and another electrode connected to the second control line.

[0024] A second scanning level among the multiple scanning levels may include: a 30th transistor having a gate electrode connected to a second Q node, an electrode connected to a second scanning line, and another electrode connected to a second scanning clock line; a fourth capacitor connecting the gate electrode and an electrode of the 30th transistor to each other; a 31st transistor having a gate electrode connected to a second Q node, an electrode connected to a second sensing line, and another electrode connected to a second sensing clock line; a fifth capacitor connecting the gate electrode and an electrode of the 31st transistor to each other; and a 32nd transistor having a gate electrode connected to a second Q node, an electrode connected to a second carry line, and another electrode connected to a second carry clock line.

[0025] The second scan stage may further include: a thirty-third transistor having a gate electrode connected to the first QB node, an electrode connected to the first power line, and another electrode connected to the second Q node; and a thirty-fourth transistor having a gate electrode connected to the second QB node, an electrode connected to the first power line, and another electrode connected to the second Q node.

[0026] The second scanning level may further include: a thirty-fifth transistor having a gate electrode, one electrode and another electrode, the gate electrode and the other electrode of the thirty-fifth transistor being connected to the sixth control line; a thirty-sixth transistor having a gate electrode connected to one electrode of the thirty-fifth transistor, one electrode connected to the second QB node and the other electrode connected to the sixth control line; a thirty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the third power line and the other electrode connected to the gate electrode of the thirty-sixth transistor; and a thirty-eighth transistor having a gate electrode connected to the second Q node, one electrode connected to the third power line and the other electrode connected to the gate electrode of the thirty-sixth transistor.

[0027] The second scan stage may further include: a thirty-ninth transistor having a gate electrode connected to the first QB node, an electrode connected to the first power line, and another electrode connected to the second carry line; a fortieth transistor having a gate electrode connected to the second QB node, an electrode connected to the first power line, and another electrode connected to the second carry line; a forty-first transistor having a gate electrode connected to the first QB node, an electrode connected to the second power line, and another electrode connected to the second sense line; a forty-second transistor having a gate electrode connected to the second QB node, an electrode connected to the second power line, and another electrode connected to the second sense line; a forty-third transistor having a gate electrode connected to the first QB node, an electrode connected to the second power line, and another electrode connected to the second scan line; and a forty-fourth transistor having a gate electrode connected to the second QB node, an electrode connected to the second power line, and another electrode connected to the second scan line.

[0028] The second scan stage may further include: a forty-fifth transistor having a gate electrode connected to the second sensing carry line and an electrode connected to the third sensing carry line; a forty-sixth transistor having a gate electrode connected to the first control line and an electrode connected to the other electrode of the forty-fifth transistor; a forty-seventh transistor having a gate electrode connected to the third control line, an electrode connected to the second Q node, and another electrode connected to the second node; a forty-eighth transistor having a gate electrode connected to the other electrode of the forty-sixth transistor, an electrode connected to the second node, and another electrode connected to the second control line; and a sixth capacitor having one electrode connected to the gate electrode of the forty-eighth transistor and another electrode connected to the other electrode of the forty-eighth transistor.

[0029] The second scan stage may further include: a 49th transistor having an electrode connected to the second Q node and a gate electrode and another electrode connected to the second scan carry line; and a 50th transistor having a gate electrode connected to the second Q node, an electrode connected to the second control line, and another electrode connected to the second node.

[0030] The second scan stage may further include: a fifty-first transistor having a gate electrode connected to the other electrode of the forty-sixth transistor and an electrode connected to the first power line; and a fifty-second transistor having a gate electrode connected to the third control line, an electrode connected to the other electrode of the fifty-first transistor, and another electrode connected to the second QB node.

[0031] The second scan stage may further include: a fifty-third transistor having a gate electrode connected to the second Q node, an electrode connected to the second QB node, and another electrode connected to the first power line; and a fifty-fourth transistor having a gate electrode connected to the first scan carry line, an electrode connected to the second QB node, and another electrode connected to the first power line.

[0032] The second scan stage may further include: a fifty-fifth transistor having a gate electrode connected to a fourth control line, an electrode connected to the first power line, and another electrode connected to the second Q node; and a fifty-sixth transistor having a gate electrode connected to the first reset carry line, an electrode connected to the first power line, and another electrode connected to the second Q node.

[0033] The second scan stage may further include a fifty-seventh transistor having a gate electrode connected to the fourth control line, one electrode connected to the gate electrode of the forty-eighth transistor, and the other electrode connected to the first power line.

[0034] The fifty-seventh transistor may include: a third sub-transistor having a gate electrode connected to a fourth control line and one electrode connected to another electrode of the forty-sixth transistor; and a fourth sub-transistor having a gate electrode connected to the fourth control line, one electrode connected to another electrode of the third sub-transistor, and another electrode connected to the first power line. The second scanning stage may further include: a fifty-eighth transistor having a gate electrode connected to another electrode of the forty-sixth transistor, one electrode connected to the second control line, and another electrode connected to one electrode of the forty-sixth transistor.

[0035] Another exemplary embodiment of the present invention provides a scan driver including a plurality of scan stages. A first scan stage among the plurality of scan stages includes: a first transistor having a gate electrode connected to a first Q node, an electrode connected to a first scan clock line, and another electrode connected to the first scan line; a second transistor having a gate electrode and an electrode connected to a first scan carry line, and another electrode connected to the first Q node; a third transistor having a gate electrode connected to a first sense carry line, and an electrode connected to a first control line; a fourth transistor having a gate electrode connected to a second sense carry line, and an electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, an electrode connected to a second control line, and another electrode connected to the first node; a first capacitor having an electrode connected to an electrode of a fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to a third control line, an electrode connected to a first node, and another electrode connected to the first Q node.

[0036] Another exemplary embodiment of the present invention provides a scan driver including a plurality of scan stages. The odd-numbered stages among the scan stages are connected to the first sub-control line, and the even-numbered stages among the scan stages are connected to the second sub-control line. The first scan stage among the plurality of scan stages includes: a first transistor having a gate electrode connected to a first Q node, an electrode connected to a first scan clock line, and another electrode connected to the first scan line; a second transistor having a gate electrode and an electrode connected to a first scan carry line and another electrode connected to the first Q node; a third transistor having a gate electrode and an electrode connected to a first sense carry line; a fourth transistor having a gate electrode connected to the first sub-control line and an electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, an electrode connected to the second control line, and another electrode connected to the first node; a first capacitor having an electrode connected to an electrode of a fifth transistor and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to the third control line, an electrode connected to the first node, and another electrode connected to the first Q node.

[0037] A second scanning stage among the plurality of scanning stages may include: a seventh transistor having a gate electrode connected to a second Q node, an electrode connected to a second scanning clock line, and another electrode connected to the second scanning line; an eighth transistor having a gate electrode and an electrode connected to a second scanning carry line, and another electrode connected to a second Q node; a ninth transistor having a gate electrode and an electrode connected to a second sensing carry line; a tenth transistor having a gate electrode connected to a second sub-control line and an electrode connected to another electrode of the ninth transistor; an eleventh transistor having a gate electrode connected to another electrode of the tenth transistor, an electrode connected to the second control line, and another electrode connected to the second node; a second capacitor having an electrode connected to an electrode of the eleventh transistor and another electrode connected to the gate electrode of the eleventh transistor; and a twelfth transistor having a gate electrode connected to a third control line, an electrode connected to the second node, and another electrode connected to the second Q node.

[0038] Another exemplary embodiment of the present invention provides a scan driver including a plurality of scan stages. The odd-numbered stages among the scan stages are connected to the first sub-control line, and the even-numbered stages among the scan stages are connected to the second sub-control line. The first scan stage among the plurality of scan stages includes: a first transistor having a gate electrode connected to a first Q node, an electrode connected to a first scan clock line, and another electrode connected to the first scan line; a second transistor having a gate electrode and an electrode connected to a first scan carry line and another electrode connected to the first Q node; a third transistor having a gate electrode connected to a first sense carry line and an electrode connected to the first sub-control line; a fourth transistor having a gate electrode connected to the first sense carry line and an electrode connected to another electrode of the third transistor; a fifth transistor having a gate electrode connected to another electrode of the fourth transistor, an electrode connected to the second control line, and another electrode connected to the first node; a first capacitor having an electrode connected to an electrode of a fifth transistor and another electrode connected to the gate electrode of the fifth transistor; and a sixth transistor having a gate electrode connected to the third control line, an electrode connected to the first node, and another electrode connected to the first Q node.

[0039] According to the scan driver conceived in the present invention, two or more stages can be selected by a pulse of a selection signal (or a first control signal) during a display period within one frame, and during a sensing period within one frame, the two or more stages can sequentially provide scan signals (and sensing signals) to the scan lines according to different clock signals (and sensing clock signals).

[0040] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0042] Figure 1 is a diagram for describing a display device according to an exemplary embodiment of the present invention.

[0043] Figure 2 The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device.

[0044] Figure 3 The diagram is included in Figure 1 FIG. 1 is a diagram of an example of a scan driver in a display device.

[0045] Figure 4 The diagram is included in Figure 3 A circuit diagram of an example of the m-th stage group in a scan driver.

[0046] Figure 5 The diagram is driven during the display period Figure 3 Waveform diagram of the scan driver method.

[0047] Figure 6 The diagram is applied to Figure 3 Diagram of the control signals of the scan driver.

[0048] Figure 7 The diagram shows the driving during the sensing period. Figure 3 Waveform diagram of the scan driver method.

[0049] Figure 8 It is used to describe the drive Figure 3 FIG. 1 is a diagram of a method of scanning a drive.

[0050] Fig. 9 The diagram is included in Figure 3 A circuit diagram of another example of the m-th stage group in a scan driver.

[0051] Fig.10 The diagram is included in Figure 1 FIG. 1 is a diagram of another example of a scan driver in a display device of FIG.

[0052] Fig.11 The diagram is included in Fig.10 A circuit diagram of an example of the m-th stage group in a scan driver.

[0053] Fig.12 The diagram is driven during the display period Fig.10 Waveform diagram of the scan driver method.

[0054] Fig.13 The diagram is applied to Fig.10 Diagram of the control signals of the scan driver.

[0055] Fig.14 It is used to describe the drive Fig.10 FIG. 1 is a diagram of a method of scanning a drive.

[0056] Fig.15 The diagram is included in Fig.10 A circuit diagram of another example of the m-th stage group in a scan driver. DETAILED DESCRIPTION

[0057] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a comprehensive understanding of the various exemplary embodiments of the present invention. As used herein, "embodiment" is a non-limiting example of a device or method that adopts one or more of the inventive concepts disclosed herein. However, it is apparent that the various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, well-known structures and devices are shown in the form of block diagrams in order to avoid unnecessary obscurity of the various exemplary embodiments. In addition, the various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0058] Unless otherwise specified, the illustrated exemplary embodiments should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter referred to as "elements" or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0059] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0060] When an element such as a layer is referred to as "being located on another element or layer", "being connected to" or "being coupled to" another element or layer, the element may be directly located on another element or layer, directly connected to or coupled to another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as "being directly located on another element or layer", "being directly connected to" or "being directly coupled to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection using or not using an intermediate element. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be interpreted as any combination of only X, only Y, only Z or two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0061] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0062] For the purpose of description, spatial relative terms such as "below", "below", "under", "down", "above", "up", "above", "higher", and "side" (e.g., as in "sidewall"), etc. may be used herein, and the relationship of one element to another element as illustrated in the accompanying drawings is described thereby. Spatially relative terms are intended to encompass different orientations of the device in use, in operation, and / or in manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, the element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the exemplary term "below" can encompass both above and below orientations. In addition, the device can be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and therefore the spatial relative descriptors used herein should be interpreted accordingly.

[0063] The terms used herein are for the purpose of describing specific embodiments, and are not intended to limit. As used herein, the "one" and "the" in the singular are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate the presence of described features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms, and are not used as terms of degree, and are therefore used to consider the inherent deviations in the values ​​measured, calculated and / or provided that will be recognized by those of ordinary skill in the art.

[0064] As is customary in the art, some exemplary embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (e.g., logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein, and can be optionally driven by firmware and / or software. It is also expected that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and related circuits) that perform certain functions to perform other functions. In addition, each block, unit and / or module in some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules without departing from the scope of the inventive concept. Further, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. Terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0066] Figure 1 is a diagram for describing a display device according to an exemplary embodiment of the present invention.

[0067] refer to Figure 1, the display device 10 may include a timing controller 11 , a data driver 12 , a scan driver 13 , a sensing unit 14 , and a pixel unit 15 .

[0068] The timing controller 11 may provide a grayscale value and a control signal, etc. to the data driver 12. In addition, the timing controller 11 may provide a clock signal and a control signal, etc. to each of the scan driver 13 and the sensing unit 14.

[0069] The data driver 12 may generate a data signal using the grayscale value and control signal etc. received from the timing controller 11. For example, the data driver 12 may sample the grayscale value using the clock signal and apply the data signal corresponding to the grayscale value to the data lines D1, D2, ... Dq (where q is a positive integer) in units of pixel columns.

[0070] The scan driver 13 may receive a clock signal and a control signal from the timing controller 11, and generate a scan signal to be provided to the scan lines SC1, SC2, ... SCp (where p is a positive integer). For example, the scan driver 13 may sequentially provide a scan signal having a pulse of a conduction level to the scan lines SC1 to SCp. For example, the scan driver 13 may generate a scan signal in a manner that sequentially transmits a pulse of a conduction level to the next scan level according to a clock signal. For example, the scan driver 13 may be configured in the form of a shift register.

[0071] In addition, the scan driver 13 may generate a sensing signal to be provided to the sensing lines SS1, SS2, ... SSp. For example, the scan driver 13 may sequentially provide a sensing signal having a pulse of an on level to the sensing lines SS1 to SSp. For example, the scan driver 13 may generate a sensing signal by sequentially transmitting a pulse of an on level to a next scanning stage according to a clock signal.

[0072] However, the operation of the scan driver 13 described above involves Figure 5 operations during the display period, and Figure 7 The operations in the sensing period will be described separately. One frame period (or one frame) may include one display period and one sensing period.

[0073] The sensing unit 14 can measure the degradation information of the pixel according to the current or voltage received through the receiving lines R1, R2, R3, ... Rq. For example, the degradation information of the pixel can be the mobility information and threshold voltage information of the driving transistor and the degradation information of the light-emitting element. In addition, the sensing unit 14 can measure the characteristic information of the pixel according to the environment according to the current or voltage received through the receiving lines R1 to Rq. For example, the sensing unit 14 can also measure the characteristic information of the pixel according to the change of temperature or humidity.

[0074] The pixel unit 15 includes pixels PXij (where each of i and j is a positive integer). Each pixel PXij can be connected to a corresponding data line, a scan line, a sensing line, and a receiving line. The pixel PXij can refer to a pixel circuit in which a scan transistor is connected to the i-th scan line and the j-th data line.

[0075] Figure 2 The diagram is included in Figure 1 A circuit diagram of an example of a pixel in a display device.

[0076] refer to Figure 2 , the pixel PXij may include thin film transistors (or transistors) M1, M2, and M3, a storage capacitor Cst, and a light emitting element LD. The thin film transistors M1, M2, and M3 may be N-type transistors.

[0077] In the first thin film transistor M1, a gate electrode may be connected to the gate node Na, one electrode (or first electrode) may be connected to the power line ELVDD, and the other electrode (or second electrode) may be connected to the source node Nb. The first thin film transistor M1 may be referred to as a "driving transistor".

[0078] In the second thin film transistor M2, a gate electrode may be connected to the scan line SCi, one electrode may be connected to the data line Dj, and the other electrode may be connected to the gate node Na. The second thin film transistor M2 may be referred to as a switching transistor or a scan transistor, etc.

[0079] In the third thin film transistor M3, a gate electrode may be connected to the sensing line SSi, one electrode may be connected to the receiving line Rj, and the other electrode may be connected to the source node Nb. The third thin film transistor M3 may be called an initialization transistor or a sensing transistor, etc.

[0080] In the storage capacitor Cst, one electrode may be connected to the gate node Na, and the other electrode may be connected to the source node Nb.

[0081] In the light emitting element LD, an anode may be connected to the source node Nb, and a cathode may be connected to the power supply line ELVSS. The light emitting element LD may be an organic light emitting diode or an inorganic light emitting diode, or the like.

[0082] Figure 3 The diagram is included in Figure 1 FIG. 1 is a diagram of an example of a scan driver in a display device.

[0083] refer to Figure 3 , the scan driver 13 includes a plurality of stage groups...STG(m-2), STG(m-1), STGm, STG(m+1), STG(m+2) and...(wherein m is an integer equal to or greater than 2). Figure 3 Only a portion of the scan driver 13 necessary for the description is shown.

[0084] Each stage group STG(m-2) to STG(m+2) may include a first scanning level and a second scanning level. The first scanning level may be an odd scanning level, and the second scanning level may be an even scanning level. For example, the m-2 stage group STG(m-2) may include an n-4th (where n is an integer equal to or greater than 4) scanning level ST(n-4) and an n-3rd scanning level ST(n-3); the m-1 stage group STG(m-1) may include an n-2th scanning level ST(n-2) and an n-1th scanning level ST(n-1); the m-stage group STGm may include an n-1st scanning level STn and an n+1th scanning level ST(n+1); the m+1 stage group STG(m+1) may include an n+2th scanning level ST(n+2) and an n+3th scanning level ST(n+3); and the m+2 stage group STG(m+2) may include an n+4th scanning level ST(n+4) and an n+5th scanning level ST(n+5). Each of the n-4th scanning level ST(n-4), the n-2nd scanning level ST(n-2), the nth scanning level STn, the n+2nd scanning level ST(n+2) and the n+4th scanning level ST(n+4) may be an odd scanning level, and each of the n-3rd scanning level ST(n-3), the n-1th scanning level ST(n-1), the n+1th scanning level ST(n+1), the n+3rd scanning level ST(n+3) and the n+5th scanning level ST(n+5) may be an even scanning level.

[0085] Each of the scanning stages ST(n-4) to ST(n+5) may be connected to first to sixth control lines CS1, CS2, CS3, CS4, CS5, and CS6. A common control signal may be applied to the scanning stages ST(n-4) to ST(n+5) through the first to sixth control lines CS1 to CS6.

[0086] Each of the scanning stages ST(n-4) to ST(n+5) can be connected to the corresponding scan clock lines SCCK1, SCCK2, SCCK3, SCCK4, SCCK5 and SCCK6, the sense clock lines SSCK1, SSCK2, SSCK3, SSCK4, SSCK5 and SSCK6 and the corresponding clock lines among the carry clock lines CRCK1, CRCK2, CRCK3, CRCK4, CRCK5 and CRCK6.

[0087] For example, the n-4th scanning stage ST(n-4) may be connected to the first scanning clock line SCCK1, the first sensing clock line SSCK1, and the first carry clock line CRCK1, and the n-3th scanning stage ST(n-3) may be connected to the second scanning clock line SCCK2, the second sensing clock line SSCK2, and the second carry clock line CRCK2. The n-2th scanning stage ST(n-2) may be connected to the third scanning clock line SCCK3, the third sensing clock line SSCK3, and the third carry clock line CRCK3, and the n-1th scanning stage ST(n-1) may be connected to the fourth scanning clock line SCCK4, the fourth sensing clock line SSCK4, and the fourth carry clock line CRCK4. The nth scanning stage STn may be connected to the fifth scanning clock line SCCK5, the fifth sensing clock line SSCK5, and the fifth carry clock line CRCK5, and the n+1th scanning stage ST(n+1) may be connected to the sixth scanning clock line SCCK6, the sixth sensing clock line SSCK6, and the sixth carry clock line CRCK6.

[0088] In addition, repeatedly, the n+2th scanning stage ST(n+2) can be connected to the first scanning clock line SCCK1, the first sensing clock line SSCK1 and the first carry clock line CRCK1, and the n+3th scanning stage ST(n+3) can be connected to the second scanning clock line SCCK2, the second sensing clock line SSCK2 and the second carry clock line CRCK2. The n+4th scanning stage ST(n+4) can be connected to the third scanning clock line SCCK3, the third sensing clock line SSCK3 and the third carry clock line CRCK3, and the n+5th scanning stage ST(n+5) can be connected to the fourth scanning clock line SCCK4, the fourth sensing clock line SSCK4 and the fourth carry clock line CRCK4.

[0089] The input signals of the corresponding scanning stages ST(n-4) to ST(n+5) are applied to the first control line CS1 to the sixth control line CS6, the first scanning clock line SCCK1 to the sixth scanning clock line SCCK6, the first sensing clock line SSCK1 to the sixth sensing clock line SSCK6, and the first carry clock line CRCK1 to the sixth carry clock line CRCK6.

[0090] The scanning stages ST(n-4) to ST(n+5) may be connected to corresponding lines among the scan lines SC(n-4), SC(n-3), SC(n-2), SC(n-1), SCn, SC(n+1), SC(n+2), SC(n+3), SC(n+4) and SC(n+5), the sensing lines SS(n-4), SS(n-3), SS(n-2), SS(n-1), SSn, SS(n+1), SS(n+2), SS(n+3), SS(n+4) and SS(n+5), and the carry lines CR(n-4), CR(n-3), CR(n-2), CR(n-1), CRn, CR(n+1), CR(n+2), CR(n+3), CR(n+4) and CR(n+5).

[0091] For example, the n-4th scanning stage ST(n-4) can be connected to the n-4th scanning line SC(n-4), the n-4th sensing line SS(n-4) and the n-4th carry line CR(n-4); and the n-3th scanning stage ST(n-3) can be connected to the n-3th scanning line SC(n-3), the n-3th sensing line SS(n-3) and the n-3th carry line CR(n-3). The n-2th scanning stage ST(n-2) can be connected to the n-2th scanning line SC(n-2), the n-2th sensing line SS(n-2) and the n-2th carry line CR(n-2); and the n-1th scanning stage ST(n-1) can be connected to the n-1th scanning line SC(n-1), the n-1th sensing line SS(n-1) and the n-1th carry line CR(n-1). The nth scanning stage STn may be connected to the nth scanning line SCn, the nth sensing line SSn, and the nth carry line CRn; and the n+1th scanning stage ST(n+1) may be connected to the n+1th scanning line SC(n+1), the n+1th sensing line SS(n+1), and the n+1th carry line CR(n+1). The n+2th scanning stage ST(n+2) may be connected to the n+2th scanning line SC(n+2), the n+2th sensing line SS(n+2), and the n+2th carry line CR(n+2); and the n+3th scanning stage ST(n+3) may be connected to the n+3th scanning line SC(n+3), the n+3th sensing line SS(n+3), and the n+3th carry line CR(n+3). The n+4th scanning stage ST(n+4) can be connected to the n+4th scanning line SC(n+4), the n+4th sensing line SS(n+4) and the n+4th carry line CR(n+4); and the n+5th scanning stage ST(n+5) can be connected to the n+5th scanning line SC(n+5), the n+5th sensing line SS(n+5) and the n+5th carry line CR(n+5).

[0092] The output signals generated by the corresponding scanning stages ST(n-4) to ST(n+5) are applied to the scan lines SC(n-4) to SC(n+5), the sense lines SS(n-4) to SS(n+5), and the carry lines CR(n-4) to CR(n+5).

[0093] Figure 4 The diagram is included in Figure 3 A circuit diagram of an example of the m-th stage group in a scan driver.

[0094] refer to Figure 4 , the m-th stage group STGm includes the n-th scanning stage STn (or the first scanning stage) and the n+1-th scanning stage ST(n+1) (or the second scanning stage). Figure 3 The described other stage groups STG(m-2), STG(m-1), STG(m+1), and STG(m+2) may include substantially the same configuration as the mth stage group STGm.

[0095] First, the nth scanning stage STn (or the first scanning stage) may include transistors T1 to T29 and capacitors C1 to C3. Hereinafter, a description will be given under the assumption that the transistors T1 to T58 are N-type transistors (e.g., NMOS). However, those skilled in the art may configure the mth stage group STGm by replacing some or all of the transistors T1 to T58 with P-type transistors (e.g., PMOS).

[0096] In the first transistor T1 , a gate electrode may be connected to the first Q node Qn, one electrode may be connected to the fifth scan clock line SCCK5 , and the other electrode may be connected to the nth scan line SCn (or the first scan line).

[0097] In the second transistor T2, the gate electrode and one electrode may be connected to the n-3 carry line CR (n-3) (or the first scan carry line), and the other electrode may be connected to the first Q node Qn. For example, the carry signal output from the n-3 scan stage ST (n-3) may be applied to the n-3 carry line CR (n-3).

[0098] In an exemplary embodiment, the second transistor T2 may include a first sub-transistor T2a and a second sub-transistor T2b connected in series. A gate electrode and one electrode of the first sub-transistor T2a may be connected to the n-3 carry line CR(n-3), and the other electrode may be connected to the first node N1. A gate electrode of the second sub-transistor T2b may be connected to the n-3 carry line CR(n-3), one electrode may be connected to the first node N1, and the other electrode may be connected to the first Q node Qn.

[0099] In the third transistor T3, the gate electrode may be connected to the nth carry line CRn (or the first sensing carry line), one electrode may be connected to the n+1th carry line CR(n+1) (or the second sensing carry line), and the other electrode may be connected to one electrode of the fourth transistor T4. For example, the carry signal output from the nth scanning stage STn may be applied to the nth carry line CRn, and the carry signal output from the n+1th scanning stage ST(n+1) may be applied to the n+1th carry line CR(n+1).

[0100] In the fourth transistor T4 , a gate electrode may be connected to the first control line CS1 , one electrode may be connected to the other electrode of the third transistor T3 , and the other electrode may be connected to the other electrode of the first capacitor C1 .

[0101] In the fifth transistor T5 , a gate electrode may be connected to the other electrode of the fourth transistor T4 , one electrode may be connected to the second control line CS2 , and the other electrode may be connected to the first node N1 .

[0102] In the first capacitor C1 , one electrode may be connected to one electrode of the fifth transistor T5 , and the other electrode may be connected to a gate electrode of the fifth transistor T5 .

[0103] In the sixth transistor T6 , a gate electrode may be connected to the third control line CS3 , one electrode may be connected to the first node N1 , and the other electrode may be connected to the first Q-node Qn.

[0104] In the seventh transistor T7 , a gate electrode may be connected to the first Q node Qn, one electrode may be connected to the second control line CS2 , and the other electrode may be connected to the first node N1 .

[0105] In the second capacitor C2 , one electrode may be connected to the gate electrode of the first transistor T1 , and the other electrode may be connected to the other electrode of the first transistor T1 .

[0106] In the eighth transistor T8 , a gate electrode may be connected to the first Q node Qn, one electrode may be connected to the fifth sensing clock line SSCK5 , and the other electrode may be connected to the nth sensing line SSn (or the first sensing line).

[0107] In the third capacitor C3 , one electrode may be connected to the gate electrode of the eighth transistor T8 , and the other electrode may be connected to the other electrode of the eighth transistor T8 .

[0108] In the ninth transistor T9, a gate electrode may be connected to the first Q node Qn, one electrode may be connected to the fifth carry clock line CRCK5, and the other electrode may be connected to the nth carry line CRn (or the first carry line).

[0109] In the tenth transistor T10, the gate electrode may be connected to the n+4th carry line CR(n+4) (or the first reset carry line), one electrode may be connected to the first Q node Qn, and the other electrode may be connected to the first power supply line VSS1. For example, the carry signal output from the n+4th scanning stage ST(n+4) may be applied to the n+4th carry line CR(n+4).

[0110] In an exemplary embodiment, the tenth transistor T10 may include a third sub-transistor T10a and a fourth sub-transistor T10b connected in series. A gate electrode of the third sub-transistor T10a may be connected to the n+4th carry line CR(n+4), one electrode may be connected to the first Q node Qn, and the other electrode may be connected to the first node N1. A gate electrode of the fourth sub-transistor T10b may be connected to the n+4th carry line CR(n+4), one electrode may be connected to the first node N1, and the other electrode may be connected to the first power supply line VSS1.

[0111] In the eleventh transistor T11 , a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the first Q node Qn, and the other electrode may be connected to the first power line VSS1 .

[0112] In an exemplary embodiment, the eleventh transistor T11 may include a fifth sub-transistor T11a and a sixth sub-transistor T11b connected in series. In the fifth sub-transistor T11a, a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the first Q node Qn, and the other electrode may be connected to the first node N1. In the sixth sub-transistor T11b, a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the first node N1, and the other electrode may be connected to the first power line VSS1.

[0113] In the twelfth transistor T12 , a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the first Q node Qn, and the other electrode may be connected to the first power line VSS1 .

[0114] In an exemplary embodiment, the twelfth transistor T12 may include a seventh sub-transistor T12a and an eighth sub-transistor T12b connected in series. In the seventh sub-transistor T12a, a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the first Q node Qn, and the other electrode may be connected to the first node N1. In the eighth sub-transistor T12b, a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the first node N1, and the other electrode may be connected to the first power line VSS1.

[0115] In the thirteenth transistor T13 , a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the n-th carry line CRn, and the other electrode may be connected to the first power line VSS1 .

[0116] In the fourteenth transistor T14 , a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the n-th carry line CRn, and the other electrode may be connected to the first power line VSS1 .

[0117] In the fifteenth transistor T15 , a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the nth sensing line SSn, and the other electrode may be connected to the second power line VSS2 .

[0118] In the sixteenth transistor T16 , a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the nth sensing line SSn, and the other electrode may be connected to the second power line VSS2 .

[0119] In the seventeenth transistor T17 , a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the nth scan line SCn, and the other electrode may be connected to the second power line VSS2 .

[0120] In the eighteenth transistor T18, a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the nth scan line SCn, and the other electrode may be connected to the second power line VSS2.

[0121] In the nineteenth transistor T19 , a gate electrode may be connected to the fourth control line CS4 , one electrode may be connected to the gate electrode of the fifth transistor T5 (or the other electrode of the first capacitor C1 ), and the other electrode may be connected to the first power line VSS1 .

[0122] In an exemplary embodiment, the nineteenth transistor T19 may include a ninth sub-transistor T19a and a tenth sub-transistor T19b connected in series. In the ninth sub-transistor T19a, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the gate electrode of the fifth transistor T5 (or the other electrode of the first capacitor C1), and the other electrode may be connected to one electrode of the tenth sub-transistor T19b (or the other electrode of the third transistor T3). In the tenth sub-transistor T19b, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the other electrode of the ninth sub-transistor T19a, and the other electrode may be connected to the first power supply line VSS1.

[0123] In the twentieth transistor T20 , a gate electrode may be connected to the fourth control line CS4 , one electrode may be connected to the first Q-node Qn, and the other electrode may be connected to the first power line VSS1 .

[0124] In an exemplary embodiment, the twentieth transistor T20 may include an eleventh sub-transistor T20a and a twelfth sub-transistor T20b connected in series. In the eleventh sub-transistor T20a, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the first Q node Qn, and the other electrode may be connected to the first node N1. In the twelfth sub-transistor T20b, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the first node N1, and the other electrode may be connected to the first power line VSS1.

[0125] In the twenty-first transistor T21 , a gate electrode may be connected to the first Q node Qn, one electrode may be connected to the first power line VSS1 , and the other electrode may be connected to the first QB node QBn.

[0126] In the twenty-second transistor T22, a gate electrode may be connected to the n-3 th carry line CR(n-3) (or the first scan carry line), one electrode may be connected to the first power line VSS1, and the other electrode may be connected to the first QB node QBn.

[0127] In the twenty-third transistor T23 , a gate electrode may be connected to the other electrode of the fourth transistor T4 (or the other electrode of the first capacitor C1 ), one electrode may be connected to the first power line VSS1 , and the other electrode may be connected to one electrode of the twenty-fourth transistor T24 .

[0128] In the twenty-fourth transistor T24 , a gate electrode may be connected to the third control line CS3 , one electrode may be connected to the other electrode of the twenty-third transistor T23 , and the other electrode may be connected to the first QB node QBn.

[0129] In the twenty-fifth transistor T25 , a gate electrode and one electrode may be connected to the fifth control line CS5 , and the other electrode may be connected to the gate electrode of the twenty-sixth transistor T26 .

[0130] In the twenty-sixth transistor T26 , a gate electrode may be connected to the other electrode of the twenty-fifth transistor T25 , one electrode may be connected to the fifth control line CS5 , and the other electrode may be connected to the first QB node QBn.

[0131] In the twenty-seventh transistor T27 , a gate electrode may be connected to the first Q node Qn, one electrode may be connected to the gate electrode of the twenty-sixth transistor T26 , and the other electrode may be connected to the third power line VSS3 .

[0132] In the twenty-eighth transistor T28 , a gate electrode may be connected to the second Q node Q(n+1), one electrode may be connected to the gate electrode of the twenty-sixth transistor T26 , and the other electrode may be connected to the third power line VSS3 .

[0133] In the twenty-ninth transistor T29 , a gate electrode may be connected to the other electrode of the fourth transistor T4 , one electrode may be connected to one electrode of the fourth transistor T4 , and the other electrode may be connected to the second control line CS2 .

[0134] Next, the (n+1)th scanning stage ST(n+1) (or the second scanning stage) may include transistors T30 to T58 and capacitors C4 to C6.

[0135] In the 30th transistor T30, the gate electrode can be connected to the second Q node Q(n+1), one electrode can be connected to the n+1th scan line SC(n+1) (or the second scan line), and the other electrode can be connected to the sixth scan clock line SCCK6.

[0136] The fourth capacitor C4 may connect the gate electrode and one electrode of the thirtieth transistor T30 .

[0137] In the thirty-first transistor T31, the gate electrode can be connected to the second Q node Q(n+1), one electrode can be connected to the n+1th sensing line SS(n+1) (or the second sensing line), and the other electrode can be connected to the sixth sensing clock line SSCK6.

[0138] The fifth capacitor C5 may connect the gate electrode and one electrode of the thirty-first transistor T31 .

[0139] In the thirty-second transistor T32, the gate electrode can be connected to the second Q node Q(n+1), one electrode can be connected to the n+1th carry line CR(n+1) (or the second carry line), and the other electrode can be connected to the sixth carry clock line CRCK6.

[0140] In the thirty-third transistor T33 , a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the first power line VSS1 , and the other electrode may be connected to the second Q node Q(n+1).

[0141] In an exemplary embodiment, the thirty-third transistor T33 may include a thirteenth sub-transistor T33a and a fourteenth sub-transistor T33b. In the thirteenth sub-transistor T33a, a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the first power line VSS1, and the other electrode may be connected to the second node N2. In the fourteenth sub-transistor T33b, a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the second node N2, and the other electrode may be connected to the second Q node Q(n+1).

[0142] In the thirty-fourth transistor T34 , a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the first power line VSS1 , and the other electrode may be connected to the second Q node Q(n+1).

[0143] In an exemplary embodiment, the thirty-fourth transistor T34 may include a fifteenth sub-transistor T34a and a sixteenth sub-transistor T34b. In the fifteenth sub-transistor T34a, a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the first power supply line VSS1, and the other electrode may be connected to the second node N2. In the sixteenth sub-transistor T34b, a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the second node N2, and the other electrode may be connected to the second Q node Q(n+1).

[0144] In the thirty-fifth transistor T35 , a gate electrode may be connected to the sixth control line CS6 , one electrode may be connected to the gate electrode of the thirty-sixth transistor T36 , and the other electrode may be connected to the sixth control line CS6 .

[0145] In the thirty-sixth transistor T36 , a gate electrode may be connected to one electrode of the thirty-fifth transistor T35 , one electrode may be connected to the second QB node QB(n+1), and the other electrode may be connected to the sixth control line CS6 .

[0146] In the thirty-seventh transistor T37 , a gate electrode may be connected to the first Q node Qn, one electrode may be connected to the third power line VSS3 , and the other electrode may be connected to the gate electrode of the thirty-sixth transistor T36 .

[0147] In the thirty-eighth transistor T38 , a gate electrode may be connected to the second Q node Q(n+1), one electrode may be connected to the third power line VSS3 , and the other electrode may be connected to the gate electrode of the thirty-sixth transistor T36 .

[0148] In the thirty-ninth transistor T39 , a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the first power line VSS1 , and the other electrode may be connected to the n+1th carry line CR(n+1).

[0149] In the fortieth transistor T40 , a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the first power line VSS1 , and the other electrode may be connected to the n+1th carry line CR(n+1).

[0150] In the forty-first transistor T41 , a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the second power line VSS2 , and the other electrode may be connected to the n+1th sensing line SS(n+1).

[0151] In the 42nd transistor T42 , a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the second power line VSS2 , and the other electrode may be connected to the n+1th sensing line SS(n+1).

[0152] In the forty-third transistor T43, a gate electrode may be connected to the first QB node QBn, one electrode may be connected to the second power line VSS2, and the other electrode may be connected to the n+1th scan line SC(n+1).

[0153] In the forty-fourth transistor T44, a gate electrode may be connected to the second QB node QB(n+1), one electrode may be connected to the second power line VSS2, and the other electrode may be connected to the n+1th scan line SC(n+1).

[0154] In the forty-fifth transistor T45, a gate electrode may be connected to the n+1th carry line CR(n+1) (or the second sensing carry line), one electrode may be connected to the n+2th carry line CR(n+2) (or the third sensing carry line), and the other electrode may be connected to one electrode of the forty-sixth transistor T46. For example, a carry signal output from the nth scanning stage STn may be applied to the nth carry line CRn, a carry signal output from the n+1th scanning stage ST(n+1) may be applied to the n+1th carry line CR(n+1), and a carry signal output from the n+2th scanning stage ST(n+2) may be applied to the n+2th carry line CR(n+2).

[0155] In the forty-sixth transistor T46 , a gate electrode may be connected to the first control line CS1 , one electrode may be connected to the other electrode of the forty-fifth transistor T45 , and the other electrode may be connected to one electrode of the sixth capacitor C6 .

[0156] In the forty-seventh transistor T47, a gate electrode may be connected to the third control line CS3, one electrode may be connected to the second Q node Q(n+1), and the other electrode may be connected to the second node N2.

[0157] In the forty-eighth transistor T48, a gate electrode may be connected to the other electrode of the forty-sixth transistor T46 (or one electrode of the sixth capacitor C6), one electrode may be connected to the second node N2, and the other electrode may be connected to the second control line CS2.

[0158] In the sixth capacitor C6 , one electrode may be connected to the gate electrode of the forty-eighth transistor T48 , and the other electrode may be connected to the other electrode of the forty-eighth transistor T48 .

[0159] In the forty-ninth transistor T49, one electrode can be connected to the second Q node Q(n+1), and the gate electrode and the other electrode can be connected to the n-1th carry line CR(n-1). The carry signal output from the n-1th scanning stage ST(n-1) can be applied to the n-1th carry line CR(n-1).

[0160] In an exemplary embodiment, the forty-ninth transistor T49 may include a seventeenth sub-transistor T49a and an eighteenth sub-transistor T49b connected in series. In the seventeenth sub-transistor T49a, a gate electrode may be connected to the n-1th carry line CR(n-1), one electrode may be connected to the second Q node Q(n+1), and the other electrode may be connected to the second node N2. In the eighteenth sub-transistor T49b, a gate electrode may be connected to the n-1th carry line CR(n-1), one electrode may be connected to the second node N2, and the other electrode may be connected to the n-1th carry line CR(n-1).

[0161] In the fiftieth transistor T50, a gate electrode may be connected to the second Q node Q(n+1), one electrode may be connected to the second control line CS2, and the other electrode may be connected to the second node N2.

[0162] In the fifty-first transistor T51 , a gate electrode may be connected to the other electrode of the forty-sixth transistor T46 , one electrode may be connected to the first power line VSS1 , and the other electrode may be connected to one electrode of the fifty-second transistor T52 .

[0163] In the fifty-second transistor T52, a gate electrode may be connected to the third control line CS3, one electrode may be connected to the other electrode of the fifty-first transistor T51, and the other electrode may be connected to the second QB node QB(n+1).

[0164] In the fifty-third transistor T53 , a gate electrode may be connected to the second Q node Q(n+1), one electrode may be connected to the second QB node QB(n+1), and the other electrode may be connected to the first power line VSS1 .

[0165] In the fifty-fourth transistor T54, a gate electrode may be connected to the n-3 th carry line CR(n-3), one electrode may be connected to the second QB node QB(n+1), and the other electrode may be connected to the first power line VSS1.

[0166] In the fifty-fifth transistor T55, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the first power line VSS1, and the other electrode may be connected to the second Q node Q(n+1).

[0167] In an exemplary embodiment, the fifty-fifth transistor T55 may include a nineteenth sub-transistor T55a and a twentieth sub-transistor T55b connected in series. In the nineteenth sub-transistor T55a, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the first power line VSS1, and the other electrode may be connected to the second node N2. In the twentieth sub-transistor T55b, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the second node N2, and the other electrode may be connected to the second Q node Q(n+1).

[0168] In the fifty-sixth transistor T56, a gate electrode may be connected to the n+4th carry line CR(n+4) (or the first reset carry line), one electrode may be connected to the first power line VSS1, and the other electrode may be connected to the second Q node Q(n+1).

[0169] In an exemplary embodiment, the fifty-sixth transistor T56 may include a twenty-first sub-transistor T56a and a twenty-second sub-transistor T56b. In the twenty-first sub-transistor T56a, a gate electrode may be connected to the n+4th carry line CR(n+4), one electrode may be connected to the first power supply line VSS1, and the other electrode may be connected to the second node N2. In the twenty-second sub-transistor T56b, a gate electrode may be connected to the n+4th carry line CR(n+4), one electrode may be connected to the second node N2, and the other electrode may be connected to the second Q node Q(n+1).

[0170] In the fifty-seventh transistor T57 , a gate electrode may be connected to the fourth control line CS4 , one electrode may be connected to the gate electrode of the forty-eighth transistor T48 (or one electrode of the sixth capacitor C6 ), and the other electrode may be connected to the first power line VSS1 .

[0171] In an exemplary embodiment, the fifty-seventh transistor T57 may include a twenty-third sub-transistor T57a and a twenty-fourth sub-transistor T57b. In the twenty-third sub-transistor T57a, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the gate electrode of the forty-eighth transistor T48 (or one electrode of the sixth capacitor C6), and the other electrode may be connected to one electrode of the twenty-fourth sub-transistor T57b (or the other electrode of the forty-fifth transistor T45). In the twenty-fourth sub-transistor T57b, a gate electrode may be connected to the fourth control line CS4, one electrode may be connected to the other electrode of the twenty-third sub-transistor T57a, and the other electrode may be connected to the first power supply line VSS1.

[0172] In the fifty-eighth transistor T58, a gate electrode may be connected to the other electrode of the forty-sixth transistor T46, one electrode may be connected to the second control line CS2, and the other electrode may be connected to one electrode of the forty-sixth transistor T46.

[0173] Figure 5 The diagram is driven during the display period Figure 3 Waveform diagram of the scan driver method.

[0174] First, refer to Figures 3 to 5 , shows signals applied to the first control line CS1, the second control line CS2, the third control line CS3, the fourth control line CS4, the scan clock lines SCCK1 to SCCK6, the sense clock lines SSCK1 to SSCK6, the carry clock lines CRCK1 to CRCK6, the n-3th carry line CR(n-3) (or the first scan carry line), the nth scan line SCn (or the first scan line), the n+1th scan line SC(n+1) (or the second scan line), the nth sense line SSn (or the first sense line), the n+1th sense line SS(n+1) (or the second sense line), the nth carry line CRn (the first carry line or the first sense carry line) and the n+1th carry line CR(n+1) (the second carry line or the second sense carry line).

[0175] In the display period, the phases of the scan clock signal, sense clock signal and carry clock signal applied to the corresponding scan clock line, sense clock line and carry clock line connected to the same scan stage may be the same. Figure 5In the figure, the signals of the first clock lines SCCK1, SSCK1 and CRCK1 are shown together, the signals of the second clock lines SCCK2, SSCK2 and CRCK2 are shown together, the signals of the third clock lines SCCK3, SSCK3 and CRCK3 are shown together, the signals of the fourth clock lines SCCK4, SSCK4 and CRCK4 are shown together, the signals of the fifth clock lines SCCK5, SSCK5 and CRCK5 are shown together, and the signals of the sixth clock lines SCCK6, SSCK6, CRCK6 are shown together.

[0176] However, the magnitudes of the scan clock signal, sense clock signal and carry clock signal applied to the corresponding scan clock line, sense clock line and carry clock line connected to the same scan level may be different from each other. For example, the low level (or logic low level) of the scan clock signal and the sense clock signal may correspond to the magnitude of the voltage applied to the second power line VSS2, and the high level (or logic high level) may correspond to the magnitude of the conduction voltage. In addition, the low level of the carry clock signal may correspond to the magnitude of the voltage applied to the first power line VSS1 or the third power line VSS3, and the high level may correspond to the magnitude of the conduction voltage. For example, the voltage applied to the second power line VSS2 may be greater than the voltage applied to the first power line VSS1 or the third power line VSS3.

[0177] The magnitude of the turn-on voltage is high enough to turn on the transistor, and the voltage applied to the power lines VSS1, VSS2, and VSS3 may be large enough to turn off the transistor. Hereinafter, a voltage level corresponding to the magnitude of the turn-on voltage may be represented as a high level, and a voltage level corresponding to the magnitude of the voltage applied to the power lines VSS1, VSS2, and VSS3 may be represented as a low level.

[0178] The high level pulses of the second clock lines SCCK2, SSCK2 and CRCK2 may be delayed in phase compared to the high level pulses of the first clock lines SCCK1, SSCK1 and CRCK1, and may partially overlap in time with the high level pulses of the first clock lines SCCK1, SSCK1 and CRCK1. For example, the high level pulses may have a length (or width) of two horizontal periods, and the overlapping length may correspond to one horizontal period. For example, the high level pulses of the second clock lines SCCK2, SSCK2 and CRCK2 may be delayed by one horizontal period compared to the high level pulses of the first clock lines SCCK1, SSCK1 and CRCK1.

[0179] Similarly, the high level pulse of the third clock line SCCK3, SSCK3 and CRCK3 can be delayed in phase than the high level pulse of the second clock line SCCK2, SSCK2 and CRCK2, and can partially overlap with the high level pulse of the second clock line SCCK2, SSCK2 and CRCK2 in time. The high level pulse of the fourth clock line SCCK4, SSCK4 and CRCK4 can be delayed in phase than the high level pulse of the third clock line SCCK3, SSCK3 and CRCK3, and can partially overlap with the high level pulse of the third clock line SCCK3, SSCK3 and CRCK3 in time. The high level pulse of the fifth clock line SCCK5, SSCK5 and CRCK5 can be delayed in phase than the high level pulse of the fourth clock line SCCK4, SSCK4 and CRCK4, and can partially overlap with the high level pulse of the fourth clock line SCCK4, SSCK4 and CRCK4 in time. The high level pulses of the sixth clock lines SCCK6, SSCK6, and CRCK6 may be delayed in phase than the high level pulses of the fifth clock lines SCCK5, SSCK5, and CRCK5, and may partially overlap in time with the high level pulses of the fifth clock lines SCCK5, SSCK5, and CRCK5. In addition, repeatedly, the high level pulses of the first clock lines SCCK1, SSCK1, and CRCK1 may be delayed in phase than the high level pulses of the sixth clock lines SCCK6, SSCK6, and CRCK6, and may partially overlap in time with the high level pulses of the sixth clock lines SCCK6, SSCK6, and CRCK6.

[0180] Hereinafter, the operation of the n-th scanning stage STn in the display period will be described. Since the operations of the other scanning stages are similar to those of the n-th scanning stage STn, repeated descriptions will be omitted.

[0181] At the first time point TP1, a high level pulse may be applied to the fourth control line CS4. In this case, the twentieth transistors T20a and T20b may be turned on, and the first Q node Qn may be discharged to a low level. In addition, the nineteenth transistors T19a and T19b may be turned on, and the first capacitor C1 may be discharged. For example, the voltage written to the gate electrode of the first capacitor C1 and the fifth transistor T5 may be reset.

[0182] At the second time point TP2, a high level pulse may appear in the n-3 carry line CR(n-3). In this case, the second transistors T2a and T2b may be turned on, and the first Q node Qn may be charged to a high level. The seventh transistor T7 may be turned on in response to the node voltage of the first Q node Qn, and the first node N1 may be charged to a high level applied to the second control line CS2.

[0183] At the third time point TP3, a high level pulse may appear in the fifth clock lines SCCK5, SSCK5, and CRCK5. In this case, the voltage of the first Q node Qn may be boosted to a level higher than the high level by the second capacitor C2 and the third capacitor C3, and the high level pulse may be output to the nth scan line SCn, the nth sensing line SSn, and the nth carry line CRn. In this case, the third transistor T3 may be turned on in response to the high level pulse of the nth carry line CRn.

[0184] On the other hand, although the first Q node Qn voltage is boosted, since a high level voltage is applied to the first node N1, the voltage difference between the drain electrode and the source electrode of the transistors T5, T2b, T20a, T10a, T12a, and T11a may be relatively small. Therefore, the degradation of the transistors T5, T2b, T20a, T10a, T12a, and T11a may be prevented.

[0185] At the fourth time point TP4, when a high-level pulse appears in the sixth clock line SCCK6, SSCK6 and CRCK6, similar to the operation of the nth scanning stage STn at the third time point TP3, a high-level pulse can be output from the n+1th scanning stage ST(n+1) to the n+1th scanning line SC(n+1), the n+1th sensing line SS(n+1) and the n+1th carry line CR(n+1).

[0186] At the fourth time point TP4, a high level pulse (or first pulse) may appear in the first control line CS1. In this case, the fourth transistor T4 may be turned on. A high level voltage may be written to the other electrode of the first capacitor C1 through the turned-on third transistor T3 and the turned-on fourth transistor T4. That is, when a high level pulse appears in the first control line CS1, a high level voltage may be written only to the other electrode of the first capacitor C1 of the nth scanning stage STn in which the high level pulse appears in the nth carry line CRn and the n+1th carry line CR(n+1), and the nth scanning stage STn may be selected as one of the stages operated in the sensing period to be described later.

[0187] At the fifth time point TP5, since the low level signal is applied to the fifth clock lines SCCK5, SSCK5, and CRCK5, the voltage of the first Q node Qn that has been boosted to be higher than the high level may drop to the high level. For example, at the fifth time point TP5, the voltage of the first Q node Qn may drop to the same value as the voltage of the first Q node Qn that was charged to the high level at the second time point TP2.

[0188] At the sixth time point TP6, a high level pulse may appear in the first reset carry line CR(n+4). In this case, the first Q node Qn may be connected to the first power line VSS1 through the tenth transistors T10a and T10b and discharged to a low level.

[0189] At the seventh time point TP7, a high level pulse may appear in the n+5th carry line CR(n+5).

[0190] At the eighth time point TP8, a high level pulse (or a second pulse) may appear in the first control line CS1. In this case, the fourth transistor T4 may be turned on.

[0191] However, at the eighth time point TP8, since a low-level signal is applied to the nth carry line CRn, the third transistor T3 may be turned off or maintained in a turned-off state, the low-level signal of the n+1th carry line CR(n+1) may not be transmitted to the other electrode of the first capacitor C1, and the high-level voltage written to the other electrode of the first capacitor C1 at the fourth time point TP4 may be maintained.

[0192] At the same time, at the eighth time point TP8, the high level pulse output at the seventh time point TP7 can be maintained in the n+5th carry line CR(n+5). That is, the high level pulse can be applied to the n+5th carry line CR(n+5). In addition, at the eighth time point TP8, the high level pulse can appear in the n+6th carry line CR(n+6). In this case, the n+5th carry line CR(n+5) and the n+6th carry line CR(n+6) can be used as the first sensing carry line and the second sensing carry line to write the high level voltage to the first capacitor C1 of the scanning stage (for example, the n+5th scanning stage ST(n+5) of the fifth scanning stage from the nth scanning stage STn), and together with the nth scanning stage STn, the stage can be selected as one of the stages operating in the sensing period.

[0193] In an exemplary embodiment, a high-level control signal may be alternately applied to the fifth control line CS5 and the sixth control line CS6 in a specific time period unit. The specific time period unit may correspond to, for example, a plurality of frame segments. To describe the control signal applied to the fifth control line CS5 and the sixth control line CS6, reference may be made to Figure 6 .

[0194] Figure 6 The diagram is applied to Figure 3 Diagram of the control signals of the scan driver.

[0195] refer to Figure 6Each of the frame periods (or frames) FRAME1 and FRAME2 may include a display period P_DISP and a sensing period P_BLANK. In the display period P_DISP, the signal of the first control line CS1, the signal of the second control line CS2, the signal of the third control line CS3, and the signal of the fourth control line CS4 are connected to the reference Figure 5 The signal of the first control line CS1, the signal of the second control line CS2, the signal of the third control line CS3 and the signal of the fourth control line CS4 described in the drawings are substantially the same. Therefore, the completely identical description will not be repeated. Meanwhile, reference will be made later to Figure 7 A signal of the first control line CS1 , a signal of the second control line CS2 , a signal of the third control line CS3 , and a signal of the fourth control line CS4 in the sensing period P_BLANK are described.

[0196] During the first frame period FRAME1, a high-level control signal may be applied to the fifth control line CS5, and a low-level control signal may be applied to the sixth control line CS6. In this case, the twenty-fifth transistor T25 and the twenty-sixth transistor T26 may be turned on, and thus the first QB node QBn may be charged to a high level. Therefore, the eleventh transistors T11a and T11b may be turned on, and thus the first Q node Qn may be discharged to a low level, the thirteenth transistor T13 may be turned on, and thus the n-th carry line CRn may be discharged to a low level, the fifteenth transistor T15 may be turned on, and thus the n-th sense line SSn may be discharged to a low level, and the seventeenth transistor T17 may be turned on, and thus the n-th scan line SCn may be discharged to a low level.

[0197] During the second frame period FRAME2, a low-level control signal may be applied to the fifth control line CS5, and a high-level control signal may be applied to the sixth control line CS6. In this case, the 35th transistor T35 and the 36th transistor T36 may be turned on, and therefore the second QB node QB (n + 1) may be charged to a high level. Therefore, the 12th transistor T12a and T12b may be turned on, and therefore the first Q node Qn may be discharged to a low level, the 14th transistor T14 may be turned on, and therefore the nth carry line CRn may be discharged to a low level, the 16th transistor T16 may be turned on, and therefore the nth sense line SSn may be discharged to a low level, and the 18th transistor T18 may be turned on, and therefore the nth scan line SCn may be discharged to a low level.

[0198] Therefore, a period in which an on bias is applied to a transistor used during the first frame period FRAME1 and the second frame period FRAME2 can be shortened, and degradation of the transistor can be prevented.

[0199] According to reference Figure 5 The drive of the scan driver described above, a high level pulse can be applied to the reference during the display period of a frame period. Figure 2 The scan line SCi and the sensing line SSi described above. At this time, the corresponding data signal may be applied to the data line Dj, and the first reference voltage may be applied to the receiving line Rj. Therefore, the reference Figure 2 The storage capacitor Cst described may store a voltage corresponding to the difference between the data signal and the first reference voltage when the second thin film transistor M2 and the third thin film transistor M3 are turned on. Thereafter, when the second thin film transistor M2 and the third thin film transistor M3 are turned off, the amount of driving current flowing through the first thin film transistor M1 may be determined corresponding to the voltage stored in the storage capacitor Cst, and the light emitting element LD may emit light at a brightness corresponding to the amount of driving current.

[0200] As reference Figure 4 and Figure 5 As described, a high-level signal may be applied to the first control line CS1 corresponding to a time period in which a high-level signal is applied to both adjacent carry lines. Therefore, a high-level voltage may be written to the first capacitor C1 (or the sixth capacitor C6) of the scanning stage using two adjacent carry lines as the first sensing carry line and the second sensing carry line, corresponding to the signal of the first control line CS1, and the scanning stage may be selected as one of the stages that operate in the sensing period to output a signal in the sensing period. Alternatively, at the first capacitor C1 (or the sixth capacitor C6) of the scanning stage that does not use any of the two adjacent carry lines as the sensing carry line (the first sensing carry line and the second sensing carry line), a low-level voltage may be maintained, and the scanning stage may not output a signal to the scanning line and the sensing line in the sensing period. Therefore, only the scanning stage selected as the stage that operates in the sensing period may output a signal in the sensing period.

[0201] Figure 7 The diagram shows the driving during the sensing period. Figure 3 Waveform diagram of the scan driver method.

[0202] refer to Figure 4 and Figure 7 , shows signals applied to the third control line CS3, the fourth scan clock line SCCK4, the fourth sensing clock line SSCK4, the fifth scan clock line SCCK5, the fifth sensing clock line SSCK5, the carry clock lines CRCK1 to CRCK6, the nth scan line SCn, the n+5th scan line SC(n+5), the nth carry line CRn, the n+5th carry line CR(n+5), the nth sensing line SSn and the n+5th sensing line SS(n+5).

[0203] At the ninth time point TP9, a high level pulse may appear in the third control line CS3. In this case, the sixth transistor T6 (reference Figure 4 ) can be turned on. Since the first capacitor C1 is at a voltage during the display period (ie, reference Figure 5 The state that is charged during the period between the fourth time point TP4 and the fifth time point TP5 described above, so the fifth transistor T5 can be turned on. Therefore, the high level voltage applied to the second control line CS2 can be applied to the first Q node Qn through the fifth transistor T5 and the sixth transistor T6.

[0204] At this time, since the fifth transistor (or the forty-eighth transistor) is turned off in the scanning stages except the n-th scanning stage STn, the first Q node and the second Q node of the other scanning stages can maintain a low level.

[0205] As reference Figure 4 As described, the n+5th scanning stage ST(n+5) may include a configuration substantially the same as the n+1th scanning stage ST(n+1). In an exemplary embodiment, the sixth capacitor C6 of the n+5th scanning stage ST(n+5) may be in a state where the voltage is charged during the display period. In this case, the 48th transistor T48 may be turned on. In addition, since the high level pulse appears in the third control line CS3, and therefore the 47th transistor T47 is also turned on, the high level voltage applied to the second control line CS2 may also be applied to the second Q node Q(n+1) through the 47th transistor T47 and the 48th transistor T48.

[0206] Thereafter, at the tenth time point TP10, a high level signal may be applied to the fifth scan clock line SCCK5 and the fifth sense clock line SSCK5. In this case, the voltage of the first Q node Qn may be boosted by the second capacitor C2 and the third capacitor C3 (reference Figure 4 ), and the high level signal may be output to the nth scan line SCn and the nth sensing line SSn.

[0207] Therefore, the thin film transistors M2 and M3 (refer to FIG. 1 ) of the pixels connected to the nth scan line SCn and the nth sensing line SSn. Figure 2 ) may be turned on. In this case, the second reference voltage may be applied to the data lines Dj, . . . , and the sensing unit 14 (reference voltage) Figure 1 ) can measure the degradation information or characteristic information of the pixel based on the current value or voltage value received through the receiving lines Rj,...

[0208] However, at the tenth time point TP10, a low level signal may be applied to the fourth scan clock line SCCK4 and the fourth sensing clock line SSCK4. Therefore, a low level signal may be output to the n+5th scan line SC(n+5) and the n+5th sensing line SS(n+5).

[0209] In addition, since the node corresponding to the first Q node Qn or the second Q node Q(n+1) in other scanning levels other than the nth scanning level STn (for example, the level connected to the fifth scanning clock line SCCK5 and the fifth sensing clock line SSCK5) is at a low level, regardless of the high level pulse applied to the fifth scanning clock line SCCK5 and the fifth sensing clock line SSCK5, a low level signal can also be output to the corresponding scanning line and sensing line.

[0210] At the eleventh time point TP11, a high level signal may be applied to the fifth scan clock line SCCK5 and the fifth sense clock line SSCK5. In this case, the most recent previous data signal may be applied to the data line again. Therefore, the pixel connected to the nth scan line SCn and the nth sense line SSn may emit light again at a grayscale based on the most recent previous data signal.

[0211] That is, during the period between the tenth time point TP10 and the eleventh time point TP11, the pixels connected to the nth scan line SCn and the nth sensing line SSn may not emit light in grayscale based on the data signal. However, after the eleventh time point TP11, the pixels connected to the nth scan line SCn and the nth sensing line SSn emit light in grayscale based on the data signal again, and the pixels connected to other scan lines and sensing lines may continue to emit light in grayscale based on the data signal during the sensing period. Therefore, there may be no problem of the user recognizing the frame.

[0212] Thereafter, at the twelfth time point TP12, a high level signal may be applied to the fourth scan clock line SCCK4 and the fourth sense clock line SSCK4. In this case, the voltage of the second Q node Q(n+1) may be connected to the fourth capacitor C4 and the fifth capacitor C5 (reference Figure 4 ) is boosted, and a high level signal may be output to the n+5th scan line SC(n+5) and the n+5th sensing line SS(n+5).

[0213] Therefore, the thin film transistors M2 and M3 (refer to FIG. 1 ) of the pixels connected to the n+5th scan line SC(n+5) and the n+5th sensing line SS(n+5) are connected to the thin film transistors M2 and M3 of the pixels connected to the n+5th scan line SC(n+5) and the n+5th sensing line SS(n+5). Figure 2 ) may be turned on. In this case, the second reference voltage may be applied to the data lines Dj, . . . , and the sensing unit 14 (reference voltage) Figure 1) can measure the degradation information or characteristic information of the pixel based on the current value or voltage value received through the receiving lines Rj,...

[0214] At the thirteenth time point TP13, a high level signal may be applied to the fourth scan clock line SCCK4 and the fourth sense clock line SSCK4. In this case, the most recent previous data signal may be applied to the data line again. Therefore, the pixel connected to the n+5th scan line SC(n+5) and the n+5th sense line SS(n+5) may emit light again at a grayscale based on the most recent previous data signal.

[0215] However, the time points when the high-level signal is applied to the scan clock lines SCCK4 and SCCK5 and the sense clock lines SSCK4 and SSCK5 in the sensing period are exemplary. The high-level signal can be applied to the fourth scan clock line SCCK4 and the fourth sense clock line SSCK4 at the tenth time point TP10, and the high-level signal can be applied to the fifth scan clock line SCCK5 and the fifth sense clock line SSCK5 at the twelfth time point TP12.

[0216] As reference Figure 7 As described, the degradation information or characteristic information of the pixels connected to the nth scan line SCn and the nth sensing line SSn can be measured by applying a high level signal to the fifth scan clock line SCCK5 and the fifth sensing clock line SSCK5 in the period between the tenth time point TP10 and the eleventh time point TP11. In addition, the degradation information or characteristic information of the pixels connected to the n+5th scan line SC(n+5) and the n+5th sensing line SS(n+5) can be measured by applying a high level signal to the fourth scan clock line SCCK4 and the fourth sensing clock line SSCK4 in the period between the twelfth time point TP12 and the thirteenth time point TP13. That is, the characteristics of the pixels included in different pixel rows can be sensed (or sensed multiple times) during one frame period, and the number of pixels used to sense the pixel unit 15 (reference time) can be reduced. Figure 1 ) can be used to measure the total time (or sensing period) of the characteristics of all pixels in the image, and the characteristics of the pixels can be further compensated in real time.

[0217] Figure 8 It is used to describe the drive Figure 3 FIG. 1 is a diagram of a method of scanning a drive.

[0218] refer to Figure 8 , shows signals applied to the first control line CS1, the scan clock lines SCCK1 to SCCK6, and the sense clock lines SSCK1 to SSCK6.

[0219] In the display period P_DISP, the signals respectively applied to the scan clock lines SCCK1 to SCCK6 and the sense clock lines SSCK1 to SSCK6 may have the same values ​​as the reference clock lines SCCK1 to SCCK6. Figure 5 The signals respectively applied to the scan clock lines SCCK1 to SCCK6 and the sense clock lines SSCK1 to SSCK6 are described as being substantially the same or having the same waveform, and thus an identical description will not be repeated.

[0220] In the display period P_DISP, the signal of the first control line CS1 may include a plurality of high level pulses. For example, the signal of the first control line CS1 may include first to sixth pulses PS1 to PS6 having a high level.

[0221] The first pulse PS1 may overlap with a period during which a high-level signal is applied to the first scan clock line SCCK1 and the first sense clock line SSCK1 and a high-level signal is applied to the second scan clock line SCCK2 and the second sense clock line SSCK2. However, this is exemplary, and the first pulse PS1 may overlap with a period during which a high-level signal is applied to the second scan clock line SCCK2 and the second sense clock line SSCK2 and a high-level signal is applied to the third scan clock line SCCK3 and the third sense clock line SSCK3.

[0222] Similarly, the second pulse PS2 may overlap with a period during which a high-level signal is applied to the second scan clock line SCCK2 and the second sensing clock line SSCK2 and a high-level signal is applied to the third scan clock line SCCK3 and the third sensing clock line SSCK3, the third pulse PS3 may overlap with a period during which a high-level signal is applied to the third scan clock line SCCK3 and the third sensing clock line SSCK3 and a high-level signal is applied to the fourth scan clock line SCCK4 and the fourth sensing clock line SSCK4, and the fourth pulse PS4 may overlap with a period during which a high-level signal is applied to the fourth scan clock line SCCK4 and the fourth sensing clock line SSCK4. CK4 and a high level signal is applied to the fifth scan clock line SCCK5 and the fifth sense clock line SSCK5 during the overlap, the fifth pulse PS5 can overlap with the period during which the high level signal is applied to the fifth scan clock line SCCK5 and the fifth sense clock line SSCK5 and the high level signal is applied to the sixth scan clock line SCCK6 and the sixth sense clock line SSCK6, and the sixth pulse PS6 can overlap with the period during which the high level signal is applied to the sixth scan clock line SCCK6 and the sixth sense clock line SSCK6 and the high level signal is applied to the first scan clock line SCCK1 and the first sense clock line SSCK1. That is, the first pulse PS1 to the sixth pulse PS6 can correspond to two adjacent scan clock lines that are different from each other (and two adjacent random sense clock lines that are different from each other) having a high level. In this case, the front scan level of the two scan levels respectively connected to the two adjacent scan clock lines that are different from each other (and two adjacent sense clock lines that are different from each other) can be selected as the level operated in the sensing period.

[0223] Thereafter, a high level signal may be sequentially applied to the scan clock lines SCCK1 to SCCK6 and the sense clock lines SSCK1 to SSCK6 in the sensing period P_BLANK. The signals respectively applied to the scan clock lines SCCK1 to SCCK6 may have the same level as the reference clock lines SCCK1 to SCCK6. Figure 7 The signal described above (ie, the signal applied to the fifth scan clock line SCCK5) may have substantially the same or the same waveform as the reference clock line SSCK1, SSCK6, and the signals applied to the sense clock lines SSCK1 to SSCK6 may have substantially the same or the same waveform as the reference clock line SSCK5. Figure 7 The described signals (ie, the signal applied to the fifth sensing clock line SSCK5) are substantially the same or have the same waveform. Therefore, the exactly the same description will not be repeated.

[0224] By sequentially applying high-level signals to the scan clock lines SCCK1 to SCCK6 and the sense clock lines SSCK1 to SSCK6, the selected stages in the display period P_DISP can be sequentially operated, and the high-level signals can be output to the corresponding scan lines and sense lines. Therefore, the characteristics of the pixels included in the six pixel rows can be sensed (or sensed multiple times) during the sensing period P_BLANK.

[0225] Meanwhile, although the signal applied to the first control line CS1 is Figure 8 The display period P_DISP in FIG. 1 includes six pulses, but this is exemplary and not limited thereto. For example, the signal applied to the first control line CS1 may include two to five pulses during the display period P_DISP. As another example, when the scan driver 13 (refer to FIG. 1 ) Figure 1 ) includes k scan clock lines and k sensing clock lines that are different from each other, the signal applied to the first control line CS1 may include k pulses during the display period P_DISP.

[0226] Fig. 9 The diagram is included in Figure 3 A circuit diagram of another example of the m-th stage group in a scan driver.

[0227] refer to Figure 4 and Fig. 9 , Fig. 9 The mth level group STGm_1 and Figure 4 The m-th stage group STGm is substantially the same or similar except for the connection configuration of the third transistor T3, the fourth transistor T4, the forty-fifth transistor T45 and the forty-sixth transistor T46. Therefore, the exactly the same description will not be repeated.

[0228] One electrode of the third transistor T3 may be connected to the first control line CS1, and a gate electrode of the fourth transistor T4 may be connected to the n+1th carry line CR(n+1) (or the second sensing carry line).

[0229] One electrode of the forty-fifth transistor T45 may be connected to the first control line CS1, and a gate electrode of the forty-sixth transistor T46 may be connected to the n+2 th carry line CR(n+2).

[0230] refer to Figure 5 and Fig. 9 , a high level pulse may be applied to the nth carry line CRn and the n+1th carry line CR(n+1). In this case, the third transistor T3 and the fourth transistor T4 may be turned on, or may maintain a turned-on state.

[0231] In addition, at the fourth time point TP4, a high level pulse may appear in the first control line CS1. Therefore, a high level voltage may be written to the other electrode of the first capacitor C1 through the turned-on third transistor T3 and the turned-on fourth transistor T4. That is, when a high level pulse appears in the first control line CS1, a high level voltage may be written only to the other electrode of the first capacitor C1 of the nth scanning stage STn in which the high level pulse appears in the nth carry line CRn and the n+1th carry line CR(n+1), and the nth scanning stage STn may be selected as one of the stages operated in the sensing period to be described later.

[0232] Fig.10 The diagram is included in Figure 1 FIG. 1 is a diagram of another example of a scan driver in a display device of FIG.

[0233] refer to Figure 3 and Fig.10 , Fig.10 The scanning driver 13_1 and Figure 3 The difference of the scan driver 13 is that Fig.10 The scan driver 13_1 is connected to the first sub-control line CS1a and the second sub-control line CS1b instead of the first control line CS1. Fig.10 The scanning driver 13_1 and Figure 3 The scan driver 13 is substantially the same or similar, and thus the exact same description will not be repeated.

[0234] The scan driver 13_1 may include a plurality of stage groups ... STG(m-2)_2, STG(m-1)_2, STGm_2, STG(m+1)_2, STG(m+2)_2, and ...

[0235] Each of the stage groups STG(m-2)_2 to STG(m+2)_2 may include a first scanning stage and a second scanning stage. The first scanning stage may be an odd-numbered scanning stage, and the second scanning stage may be an even-numbered scanning stage. For example, the m-2th level group STG(m-2)_2 may include the n-4th (where n is an integer equal to or greater than 4) scanning level ST(n-4)_2 and the n-3th scanning level ST(n-3)_2, the m-1th level group STG(m-1)_2 may include the n-2th scanning level ST(n-2)_2 and the n-1th scanning level ST(n-1)_2, the m-1th level group STGm_2 may include the nth scanning level STn_2 and the n+1th scanning level ST(n+1)_2, the m+1th level group STG(m+1)_2 may include the n+2th scanning level ST(n+2)_2 and the n+3th scanning level ST(n+3)_2, and the m+2th level group STG(m+2)_2 may include the n+4th scanning level ST(n+4)_2 and the n+5th scanning level ST(n+5)_2. Each of the n-4th scanning level ST(n-4)_2, the n-2th scanning level ST(n-2)_2, the nth scanning level STn_2, the n+2th scanning level ST(n+2)_2 and the n+4th scanning level ST(n+4)_2 can be an odd scanning level, and each of the n-3rd scanning level ST(n-3)_2, the n-1th scanning level ST(n-1)_2, the n+1th scanning level ST(n+1)_2, the n+3rd scanning level ST(n+3)_2 and the n+5th scanning level ST(n+5)_2 can be an even scanning level.

[0236] Each of the scanning stages ST(n-4)_2 to ST(n+5)_2 may be connected to the first sub-control line CS1a or the second sub-control line CS1b. Each of the first scanning stages (or odd-numbered scanning stages) included in each of the stage groups STG(m-2)_2 to STG(m+2)_2 may be connected to the first sub-control line CS1a. A common control signal may be applied to the first scanning stage (or odd-numbered scanning stage) through the first sub-control line CS1a.

[0237] Similarly, each of the second scanning stages (or even scanning stages) included in each of the stage groups STG(m-2)_2 to STG(m+2)_2 may be connected to the second sub control line CS1b. A common control signal may be applied to the second scanning stages (or even scanning stages) through the second sub control line CS1b.

[0238] However, this is exemplary, and the connection relationship between the stage groups STG(m-2)_2 to STG(m+2)_2 and the first and second sub-control lines CS1a and CS1b is not limited thereto. For example, each of the first scanning stages (or odd-numbered scanning stages) included in each of the stage groups STG(m-2)_2 to STG(m+2)_2 may be connected to the second sub-control line CS1b, and each of the second scanning stages (or even-numbered scanning stages) included in each of the stage groups STG(m-2)_2 to STG(m+2)_2 may be connected to the first sub-control line CS1a.

[0239] Fig.11 The diagram is included in Fig.10 A circuit diagram of an example of the m-th stage group in a scan driver.

[0240] refer to Figure 4 and Fig.11 , Fig.11 The mth level group STGm_2 and Figure 4 The m-th stage group STGm is substantially the same or similar except for the connection configuration of the third transistor T3, the fourth transistor T4, the forty-fifth transistor T45 and the forty-sixth transistor T46. Therefore, the exactly the same description will not be repeated.

[0241] A gate electrode and one electrode of the third transistor T3 may be connected to the nth carry line CRn (or the first sensing carry line), and a gate electrode of the fourth transistor T4 may be connected to the first sub control line CS1a.

[0242] The gate electrode and one electrode of the forty-fifth transistor T45 may be connected to the n+1th carry line CR(n+1) (or the second sensing carry line), and the gate electrode of the forty-sixth transistor T46 may be connected to the second sub control line CS1b.

[0243] Fig.12 The diagram is driven during the display period Fig.10 Waveform diagram of the scan driver method.

[0244] exist Figures 10 to 12 In, due to the reference Figures 10 to 12 The method of driving the scanning driver described in the reference Figures 3 to 5 The described methods of driving the scan driver are substantially the same or similar, and thus the exact same description will not be repeated.

[0245] refer to Figures 10 to 12, shows signals applied to the first sub-control line CS1a, the second sub-control line CS1b, the second control line CS2, the third control line CS3, the fourth control line CS4, the scan clock lines SCCK1 to SCCK6, the sense clock lines SSCK1 to SSCK6, the carry clock lines CRCK1 to CRCK6, the n-3th carry line CR(n-3) (or the first scan carry line), the nth scan line SCn (or the first scan line), the n+1th scan line SC(n+1) (or the second scan line), the nth sense line SSn (or the first sense line), the n+1th sense line SS(n+1) (or the second sense line), the nth carry line CRn (the first carry line or the first sense carry line) and the n+1th carry line CR(n+1) (the second carry line or the second sense carry line).

[0246] At the third time point TP3, a high level pulse may be output to the n-th carry line CRn. In this case, the third transistor T3 may be turned on in response to the high level pulse of the n-th carry line CRn.

[0247] In addition, at the fourth time point TP4, a high level pulse may appear in the first sub-control line CS1a. In this case, the fourth transistor T4 may be turned on. The high level voltage may be written to the other electrode of the first capacitor C1 through the turned-on third transistor T3 and the turned-on fourth transistor T4. That is, when the high level pulse appears in the first sub-control line CS1a, the high level voltage may be written only to the other electrode of the first capacitor C1 of the nth scanning stage STn in which the high level pulse appears in the nth carry line CRn, and the nth scanning stage STn may be selected as one of the stages operated in the sensing period.

[0248] Meanwhile, at the fourth time point TP4, a high level pulse may be applied to the n+1th carry line CR(n+1). In this case, the forty-fifth transistor T45 may be turned on.

[0249] However, at the fourth time point TP4, since the low level pulse is applied to the second sub-control line CS1b, the 46th transistor T46 may be turned off or maintained in an off state. Since the 46th transistor T46 is turned off, the low level voltage of one electrode of the sixth capacitor C6 may be maintained. Therefore, the low level voltage is maintained at one electrode of the sixth capacitor C6 of the n+1 scanning stage ST(n+1) in which the high level pulse appears in the n+1 carry line CR(n+1), and the n+1 scanning stage ST(n+1) may not be selected as the stage to operate in the sensing period.

[0250] At the eighth time point TP8 , a high level pulse may appear in the second sub control line CS1 b .

[0251] However, at the eighth time point TP8, since the low level signal is applied to the n-th carry line CRn, the third transistor T3 may be turned off or maintained in an off state, and since the low level signal is applied to the first sub-control line CS1a, the fourth transistor T4 may be turned off or maintained in an off state. Therefore, the low level signal of the n-th carry line CRn may not be transmitted to the other electrode of the first capacitor C1, and the high level voltage written to the other electrode of the first capacitor C1 at the fourth time point TP4 may be maintained.

[0252] At the same time, at the eighth time point TP8, the high level pulse output at the seventh time point TP7 can be maintained in the n+5th carry line CR(n+5). That is, the high level pulse can be applied to the n+5th carry line CR(n+5). In this case, the n+5th carry line CR(n+5) can be used as the first sensing carry line to write a high level voltage to the first capacitor C1 of the scanning stage (for example, the n+5th scanning stage ST(n+5) of the fifth scanning stage from the nth scanning stage STn), and together with the nth scanning stage STn, the stage can be selected as one of the stages operating in the sensing period.

[0253] As reference Fig.11 and Fig.12 As described, the first sub-control line CS1a and the second sub-control line CS1b are alternately connected to the scanning stage. Therefore, even if a high-level signal is applied to the first sub-control line CS1a, since a low-level signal is applied to the second sub-control line CS1b, and the forty-sixth transistor T46 (or the fourth transistor T4) is turned off or remains in an off state, although a high-level signal is applied to the carry line, and therefore the forty-fifth transistor T45 (or the third transistor T3) is turned on, the scanning stage connected to the second sub-control line CS1b, which is adjacent to the scanning stage connected to the first sub-control line CS1a and selected as one of the stages to be operated in the sensing period, may not output a signal to the scanning line and the sensing line in the sensing period. Therefore, only the scanning stage selected as the stage to be operated in the sensing period may output a signal in the sensing period.

[0254] Fig.13 The diagram is applied to Fig.10 Diagram of the control signals of the scan driver.

[0255] refer to Fig.13 In addition to the signal of the first sub-control line CS1a and the signal of the second sub-control line CS1b, the waveforms of the control signals CS2, CS3, CS4, CS5 and CS6 are respectively Figure 6 The waveforms of the control signals CS2, CS3, CS4, CS5 and CS6 shown in FIG. 1 are substantially the same. Therefore, the exactly the same description will not be repeated.

[0256] In addition to the signal of the first sub-control line CS1a and the signal of the second sub-control line CS1b in the display period P_DISP, the waveforms of the control signals CS2, CS3, CS4, CS5 and CS6 are respectively the same as those of Figure 6 The waveforms of the control signals CS2, CS3, CS4, CS5 and CS6 shown in FIG. 1 are substantially the same. Therefore, the exactly the same description will not be repeated.

[0257] In addition, in the display period P_DISP, the signal of the first sub-control line CS1a and the signal of the second sub-control line CS1b are respectively connected to the reference Fig.12 The signal of the first sub-control line CS1a and the signal of the second sub-control line CS1b are described to be substantially the same, and therefore, the completely identical description will not be repeated.

[0258] In the display period P_DISP, a high level signal may be applied to the first sub-control line CS1a and the second sub-control line CS1b at different time points. Fig.11 and Fig.12 As described, even if a high-level signal is applied to the first sub-control line CS1a, the scanning level connected to the second sub-control line CS1b, which is adjacent to the scanning level connected to the first sub-control line CS1a and selected as one of the levels operating in the sensing period, may not output a signal to the scanning line and the sensing line in the sensing period.

[0259] The number of high-level pulses appearing in the first sub-control line CS1a in the display period D_DISP included in one frame period (e.g., FRAME1) may be the same as the number of high-level pulses appearing in the second sub-control line CS1b in the display period D_DISP included in the frame period. However, this is exemplary, and the number of pulses of each sub-control line may be different. For example, when sensing the characteristics of pixels included in three pixel rows during one frame period, the number of high-level pulses appearing in the first sub-control line CS1a in the display period D_DISP included in one frame period may be three, and no high-level pulses appear in the second sub-control line CS1b in the display period D_DISP included in the frame period. Alternatively, when sensing the characteristics of pixels included in three pixel rows during one frame period, the number of high-level pulses appearing in the first sub-control line CS1a in the display period D_DISP included in one frame period may be two, and the number of high-level pulses appearing in the second sub-control line CS1b in the display period D_DISP included in the frame period may be one.

[0260] Meanwhile, in the sensing period P_BLANK, a low level signal is applied to the first control line CS1 (reference Figure 6), the first sub-control line CS1a and the second sub-control line CS1b. In addition, in the sensing period P_BLANK, the signal of the second control line CS2, the signal of the third control line CS3, the signal of the fourth control line CS4, the signal of the fifth control line CS5 and the signal of the sixth control line CS6 are connected to the reference Figure 6 and Figure 7 The signal of the second control line CS2, the signal of the third control line CS3, the signal of the fourth control line CS4, the signal of the fifth control line CS5 and the signal of the sixth control line CS6 described above are substantially the same. Fig.13 The scanning driver 13_1 (reference Fig.10 ) can be operated with the reference Figure 7 The scanning driver 13 (refer to Figure 3 ) is basically the same. Therefore, the operation of scanning driver 13_1 in the sensing period (reference Fig.10 ) operations are exactly the same as described above.

[0261] Fig.14 It is used to describe the drive Fig.10 FIG. 1 is a diagram of a method of scanning a drive.

[0262] refer to Fig.14 , shows signals applied to the first sub control line CS1a, the second sub control line CS1b, the scan clock lines SCCK1 to SCCK6, and the sense clock lines SSCK1 to SSCK6.

[0263] In the display period P_DISP, the signals respectively applied to the scan clock lines SCCK1 to SCCK6 and the sense clock lines SSCK1 to SSCK6 may have the same values ​​as the reference clock lines SCCK1 to SCCK6. Figure 5 and Fig.12 The signals respectively applied to the scanning clock lines SCCK1 to SCCK6 and the sensing clock lines SSCK1 to SSCK6 are described as being substantially the same or having the same waveforms. Therefore, the exactly the same description will not be repeated.

[0264] In the display period P_DISP, the signal of the first sub-control line CS1a may include a plurality of high-level pulses. Similarly, the signal of the second sub-control line CS1b may include a plurality of high-level pulses. In an exemplary embodiment, a high-level control signal may be alternately applied to the first sub-control line CS1a and the second sub-control line CS1b. For example, the signal of the first sub-control line CS1a may include a first pulse PS1, a third pulse PS3, and a fifth pulse PS5 having a high level. In addition, the signal of the second sub-control line CS1b may include a second pulse PS2, a fourth pulse PS4, and a sixth pulse PS6 having a high level. However, this is exemplary, and the signal of the first sub-control line CS1a may include a second pulse PS2, a fourth pulse PS4, and a sixth pulse PS6 having a high level, and the signal of the second sub-control line CS1b may include a first pulse PS1, a third pulse PS3, and a fifth pulse PS5 having a high level.

[0265] refer to Figure 8 and Fig.14 , Fig.14 Scan driver 13_1 (reference Fig.10 ) can be used with reference Figure 8 The scan driver 13 described (refer to Figure 3 ) is substantially the same except that each of the signal of the first sub-control line CS1a and the signal of the second sub-control line CS1b includes a plurality of high-level pulses. Therefore, the operation of the scan driver 13_1 (reference Fig.10 ) operations are exactly the same as described above.

[0266] Fig.15 The diagram is included in Fig.10 A circuit diagram of another example of the m-th stage group in a scan driver.

[0267] refer to Fig.11 and Fig.15 , Fig.15 The mth level group STGm_3 and Fig.11 The m-th stage group STGm_2 is substantially the same or similar except for the connection configuration of the third transistor T3, the fourth transistor T4, the forty-fifth transistor T45 and the forty-sixth transistor T46. Therefore, the exactly the same description will not be repeated.

[0268] One electrode of the third transistor T3 may be connected to the first sub control line CS1 a , and a gate electrode of the fourth transistor T4 may be connected to the n th carry line CRn (or the first sensing carry line).

[0269] One electrode of the forty-fifth transistor T45 may be connected to the second sub control line CS1b, and a gate electrode of the forty-sixth transistor T46 may be connected to the n+1th carry line CR(n+1) (or the second sensing carry line).

[0270] refer to Fig.12 and Fig.15 , at the third time point TP3, a high level pulse may be applied to the nth carry line CRn. In this case, the third transistor T3 and the fourth transistor T4 may be turned on.

[0271] In addition, at the fourth time point TP4, a high level pulse may appear in the first sub control line CS1a. The high level voltage may be written to the other electrode of the first capacitor C1 through the turned-on third transistor T3 and the turned-on fourth transistor T4. That is, when the high level pulse appears in the first sub control line CS1a, the high level voltage may be written only to the other electrode of the first capacitor C1 of the nth scanning stage STn in which the high level pulse appears in the nth carry line CRn, and the nth scanning stage STn may be selected as one of the stages operating in the sensing period.

[0272] Meanwhile, at the fourth time point TP4, a high level pulse may be applied to the n+1th carry line CR(n+1). In this case, the forty-fifth transistor T45 and the forty-sixth transistor T46 may be turned on.

[0273] However, at the fourth time point TP4, since a low-level pulse is applied to the second sub-control line CS1b, a low-level voltage is written to one electrode of the sixth capacitor C6 through the turned-on forty-fifth transistor T45 and the turned-on forty-sixth transistor T46, and the n+1th scanning stage ST(n+1) may not be selected as the stage operating in the sensing period.

[0274] Although specific exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements, which are apparent to those of ordinary skill in the art.

Claims

1. A scanning driver, comprising: Multiple scan levels, The first scanning level among the plurality of scanning levels comprises: a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and an electrode connected to the first scan-in bit line and another electrode connected to the first Q node; a third transistor having a gate electrode connected to the first sense carry line and an electrode connected to the second sense carry line; a fourth transistor having a gate electrode connected to the first control line and one electrode connected to the other electrode of the third transistor; a fifth transistor having a gate electrode connected to the other electrode of the fourth transistor, one electrode connected to the second control line, and another electrode connected to the first node; a first capacitor having one electrode connected to the one electrode of the fifth transistor and the other electrode connected to the gate electrode of the fifth transistor; and A sixth transistor has a gate electrode connected to the third control line, one electrode connected to the first node, and the other electrode connected to the first Q node.

2. The scan driver according to claim 1, wherein: The first scanning stage further comprises: A seventh transistor has a gate electrode connected to the first Q node, one electrode connected to the second control line, and the other electrode connected to the first node.

3. The scan driver according to claim 1, wherein: The first control signal provided through the first control line includes a plurality of pulses during one frame; and When a pulse of a first sense-carry signal provided through the first sense-carry line and a pulse of a second sense-carry signal provided through the second sense-carry line both overlap with one of the pulses of the first control signal, the second sense-carry signal is written into the first capacitor.

4. The scan driver according to claim 2, wherein: The first scanning stage further comprises: a second capacitor having one electrode connected to the gate electrode of the first transistor and another electrode connected to the other electrode of the first transistor; an eighth transistor having a gate electrode connected to the first Q node, one electrode connected to the first sensing clock line, and another electrode connected to the first sensing line; a third capacitor having one electrode connected to the gate electrode of the eighth transistor and another electrode connected to the other electrode of the eighth transistor; and A ninth transistor has a gate electrode connected to the first Q node, one electrode connected to the first carry clock line, and the other electrode connected to the first carry line.

5. The scan driver according to claim 4, wherein: The first scanning stage further comprises: A tenth transistor has a gate electrode connected to the first reset carry line, one electrode connected to the first Q node, and the other electrode connected to the first power supply line.

6. The scan driver according to claim 5, wherein: The first scanning stage further comprises: an eleventh transistor having a gate electrode connected to the first QB node, one electrode connected to the first Q node, and the other electrode connected to the first power line; and A twelfth transistor has a gate electrode connected to the second QB node, one electrode connected to the first Q node, and the other electrode connected to the first power line.

7. The scan driver according to claim 6, wherein: The first scanning stage further comprises: a thirteenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first carry line, and another electrode connected to the first power line; a fourteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first carry line, and another electrode connected to the first power line; a fifteenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first sensing line, and another electrode connected to a second power line; a sixteenth transistor having a gate electrode connected to the second QB node, one electrode connected to the first sensing line, and another electrode connected to the second power line; a seventeenth transistor having a gate electrode connected to the first QB node, one electrode connected to the first scan line, and the other electrode connected to the second power line; and An eighteenth transistor has a gate electrode connected to the second QB node, one electrode connected to the first scan line, and the other electrode connected to the second power line.

8. The scan driver according to claim 7, wherein: The first scanning stage further comprises: A nineteenth transistor has a gate electrode connected to a fourth control line, one electrode connected to the gate electrode of the fifth transistor, and the other electrode connected to the first power line.

9. The scan driver according to claim 8, wherein: The first scanning stage further comprises: a twentieth transistor having a gate electrode connected to the fourth control line, one electrode connected to the first Q node, and another electrode connected to the first power line; a twenty-first transistor having a gate electrode connected to the first Q node, one electrode connected to the first power line, and the other electrode connected to the first QB node; and A twenty-second transistor has a gate electrode connected to the first scan-carry line, one electrode connected to the first power line, and the other electrode connected to the first QB node.

10. The scan driver according to claim 9, wherein: The first scanning stage further comprises: a twenty-third transistor having a gate electrode connected to the other electrode of the fourth transistor and one electrode connected to the first power supply line; and A twenty-fourth transistor has a gate electrode connected to the third control line, one electrode connected to the other electrode of the twenty-third transistor, and the other electrode connected to the first QB node.

11. The scan driver according to claim 10, wherein: The first scanning stage further comprises: a twenty-fifth transistor having a gate electrode connected to a fifth control line and an electrode; and The twenty-sixth transistor has a gate electrode connected to the other electrode of the twenty-fifth transistor, one electrode connected to the fifth control line, and the other electrode connected to the first QB node.

12. The scan driver according to claim 11, wherein: The first scanning stage further comprises: a twenty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and the other electrode connected to a third power supply line; and The twenty-eighth transistor has a gate electrode connected to the second Q node, one electrode connected to the gate electrode of the twenty-sixth transistor, and the other electrode connected to the third power supply line.

13. The scan driver according to claim 12, wherein: The nineteenth transistor comprises: a first sub-transistor having a gate electrode connected to the fourth control line and one electrode connected to the other electrode of the fourth transistor; and a second sub-transistor having a gate electrode connected to the fourth control line, one electrode connected to the other electrode of the first sub-transistor, and the other electrode connected to the first power line; and The first scanning stage further comprises: A twenty-ninth transistor has a gate electrode connected to the other electrode of the fourth transistor, one electrode connected to the one electrode of the fourth transistor, and another electrode connected to the second control line.

14. The scan driver according to claim 13, wherein: A second scanning stage among the plurality of scanning stages comprises: a thirtieth transistor having a gate electrode connected to the second Q node, one electrode connected to the second scan line, and another electrode connected to the second scan clock line; a fourth capacitor connecting the gate electrode and the one electrode of the thirtieth transistor to each other; a thirty-first transistor having a gate electrode connected to the second Q node, one electrode connected to a second sensing line, and another electrode connected to a second sensing clock line; a fifth capacitor connecting the gate electrode and the one electrode of the thirty-first transistor to each other; and The thirty-second transistor has a gate electrode connected to the second Q node, one electrode connected to the second carry line, and the other electrode connected to the second carry clock line.

15. The scan driver according to claim 14, wherein: The second scanning stage further comprises: a thirty-third transistor having a gate electrode connected to the first QB node, one electrode connected to the first power line, and the other electrode connected to the second Q node; and A thirty-fourth transistor has a gate electrode connected to the second QB node, one electrode connected to the first power line, and the other electrode connected to the second Q node.

16. The scan driver according to claim 15, wherein: The second scanning stage further comprises: A thirty-fifth transistor having a gate electrode, one electrode and another electrode, wherein the gate electrode and the another electrode of the thirty-fifth transistor are connected to a sixth control line; a thirty-sixth transistor having a gate electrode connected to the one electrode of the thirty-fifth transistor, one electrode connected to the second QB node, and another electrode connected to the sixth control line; a thirty-seventh transistor having a gate electrode connected to the first Q node, one electrode connected to the third power supply line, and the other electrode connected to the gate electrode of the thirty-sixth transistor; and A thirty-eighth transistor has a gate electrode connected to the second Q node, one electrode connected to the third power supply line, and the other electrode connected to the gate electrode of the thirty-sixth transistor.

17. The scan driver according to claim 16, wherein: The second scanning stage further comprises: a thirty-ninth transistor having a gate electrode connected to the first QB node, one electrode connected to the first power line, and another electrode connected to the second carry line; a fortieth transistor having a gate electrode connected to the second QB node, one electrode connected to the first power line, and another electrode connected to the second carry line; a forty-first transistor having a gate electrode connected to the first QB node, one electrode connected to the second power line, and another electrode connected to the second sensing line; a forty-second transistor having a gate electrode connected to the second QB node, one electrode connected to the second power line, and another electrode connected to the second sensing line; a forty-third transistor having a gate electrode connected to the first QB node, one electrode connected to the second power line, and the other electrode connected to the second scan line; and A forty-fourth transistor has a gate electrode connected to the second QB node, one electrode connected to the second power line, and the other electrode connected to the second scan line.

18. The scan driver according to claim 17, wherein: The second scanning stage further comprises: a forty-fifth transistor having a gate electrode connected to the second sensing carry line and an electrode connected to a third sensing carry line; a forty-sixth transistor having a gate electrode connected to the first control line and one electrode connected to the other electrode of the forty-fifth transistor; a forty-seventh transistor having a gate electrode connected to the third control line, one electrode connected to the second Q node, and the other electrode connected to the second node; a forty-eighth transistor having a gate electrode connected to the other electrode of the forty-sixth transistor, one electrode connected to the second node, and the other electrode connected to the second control line; and A sixth capacitor having one electrode connected to the gate electrode of the forty-eighth transistor and another electrode connected to the other electrode of the forty-eighth transistor.

19. The scan driver according to claim 18, wherein: The second scanning stage further comprises: a forty-ninth transistor having one electrode connected to the second Q node and a gate electrode and another electrode connected to a second scan-carry line; and A fiftieth transistor has a gate electrode connected to the second Q node, one electrode connected to the second control line, and the other electrode connected to the second node.

20. The scan driver according to claim 19, wherein: The second scanning stage further comprises: a fifty-first transistor having a gate electrode connected to the other electrode of the forty-sixth transistor and one electrode connected to the first power supply line; and A fifty-second transistor has a gate electrode connected to the third control line, one electrode connected to the other electrode of the fifty-first transistor, and the other electrode connected to the second QB node.

21. The scan driver according to claim 20, wherein: The second scanning stage further comprises: a fifty-third transistor having a gate electrode connected to the second Q node, one electrode connected to the second QB node, and the other electrode connected to the first power line; and A fifty-fourth transistor has a gate electrode connected to the first scan-carry line, one electrode connected to the second QB node, and the other electrode connected to the first power line.

22. The scan driver according to claim 21, wherein: The second scanning stage further comprises: a fifty-fifth transistor having a gate electrode connected to the fourth control line, one electrode connected to the first power line, and the other electrode connected to the second Q node; and A fifty-sixth transistor has a gate electrode connected to the first reset carry line, one electrode connected to the first power supply line, and the other electrode connected to the second Q node.

23. The scan driver according to claim 22, wherein: The second scanning stage further comprises: A fifty-seventh transistor having a gate electrode connected to the fourth control line, one electrode connected to the gate electrode of the forty-eighth transistor, and the other electrode connected to the first power line.

24. The scan driver according to claim 23, wherein: The fifty-seventh transistor comprises: a third sub-transistor having a gate electrode connected to the fourth control line and one electrode connected to the other electrode of the forty-sixth transistor; and a fourth sub-transistor having a gate electrode connected to the fourth control line, one electrode connected to the other electrode of the third sub-transistor, and the other electrode connected to the first power line, and The second scanning stage further comprises: A fifty-eighth transistor having a gate electrode connected to the other electrode of the forty-sixth transistor, an electrode connected to the second control line, and another electrode connected to the one electrode of the forty-sixth transistor.

25. A scanning driver, comprising: Multiple scan levels, The first scanning level among the plurality of scanning levels comprises: a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and an electrode connected to the first scan-in bit line and another electrode connected to the first Q node; a third transistor having a gate electrode connected to the first sense carry line and an electrode connected to the first control line; a fourth transistor having a gate electrode connected to the second sense carry line and an electrode connected to the other electrode of the third transistor; a fifth transistor having a gate electrode connected to the other electrode of the fourth transistor, one electrode connected to the second control line, and another electrode connected to the first node; a first capacitor having one electrode connected to the one electrode of the fifth transistor and the other electrode connected to the gate electrode of the fifth transistor; and A sixth transistor has a gate electrode connected to the third control line, one electrode connected to the first node, and the other electrode connected to the first Q node.

26. A scanning driver, comprising: Multiple scan levels, in: The odd-numbered stages among the scanning stages are connected to the first sub-control line, and the even-numbered stages among the scanning stages are connected to the second sub-control line; and A first scanning stage among the plurality of scanning stages comprises: a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and an electrode connected to the first scan-in bit line and another electrode connected to the first Q node; a third transistor having a gate electrode connected to the first sense carry line and an electrode; a fourth transistor having a gate electrode connected to the first sub-control line and one electrode connected to the other electrode of the third transistor; a fifth transistor having a gate electrode connected to the other electrode of the fourth transistor, one electrode connected to the second control line, and another electrode connected to the first node; a first capacitor having one electrode connected to the one electrode of the fifth transistor and the other electrode connected to the gate electrode of the fifth transistor; and A sixth transistor has a gate electrode connected to the third control line, one electrode connected to the first node, and the other electrode connected to the first Q node.

27. The scan driver according to claim 26, wherein: A second scanning stage among the plurality of scanning stages comprises: a seventh transistor having a gate electrode connected to the second Q node, one electrode connected to the second scan clock line, and another electrode connected to the second scan line; an eighth transistor having a gate electrode and one electrode connected to the second scan-carry line and another electrode connected to the second Q node; a ninth transistor having a gate electrode connected to the second sense carry line and an electrode; a tenth transistor having a gate electrode connected to the second sub-control line and one electrode connected to the other electrode of the ninth transistor; an eleventh transistor having a gate electrode connected to the other electrode of the tenth transistor, one electrode connected to the second control line, and another electrode connected to the second node; a second capacitor having one electrode connected to the one electrode of the eleventh transistor and the other electrode connected to the gate electrode of the eleventh transistor; and A twelfth transistor has a gate electrode connected to the third control line, one electrode connected to the second node, and the other electrode connected to the second Q node.

28. A scanning driver, comprising: Multiple scan levels, in: The odd-numbered stages among the scanning stages are connected to the first sub-control line, and the even-numbered stages among the scanning stages are connected to the second sub-control line; and A first scanning stage among the plurality of scanning stages comprises: a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line; a second transistor having a gate electrode and an electrode connected to the first scan-in bit line and another electrode connected to the first Q node; a third transistor having a gate electrode connected to the first sensing carry line and an electrode connected to the first sub-control line; a fourth transistor having a gate electrode connected to the first sense carry line and one electrode connected to the other electrode of the third transistor; a fifth transistor having a gate electrode connected to the other electrode of the fourth transistor, one electrode connected to the second control line, and another electrode connected to the first node; a first capacitor having one electrode connected to the one electrode of the fifth transistor and the other electrode connected to the gate electrode of the fifth transistor; and A sixth transistor has a gate electrode connected to the third control line, one electrode connected to the first node, and the other electrode connected to the first Q node.

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