Integrated circuit device and method of manufacturing the same

Abstract

In some embodiments, the present invention relates to integrated circuit devices. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source / drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower interlayer dielectric (ILD) layer and contacts a first source / drain region. A cap layer is disposed directly above the lower conductive plug. An upper interlayer dielectric (ILD) layer is disposed above the cap layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and is located directly above the cap layer. Embodiments of the present invention also relate to methods of fabricating integrated circuit devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] In the fabrication of integrated circuits (ICs), devices are formed on wafers and interconnected via conductive interconnect layers. These conductive interconnect layers can be formed during what are known as mid-stage (MOL) or back-end (BEOL) processes. MOL and BEOL processes are similar because they both form openings (e.g., contact holes, trenches, or vias) in dielectric layers and then fill these openings with a conductive material. The difference between MOL and BEOL is that MOL typically occurs earlier in the manufacturing process and can refer to the process of forming contacts in the substrate to conductive regions (such as source / drain regions); however, BEOL typically occurs later in the manufacturing process and can refer to the process of forming continuous metallization layers and vias over the contacts formed by MOL. Summary of the Invention

[0003] Some embodiments of the present invention provide an integrated circuit device, comprising: a transistor structure including a pair of source / drain regions disposed on a substrate and a gate electrode located between the pair of source / drain regions, the gate electrode being separated from the substrate by a gate dielectric; a lower conductive plug configured to pass through a lower interlayer dielectric (ILD) layer and contact a first source / drain region; a capping layer disposed directly above the lower conductive plug; an upper interlayer dielectric (ILD) layer disposed above the capping layer and the lower interlayer dielectric layer; and an upper conductive plug configured to pass through the upper interlayer dielectric layer and be located directly above the capping layer.

[0004] Other embodiments of the present invention provide a method of manufacturing an integrated circuit device, comprising: forming a lower interlayer dielectric (ILD) layer over a substrate; forming a lower conductive plug extending through the lower interlayer dielectric layer to a source / drain region of a transistor structure; forming a capping layer on the lower conductive plug; forming an upper interlayer dielectric layer over the lower interlayer dielectric layer and the capping layer; and forming an upper conductive plug extending through the upper interlayer dielectric layer to the capping layer; wherein the upper conductive plug is formed by forming a metal core and a subsequent annealing process to form a hybrid barrier layer lining the interface between the metal core and the upper interlayer dielectric layer.

[0005] Some embodiments of the present invention provide an integrated circuit device, comprising: an interlayer dielectric (ILD) layer disposed above a substrate; a lower conductive plug disposed in the interlayer dielectric layer; a lower barrier layer disposed along the sidewall surface of the lower conductive plug; an upper interlayer dielectric layer disposed above the interlayer dielectric layer; an upper conductive plug disposed in the upper interlayer dielectric layer and comprising a metal core and a hybrid barrier layer disposed along the sidewall surface of the metal core; wherein the hybrid barrier layer comprises atoms of the metal core and the upper interlayer dielectric layer. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated circuits with ruthenium contact structures are shown.

[0008] Figure 2 Cross-sectional views of some additional embodiments of an integrated circuit with a ruthenium contact structure are shown.

[0009] Figure 3 Some embodiments of integrated circuits having interconnect structures including hybrid barrier layers are shown.

[0010] Figures 4 to 17 Cross-sectional views of some embodiments of a method for forming an integrated circuit with a ruthenium contact structure are shown.

[0011] Figure 18 Flowcharts of some embodiments of a method for forming an integrated circuit with a ruthenium contact structure are shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] In mid-stage (MOL) interconnect structures, contacts, interconnect vias, and metal lines all play crucial roles in transistor and circuit performance. As scaling continues, contact resistance and interconnect resistance are becoming critical factors limiting device performance. Several solutions are emerging. For example, MOL contacts may be migrated from traditional tungsten materials to cobalt, which reduces line resistance within the chip. As an example, a first adhesive layer (e.g., made of titanium nitride (TiN) or tantalum nitride (TaN) and also serving as a barrier pad) is first formed to line the lower plug opening. Then, a lower plug made of cobalt is formed to fill the remainder of the lower plug opening. A second adhesive layer (e.g., made of titanium, titanium nitride, or tantalum nitride) can be deposited on top of the cobalt plug, lining the upper plug opening and reaching the top surface of the lower plug. The upper plug opening is then filled with an upper plug made of tungsten. Implementing adhesive layers to grow the lower and upper plugs increases conformal adhesion between the sidewall interlayer dielectric and the metal plug and prevents metal diffusion into the sidewall interlayer dielectric. Due to the phase transition introduced by high-temperature deposition, tungsten plugs can have relatively high resistance.

[0015] The manufacturing process for cobalt / tungsten plugs may require several ion implantation processes. For example, a first germanium ion implantation process may be applied between the filling of the lower cobalt plug and the upper tungsten plug to prevent corrosion effects on the lower plug. It should be understood that removing the workpiece from the vacuum chamber after the formation of the metal liner and barrier liner (i.e., before the subsequent annealing process) has disadvantages. The surrounding environment can cause oxidation of the metal liner and / or barrier liner, which increases the resistance of the resulting interconnect structure. While this oxidation can be removed by redox processes, the removal of the oxide material can lead to the formation of voids. These voids can result in poor electrical connections and reduced reliability. After the filling of the upper tungsten plug, a second germanium ion implantation process is required to enhance the tungsten sidewall interface and sidewall interlayer dielectric.

[0016] Therefore, this invention relates to improved MOL interconnect structures and related manufacturing methods to reduce contact resistance, reduce voids, improve reliability, and simplify manufacturing processes. In some embodiments, a metal core material is filled into the contact or via opening of the interlayer dielectric without first forming an adhesive or barrier layer. The metal core material is carefully selected such that a thin metal-dielectric hybrid barrier layer can be formed at the interface between the metal core and the interlayer dielectric through a suitable annealing process. The metal-dielectric hybrid barrier layer serves as both an adhesive and a barrier layer to bond the metal core and prevent its diffusion into the interlayer dielectric. In a more detailed embodiment, the integrated circuit includes a contact structure having contact source / drain regions and configured to pass through a lower conductive plug of the lower interlayer dielectric (ILD) layer. An upper conductive plug is disposed above the lower conductive plug and passes through the upper ILD layer. The upper conductive plug may be made of ruthenium (Ru). A ruthenium oxide hybrid barrier layer may be disposed between the upper conductive plug and the upper ILD layer and serves as a uniform adhesive layer between them. The hybrid barrier layer may be formed by an annealing process following the filling process of the ruthenium conductive plug. Ruthenium is a better material for forming contacts because the resistivity of ruthenium films is lower than that of tungsten and cobalt. Furthermore, ruthenium has a higher melting point than cobalt, thus providing greater tolerance to subsequent manufacturing processes. This reduces contact resistance. Additionally, by forming a ruthenium oxide hybrid barrier layer through an annealing process, the deposition process for forming the barrier layer is eliminated. The hybrid barrier layer firmly binds the upper conductive plug to the upper ILD layer, preventing the formation of voids. Due to the excellent adhesion properties of the hybrid barrier layer, ion implantation is no longer required. Therefore, manufacturing is simplified and device reliability is improved.

[0017] In some further embodiments, a capping layer is disposed between the lower conductive plug and the upper conductive plug. A lower barrier layer is configured to cover the sidewalls of the capping layer and the sidewalls of the lower conductive plug. The capping layer is made of a conductive material, such as tungsten. By disposing the capping layer on the lower conductive plug, the upper conductive plug can be electrically coupled to the lower conductive plug, and the forming process of the upper conductive plug can be integrated with the forming of the gate electrode plug coupled to the gate electrode.

[0018] Figure 1 A cross-sectional view of an integrated circuit 100 according to some embodiments is shown. Figure 1As shown, transistor structure 101 is disposed above substrate 102. Transistor structure 101 may be a logic device including a gate electrode 104 separated from substrate 102 by a gate dielectric layer 105. A pair of source / drain regions 103a, 103b are disposed within substrate 102 on opposite sides of gate electrode 104. In some embodiments, transistor structure 101 may be a single-gate planar device and located on a multi-gate device (such as a FinFET device). Transistor structure 101 may also be other devices, such as gate all-around (GAA) devices, omega gate devices, or Pi gate devices, as well as strained semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI (PD-SOI) devices, fully depleted SOI (FD-SOI) devices, or other suitable devices known in the art.

[0019] Contacts are respectively coupled to the gate electrode 104, source / drain regions 103a, 103b, body contact region (not shown), or other active regions of transistor structure 101. In some embodiments, the contacts may include a lower contact structure 142 surrounded by a lower interlayer dielectric (ILD) layer 110 and electrically connected to an upper contact structure 144 surrounded by an upper interlayer dielectric (ILD) layer 128 and disposed above the lower ILD layer 110. In some embodiments, the lower contact structure 142 includes a lower conductive plug 120 configured to pass through the lower ILD layer 110 and contact the first source / drain region 103a. In some embodiments, the lower conductive plug 120 comprises cobalt or is made of cobalt. In some embodiments, a capping layer 124 is disposed directly above the lower conductive plug 120. In some embodiments, the capping layer 124 comprises tungsten or is made of tungsten. In some embodiments, a lower barrier layer 119 is configured along the sidewall of the lower conductive plug 120. The lower barrier layer 119 may cover the sidewalls of the cover layer 124 and the sidewalls of the lower conductive plug 120. In some embodiments, the cover layer 124 may have a thickness in the range of 8 nm to 15 nm.

[0020] In some embodiments, the upper contact structure 144 includes an upper conductive plug 137 configured to pass through the upper ILD layer 128 and directly reach the capping layer 124. In some embodiments, the capping layer 124 separates the upper conductive plug 137 and the lower conductive plug 120, and may have a top surface directly contacting the upper conductive plug 137 and a bottom surface directly contacting the lower conductive plug 120. In some embodiments, the upper conductive plug 137 includes a metal core 138 and a hybrid barrier layer 140 lining the interface between the metal core 138 and the upper ILD layer 128. The hybrid barrier layer 140 may be a material mixed from the materials of the metal core 138 and the upper ILD layer 128. In some embodiments, the metal core 138 includes or is made of ruthenium. In some embodiments, the hybrid barrier layer 140 comprises ruthenium and oxygen. In some embodiments, the hybrid barrier layer 140 includes or is made of ruthenium oxide. In some embodiments, the hybrid barrier layer 140 comprises ruthenium, silicon, and oxygen. In some embodiments, the hybrid barrier layer 140 comprises ruthenium, aluminum, and oxygen. Ruthenium is a better material for forming contacts because the resistivity of ruthenium films is lower than that of tungsten and cobalt. Compared to tungsten, when deposited at temperatures ranging from 100°C to 200°C, ruthenium metal cores may only have an hcp (hexagonal tight-packed) lattice structure, while tungsten may have a β-W phase transition. The bulk resistance of ruthenium plugs can be 40% lower than that of tungsten plugs. Furthermore, ruthenium has a higher melting point than cobalt, and therefore provides greater tolerance to subsequent manufacturing processes. This reduces contact resistance. A hybrid barrier layer 140 acts as both an adhesive and a barrier layer to bond the metal core 138, prevent void formation, and prevent the metal core 138 from diffusing to the upper ILD layer 128. This improves device reliability.

[0021] In some embodiments, the hybrid barrier layer 140 has a thickness ranging from about 10 nm to about 15 nm. In some embodiments, the upper contact structure 144 further includes a gate electrode plug 139 configured to be adjacent to the upper conductive plug 137 and extending through the upper ILD layer 128. The gate electrode plug 139 can be electrically coupled to the gate electrode 104 via the gate barrier layer 114. The gate electrode 104 may include a stack of metal layers comprising a work function metal disposed on the core gate metal. The gate barrier layer 114 may include or be made of fluorine-free tungsten (FFW). In some embodiments, the gate electrode plug 139 includes or is made of the same material as the upper conductive plug 137 (i.e., the metal core 138 and the hybrid barrier layer 140 configured along the sidewalls of the metal core 138).

[0022] In some embodiments, a first contact etch stop layer (CESL) 116 is disposed between the upper ILD layer 128 and the lower ILD layer 110. The first contact etch stop layer 116 may have a top surface coplanar with the top surface of the capping layer 124. As an example, the first contact etch stop layer 116 may comprise or be made of silicon nitride. In some embodiments, a hybrid barrier layer 140 is disposed at the interface between the metal core 138 and the upper ILD layer 128, but not at the interface between the metal core 138 and the first contact etch stop layer 116 or at the interface between the metal core 138 and the gate barrier layer 114.

[0023] Figure 2 A cross-sectional view of an integrated circuit 200 according to some additional embodiments is shown. In addition to the above... Figure 1 In addition to the upper conductive plug 137 and the gate electrode plug 139, the upper contact structure 144 may also include a power rail (VDR) conductive plug 141, which includes a metal core 138 and a hybrid barrier layer 140 lining the interface between the metal core 138 and the upper ILD layer 128. The VDR conductive plug 141 includes a first portion 141a electrically coupled to the source / drain region 103 via the lower conductive plug 120 and a second portion 141b configured to pass through the first contact etch stop layer 116 and be electrically coupled to the gate electrode 104. The first portion 141a has a bottom surface 141s disposed on the capping layer 124. In some embodiments, the VDR conductive plug 141 includes or is made of the same material as the upper conductive plug 137 and the gate electrode plug 139, i.e., the metal core 138 and the hybrid barrier layer 140 configured along the sidewalls of the metal core 138. The hybrid barrier layer 140 of the VDR conductive plug 141 may not be located at the interface between the bottom surface 141s and the metal core 138 and the first contact etch stop layer 116. In some embodiments, the VDR conductive plug 141 may have a depth in the range of 18 nm to 33 nm and a width in the range of 20 nm to 35 nm, the upper conductive plug 137 may have a depth in the range of 18 nm to 22 nm and a width in the range of 9 nm to 17 nm, and the gate electrode plug 139 may have a depth in the range of 28 nm to 35 nm and a width in the range of 7 nm to 15 nm.

[0024] In some embodiments, a second contact etch stop layer 126 is formed over the first contact etch stop layer 116, and an upper ILD layer 128 is formed over the second contact etch stop layer 126. As an example, the second contact etch stop layer 126 may include or be made of alumina. The second contact etch stop layer 126 may also include or be made of a nitride dielectric material (such as silicon nitride). In some embodiments, the upper ILD layer 128 may include or be made of a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)) and / or other suitable dielectric materials. Therefore, in some cases, the upper ILD layer 128 may be substantially identical to the lower ILD layer 110. In some embodiments, the mixing barrier layer 140 may include an upper portion and a lower portion. The upper portion covers the interface between the metal core 138 and the upper ILD layer 128. The lower portion covers the interface between the metal core 138 and the second contact etch stop layer 126. In some embodiments, the upper ILD layer 128 and the second contact etch stop layer 126 may include or be made of materials with different oxygen atom ratios, such that the oxygen atom ratios in the lower and upper portions of the hybrid barrier layer 140 may be different. In some alternative embodiments, the hybrid barrier layer 140 may be disposed at the interface between the metal core 138 and the upper ILD layer 128, but not at the interface between the metal core 138 and the second contact etch stop layer 126. In this case, the second contact etch stop layer 126 may include a non-oxide dielectric material, such as silicon nitride. In some embodiments, the hybrid barrier layer 140 may not cover the interface between the metal core 138 and the first contact etch stop layer 116, and the metal core 138 may directly contact the first contact etch stop layer 116. In this case, the first contact etch stop layer 116 may include silicon nitride. In some instances, the second contact etch stop layer 126 has a thickness of about 5-20 nm, and the upper ILD layer 128 has a thickness of about 5-40 nm.

[0025] Figure 3 Some embodiments of an integrated circuit 300 having an interconnect structure including a metal core separated from an ILD layer by a hybrid barrier layer are shown. While the above is combined Figure 1 and Figure 2The illustrated upper contact structure 144 describes a hybrid barrier layer structure; however, it should be understood that similar structures and fabrication processes can also be used to form other conductive vias or even metal lines for MOL interconnect structures or even other interconnect structures to achieve improved connectivity. In some embodiments, the integrated circuit 300 includes a dielectric layer 306 disposed above the substrate 102. A conductive interconnect structure 320 is disposed within an opening 322 extending vertically through the dielectric layer 306. The conductive interconnect structure 320 may be a contact plug, via, or metal line connecting two conductive components 304, 318. In some embodiments, conductive components 304 and 318 may be metal lines or metal vias of the interconnect structure, respectively. In some alternative embodiments, conductive component 304 is an active region of a semiconductor device with a mid-stage process (MOL) structure, including doped semiconductor structures such as source / drain regions of a transistor or a polysilicon gate or a metal gate.

[0026] The conductive interconnect structure 320 includes a metal core 138 and a hybrid barrier layer 140 lining the interface between the metal core 138 and the dielectric layer 306. Similar to the above, the hybrid barrier layer 140 may be a mixture of the materials of the metal core 138 and the dielectric layer 306. The metal core 138 may be a continuous conductor of a uniform material having a thickness from about 200 nm to about 600 nm. The hybrid barrier layer 140 may be formed by performing an annealing process to mix the metal core 138 and the dielectric layer 306 and form a very thin pad. The thickness of the hybrid barrier layer 140 may range from about 10 nm to about 15 nm. In some embodiments, the metal core 138 is ruthenium, and the hybrid barrier layer 140 comprises or is made of a compound of oxygen and ruthenium atoms, thereby providing adhesion and isolation between the conductive interconnect structure 320 and the dielectric layer 306.

[0027] Figures 4 to 17 Cross-sectional views 400-1700 illustrate some embodiments of a method for forming an integrated circuit with a ruthenium contact structure. Although the method is described... Figures 4 to 17 However, it should be understood that Figures 4 to 17 The structures disclosed are not limited to this method, but can exist independently of the method.

[0028] like Figure 4 and Figure 5 As shown, a transistor structure 101 is formed above a substrate 102 and surrounded by a lower ILD layer 110. In some embodiments, the transistor structure 101 has a gate dielectric layer 105 above the substrate 102, a gate electrode 104 above the gate dielectric layer 105, and a pair of source / drain regions 103 located in the substrate 102 on opposite sides of the gate electrode 104 (see Figure 100). Figure 5The gate electrode 104 can be a polysilicon gate or a metal gate. The gate dielectric layer 105 can include or be made of a silicon dioxide layer or a high-k dielectric material (such as hafnium dioxide). The gate electrode 104 and the gate dielectric layer 105 can be formed by a replacement gate process, wherein a dummy gate 404 is first formed and patterned over the substrate 102. Sidewall spacers 106, 108 can be formed along the edge of the dummy gate 404, lining or covering the sidewall of the dummy gate 404 (see [link to relevant documentation]). Figure 4 Then, source / drain regions 103 can be formed on opposite sides of sidewall spacers 106, 108 within substrate 102. In some cases, each of sidewall spacers 106, 108 comprises a material with a different dielectric constant value (e.g., k-value). In various embodiments, sidewall spacers 106, 108 comprise silicon oxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, or combinations thereof, or other suitable dielectric materials. In some embodiments, sidewall spacers 106, 108 comprise multiple layers, such as main spacer walls, pad layers, etc. As an example, sidewall spacers 106, 108 can be formed by depositing dielectric material over dummy gate 404 and vertically etching back the dielectric material to have a top surface substantially coplanar with the top surface of dummy gate 404.

[0029] like Figure 5 As shown, a dielectric layer is deposited above transistor structure 101, followed by a planarization process to form lower ILD layer 110. As an example, the dielectric layer may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)) and / or other suitable dielectric materials. Lower ILD layer 110 can be deposited using subatmospheric pressure CVD (SACVD), flowable CVD, or other suitable deposition techniques. The dielectric layer can be planarized using a chemical mechanical planarization (CMP) process to have a top surface substantially coplanar with the top surfaces of sidewall spacers 106, 108. As an example, lower ILD layer 110 has a thickness of approximately 5-40 nm. For gate replacement processes, the dielectric layer is then removed... Figure 4 A dummy gate 404 is installed and replaced with a gate electrode 104. A gate dielectric layer 105 can also be formed after removing the dummy gate 404. To form the gate electrode 104, a stack of metal material can be filled into the gate opening, followed by a planarization process to remove excess material above the lower ILD layer 110. For different devices, the stack of metal material can include or be made of materials such as titanium nitride, tantalum nitride, aluminum titanium, and aluminum. Other materials can also be used for the gate electrode 104.

[0030] like Figure 6As shown, the gate electrode 104 is recessed. In some embodiments, a patterning process is first performed to form a mask layer 112 over the lower ILD layer 110, thereby exposing the gate electrode. Then, an etching process is performed on the gate electrode 104 to lower the top surface of the gate electrode to a position below the top surface of the sidewall spacers 106, 108. The etching process controls the thickness of the gate electrode and thus adjusts the effective work function of the gate electrode 104 to a desired value.

[0031] like Figure 7 As shown, a gate barrier layer 114 is formed on a recessed upper surface of the gate electrode 104 and can serve as a diffusion barrier. In some embodiments, the gate barrier layer 114 comprises or is made of fluorine-free tungsten (FFW). The gate barrier layer 114 prevents material mixing between the gate electrode 104 and the gate electrode plug to be formed, thereby reducing or preventing threshold voltage drop. In some embodiments, the gate barrier layer 114 can be deposited using a fluorine-free (F)-organic tungsten source. Since fluorine (F) is not included in the layer, the surface of the underlying gate electrode 104 is not degraded. The gate barrier layer 114 can be etched back to have a top surface lowered to a position below the top surface of the sidewall spacers 106, 108. In some embodiments, the mask layer 112 comprises or is made of a photoresist material. In some alternative embodiments, the mask layer 112 may comprise or be made of a hard mask material, such as silicon oxide, silicon nitride, or other suitable metals or dielectrics.

[0032] like Figure 8 As shown, a first contact etch stop layer 116 is formed over the gate barrier layer 114, thereby filling the remaining upper portion of the sidewall spacers 106. The first contact etch stop layer 116 may include or be made of silicon nitride, and may be deposited and then planarized to cover the top surfaces of the lower ILD layer 110 and the sidewall spacers 106, 108.

[0033] like Figure 9 As shown, a first pattern including opening 118 is formed through the first contact etch stop layer 116 and the lower ILD layer 110. In some cases, opening 118 provides access to a source, drain, or body contact region. As an example, opening 118 can be formed by a suitable combination of photolithographic patterning and etching (e.g., wet or dry etching) processes. Metallization processes can be implemented to form a semiconductor metal compound (such as silicide, germanide, germanium silicide) layer on the exposed portion of substrate 102 (e.g., exposed through opening 118), thereby providing a low-resistance contact.

[0034] like Figure 10As shown, in some instances, an under-resin or barrier layer 119 may be formed within the opening 118. In some cases, the under-resin or barrier layer 119 may comprise Ti, TiN, Ta, TaN, W, or other suitable materials. A lower conductive plug 120 may then be formed on the under-resin or barrier layer 119 within the opening 118. In some instances, the lower conductive plug 120 may comprise cobalt or other suitable materials such as W, Cu, Ru, Al, Rh, Mo, Ta, Ti. After the deposition of the lower conductive plug 120, a chemical mechanical planarization (CMP) process may be performed to remove excess material from the under-resin or barrier layer 119 and the lower conductive plug 120, and to planarize the top surface of the workpiece. In some embodiments, an annealing process may be performed after filling the lower barrier layer 119 and the lower conductive plug 120 to form a semiconductor-metal compound film at the interface between the lower barrier layer 119 and the exposed portion of the upper surface of the source / drain region 103.

[0035] like Figure 11 As shown, the lower conductive plug 120 is recessed, thus forming an opening 122 in the upper part of the lower barrier layer 119. An etching process is performed on the lower conductive plug 120 to lower the top surface of the lower conductive plug 120 to a position below the top surface of the barrier layer 119.

[0036] like Figure 12 As shown, a capping layer 124 is formed to fill the opening 122 within the upper portion of the lower barrier layer 119. In some embodiments, the capping layer 124 can be formed by selective tungsten deposition followed by a CMP process. The capping layer 124 may have a top surface substantially coplanar with the top surface of the first etch stop layer 116 and / or the lower barrier layer 119. The lower barrier layer 119 may cover the entire surface of the lower conductive plug 120 and the capping layer 124. The capping layer 124 provides protection and isolation for the lower conductive plug 120.

[0037] like Figure 13As shown, a second contact etch stop layer 126 is formed over the first contact etch stop layer 116, and an upper ILD layer 128 is formed over the second contact etch stop layer 126. As an example, the second contact etch stop layer 126 may include or be made of alumina. The second contact etch stop layer 126 may also include or be made of silicon nitride (SiN) or zirconium oxide (ZrO2). Other suitable dielectric materials may also be used for the second contact etch stop layer 126. In some embodiments, the upper ILD layer 128 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)) and / or other suitable dielectric materials. Therefore, in some cases, the upper ILD layer 128 may be substantially identical to the lower ILD layer 110. In various embodiments, the second contact etch stop layer 126 and the upper ILD layer 128 can be deposited using subatmospheric pressure CVD (SACVD), flowable CVD, ALD, PVD, or other suitable deposition techniques. In some instances, the second contact etch stop layer 126 has a thickness of approximately 5-20 nm, and the upper ILD layer 128 has a thickness of approximately 5-40 nm.

[0038] like Figures 14 to 16 As shown, a plurality of openings 130, 132, 134, and 136 are formed to reach the gate barrier layer 114 or the capping layer 124, and then filled with a metal core material. In some embodiments, the metal core material is ruthenium. The plurality of openings 130, 132, 134, and 136 can be formed sequentially in any order or in some combination, but the plurality of openings 130, 132, 134, and 136 can all be formed simultaneously before filling with the metal core material. The openings 130, 132, 134, and 136 can be formed separately by a multi-step etching process to improve etch selectivity and provide over-etch control. For example, see reference... Figure 15 The opening 134 can be formed by performing a first etch with a high etch rate on the upper ILD layer 128 and stopping on the second etch stop layer 126. Then, a second etch is performed to slowly etch the second etch stop layer 126, thus exposing the cover layer 124 without much over-etching. Similarly, see reference... Figure 14The opening 130 can be formed by performing a first etch with a high etch rate on the upper ILD layer 128 and stopping on the second etch stop layer 126. Then, a second etch is performed to slowly etch the second etch stop layer 126 and the first etch stop layer 116, thus exposing the gate barrier layer 114 without much over-etching. Alternatively, the opening 130 can be formed by performing a first etch with a high etch rate on the upper ILD layer 128 and the second etch stop layer 126 and stopping on the first etch stop layer 116. Then, a second etch is performed to slowly etch the first etch stop layer 116, thus exposing the gate barrier layer 114 without much over-etching. As an example, in Figure 14 In this configuration, a second pattern, including an opening 130, is formed to pass through the upper ILD layer 128, the second contact etch stop layer 126, and the first contact etch stop layer 116. In some embodiments, the patterning process (e.g., for forming multiple openings) may include a multi-step etching process to etch the upper ILD layer 128, the second contact etch stop layer 126, and the first contact etch stop layer 116, respectively, to improve etch selectivity and provide over-etch control. The opening 130 may also be formed by a suitable combination of photolithographic patterning and etching (e.g., wet or dry etching) processes. In some cases, the opening 130 provides access to the gate electrode 104 through the gate barrier layer 114.

[0039] exist Figure 15 In this process, a third pattern, including a first opening 134 and a second opening 136, is formed to pass through the upper ILD layer 128 and the second contact etch stop layer 126. In some embodiments, the patterning process (e.g., for forming multiple openings) may include a multi-step etching process to etch the upper ILD layer 128 and the second contact etch stop layer 126, respectively, to improve etch selectivity and provide over-etch control. Openings 134, 136 may also be formed by a suitable combination of photolithographic patterning and etching (e.g., wet etching or dry etching) processes. In some embodiments, it may be possible to... Figure 14 An additional opening 132 is formed in it, and it can be connected with the one in Figure 15 The openings formed in the middle merge to form opening 136.

[0040] like Figure 16As shown, one or more metal layers are deposited to form a metal core 138 in openings 130, 134, and 136. In some cases, a VDR conductive plug 141 provides a direct contact between the gate electrode 104 and adjacent source, drain, and / or body regions. An upper conductive plug 137 provides access to the source / drain regions within the substrate 102 via a lower conductive plug 120, while a gate electrode plug 139 provides access to the gate electrode 104. As described above, a capping layer 124 isolates and protects the lower conductive plug 120. A gate barrier layer 114 isolates and protects the gate electrode 104. By arranging the first etch stop layer 116, the second etch stop layer 126, the capping layer 124 on the lower conductive plug 120, and the gate barrier layer 114 on the gate electrode 104 as disclosed, the formation process of the upper conductive plug 137 can be integrated with the formation of the gate electrode plug 139 and the VDR conductive plug 141. In some embodiments, the metal core 138 is formed by a chemical vapor deposition (CVD) process of ruthenium at a temperature ranging from 120°C to 220°C. The ruthenium precursor can be solid. The ruthenium precursor is composed of Ru, C, and O or is made of Ru, C, and O. The precursor can be evaporated at a temperature ranging from 120°C to 260°C. Ruthenium can be deposited on SiO2, AlO2, etc. x On W, SiN or Co materials.

[0041] like Figure 17As shown, an annealing process is performed to form a metal-dielectric hybrid barrier layer 140 at the interface between the metal core 138 and the upper ILD layer 128. The hybrid barrier layer 140 may be formed at the interface between the metal core 138 and a dielectric material containing certain atoms. For example, ruthenium and oxygen atoms may form a self-limiting hybrid layer. The metal core 138, made of ruthenium, forms the hybrid barrier layer 140 with a dielectric material containing oxygen atoms. Thus, the hybrid barrier layer 140 may include an upper portion and a lower portion. The upper portion covers the interface between the metal core 138 and the upper ILD layer 128. The lower portion covers the interface between the metal core 138 and the second contact etch stop layer 126. In some embodiments, the upper ILD layer 128 and the second contact etch stop layer 126 may include or be made of materials with different oxygen atom ratios, such that the oxygen atom ratios in the lower and upper portions of the hybrid barrier layer 140 may be different. In some embodiments, the hybrid barrier layer 140 may not cover the interface between the metal core 138 and the first contact etch stop layer 116. Therefore, the metal core 138 can directly contact the first contact etch stop layer 116. The metal-dielectric hybrid barrier layer 140 serves as a barrier and adhesive layer between the metal material of the metal core 138 and the dielectric material of the upper ILD layer 128. The growth and reflow of the metal core 138 can be regulated by adjusting the operating temperature. The required annealing conditions depend on the materials and device structure. The annealing process for the ruthenium metal core and oxide dielectric material should be performed at a temperature greater than 450°C. For example, annealing at 530°C for three hours can form a ruthenium-oxide hybrid barrier layer with a thickness ranging from 14 Å to 34 Å. In some embodiments, the annealing process is performed at a temperature ranging from 490°C to 550°C. The hybrid barrier layer 140 can have a thickness ranging from 10 nm to 15 nm.

[0042] Figure 18 Flowcharts of some embodiments of a method 1800 for forming an integrated chip having an interconnect structure including a hybrid barrier layer are shown.

[0043] Although method 1800 is shown and described below as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events in addition to those shown and / or described herein. Furthermore, implementing one or more aspects or embodiments described herein may not require all the steps shown. Additionally, one or more steps described herein may be performed in one or more separate steps and / or stages.

[0044] In step 1802, a transistor structure surrounded by a lower ILD layer is formed. The transistor structure includes a gate electrode formed above the substrate and a pair of source / drain regions disposed on opposite sides of the gate electrode. Sidewall spacers are formed along the edges of the gate electrode, thereby lining or covering the sidewalls of the gate electrode. Figures 4 to 5 Cross-sectional views 400-500 are shown for some embodiments corresponding to step 1802.

[0045] In 1804, the gate electrode is recessed and a gate barrier layer is formed on the recessed upper surface of the gate electrode. In some embodiments, the gate barrier layer comprises or is made of fluorine-free tungsten (FFW). In some embodiments, a first contact etch stop layer is formed over the gate barrier layer to fill the remaining upper portion of the sidewall spacer. Figures 6 to 8 Cross-sectional views 600-800 are shown for some embodiments corresponding to step 1804.

[0046] In 1806, the lower barrier layer and the lower conductive plug pass through the lower ILD layer to reach the source / drain regions on the transistor structure within the substrate. Figures 9 to 10 Cross-sectional views 900-1000 are shown for some embodiments corresponding to step 1806.

[0047] In step 1808, the lower conductive plug is recessed and a capping layer is formed to fill the upper portion of the lower barrier layer. In some embodiments, the capping layer can be formed by selective tungsten deposition followed by a CMP process. Figures 11 to 12 Cross-sectional views 1100-1200 are shown for some embodiments corresponding to step 1808.

[0048] In 1810, an upper ILD layer is formed above the lower ILD layer and the overlay layer. Figure 13 A cross-sectional view 1300 corresponding to some embodiments of step 1810 is shown.

[0049] In 1812, multiple openings are formed that pass through the upper ILD layer and / or the first contact etch stop layer to reach the gate barrier layer or capping layer. Figures 14 to 15 Cross-sectional views 1400-1500 are shown for some embodiments corresponding to step 1812.

[0050] In 1814, multiple openings are filled with a metallic material to form multiple conductive plugs. In some embodiments, the metallic material is ruthenium. Figure 16 A cross-sectional view 1600 corresponding to some embodiments of step 1814 is shown.

[0051] In step 1816, an annealing process is performed, thereby forming a metal-dielectric hybrid barrier layer at the interface between the plurality of conductive plugs and the upper ILD layer. The metal-dielectric hybrid barrier layer serves as a barrier and adhesive layer between the metal material of the plurality of conductive plugs and the dielectric material of the upper ILD layer. In some embodiments, the metal material is ruthenium. Figure 17 A cross-sectional view 1700 is shown, corresponding to some embodiments of step 1816.

[0052] Therefore, the present invention relates to novel integrated circuit devices that eliminate adhesive or barrier layers located between interconnect components and surrounding ILD layers, and to a method for manufacturing such devices by forming a metal-dielectric hybrid barrier layer using an annealing process.

[0053] Therefore, in some embodiments, the present invention relates to integrated circuit devices. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source / drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is configured to pass through a lower interlayer dielectric (ILD) layer and contact the first source / drain regions. A capping layer is disposed directly above the lower conductive plug. An upper interlayer dielectric (ILD) layer is disposed above the capping layer and the lower ILD layer. An upper conductive plug is configured to pass through the upper ILD layer and be located directly above the capping layer.

[0054] In other embodiments, the present invention relates to an integrated circuit device. A lower interlayer dielectric (ILD) layer is disposed above a substrate and has a lower plug opening extending vertically through the lower ILD layer. A lower barrier layer is configured along the sidewall surface of the lower plug opening, and a lower conductive plug fills the lower portion of the lower plug opening. An upper ILD layer is disposed above the lower ILD layer and has an upper plug opening extending vertically through the upper ILD layer. An upper conductive plug fills the upper plug opening and includes a hybrid barrier layer configured along the sidewall surface of the upper plug opening and a metal core filling the remaining space of the upper plug opening.

[0055] In another embodiment, the present invention relates to a method of forming an integrated circuit device. The method includes forming a lower interlayer dielectric (ILD) layer over a substrate and forming a lower conductive plug extending through the lower ILD layer to the source / drain regions of a transistor structure within the substrate. The method further includes forming a capping layer on the lower conductive plug and forming an upper ILD layer over the lower ILD layer and the capping layer. The method further includes forming an upper conductive plug extending through the upper ILD layer to the capping layer. The upper conductive plug is formed by forming a metal core and a subsequent self-protecting annealing process to form a hybrid barrier layer at the interface between the inner metal core and the upper ILD layer.

[0056] Some embodiments of the present invention provide an integrated circuit device comprising: a transistor structure including a pair of source / drain regions disposed on a substrate and a gate electrode located between the pair of source / drain regions, the gate electrode being separated from the substrate by a gate dielectric; a lower conductive plug configured to pass through a lower interlayer dielectric (ILD) layer and contact a first source / drain region; a capping layer disposed directly above the lower conductive plug; an upper interlayer dielectric (ILD) layer disposed above the capping layer and the lower interlayer dielectric layer; and an upper conductive plug configured to pass through the upper interlayer dielectric layer and be located directly above the capping layer. In some embodiments, the capping layer comprises tungsten. In some embodiments, the upper conductive plug comprises a metal core and a hybrid barrier layer lining the interface between the metal core and the upper interlayer dielectric layer. In some embodiments, the metal core comprises ruthenium; and wherein the hybrid barrier layer comprises ruthenium oxide. In some embodiments, the hybrid barrier layer has a thickness in the range of 10 nm to 15 nm. In some embodiments, the lower conductive plug comprises cobalt. In some embodiments, the integrated circuit device further includes: a first contact etch stop layer disposed between the upper interlayer dielectric layer and the lower interlayer dielectric layer; wherein the first contact etch stop layer has a top surface coplanar with the top surface of the cover layer. In some embodiments, the integrated circuit device further includes: a VDR conductive plug including a first portion and a second portion, wherein the first portion is configured to pass through the first contact etch stop layer, and the second portion includes a bottom surface disposed on the cover layer; wherein the VDR conductive plug includes a metal core and a hybrid barrier layer lining the sidewalls of the metal core, wherein the hybrid barrier layer includes an upper portion covering the interface between the metal core and the upper interlayer dielectric layer, wherein the metal core directly contacts the first contact etch stop layer. In some embodiments, the integrated circuit device further includes: a second contact etch stop layer disposed between the upper interlayer dielectric layer and the first contact etch stop layer; wherein the hybrid barrier layer includes a lower portion lining the interface between the metal core and the second contact etch stop layer. In some embodiments, the upper and lower portions of the hybrid barrier layer comprise different materials. In some embodiments, the integrated circuit device further includes: a gate electrode plug contacting the gate electrode; wherein the gate electrode plug comprises the same material as the upper conductive plug. In some embodiments, the integrated circuit device further includes a lower barrier layer covering the sidewalls of the overlay layer and the lower conductive plug.

[0057] Other embodiments of the present invention provide a method of manufacturing an integrated circuit device, comprising: forming a lower interlayer dielectric (ILD) layer over a substrate; forming a lower conductive plug extending through the lower interlayer dielectric layer to a source / drain region of a transistor structure; forming a capping layer on the lower conductive plug; forming an upper interlayer dielectric layer over the lower interlayer dielectric layer and the capping layer; and forming an upper conductive plug extending through the upper interlayer dielectric layer to the capping layer; wherein the upper conductive plug is formed by forming a metal core and a subsequent annealing process to form a hybrid barrier layer lining the interface between the metal core and the upper interlayer dielectric layer. In some embodiments, the metal core is formed by a chemical vapor deposition (CVD) process of ruthenium, and the hybrid barrier layer comprises ruthenium and oxygen. In some embodiments, the metal core is deposited at a temperature ranging from 120°C to 260°C. In some embodiments, the annealing process is performed at a temperature ranging from 490°C to 550°C. In some embodiments, the metal core is formed directly above the sidewall of the upper interlayer dielectric layer.

[0058] Some embodiments of the present invention provide an integrated circuit device, comprising: an interlayer dielectric (ILD) layer disposed above a substrate; a lower conductive plug disposed in the interlayer dielectric layer; a lower barrier layer disposed along a sidewall surface of the lower conductive plug; an upper interlayer dielectric layer disposed above the interlayer dielectric layer; and an upper conductive plug disposed in the upper interlayer dielectric layer and comprising a metal core and a hybrid barrier layer disposed along a sidewall surface of the metal core; wherein the hybrid barrier layer comprises atoms of the metal core and the upper interlayer dielectric layer. In some embodiments, the integrated circuit device further comprises: a contact etch stop layer (CELL) disposed between the upper interlayer dielectric layer and the interlayer dielectric layer; wherein the upper conductive plug extends through the contact etch stop layer, and wherein the hybrid barrier layer is not at the interface between the metal core and the contact etch stop layer. In some embodiments, the integrated circuit device further comprises: a tungsten capping layer disposed between the lower conductive plug and the upper conductive plug and in direct contact with the lower conductive plug and the upper conductive plug.

[0059] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit device, comprising: A transistor structure includes a pair of source / drain regions disposed on a substrate and a gate electrode located between the pair of source / drain regions, the gate electrode being separated from the substrate by a gate dielectric; The lower conductive plug is configured to pass through the lower interlayer dielectric layer and contact the first source / drain region; A cover layer is disposed directly above the lower conductive plug; An upper interlayer dielectric layer is disposed above the cover layer and the lower interlayer dielectric layer; as well as The upper conductive plug is configured to pass through the upper interlayer dielectric layer and be located directly above the cover layer; A first contact etch stop layer is disposed between the upper interlayer dielectric layer and the lower interlayer dielectric layer; as well as A power rail conductive plug, comprising: a metal core located above a gate electrode and a first source / drain region, a hybrid barrier layer lining the sidewalls of the metal core, a first portion passing through a first contact etch stop layer and electrically coupled to the gate electrode, and a second portion electrically coupled to the first source / drain region via a lower conductive plug, the first portion having an overhang beyond the second portion, wherein the bottom surface of the first contact etch stop layer is lower than the top surface of the lower interlayer dielectric layer, and the metal core directly contacts the first contact etch stop layer. The first contact etch stop layer surrounds the extended portion and the cover layer, and extends continuously between the extended portion and the cover layer. The hybrid barrier layer is not located at the interface between the first contact etch stop layer and the extended portion. The hybrid barrier layer comprises atoms of the metal core and the upper interlayer dielectric layer; the contact surface between the hybrid barrier layer and the capping layer is higher than the bottom surface of the metal core located above the gate electrode.

2. The integrated circuit device according to claim 1, wherein, The covering layer includes tungsten.

3. The integrated circuit device according to claim 1, wherein, The upper conductive plug includes a metal core and a hybrid barrier layer lining the interface between the metal core and the upper interlayer dielectric layer.

4. The integrated circuit device according to claim 3, wherein, The metal core comprises ruthenium; and the hybrid barrier layer comprises ruthenium oxide.

5. The integrated circuit device according to claim 4, wherein, The hybrid barrier layer has a thickness ranging from 10 nm to 15 nm.

6. The integrated circuit device according to claim 1, wherein, The lower conductive plug comprises cobalt.

7. The integrated circuit device according to claim 1, wherein, The first contact etch stop layer has a top surface that is coplanar with the top surface of the cover layer.

8. The integrated circuit device according to claim 7, wherein, The second part includes a bottom surface disposed on the cover layer; The hybrid barrier layer includes the upper portion covering the interface between the metal core and the upper interlayer dielectric layer.

9. The integrated circuit device according to claim 8, further comprising: A second contact etch stop layer is disposed between the upper interlayer dielectric layer and the first contact etch stop layer; The hybrid barrier layer includes the lower portion of the interface between the metal core and the second contact etch stop layer.

10. The integrated circuit device according to claim 9, wherein, The upper and lower parts of the hybrid barrier layer comprise different materials.

11. The integrated circuit device according to claim 1, further comprising: The gate electrode plug contacts the gate electrode; The gate electrode plug is made of the same material as the upper conductive plug.

12. The integrated circuit device of claim 1, further comprising a lower barrier layer covering the sidewalls of the cover layer and the lower conductive plug.

13. A method for manufacturing an integrated circuit device, comprising: An interlayer dielectric layer is formed above the substrate; A lower conductive plug is formed that passes through the lower interlayer dielectric layer to reach the source / drain region of the transistor structure; A covering layer is formed on the lower conductive plug; An upper interlayer dielectric layer is formed above the lower interlayer dielectric layer and the cover layer; as well as A conductive plug is formed that passes through the interlayer dielectric layer to reach the cover layer; The upper conductive plug is formed by forming a first metal core and then an annealing process to form a first hybrid barrier layer lining the interface between the first metal core and the upper interlayer dielectric layer. The method further includes forming a first contact etch stop layer between the upper interlayer dielectric layer and the lower interlayer dielectric layer; and A second contact etch stop layer is formed between the upper interlayer dielectric layer and the first contact etch stop layer; Wherein, the first hybrid barrier layer includes the atoms of the first metal core and the upper interlayer dielectric layer, and wherein the bottom surface of the first hybrid barrier layer is located above the top surface of the lower interlayer dielectric layer and exists at the interface between the second contact etch stop layer and the first metal core but not at the interface between the first contact etch stop layer and the first metal core. A power rail conductive plug is formed in the upper interlayer dielectric layer. The power rail conductive plug includes: a second metal core located above the gate electrode and the first source / drain region and a second hybrid barrier layer lining the sidewalls of the second metal core; a first portion passing through the first contact etch stop layer and electrically coupled to the gate electrode; and a second portion electrically coupled to the first source / drain region through the lower conductive plug. The first portion has an overhang portion extending beyond the second portion. The first contact etch stop layer surrounds the overhang and the cover layer and extends continuously between the overhang and the cover layer; the second hybrid barrier layer is not located at the interface between the first contact etch stop layer and the overhang. The second hybrid barrier layer comprises atoms of the second metal core and the upper interlayer dielectric layer; the bottom surface of the second hybrid barrier layer is located above the first source / drain region and is higher than the bottom surface of the second metal core located above the gate electrode.

14. The method according to claim 13, wherein, The first metal core is formed by chemical vapor deposition of ruthenium, and the first and second hybrid barrier layers comprise ruthenium and oxygen.

15. The method according to claim 13, wherein, The first metal core is deposited at a temperature ranging from 120°C to 260°C.

16. The method according to claim 13, wherein, The annealing process is carried out at temperatures ranging from 490°C to 550°C.

17. The method according to claim 13, wherein, The first metal core is formed directly above the sidewall of the upper interlayer dielectric layer.

18. An integrated circuit device, comprising: The lower interlayer dielectric layer is disposed above the substrate; A lower conductive plug is disposed in the lower interlayer dielectric layer; The lower barrier layer is configured to run along the sidewall surface of the lower conductive plug; An upper interlayer dielectric layer is disposed above the lower interlayer dielectric layer; An upper conductive plug is disposed in the upper interlayer dielectric layer and includes a first metal core and a first hybrid barrier layer configured to run along the sidewall surface of the first metal core; a first contact etch stop layer is disposed between the upper interlayer dielectric layer and the lower interlayer dielectric layer; A second contact etch stop layer is disposed between the upper interlayer dielectric layer and the first contact etch stop layer; A tungsten capping layer is disposed between the lower conductive plug and the upper conductive plug and directly contacts the lower conductive plug and the upper conductive plug; The first hybrid barrier layer comprises atoms of the first metal core and the upper interlayer dielectric layer, and the bottom surface of the first hybrid barrier layer is located above the top surface of the lower interlayer dielectric layer and exists at the interface between the second contact etch stop layer and the first metal core, but not at the interface between the first contact etch stop layer and the first metal core. A power rail conductive plug includes: a second metal core located above a gate electrode and a first source / drain region and a second hybrid barrier layer lining the sidewalls of the second metal core; a first portion passing through the first contact etch stop layer and electrically coupled to the gate electrode; and a second portion electrically coupled to the first source / drain region via the lower conductive plug, the first portion having an overhang portion extending beyond the second portion. The first contact etch stop layer surrounds the protruding portion and the tungsten capping layer, and extends continuously between the protruding portion and the tungsten capping layer. The second hybrid barrier layer is not located at the interface between the first contact etch stop layer and the protruding portion. The second hybrid barrier layer includes the atoms of the second metal core and the upper interlayer dielectric layer; the bottom surface of the second hybrid barrier layer is located above the first source / drain region and is higher than the bottom surface of the second metal core located above the gate electrode.

19. The integrated circuit device according to claim 18, wherein, The upper conductive plug extends through the first contact etch stop layer.

20. The integrated circuit device according to claim 18, wherein, The material of the second metal core is ruthenium, and the second hybrid barrier layer is formed by the ruthenium of the second metal core, the upper interlayer dielectric layer containing oxygen atoms, and the second contact etch stop layer.

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