Semiconductor package including stacked semiconductor chips and method of manufacturing the same

Abstract

Semiconductor package including stacked semiconductor chips and method for manufacturing the same. A semiconductor package may include: a chip stack including a plurality of semiconductor chips stacked in a vertical direction; a plurality of vertical interconnectors, each of which has a first end connected to the plurality of semiconductor chips and extends in the vertical direction; a molding layer covering the chip stack and the vertical interconnectors while exposing the second ends of the vertical interconnectors; a plurality of landing pads formed over one surface of the molding layer to contact the second ends of the vertical interconnectors, respectively, wherein the plurality of landing pads are conductive and overlap the first ends of the vertical interconnectors, respectively; and a package redistribution layer electrically connected to the vertical interconnectors through the landing pads.

Description

Technical Field

[0001] The present disclosure relates generally to a semiconductor package, and more particularly, to a semiconductor package including a plurality of chips stacked therein. Background Art

[0002] Electronic products are required to process large amounts of data while their physical size continues to shrink. Therefore, it is necessary to increase the integration of semiconductor devices used in these electronic products.

[0003] However, due to the limitation of semiconductor integration technology, the required functions cannot be satisfied by only a single semiconductor chip. Therefore, it is necessary to manufacture a semiconductor package having a plurality of semiconductor chips embedded therein.

[0004] Although a semiconductor package includes a plurality of semiconductor chips, the semiconductor package needs to have a specified size or a size smaller than the specified size based on requirements of an electronic product on which the semiconductor package is to be mounted. Summary of the invention

[0005] In an embodiment, a semiconductor package may include: a chip stack including a plurality of semiconductor chips stacked in a vertical direction; a plurality of vertical interconnectors, each of the vertical interconnectors having a first end respectively connected to the plurality of semiconductor chips and extending in the vertical direction; a molding layer covering the chip stack and the vertical interconnectors while exposing second ends of the vertical interconnectors; a plurality of landing pads formed over a surface of the molding layer to respectively contact the second ends of the vertical interconnectors, wherein the plurality of landing pads are conductive and respectively overlap with the first ends of the vertical interconnectors; and a package redistribution layer electrically connected to the vertical interconnectors through the landing pads.

[0006] In another embodiment, a method for manufacturing a semiconductor package may include the following steps: stacking a plurality of semiconductor chips in a vertical direction on a substrate to form a chip stack; forming a plurality of vertical interconnectors extending in the vertical direction, wherein first ends of the plurality of vertical interconnectors are respectively connected to the plurality of semiconductor chips; forming a molding layer to cover the chip stack and the vertical interconnectors while exposing second ends of the vertical interconnectors; forming a plurality of landing pads above the molding layer to respectively contact the second ends of the vertical interconnectors, wherein the plurality of landing pads are conductive and respectively overlap with the first ends of the vertical interconnectors; and forming a package redistribution layer electrically connected to the vertical interconnectors through the landing pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a plan view illustrating an effective surface of a semiconductor chip according to an embodiment.

[0008] Figure 1B It is along Figure 1AA cross-sectional view taken along line A1-A1'.

[0009] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 and Figure 7 2 is a diagram illustrating a semiconductor package and a method of manufacturing the same according to an embodiment.

[0010] Figure 8 The sweep of a vertical lead is illustrated.

[0011] Fig. 9 is a cross-sectional view illustrating a semiconductor package and a method of manufacturing the same according to another embodiment.

[0012] Fig. 10A is based on vertical interconnectors connected to the lowermost semiconductor chip of the first chip stack and adjacent to each other, Fig. 9 Magnified plan view of a landing pad and package redistribution layer in a semiconductor package.

[0013] Fig. 10B is with Fig. 10A The cross-sectional view corresponding to the plan view.

[0014] Fig. 10C yes Fig. 10A An enlarged plan view of a portion of the.

[0015] Fig.11A is a cross-sectional view illustrating a semiconductor package according to another embodiment.

[0016] Fig. 11B It is shown Fig.11A A plan view of a chip stack and vertical interconnects of a semiconductor package.

[0017] Fig. 12A is a cross-sectional view illustrating a semiconductor package according to another embodiment.

[0018] Fig. 12B It is shown Fig. 12A A plan view of first and second chip stacks and first and second vertical interconnectors of a semiconductor package.

[0019] Fig.13 yes Fig. 9 An enlarged view of region R2 of a semiconductor package.

[0020] Fig.14A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0021] Fig.15 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. DETAILED DESCRIPTION

[0022] Various examples and implementations of the disclosed technology are described below with reference to the accompanying drawings.

[0023] The drawings may not necessarily be to scale, and in some cases, the scale of at least some structures in the drawings may have been exaggerated in order to clearly illustrate specific features of the described examples or implementations. When a specific example in a drawing or description having two or more layers is presented as a multilayer structure, the relative positioning relationship of these layers or the order in which the layers are arranged as shown reflects the specific implementation of the described or illustrated example, and different relative positioning relationships or orders of arrangement of layers may be feasible. In addition, the described or illustrated examples of multilayer structures may not reflect all layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0024] In the following description of the embodiments, when a parameter is referred to as being "predetermined", it may be intended to mean that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or may be set during the period of execution of the process or algorithm.

[0025] It will be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0026] In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0027] Various embodiments are directed to a semiconductor package having a small thickness and satisfying high performance and high capacity requirements while reducing process defects by a method of stacking a plurality of semiconductor chips and connecting the semiconductor chips to a redistribution layer using a vertical interconnector.

[0028] Figure 1A is a plan view illustrating an effective surface of a semiconductor chip according to an embodiment, Figure 1B It is along Figure 1A A cross-sectional view taken along line A1-A1'.

[0029] Reference Figure 1A and Figure 1B The semiconductor chip 100 may include an active surface 101 provided with a chip pad 110 , an inactive surface 102 located at an opposite side of the active surface 101 , and side surfaces 103 , 104 , 105 , and 106 connecting the active surface 101 and the inactive surface 102 .

[0030] Since the semiconductor chip 100 has a planar rectangular shape or a similar shape thereof, the semiconductor chip 100 may include four side surfaces 103, 104, 105, and 106. Among the side surfaces 103, 104, 105, and 106, the side surfaces 103 and 105 facing each other in a first direction parallel to the effective surface 101 and / or the ineffective surface 102 of the semiconductor chip 100 will be referred to as the first side surface 103 and the third side surface 105. In addition, the side surfaces 104 and 106 facing each other in a second direction perpendicular to the first direction while being parallel to the effective surface 101 and / or the ineffective surface 102 of the semiconductor chip 100 will be referred to as the second side surface 104 and the fourth side surface 106. In an embodiment, the lengths of the first side surface 103 and the third side surface 105 may be smaller than the second side surface 104 and the fourth side surface 106. However, the present embodiment is not limited thereto, and the lengths of the side surfaces may be set to various values.

[0031] The chip pad 110 may be arranged at two edge regions (i.e., edge regions adjacent to the first side surface 103 and edge regions adjacent to the third side surface 105) of the effective surface 101 in the first direction. That is, the chip pad 110 may be arranged by edge pad type. Among the chip pads 110, the chip pad 110 arranged at the edge region near the first side surface 103 will be referred to as one side chip pad 110A. The chip pad 110 arranged at the edge region near the third side surface 105 will be referred to as the other side chip pad 110B. In an embodiment, the chip pads 110A on one side may be arranged in a row along the second direction, and the chip pads 110B on the other side may also be arranged in a row along the second direction. However, the present embodiment is not limited thereto, and the chip pads 110A on one side and / or the chip pads 110B on the other side may be arranged at the two edge regions in the first direction in various ways. In an embodiment, the number of chip pads 110A on one side may be greater than the number of chip pads 110B on the other side. However, the present embodiment is not limited thereto, and the number of chip pads 110A on one side and the number of chip pads 110B on the other side may be set to various values. In an embodiment, the chip pad 110 may have a planar rectangular shape. However, the present embodiment is not limited thereto, and the planar shape of the chip pad 110 may be modified in various ways.

[0032] When these semiconductor chips 100 are stacked in a vertical direction, it is difficult to simultaneously expose one side chip pad 110A and the other side chip pad 110B regardless of the method for stacking semiconductor chips 100. To solve this problem, semiconductor chip 100 may further include a chip redistribution layer 120 formed on active surface 101.

[0033] The chip redistribution layer 120 may include redistribution dielectric layers 121 and 125 and a redistribution conductive layer 123 .

[0034] For example, the redistribution conductive layer 123 may include Figure 1AThe redistribution pads 123A and the redistribution lines 123B in the plan view shown. The redistribution pads 123A may be arranged at an edge region close to the fourth side surface 106 among the two edge regions in the second direction. The redistribution lines 123B may extend from the redistribution pads 123A to the chip pads 110B on the other side. In an embodiment, the redistribution pads 123A may be arranged in a row along the first direction, and the number of the redistribution pads 123A is set to the same value as the number of the chip pads 110B on the other side, so that the redistribution pads 123A correspond to the chip pads 110B on the other side one by one. However, the present embodiment is not limited thereto, and the number and arrangement of the redistribution pads 123A may be modified in various ways. In an embodiment, the redistribution pads 123A may be arranged at an edge region close to the fourth side surface 106. However, the present embodiment is not limited thereto, and the redistribution pads 123A may be arranged at an edge region close to the second side surface 104. The edge area where the redistribution pad 123A is set among the two edge areas in the second direction can be determined based on the offset stacking direction of the semiconductor chip 100 to be described below. In an embodiment, the redistribution pad 123A can be electrically connected to the chip pad 110B on the other side. However, the present embodiment is not limited to this, and the redistribution pad 123A can be electrically connected to the chip pad 110A on one side. The chip pad connected with the redistribution pad 123A among the chip pad 110A on one side and the chip pad 110B on the other side can be determined based on the offset stacking direction of the semiconductor chip 100 to be described below. When the redistribution pad 123A is electrically connected to the chip pad 110B on the other side, the redistribution pad 123A can be as Figure 1A As shown, the redistribution pads 123A are arranged relatively close to the third side surface 105 in the first direction, which makes it possible to shorten the connection path to the chip pads 110B on the other side. On the other hand, when the redistribution pads 123A are connected to the chip pads 110A on one side, the redistribution pads 123A can be arranged relatively close to the first side surface 103 in the first direction in the opposite manner of the structure shown. When the redistribution pads 123A are connected to the chip pads 110B on the other side, and the chip pads 110B on the other side are less than the chip pads 110A on the one side, the chip redistribution layer 120 and the package redistribution layer 600 (see Figure 7 ) can be relatively simplified. In an embodiment, the redistribution pad 123A may have a planar rectangular shape that is the same as or similar to the chip pad 110. For ease of description, the redistribution pad 123A is represented by a thicker solid line than the chip pad 110. However, the present embodiment is not limited thereto, and the planar shape of the redistribution pad 123A may be modified in various ways. The redistribution lines 123B may be formed so as not to cross each other. For this structure, the redistribution pad 123A and the other side chip pad 110B may be connected to each other in ascending order of the distance between them.

[0035] Reference Figure 1B In the cross section shown, the redistribution conductive layer 123 may be covered by the redistribution dielectric layers 121 and 125, except for the portion exposed by the openings of the redistribution dielectric layers 121 and 125, to electrically isolate the redistribution conductive layer 123 from other components. The first redistribution dielectric layer 121 covering the effective surface 101 of the semiconductor chip 100 may have an opening exposing the chip pad 110. The redistribution line 123B may fill the opening of the first redistribution dielectric layer 121 to be electrically connected to the chip pad 110. The redistribution line 123B may extend over the first redistribution dielectric layer 121. The redistribution line 123B may extend in a line shape with a smaller width. The redistribution line 123B may have an end portion with a relatively large width. When covering the redistribution line 123B and the first redistribution dielectric layer 121, the second redistribution dielectric layer 125 may have an opening exposing the end portion of the redistribution line 123B. Portions of the ends of the redistribution lines 123B exposed through the openings formed in the second redistribution dielectric layer 125 may constitute redistribution pads 123A.

[0036] The semiconductor chip 100 according to the embodiment may include a mobile dynamic random access memory (DRAM). However, the present embodiment is not limited thereto, and the semiconductor chip 100 may include a nonvolatile memory such as a flash memory, a phase change RAM (PRAM) or a magnetoresistive RAM (MRAM) or a volatile memory such as a DRAM or a static RAM (SRAM).

[0037] The plurality of semiconductor chips 100 may be stacked in a vertical direction to form a semiconductor package. Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 and Figure 7 To describe the structure.

[0038] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 and Figure 7 is a diagram illustrating a semiconductor package and a method for manufacturing the same according to an embodiment. For example, Figure 2A , Figure 3A , Figure 4A and Figure 5A It is a plan view of a semiconductor package viewed in the direction of the active surface. Figure 2B , Figure 3B, Figure 4B and Figure 5B are respectively FIG. 2A to FIG. 5B Corresponding cross-sectional view. Specifically, Figures 2B to 5B Along the FIG. 2A to FIG. 5A A cross-sectional view taken along line A2-A2'. Figure 6 and Figure 7 is an example of a reference Figure 5A and Figure 5B The following will be omitted with reference to Figure 1A and Figure 1B The components described are the same as the components described.

[0039] First, the manufacturing method will be described.

[0040] Reference Figure 2A and Figure 2B , a carrier substrate 200 may be provided. The carrier substrate 200 may be a glass carrier substrate, a silicon carrier substrate, a ceramic carrier substrate, etc. Alternatively, the carrier substrate 200 may be a wafer, and a plurality of packages may be formed on the carrier substrate 200 at the same time.

[0041] Then, a first chip stack 300 may be formed on the first surface 201 of the carrier substrate 200. The first chip stack 300 may include a plurality of first semiconductor chips 300-1 to 300-4 stacked in a direction perpendicular to the first surface 201 of the carrier substrate 200. In an embodiment, the first chip stack 300 may include four first semiconductor chips 300-1 to 300-4. However, the present embodiment is not limited thereto, and the number of semiconductor chips included in the first chip stack 300 may be set to various values, such as but not limited to 2 and 8. For convenience of description, the four first semiconductor chips are sequentially represented by reference numerals 300-1 to 300-4 in ascending order of distance from the carrier substrate 200.

[0042] Each of the first semiconductor chips 300 - 1 to 300 - 4 may have a Figure 1A and Figure 1B The semiconductor chip 100 described above has substantially the same structure. Therefore, each of the first semiconductor chips 300-1 to 300-4 may include an active surface 301, and a chip pad 310 and a redistribution conductive layer 323 (including a redistribution pad 323A and a redistribution line 323B) are disposed on the active surface 301. Each of the first semiconductor chips 300-1 to 300-4 may also include an ineffective surface 302 located on the opposite side of the active surface 301. In addition, each of the first semiconductor chips 300-1 to 300-4 may include first to fourth side surfaces 303, 304, 305 and 306 connecting the active surface 301 and the ineffective surface 302. For reference, Figure 2B It is along Figure 2A The cross-sectional view taken along the line A2-A2' of FIG. 1 is a cross-sectional view in which the chip pad 310 cannot be seen. For the convenience of description, Figure 2B The cross-sectional view omits illustration of the redistribution line 323B and the redistribution dielectric layer. However, each of the first semiconductor chips 300-1 to 300-4 may include the same Figure 1B The cross-sectional view of the chip redistribution layer 120 depicts the same redistribution layer. Each of the first semiconductor chips 300-1 to 300-4 may be the same memory chip (eg, the same mobile DRAM chip).

[0043] A plurality of first semiconductor chips 300-1 to 300-4 may be stacked on the carrier substrate 200 so that the ineffective surface 302 faces the carrier substrate 200 and the effective surface 301 is located on the opposite side of the ineffective surface 302. That is, the plurality of first semiconductor chips 300-1 to 300-4 may be stacked in a face-up manner. An adhesive layer 330 may be formed on the ineffective surface 302 of each of the first semiconductor chips 300-1 to 300-4. Through the adhesive layer 330, each of the first semiconductor chips 300-1 to 300-4 may be attached to the first semiconductor chip or the first surface 201 of the carrier substrate 200 immediately below. The adhesive layer 330 may include a dielectric adhesive material such as a die attach film (DAF).

[0044] A plurality of first semiconductor chips 300-1 to 300-4 may be stacked so that the chip pad 310A and the redistribution pad 323A of one side of each of the first semiconductor chips 300-1 to 300-4 are fully exposed. For example, any one of the first semiconductor chips 300-1 to 300-4 may be stacked with a constant offset relative to another first semiconductor chip adjacent in the stacking direction in a predetermined direction parallel to the first surface 201 of the carrier substrate 200. The predetermined direction may indicate a direction away from the first side surface 303 close to the chip pad 310A on one side and the fourth side surface 306 close to the redistribution pad 323A in a third direction intersecting the first direction and the second direction. The predetermined direction will be referred to as the first offset direction below. Hereinafter, the offset between the first semiconductor chips 300-1 to 300-4, each adjacent to each other, will be referred to as the first offset D1. The first offset D1 may be constant or may not be constant. However, the first offset D1 needs to have a value capable of exposing at least the chip pad 310A and the redistribution pad 323A on one side. Intercepted from a third party Figure 2B The cross-sectional view of FIG. 1 shows the first chip stack 300 having a stepped shape from this angle.

[0045] As the first semiconductor chips are offset and stacked, the chip pads 310A and the redistribution pads 323A on one side of the bottom semiconductor chip 300-1 may not be covered by other first semiconductor chips 300-2 to 300-4. On the contrary, the chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chip 300-1 may be exposed. Similarly, the chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chip 300-2 may not be covered by the first semiconductor chips 300-3 and 300-4 above the first semiconductor chip 300-2. On the contrary, the chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chip 300-2 may be exposed. The chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chip 300-3 may not be covered by the first semiconductor chip 300-4 located on the first semiconductor chip 300-3. On the contrary, the chip pad 310A and the redistribution pad 323A on one side of the first semiconductor chip 300-3 may be exposed. Since the uppermost first semiconductor chip 300-4 is located at the uppermost portion of the first chip stack 300, if the semiconductor package includes only the first chip stack 300, the uppermost first semiconductor chip 300-4 may always be exposed regardless of the stacking structure. In this case, the redistribution pad 323A and the redistribution line 323B of the uppermost first semiconductor chip 300-4 may be omitted. As will be described below, however, when another semiconductor chip (e.g., Figure 3A and Figure 3B When the second semiconductor chip 400-1) is located on the first semiconductor chip 300-4, similar to the other first semiconductor chips 300-1 to 300-3, the first semiconductor chip 300-4 may include redistribution pads 323A and redistribution lines 323B.

[0046] Reference Figure 3A , Figure 3B , Figure 4A and Figure 4B , a second chip stack 400 may be formed on the first chip stack 300. According to an embodiment, Figure 3A and Figure 3B Only the second semiconductor chip 400 - 1 located at the lowermost portion of the second semiconductor chips 400 - 1 to 400 - 4 included in the second chip stack 400 is shown. Figure 4A and Figure 4B The entire second chip stack 400 (including the second semiconductor chips 400 - 1 to 400 - 4 ) is shown.

[0047] The second chip stack 400 may include a plurality of second semiconductor chips 400-1 to 400-4 stacked in a vertical direction. The number of second semiconductor chips 400-1 to 400-4 included in the second chip stack 400 may be set to four (which is equal to the number of first semiconductor chips 300-1 to 300-4 included in the first chip stack 300). However, the present embodiment is not limited thereto, and the number of semiconductor chips included in the second chip stack 400 may be set to various values, such as but not limited to 2 and 8. In addition, the number of semiconductor chips included in the second chip stack 400 may be different from the number of semiconductor chips included in the first chip stack 300. For convenience of description, the four second semiconductor chips are sequentially represented by reference numerals 400-1 to 400-4 in ascending order of distance from the carrier substrate 200.

[0048] Each of the second semiconductor chips 400 - 1 to 400 - 4 may have Figure 1A and Figure 1B The semiconductor chip 100 and / or each of the first semiconductor chips 300-1 to 300-4 may have substantially the same structure. Therefore, each of the second semiconductor chips 400-1 to 400-4 may include an active surface 401 provided with a chip pad 410 and a redistribution conductive layer 423, the redistribution conductive layer 423 including a redistribution pad 423A and a redistribution line 423B. Each of the second semiconductor chips 400-1 to 400-4 may also include an inactive surface 402 located on the opposite side of the active surface 401 and a first side surface 403 to a fourth side surface 406 connecting the active surface 401 and the inactive surface 402.

[0049] However, each of the second semiconductor chips 400-1 to 400-4 may be stacked offset in the opposite direction compared to the first semiconductor chips 300-1 to 300-4. Each of the second semiconductor chips 400-1 to 400-4 may be formed by rotating the semiconductor chip 100 by 180 degrees around the axis in a direction parallel to the side surfaces 103 to 106 of the semiconductor chip 100 (i.e., a direction passing through the effective surface 101 and the ineffective surface 102). Therefore, the first side surface 403 to the fourth side surface 406 of each of the second semiconductor chips 400-1 to 400-4 may be located at a position opposite to the position of the first side surface 303 to the fourth side surface 306 of each of the first semiconductor chips 300-1 to 300-4, respectively. That is, assuming that the first side surface 303 to the fourth side surface 306 of each of the first semiconductor chips 300-1 to 300-4 are respectively located at the top side, the right side, the bottom side and the left side in the plan view, the first side surface 403 to the fourth side surface 406 of each of the second semiconductor chips 400-1 to 400-4 may be respectively located at the bottom side, the left side, the top side and the right side in the plan view. In addition, the chip pads 410 and the redistribution conductive layer 423 of the second semiconductor chips 400-1 to 400-4 may also be located at positions opposite to those of the chip pads 310 and the redistribution conductive layer 323 of the first semiconductor chips 300-1 to 300-4. That is, assuming that the one side chip pad 310A and the other side chip pad 310B of the first semiconductor chips 300-1 to 300-4 are located at the top edge area and the bottom edge area in the plan view, and the redistribution pad 323A is set to be close to the bottom side at the left edge area in the plan view, then the one side chip pad 410A and the other side chip pad 410B of the second semiconductor chips 400-1 to 400-4 may be located at the bottom edge area and the top edge area in the plan view, and the redistribution pad 423A may be set to be close to the top side at the right edge area in the plan view.

[0050] For reference, something like Figure 2B , Figure 3B and Figure 4B 4 is a cross-sectional view taken along line A2-A2'. Unlike the first semiconductor chips 300-1 to 300-4, the chip pads 410A on one side of the second semiconductor chips 400-1 to 400-4 can be seen in the cross-sectional view, and the chip pads 410B on the other side and the redistribution pads 423A cannot be seen in the cross-sectional view. For convenience of description, Figure 3B and Figure 4B The cross-sectional view omits illustration of the redistribution line 423B and the redistribution dielectric layer. However, each of the second semiconductor chips 400-1 to 400-4 may include the same Figure 1B The cross-sectional view of the chip redistribution layer 120 depicts the same redistribution layer.

[0051] Each of the second semiconductor chips 400-1 to 400-4 may be the same memory chip (eg, the same mobile DRAM chip). The second semiconductor chips 400-1 to 400-4 may be the same memory chip as the first semiconductor chips 300-1 to 300-4.

[0052] A plurality of second semiconductor chips 400-1 to 400-4 may be stacked on the first chip stack 300 so that the ineffective surface 402 faces the carrier substrate 200 and the effective surface 401 is located on the opposite side of the ineffective surface 402. That is, the plurality of second semiconductor chips 400-1 to 400-4 may be stacked in a face-up manner. An adhesive layer 430 may be formed on the ineffective surface 402 of each of the second semiconductor chips 400-1 to 400-4. Through the adhesive layer 430, each of the second semiconductor chips 400-1 to 400-4 may be attached to the effective surface 301 of the uppermost first semiconductor chip 300-4 of the corresponding second semiconductor chip immediately below or the first chip stack 300. The adhesive layer 430 may include a dielectric adhesive material such as DAF.

[0053] The plurality of second semiconductor chips 400-1 to 400-4 may be stacked so that the chip pad 410A and the redistribution pad 423A on one side of each of the second semiconductor chips 400-1 to 400-4 are all exposed. For example, any one of the second semiconductor chips 400-1 to 400-4 may be stacked with a constant offset relative to another second semiconductor chip adjacent in the stacking direction in a predetermined direction parallel to the first surface 201 of the carrier substrate 200. The predetermined direction may indicate a direction away from the first side surface 403 close to the chip pad 410A on one side and the fourth side surface 406 close to the redistribution pad 423A in a third direction intersecting the first direction and the second direction. The predetermined direction will be referred to as the second offset direction hereinafter. Since the chip pads 410A and the redistribution pads 423A on one side of the second semiconductor chips 400-1 to 400-4 are respectively located on the opposite sides of the chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chips 300-1 to 300-4, the second offset direction may face in the opposite direction of the first offset direction. For example, when the first offset direction faces between the right side and the bottom side, the second offset direction may face between the top side and the left side when parallel to the first offset direction. Hereinafter, the offset between the second semiconductor chips 400-1 to 400-4 adjacent to each other will be referred to as the second offset D2. The second offset D2 may be constant or may not be constant. However, the second offset D2 needs to have a value that can expose at least one side of the chip pads 410A and the redistribution pads 423A. In an embodiment, the second offset D2 may be equal to the first offset D1. However, in other embodiments, the second offset D2 may be different from the first offset D1. As a cross-sectional view taken in a third direction, Figure 4B The second chip stack 400 having a stepped shape facing the opposite direction of the first chip stack 300 is shown.

[0054] As the second semiconductor chips are offset and stacked, the chip pads 410A and the redistribution pads 423A on one side of the lowermost second semiconductor chip 400-1 may not be covered by other second semiconductor chips 400-2 to 400-4. On the contrary, the chip pads 410A and the redistribution pads 423A on one side of the second semiconductor chip 400-1 may be exposed. Similarly, the chip pads 410A and the redistribution pads 423A on one side of the second semiconductor chip 400-2 may not be covered by the second semiconductor chips 400-3 and 400-4 above the second semiconductor chip 400-2. On the contrary, the chip pads 410A and the redistribution pads 423A on one side of the second semiconductor chip 400-2 may be exposed. The chip pads 410A and the redistribution pads 423A on one side of the second semiconductor chip 400-3 may not be covered by the second semiconductor chip 400-4 located on the second semiconductor chip 400-3. On the contrary, the chip pad 410A and the redistribution pad 423A on one side of the second semiconductor chip 400-3 may be exposed. Since the second semiconductor chip 400-4 is located at the uppermost portion of the second chip stack 400, when the semiconductor package includes only the first chip stack 300 and the second chip stack 400 and no other electronic components are disposed on the second chip stack 400, the second semiconductor chip 400-4 may be exposed. Figure 4A The redistribution layer including the redistribution pads 423A and the redistribution lines 423B is omitted from the uppermost second semiconductor chip 400-4. However, when an electronic component (not shown) such as another semiconductor chip is disposed on the second chip stack 400, the uppermost second semiconductor chip 400-4 may include the redistribution pads 423A and the redistribution lines 423B, like the other second semiconductor chips 400-1 to 400-3.

[0055] The chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chips 300-1 to 300-4 may be exposed. That is, the chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chips 300-1 to 300-4 may not be covered by the second chip stack 400. This is to form a vertical interconnector on the chip pads 310A and the redistribution pads 323A on one side to extend in the vertical direction. In addition, since the offset stacking direction of the second chip stack 400 is in the opposite direction opposite to the offset stacking direction of the first chip stack 300, the second chip stack 400 is likely to cover at least some of the chip pads 310A and the redistribution pads 323A on one side of the first semiconductor chips 300-1 to 300-4. In some embodiments, to prevent such a risk, a distance D3 in the third direction between the lowermost second semiconductor chip 400-1 of the second chip stack 400 and the uppermost first semiconductor chip 300-4 of the first chip stack 300 may be increased as much as possible. In addition, the second offset D2 may be reduced as much as possible.

[0056] However, when the distance D3 is excessively increased, the second chip stack 400 may not be reliably supported by the first chip stack 300, causing the second chip stack 400 to tilt to one side. To prevent this tilt, the distance D3 may be appropriately adjusted, or a support structure (not shown) having substantially the same thickness as the first chip stack 300 may be formed under the second chip stack 400.

[0057] In this way, the first chip stack 300 and the second chip stack 400 may be formed in an arrow shape facing the first offset direction over the carrier substrate 200. In this state, the one side chip pads 310A and the redistribution pads 323A of the first semiconductor chips 300-1 to 300-4 of the first chip stack 300 may be fully exposed, and the one side chip pads 410A and the redistribution pads 423A of the second semiconductor chips 400-1 to 400-3 except the uppermost second semiconductor chip 400-4 of the second chip stack 400 may be fully exposed. Since the entire effective surface 401 of the uppermost second semiconductor chip 400-4 is exposed, all the chip pads 410 may be exposed.

[0058] Reference Figure 5A and Figure 5B , the first vertical interconnectors 340 may be respectively formed on the one side chip pads 310A and the redistribution pads 323A of the first semiconductor chips 300-1 to 300-4 and may extend in the vertical direction while being connected to the one side chip pads 310A and the redistribution pads 323A. The second vertical interconnectors 440 may be respectively formed on the one side chip pads 410A and the redistribution pads 423A of the second semiconductor chips 400-1 to 400-3 and the chip pads 410 of the uppermost second semiconductor chip 400-4 of the second chip stack 400 and extend in the vertical direction while being connected to the one side chip pads 410A, the redistribution pads 423A and the chip pads 410.

[0059] For example, the first vertical interconnector 340 and the second vertical interconnector 440 may be bonding wires. The process of forming the first vertical interconnector 340 and the second vertical interconnector 440 will be briefly described below. First, with respect to the first vertical interconnector 340 connected to the chip pad 310A on one side, the first end of the lead may be bonded to the chip pad 310A on one side by a wire bonding machine (not shown). The lead may include a metal (e.g., gold, silver, copper, and platinum or an alloy thereof), which may be welded to the chip pad 310A on one side by ultrasonic energy and / or heat. Then, the second end of the lead may be pulled away from the carrier substrate 200 (e.g., from bottom to top) in a vertical direction by the wire bonding machine. Subsequently, when the second end of the lead extends to a desired position, the second end of the lead may be cut. In this way, a first vertical interconnector 340 having a first end (e.g., a lower end) bonded to the chip pad 310A on one side and a second end (e.g., an upper end) located at a predetermined distance from the first surface 201 of the carrier substrate 200 may be formed. The predetermined distance may have a value greater than a distance from the first surface 201 of the carrier substrate 200 to an upper surface of the second chip stack 400 .

[0060] Alternatively, the second vertical interconnector 440 connected to each chip pad 410 of the second semiconductor chip 400-4 located at the uppermost portion of the second chip stack 400 may be another type of interconnector, rather than a bonding wire. For example, the second vertical interconnector 440 connected to each chip pad 410 of the second semiconductor chip 400-4 may be various types of bumps, such as a stud bump and a column bump. The bump may include metals such as copper, silver, tin, and lead.

[0061] Reference Figure 6 , a molding layer 500 may be formed on the carrier substrate 200 on which the first and second chip stacks 300 and 400 and the first and second vertical interconnectors 340 and 440 are formed.

[0062] The molding layer 500 may be formed by a molding process involving filling an empty space of a mold (not shown) with a molding material and then curing the molding material. The molding material may include a thermosetting resin, such as epoxy molding compound (EMC).

[0063] The molding layer 500 may be formed to expose the second end (e.g., upper end) of the first vertical interconnector 340 and the second vertical interconnector 440 when covering the first chip stack 300 and the second chip stack 400 and the first vertical interconnector 340 and the second vertical interconnector 440. For this structure, after the molding layer 500 is formed to cover the first chip stack 300 and the second chip stack 400 and the first vertical interconnector 340 and the second vertical interconnector 440, a grinding process may be performed on the molding layer 500. The grinding process may include a mechanical or chemical polishing process. Alternatively, by adjusting the shape of the first vertical interconnector 340 and the second vertical interconnector 440 and / or the shape of the mold without performing the grinding process, the second end of the first vertical interconnector 340 and the second vertical interconnector 440 may be exposed.

[0064] Thus, the mold layer 500 may have a first surface 501 formed at substantially the same level as the second ends of the first and second vertical interconnectors 340 and 440 , and the second ends of the first and second vertical interconnectors 340 and 440 may be exposed through the first surface 501 .

[0065] Reference Figure 7 A package redistribution layer 600 may be formed on the first surface 501 of the mold layer 500. The redistribution layer formed on the first surface 501 of the mold layer 500 is referred to as a package redistribution layer 600 in order to be distinguished from the redistribution layers 120, 323, and 423 formed in the semiconductor chip.

[0066] The formation process of the package redistribution layer 600 will be described below. First, a first redistribution dielectric layer 610 may be formed on the first surface 501 of the mold layer 500. The first redistribution dielectric layer 610 may be patterned to have openings that expose the second ends of the first vertical interconnector 340 and the second vertical interconnector 440, respectively. Then, a redistribution conductive layer 620 may be formed on the first redistribution dielectric layer 610. The redistribution conductive layer 620 may fill the opening of the first redistribution dielectric layer 610 to be electrically connected to the second ends of the first vertical interconnector 340 and the second vertical interconnector 440. The redistribution conductive layer 620 may be patterned into various shapes. The redistribution conductive layer 620 connected to the first vertical interconnector 340 will be referred to as a first redistribution conductive layer 620A, and the redistribution conductive layer 620 connected to the second vertical interconnector 440 will be referred to as a second redistribution conductive layer 620B. Then, a second redistribution dielectric layer 630 may be formed on the first redistribution dielectric layer 610 and the redistribution conductive layer 620. The second redistribution dielectric layer 630 may be patterned to have openings exposing portions of the redistribution conductive layer 620. For convenience of description, the cross-sectional view only shows two openings of the first redistribution dielectric layer 610 respectively exposing the second ends of the first vertical interconnectors 340 connected to the lowermost first semiconductor chip 300-1 and the second ends of the second vertical interconnectors 440 connected to the lowermost second semiconductor chip 400-1, and two redistribution conductive layers 620 filling the two openings. However, the first redistribution dielectric layer 610 may have openings exposing the second ends of the first vertical interconnectors 340 connected to the remaining first semiconductor chips 300-2, 300-3, and 300-4, the second ends of the second vertical interconnectors 440 connected to the remaining second semiconductor chips 400-2, 400-3, and 400-4, and the redistribution conductive layer 620 may fill the openings.

[0067] Subsequently, external connection terminals 700 may be formed on the package redistribution layer 600 to be electrically connected to the redistribution conductive layer 620 through the opening of the second redistribution dielectric layer 630. In an embodiment, a solder ball may be used as the external connection terminal 700. However, the present embodiment is not limited thereto, and various types of electrical connectors may be used as the external connection terminal 700. The external connection terminal 700 may include a first external connection terminal 700A connected to the first redistribution conductive layer 620A and a second external connection terminal 700B connected to the second redistribution conductive layer 620B.

[0068] Then, the carrier substrate 200 may be removed. The carrier substrate 200 may be removed at any time after the molding layer 500 is formed.

[0069] Through the above process, it can be manufactured Figure 7 The semiconductor package shown.

[0070] Return to reference Figure 5A and Figure 7 , the semiconductor package may include a first chip stack 300, a first vertical interconnector 340, a second chip stack 400, and a second vertical interconnector 440. The first chip stack 300 may include a plurality of first semiconductor chips 300-1 to 300-4 stacked in a vertical direction. The first vertical interconnector 340 may be electrically coupled to the plurality of first semiconductor chips 300-1 to 300-4, respectively, and extend in the vertical direction. The second chip stack 400 may be disposed on the first chip stack 300 and may include a plurality of second semiconductor chips 400-1 to 400-4 stacked in the vertical direction. The second vertical interconnector 440 may be electrically coupled to the plurality of second semiconductor chips 400-1 to 400-4, respectively, and extend in the vertical direction.

[0071] Each of the first semiconductor chips 300-1 to 300-4 may include an active surface 301, a first chip pad 310A on one side, a first chip pad 310B on the other side, and a first redistribution pad 323A. The active surface 301 may be defined by two side surfaces in the first direction and two side surfaces in the second direction. The first chip pad 310A on one side may be disposed at an edge of the active surface 301 close to one side surface in the first direction. The first chip pad 310B on the other side may be disposed at an edge of the active surface 301 close to another side surface in the first direction. The first redistribution pad 323A may be electrically coupled to the first chip pad 310B on the other side and disposed at an edge of one side surface of the two side surfaces close to the second direction of the active surface 301.

[0072] The plurality of first semiconductor chips 300-1 to 300-4 may be stacked offset in a third direction intersecting the first direction and the second direction so that the first chip pad 310A and the first redistribution pad 323A on one side are exposed. For example, the plurality of first semiconductor chips 300-1 to 300-4 may be stacked offset in a direction away from one side surface in the first direction and one side surface in the second direction.

[0073] A first end of the first vertical interconnector 340 may be connected to the exposed one-side first chip pad 310A and the exposed first redistribution pad 323A.

[0074] Each of the second semiconductor chips 400-1 to 400-4 may be stacked and formed by rotating the first semiconductor chips 300-1 to 300-4 by 180 degrees around an axis parallel to the vertical direction. Therefore, the second semiconductor chip may include a second chip pad 410A on one side, a second chip pad 410B on the other side, and a second redistribution pad 423A located at an opposite position to the positions of the first chip pad 310A on one side, the first chip pad 310B on the other side, and the first redistribution pad 323A on the other side. However, since the second redistribution pad 423A is not required for the uppermost second semiconductor chip 400-4, the second redistribution pad 423A may be omitted from the uppermost second semiconductor chip 400-4.

[0075] The plurality of second semiconductor chips 400-1 to 400-4 may be offset stacked in the third direction so that the second chip pads 410A and the second redistribution pads 423A on one side are exposed. For example, the plurality of second semiconductor chips 400-1 to 400-4 may be offset stacked in the opposite direction of the offset stacking direction of the first semiconductor chips 300-1 to 300-4.

[0076] The first end of the second vertical interconnector 440 may be connected to the one side second chip pad 410A and the second redistribution pad 423A. However, when the second redistribution pad 423A is omitted from the uppermost second semiconductor chip 400-4, the first end of the second vertical interconnector 440 connected to the uppermost second semiconductor chip 400-4 may be connected to the one side second chip pad 410A and the other side second chip pad 410B.

[0077] The semiconductor package may further include a molding layer 500, a packaging redistribution layer 600, and external connection terminals 700. The molding layer 500 may cover the first chip stack 300 and the second chip stack 400. The packaging redistribution layer 600 and the external connection terminals 700 may be formed on a first surface 501 of the molding layer 500. Since the packaging redistribution layer 600 may be formed in a region defined by the molding layer 500, the semiconductor package may be a fan-out semiconductor package.

[0078] The first chip stack 300 may be identified as one semiconductor chip when connected to an external component through the first vertical interconnector 340, the first redistribution conductive layer 620A, and the first external connection terminal 700A connected thereto. The second chip stack 400 may be identified as another semiconductor chip different from the first chip stack 300 when connected to an external component through the second vertical interconnector 440, the second redistribution conductive layer 620B, and the second external connection terminal 700B connected thereto. That is, an electrical path through the first chip stack 300, the first vertical interconnector 340, the first redistribution conductive layer 620A, and the first external connection terminal 700A may be electrically isolated from an electrical path through the second chip stack 400, the second vertical interconnector 440, the second redistribution conductive layer 620B, and the second external connection terminal 700B and may be identified as a path separate therefrom.

[0079] Since components of the semiconductor package have been described during description of the manufacturing method, a detailed description thereof is omitted.

[0080] The semiconductor package and the method of manufacturing the same described so far can obtain the following effects.

[0081] First, a semiconductor package having a plurality of stacked semiconductor chips can be formed to meet high performance / high capacity requirements. In addition, a fan-out semiconductor package using a redistribution layer instead of an existing substrate can be formed by vertical wiring, which makes it possible to realize a semiconductor package with a small thickness.

[0082] In addition, when the semiconductor chip includes chip pads disposed at two edges thereof, the semiconductor package and manufacturing method can solve the problem that it is difficult to stack semiconductor chips while exposing all chip pads disposed at two edges thereof. For example, in order to solve this problem, a redistribution layer can be added to the semiconductor chip, and a plurality of semiconductor chips can be stacked with an offset in a diagonal direction. Specifically, a redistribution layer connected to only a chip pad disposed at one of the two edges of the semiconductor chip can be formed. Due to the formation of the redistribution layer, this makes it possible to reduce process costs or reduce process difficulty.

[0083] In the embodiment, the case where the semiconductor package includes two chip stacks stacked in the vertical direction (i.e., the first chip stack 300 and the second chip stack 400) is described. However, the semiconductor package may include only one of the first chip stack 300 and the second chip stack 400 or more stacks than the first chip stack 300 and the second chip stack 400.

[0084] When the semiconductor package includes only one chip stack, the redistribution layer of the uppermost semiconductor chip may be omitted. Therefore, the vertical interconnectors connected to the uppermost semiconductor chip may be connected to the one side chip pad and the other side chip pad, respectively. In addition, the vertical interconnectors connected to the uppermost semiconductor chip may be conductive bumps, and the vertical interconnectors connected to other semiconductor chips may be bonding wires.

[0085] When the semiconductor package includes three or more chip stacks, structures similar to the first chip stack 300 and the second chip stack 400 may be repeatedly stacked over the first chip stack 300 and the second chip stack 400. Among the semiconductor chip stacks, only the redistribution layer of the uppermost semiconductor chip of the uppermost chip stack may be omitted, and other semiconductor chips may include a redistribution layer. Three or more chip stacks may be stacked while their offset directions are alternately changed to expose all one side chip pads and redistribution pads of the semiconductor chips except the uppermost semiconductor chip.

[0086] Since a case where a semiconductor package includes only one chip stack or three or more chip stacks can be easily derived from the description of the above embodiments, a detailed description thereof is omitted.

[0087] According to the present embodiment, by a method of stacking a plurality of semiconductor chips each provided with die pads at both edges thereof, a semiconductor package having a small thickness and capable of satisfying high performance and high capacity requirements can be provided.

[0088] Furthermore, when the first vertical interconnector 340 and the second vertical interconnector 440 include bonding wires in the above-described semiconductor package, sweeping of the first vertical interconnector 340 and the second vertical interconnector 440 may occur. This will be referred to as Figure 8 Describe in more detail.

[0089] Figure 8 The sweep of the vertical lead is shown.

[0090] Reference Figure 8 , the vertical lead VW may have a first end E1 attached to the chip pad and a second end E2 located at an opposite side thereof.

[0091] The left side of the arrow shows the state immediately after the vertical wire VW is formed. In other words, the left side of the arrow shows the state immediately after the wire is cut in the wire bonding process using a wire bonding machine. As long as no external force is applied, such a vertical wire VW can maintain a substantially 90-degree vertical state.

[0092] The right side of the arrow shows the state after an external force (e.g., pressure) is applied to the vertical lead VW by the flow of the molding material during the molding process. When the pressure is applied, the first end E1 of the vertical lead VW does not move because the first end E1 is fixed to the chip pad. However, since the second end E2 of the vertical lead VW is not fixed, sweeping may occur. That is, the vertical lead VW may bend. As a result of the sweeping, the second end E2 of the vertical lead VW may shift to, for example, Figure 8 Random position within the range of the circle shown. The displacement of the second end E2 of the vertical lead VW may change due to the vortex of the molding material caused by the injection direction and pressure of the molding material and the surrounding structure. The longer the length of the vertical lead VW, the more severe the sweep. In the case of the vertical lead VW sweep, due to the change in the position of the second end E2 of the vertical lead VW, the component (e.g., the redistribution layer) to be connected to the second end E2 of the vertical lead VW may be misaligned with the second end E2 of the vertical lead VW. Therefore, a connection defect may occur between the vertical lead VW and the redistribution layer.

[0093] In other words, when the first vertical interconnectors 340 and the second vertical interconnectors 440 are bent and the positions of the second ends of the first vertical interconnectors 340 and the second vertical interconnectors 440 are changed, the first vertical interconnectors 340 and the second vertical interconnectors 440 may be misaligned with the corresponding openings of the first redistribution dielectric layer 610 and / or the corresponding redistribution conductive layer 620. As a result, poor connection between the first vertical interconnectors 340 and the second vertical interconnectors 440 and the corresponding redistribution conductive layer 620 may occur.

[0094] In the following embodiment, a semiconductor package that prevents poor connection between the first and second vertical interconnectors 340 and 440 and the redistribution conductive layer 620 will be described.

[0095] Fig. 9 is a cross-sectional view illustrating a semiconductor package and a method of manufacturing the same according to another embodiment. Fig. 10A is based on vertical interconnectors connected to the lowermost semiconductor chip of the first chip stack and adjacent to each other, Fig. 9 Magnified plan view of a landing pad and package redistribution layer in a semiconductor package. Fig. 10B is with Fig. 10A The cross-sectional view corresponding to the plan view. Fig. 10C yes Fig. 10A More specifically, Fig. 10A based on Figure 5A The vertical interconnectors in the R1 region are shown. Fig. 10B is from Fig. 10A Cross-sectional view on the left side. Fig. 10Cis an enlarged view of a landing pad located at a second position from the bottom and components connected thereto. Detailed description of components substantially the same as those of the above-described embodiment will be omitted.

[0096] Reference Fig. 9 The semiconductor package of the present embodiment may include a first chip stack 300 , a second chip stack 400 , a first vertical interconnector 340 , a second vertical interconnector 440 , and a mold layer 500 that are substantially the same as those of the above-described embodiment.

[0097] In addition, the semiconductor package may include a landing pad 800 and a package redistribution layer 600 ′ disposed on the first surface 501 of the mold layer 500 .

[0098] The landing pad 800 may be formed on the first surface 501 of the mold layer 500 to overlap each of the first vertical interconnector 340 and the second vertical interconnector 440. In other words, the landing pad 800 may be located Figure 5A The landing pads 800 are connected to the second end of the first vertical interconnector 340 connected to the lowermost first semiconductor chip 300-1, and the other landing pad 800 is connected to the second end of the second vertical interconnector 440 connected to the lowermost second semiconductor chip 400-1. The landing pads 800 may also be formed to be connected to the second ends of the first vertical interconnectors 340 of the remaining first semiconductor chips 300-2, 300-3, and 300-4 and the second ends of the second vertical interconnectors 440 of the remaining second semiconductor chips 400-2, 400-3, and 400-4, respectively.

[0099] Here, since the positions of the second ends of the first vertical interconnector 340 and the second vertical interconnector 440 may change due to the sweeping, the landing pad 800 may be arranged to be aligned with the first vertical interconnector 340 and the second vertical interconnector 440 with respect to the first ends of the first vertical interconnector 340 and the second vertical interconnector 440, respectively. As will be described later, the landing pad 800 may have a relatively large planar area and / or diameter. Therefore, even if the positions of the second ends of the first vertical interconnector 340 and the second vertical interconnector 440 change due to the sweeping of the first vertical interconnector 340 and the second vertical interconnector 440, the landing pad 800 may remain connected to the second ends of the first vertical interconnector 340 and the second vertical interconnector 440.

[0100] The landing pad 800 may include a metal material such as gold, aluminum, copper, titanium, tungsten or other conductive materials. The landing pad 800 may provide electrical connections between the first vertical interconnect 340 and the second vertical interconnect 440 and the package redistribution layer 600'. The landing pad 800 may be formed by plating or the like.

[0101] The package redistribution layer 600' may be formed on the first surface 501 of the mold layer 500 where the landing pad 800 is formed. The package redistribution layer 600' may include a first redistribution dielectric layer 610', a redistribution conductive layer 620', and a second redistribution dielectric layer 630'. The package redistribution layer 600' may be substantially the same as the package redistribution layer 600 of the above-described embodiment, except that the first redistribution dielectric layer 610' has a thickness covering the top surface and the side surface of the landing pad 800. The package redistribution layer 600' may also have openings 611 exposing the respective upper surfaces of the landing pad 800, and the redistribution conductive layer 620' may contact the upper surface of the landing pad 800 through the openings 611. The redistribution conductive layer 620' electrically connected to the first vertical interconnector 340 through the landing pad 800 will be referred to as the first redistribution conductive layer 620A'. In addition, the redistribution conductive layer 620' electrically connected to the second vertical interconnector 440 through the landing pad 800 will be referred to as a second redistribution conductive layer 620B'. Similar to the above-mentioned embodiment, for convenience of description, only two redistribution conductive layers 620' connected to the landing pad 800 are shown in this cross-sectional view. However, other redistribution conductive layers may be formed to be connected to the second end of the first vertical interconnector 340 and the second end of the second vertical interconnector 440 through the landing pad 800. For example, the redistribution conductive layer may be formed to be connected to the remaining first semiconductor chips 300-2, 300-3, and 300-4 through the first vertical interconnector 340, and further, the redistribution conductive layer may be formed to be connected to the remaining second semiconductor chips 400-2, 400-3, and 400-4 through the second vertical interconnector 440.

[0102] FIG. 10A to FIG. 10C A method of forming and aligning the first and second vertical interconnectors 340 and 440 , the landing pad 800 , and the redistribution conductive layer 620 ′ will be illustrated in detail in a plan view.

[0103] Fig. 10A and Fig. 10B Show Figure 5AThe first vertical interconnectors 340 in the region R1 of the lowermost semiconductor chip 300-1, that is, the first vertical interconnectors 340 whose first ends E1 are respectively connected to the redistribution pads 323A of the lowermost semiconductor chip 300-1, the landing pads 800 respectively connected to the second ends E2 of the first vertical interconnectors 340, and the first redistribution conductive layers 620A′ respectively connected to the landing pads 800. For convenience of description, in this figure, the line portion 620A-1′ of the first redistribution conductive layer 620A′ is represented as a shape extending in the right direction.

[0104] In the first vertical interconnector 340, Fig. 9 It can be shown in Fig. 10A The first vertical interconnect 340 on the line A3-A3' of FIG. 1 , the redistribution pad 323A connected to the first end E1 of the first vertical interconnect 340, and the landing pad 800 connected to the second end E2 of the first vertical interconnect 340 and the first redistribution conductive layer 620A'. In other words, the leftmost first vertical interconnect 340 and the redistribution pad 323A, the landing pad 800, and the first redistribution conductive layer 620A' connected thereto may correspond to the leftmost first vertical interconnect 340 on the line A3-A3' of FIG. Fig. 10A On the other hand, the remaining first vertical interconnector 340 is not shown in Fig. 9 In the cross-sectional view, it can be arranged through Fig. 9 in the direction of the cross-sectional view.

[0105] The redistribution pad 323A may have a planar rectangular shape. However, the present embodiment is not limited thereto, and the planar shape of the redistribution pad 323A may be modified in various ways. The width of the redistribution pad 323A in a plan view is represented by W0.

[0106] The first vertical interconnector 340 may have a planar circular shape. However, the present embodiment is not limited thereto, and the planar shape of the first vertical interconnector 340 may be modified in various ways. The planar width and / or diameter of the first vertical interconnector 340 will be referred to as the first width W1 hereinafter. The first end E1 of the first vertical interconnector 340 may be attached and / or bonded to the redistribution pad 323A to fix its position. The first vertical interconnector 340 may overlap and / or align with the redistribution pad 323A so that the center of the first end E1 of the first vertical interconnector 340 and the center of the redistribution pad 323A coincide with each other. On the other hand, as shown in reference Figure 8 As described, the second end E2 of the first vertical interconnector 340 may have a variable position. In other words, the center of the second end E2 of the first vertical interconnector 340 may be spaced apart from the center of the first end E1 of the first vertical interconnector 340 and / or the center of the redistribution pad 323A by a predetermined distance. Fig. 10A and Fig. 10BVarious examples of the changed position of the second end E2 of the first vertical interconnector 340 are shown.

[0107] The landing pad 800 may overlap and / or align with the first vertical interconnect 340 on the first vertical interconnect 340. Specifically, the landing pad 800 may overlap and / or align with the first vertical interconnect 340 so that its center coincides with the center of the first end E1 of the first vertical interconnect 340. Although the landing pad 800 is shown as having a planar circular shape, the present embodiment is not limited thereto, and the planar shape of the landing pad 800 may be modified differently. The planar width and / or diameter of the landing pad 800 will hereinafter be referred to as a fourth width W4.

[0108] The first redistribution conductive layer 620A' may have a line portion 620A-1' and a pad portion 620A-2'. The line portion 620A-1' may have a relatively narrow width and extend in one direction or bend in various directions, and the pad portion 620A-2' may have a relatively larger width than the line portion 620A-1' to facilitate connection with the landing pad 800. The pad portion 620A-2' of the first redistribution conductive layer 620A' may overlap and / or align with the landing pad 800 on the landing pad 800. Specifically, the pad portion 620A-2' may overlap and / or align with the landing pad 800 so that its center coincides with the center of the landing pad 800. Although the pad portion 620A-2' is shown as having a planar circular shape, the present embodiment is not limited thereto, and the planar shape of the pad portion 620A-2' may be modified differently. The plane width or diameter of the pad portion 620A- 2 ′ will hereinafter be referred to as a third width W3 .

[0109] The pad portion 620A-2' may be formed by a first redistribution dielectric layer (see Fig. 9 610') is connected to the landing pad 800. The opening 611 may also overlap and / or align with the pad portion 620A-2' and the landing pad 800, respectively. Specifically, the center of the opening 611 may coincide with the center of the pad portion 620A-2' and the center of the landing pad 800. Although the opening 611 is shown as having a planar circular shape, the present embodiment is not limited thereto, and the planar shape of the opening 611 may be modified differently. The planar width and / or diameter of the opening 611 will be referred to as the second width W2 below.

[0110] In summary, the redistribution pad 323A, the first end E1 of the first vertical interconnector 340, the first redistribution dielectric layer (see Fig. 9The opening 611 of the first redistribution conductive layer 610'), the pad portion 620A-2' of the first redistribution conductive layer 620A', and the landing pad 800 may overlap and / or align with each other so that their centers substantially coincide with each other. However, in other embodiments, these centers may be slightly shifted due to process issues, etc.

[0111] Although the redistribution pad 323A, the first end E1 of the first vertical interconnector 340, the first redistribution dielectric layer (see Fig. 9 The centers of the openings 611 of the first redistribution conductive layer 610'), the pad portions 620A-2' of the first redistribution conductive layer 620A', and the landing pad 800 are substantially aligned with each other or slightly shifted from each other, but they may be arranged to have the same pitch so that electrical connection can be made therebetween. That is, when the distance between the centers of the mutually adjacent redistribution pads 323A is referred to as the first pitch P1, the distance between the centers of the first ends E1 of the mutually adjacent first vertical interconnectors 340, the distance between the centers of the mutually adjacent openings 611, the distance between the centers of the mutually adjacent pad portions 620A-2', and the distance between the centers of the mutually adjacent landing pads 800 may be substantially the same as the first pitch P1.

[0112] Here, the first width W1 of the first vertical interconnector 340 may be the smallest, and the fourth width W4 of the landing pad 800 and the third width W3 of the pad portion 620A-2' may be greater than the first width W1, and the second width W2 of the opening 611 may be greater than the first width W1, and less than the fourth width W4 and the third width W3. The third width W3 and the fourth width W4 may be the same or similar to each other. The first width W1 may be several micrometers to several tens of micrometers. When the first width W1 (i.e., the thickness of the first vertical interconnector 340) is too small, it may be difficult to form a stable loop when forming the first vertical interconnector 340. In other words, it may be difficult to manufacture the first vertical interconnector 340 that is constantly formed in the vertical direction. In addition, since the displacement of the second end E2 of the first vertical interconnector 340 is too large due to the large influence from the flow of the molding material, it may be difficult to connect the landing pad 800 to the first vertical interconnector 340. On the other hand, when the first width W1 has an excessively large value, it may be difficult to form a loop using a wire bonding device using capillary bonding. The fourth width W4 may be determined in consideration of the displacement of the second end E2 of the first vertical interconnect 340 and the distance between the landing pads 800. More specifically, if the fourth width W4 is too small, the connection between the first vertical interconnect 340 and the landing pad 800 may be difficult. On the other hand, if the fourth width W4 is too large, an electrical short circuit between adjacent landing pads 800 may occur. In order to solve these problems, the lower limit and upper limit of the fourth width W4 must be appropriately adjusted. For example, the value of the fourth width W4 may be equal to or greater than the width W0 and / or length of the side of the chip pad (not shown) or the redistribution pad 323A, and less than the first pitch P1. In addition, the value of the fourth width W4 may be 2 to 3 times the first width W1. The third width W3 may be the same or similar to the fourth width W4. The value of the second width W2 may be between the third width W3 and the fourth width W4 and the first width W1. For example, the value of the second width W2 may be 1.2 to 1.8 times the first width W1.

[0113] In addition, the entire second end E2 of the first vertical interconnector 340 may contact the lower surface of the landing pad 800. Alternatively, when the displacement of the second end E2 of the first vertical interconnector 340 is large, a portion of the second end E2 of the first vertical interconnector 340 may contact the landing pad 800. However, even in this case, the area of ​​the portion of the second end E2 of the first vertical interconnector 340 that contacts the landing pad 800 may exceed a predetermined level to sufficiently electrically connect the landing pad 800 and the first vertical interconnector 340. For example, Fig. 10CAs shown, when a portion (see DI1) of the second end E2 of the first vertical interconnector 340 contacts the landing pad 800 and the remaining portion (see DI2) does not overlap with the landing pad 800, the value of the diameter DI1 of the portion of the second end E2 may be equal to or greater than 2 / 3 of the total diameter DI to meet the requirements of the electrical connection between the landing pad 800 and the first vertical interconnector 340.

[0114] According to the above-described semiconductor package and method of manufacturing the same, even if sweeping of the vertical interconnector occurs, the redistribution conductive layer and the vertical interconnector can be easily connected to each other by placing a relatively large landing pad between the redistribution conductive layer and the vertical interconnector.

[0115] also, Fig. 9 and FIG. 10A to FIG. 10C Show Figures 2A to 7 The connection and arrangement of vertical interconnects, landing pads, and redistribution conductive layers in a semiconductor package. Figures 2A to 7 The present embodiment can also be applied to other fan-out semiconductor packages using vertical interconnects. FIG. 11A to FIG. 12B Described as an example.

[0116] Fig.11A is a cross-sectional view illustrating a semiconductor package according to another embodiment, Fig. 11B It is shown Fig.11A A plan view of a chip stack and vertical interconnects of a semiconductor package. Fig.11A May include along Fig. 11B A cross-sectional view taken along line A4-A4'.

[0117] Reference Fig.11A and Fig. 11B , the semiconductor package may include a chip stack 1300 having a plurality of semiconductor chips 1300-1 to 1300-8 stacked in a substantially vertical direction. In this embodiment, the chip stack 1300 includes eight semiconductor chips 1300-1 to 1300-8. However, the present disclosure is not limited thereto, and the number of semiconductor chips included in the chip stack 1300 may vary.

[0118] Each of the semiconductor chips 1300-1 to 1300-8 may include an effective surface 1301 provided with a chip pad 1310 and an ineffective surface 1302 provided on the opposite side of the effective surface 1301. The chip pad 1310 may be provided at one of the two edge regions of the first direction of the effective surface 1301 (e.g., the left side). In addition, the chip pad 1310 may be arranged in a row in the second direction. However, the present disclosure is not limited thereto, and the arrangement of the chip pad 1310 may vary as long as the chip pad 1310 is provided in any one of the two edge regions in the first direction. The adhesive layer 1330 may be formed on the ineffective surface 1302 of each of the semiconductor chips 1300-1 to 1300-8.

[0119] Each of the semiconductor chips 1300 - 1 to 1300 - 8 may be the same memory chip (eg, NAND flash memory chip). However, the present disclosure is not limited thereto, and the semiconductor chips 1300 - 1 to 1300 - 8 may include different memory chips.

[0120] The semiconductor chips 1300-1 to 1300-8 may be stacked in a face-up manner with the effective surface 1301 facing upward. In this case, the semiconductor chips 1300-1 to 1300-8 may be stacked offset in a first offset direction from one side adjacent to the chip pad 1310 in the first direction toward the other side disposed opposite to the side so that all the chip pads 1310 of the semiconductor chips 1300-1 to 1300-8 are exposed. Both side walls of the semiconductor chips 1300-1 to 1300-8 in the second direction may be aligned with each other.

[0121] The vertical interconnector 1340 may extend in a substantially vertical direction, and a first end thereof may be connected to a chip pad 1310 correspondingly exposed based on the offset stacking. The vertical interconnector 1340 may be a bonding wire. Alternatively, the vertical interconnector 1340 connected to the uppermost semiconductor chip 1300-8 among the plurality of vertical interconnectors 1340 may be a conductive bump, and the remaining vertical interconnectors 1340 may be bonding wires.

[0122] The mold layer 1500 may be formed to cover the chip stack 1300 and the vertical interconnectors 1340 while having a first surface 1501 exposing second ends of the vertical interconnectors 1340 .

[0123] The landing pad 1800 may be formed to contact the second end of each vertical interconnector 1340 by being aligned with the respective vertical interconnectors 1340 on the first surface 1501 of the mold layer 1500 .

[0124] The package redistribution layer 1600 may include: a first redistribution dielectric layer 1610, which covers the first surface 1501 of the molding layer 1500 and the landing pad 1800; a redistribution conductive layer 1620, which is formed on the first redistribution dielectric layer 1610 and connected to the landing pad 1800 through the opening 1611 of the first redistribution dielectric layer 1610; and a second redistribution dielectric layer 1630, which covers the first redistribution dielectric layer 1610 and the redistribution conductive layer 1620.

[0125] The arrangement of the landing pad 1800, the opening 1611 of the first redistribution dielectric layer 1610, and the redistribution conductive layer 1620 may be similar to that described in reference to FIG. FIG. 10A to FIG. 10C Those described are substantially the same. Therefore, a detailed description thereof will be omitted.

[0126] The external connection terminals 1700 may be connected to the redistribution conductive layer 1620 through openings formed in the second redistribution dielectric layer 1630 .

[0127] Fig. 12A is a cross-sectional view illustrating a semiconductor package according to another embodiment, Fig. 12B It is shown Fig. 12A A plan view of first and second chip stacks and first and second vertical interconnectors of a semiconductor package. Fig. 12A May include along Fig. 12B A cross-sectional view taken along line A5-A5'.

[0128] Reference Fig. 12A and Fig. 12B , the semiconductor package may include: a first chip stack 2300 having a plurality of first semiconductor chips 2300-1 to 2300-4 stacked in a vertical direction; and a second chip stack 2400 disposed above the first chip stack 2300 and including a plurality of second semiconductor chips 2400-1 to 2400-4 stacked in a vertical direction. In this embodiment, each of the first chip stack 2300 and the second chip stack 2400 includes four semiconductor chips. However, the present disclosure is not limited thereto, and the number of semiconductor chips included in each of the first chip stack 2300 and the second chip stack 2400 may vary.

[0129] Each of the first semiconductor chips 2300-1 to 2300-4 may include an effective surface 2301 provided with a first chip pad 2310 and an ineffective surface 2302 provided on the opposite side of the effective surface 2301. The first chip pad 2310 may be provided at one of the two edge regions of the first direction of the effective surface 2301 (e.g., the left side). In addition, the first chip pad 2310 may be arranged in a row in the second direction. However, the present disclosure is not limited thereto, and the arrangement of the first chip pad 2310 may vary as long as the first chip pad 2310 is provided in any one of the two edge regions in the first direction. The adhesive layer 2330 may be formed on the ineffective surface 2302 of each of the first semiconductor chips 2300-1 to 2300-4.

[0130] Each of the first semiconductor chips 2300 - 1 to 2300 - 4 may be the same memory chip (eg, NAND flash memory chip). However, the present disclosure is not limited thereto.

[0131] The first semiconductor chips 2300-1 to 2300-4 may be stacked in a face-up manner with the effective surface 2301 facing upward. In this case, the first semiconductor chips 2300-1 to 2300-4 may be stacked offset in the first offset direction from one side adjacent to the first chip pad 2310 in the first direction toward the other side disposed opposite to the side so that all the first chip pads 2310 of the semiconductor chips 2300-1 to 2300-4 are exposed. Both sidewalls of the first semiconductor chips 2300-1 to 2300-4 in the second direction may be aligned with each other.

[0132] The first vertical interconnector 2340 may extend in a substantially vertical direction, with a first end thereof being connected to the first chip pad 2310 that is exposed based on the offset stacking. The first vertical interconnector 2340 may be a bonding wire.

[0133] Each of the second semiconductor chips 2400-1 to 2400-4 may include an active surface 2401 provided with a second chip pad 2410 and an inactive surface 2402 provided opposite to the active surface 2401. The second chip pad 2410 may be provided at the other of the two edge regions in the first direction of the active surface 2401 (e.g., the right side). For example, each of the second semiconductor chips 2400-1 to 2400-4 may be stacked and formed by rotating the first semiconductor chips 2300-1 to 2300-4 by 180 degrees around an axis in a substantially vertical direction. The adhesive layer 2430 may be formed on the inactive surface 2402 of each of the second semiconductor chips 2400-1 to 2400-4.

[0134] Each of the second semiconductor chips 2400-1 to 2400-4 may be the same memory chip (eg, NAND flash memory chip). In addition, each of the second semiconductor chips 2400-1 to 2400-4 may be the same memory chip as the first semiconductor chips 2300-1 to 2300-4.

[0135] The second semiconductor chips 2400-1 to 2400-4 may be stacked face-up with the active surface 2401 facing upward. In this case, the second semiconductor chips 2400-1 to 2400-4 may be stacked offset in a second offset direction opposite to the first offset direction so that all second chip pads 2410 of the second semiconductor chips 2400-1 to 2400-4 are exposed. Both sidewalls of the second semiconductor chips 2400-1 to 2400-4 in the second direction may be aligned with each other.

[0136] In addition, the second chip stack 2400 may be formed to expose all the first chip pads 2310 of the first chip stack 2300. This may be achieved by increasing the distance between the lowermost second semiconductor chip 2400-1 of the second chip stack 2400 and the uppermost first semiconductor chip 2300-4 of the first chip stack 2300 in the offset direction and / or reducing the offset between the second semiconductor chips 2400-1 to 2400-4.

[0137] The second vertical interconnector 2440 may extend in a substantially vertical direction, and a first end thereof may be connected to each second chip pad 2410 exposed based on the offset stacking. The second vertical interconnector 2440 may be a bonding wire. Alternatively, the second vertical interconnector 2440 connected to the uppermost second semiconductor chip 2400-4 among the plurality of second vertical interconnectors 2440 may be a conductive bump, and the remaining second vertical interconnectors 2440 may be bonding wires.

[0138] The mold layer 2500 may be formed to cover the first and second chip stacks 2300 and 2400 and the first and second vertical interconnectors 2340 and 2440 while having a first surface 2501 exposing second ends of the first and second vertical interconnectors 2340 and 2440 .

[0139] The landing pad 2800 may be formed to contact second ends of the first and second vertical interconnectors 2340 and 2440 by aligning with the first and second vertical interconnectors 2340 and 2440 on the first surface 2501 of the mold layer 2500 .

[0140] The package redistribution layer 2600 may include: a first redistribution dielectric layer 2610 covering the first surface 2501 of the mold layer 2500 and the landing pad 2800; a redistribution conductive layer 2620 formed on the first redistribution dielectric layer 2610 and connected to the landing pad 2800 through the opening 2611 of the first redistribution dielectric layer 2610; and a second redistribution dielectric layer 2630 covering the first redistribution dielectric layer 2610 and the redistribution conductive layer 2620. The redistribution conductive layer 2620 may include: a first redistribution conductive layer 2620A connected to the first vertical interconnector 2340 through the landing pad 2800; and a second redistribution conductive layer 2620B connected to the second vertical interconnector 2440 through the landing pad 2800.

[0141] The arrangement of the landing pad 2800, the opening 2611 of the first redistribution dielectric layer 2610, and the redistribution conductive layer 2620 may be similar to that described in reference to FIG. FIG. 10A to FIG. 10C Those described are substantially the same. Therefore, a detailed description thereof will be omitted.

[0142] The external connection terminals 2700 may be connected to the redistribution conductive layer 2620 through openings formed in the second redistribution dielectric layer 2630. The external connection terminals 2700 may include first external connection terminals 2700A connected to the first redistribution conductive layer 2620A and second external connection terminals 2700B connected to the second redistribution conductive layer 2620B.

[0143] In addition, Fig. 9 In the above-mentioned embodiment, unlike the redistribution conductive layer 620' formed on the first redistribution dielectric layer 610' of the package redistribution layer 600', the landing pad 800 may be formed to directly contact the mold layer 500. This will be referred to Fig.13 Describe in more detail.

[0144] Fig.13 yes Fig. 9 An enlarged view of region R2 of a semiconductor package.

[0145] Reference Fig.13 , the first surface 501 of the mold layer 500 may be rougher than the first surface 601 of the first redistribution dielectric layer 610'. One reason is that the mold layer 500 contains a large amount of fillers such as silicon dioxide. Due to the presence of such fillers, the first surface 501 of the mold layer 500 may not be smooth even after the grinding process is performed, and in particular, the filler loss generated during the grinding process may further increase the roughness of the first surface 501.

[0146] When the roughness of the first surface 501 of the mold layer 500 is large, the shape of the pattern formed thereon may be deformed. More specifically, in the process of forming a predetermined plating pattern on the first surface 501 of the mold layer 500 and etching a seed layer for the plating pattern, the required over-etching degree may increase as the roughness of the first surface 501 increases, thereby increasing the loss of the plating pattern. When forming a fine pattern (e.g., a redistributed conductive layer 620' having a narrow line width), the loss of the plating pattern may be a problem.

[0147] In the present embodiment, a landing pad 800 having a relatively large size may be formed on the first surface 501 of the mold layer 500. Then, a first redistribution dielectric layer 610' may be formed covering the landing pad 800 and having a smaller surface roughness than the mold layer 500. Then, a redistribution conductive layer 620' having a fine line width may be on the first redistribution dielectric layer 610'. Therefore, a semiconductor package that is not affected by the roughness of the first surface 501 of the mold layer 500 may be obtained.

[0148] Fig.14 A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to the embodiments is shown. The memory card 7800 includes a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiments.

[0149] The memory 7810 may include a nonvolatile memory device to which the technology of the embodiments of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that stored data is read out or data is stored in response to a read / write request from the host 7830 .

[0150] Fig.15 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be connected to each other through a bus 8715 that provides a path for data movement.

[0151] In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more of the semiconductor packages according to the embodiments of the present disclosure. The input / output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, etc. The memory 8713 is a device for storing data. The memory 8713 may store data and / or commands to be executed by the controller 8711, etc.

[0152] The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, the flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 may stably store a large amount of data in the flash memory system.

[0153] The electronic system 8710 may also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of a wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0154] The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission / reception system.

[0155] If the electronic system 8710 represents a device capable of performing wireless communications, the electronic system 8710 can be used in a communication system using technology such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0156] Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined in the following claims.

[0157] CROSS-REFERENCE TO RELATED APPLICATIONS

[0158] This application claims priority to Korean Patent Application No. 10-2019-0121521, filed on October 1, 2019, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor package, comprising: A chip stack including a plurality of semiconductor chips stacked in a vertical direction; a plurality of vertical interconnectors, each of which has a first end connected to the plurality of semiconductor chips, respectively, and extends in the vertical direction; a molding layer covering the chip stack and the vertical interconnector while exposing a second end of the vertical interconnector; a plurality of landing pads formed over one surface of the molding layer to respectively contact the second ends of the vertical interconnectors, wherein the plurality of landing pads are conductive and respectively overlap the first ends of the vertical interconnectors, wherein a width of the landing pads is greater than a width of the vertical interconnectors; and a package redistribution layer electrically connected to the vertical interconnector through the landing pad, wherein each of the plurality of semiconductor chips comprises a chip pad formed on an effective surface facing the package redistribution layer, wherein the plurality of semiconductor chips are stacked offset to expose the chip pads of the plurality of semiconductor chips; wherein the first end of the vertical interconnector is connected to the chip pad, and The plurality of semiconductor chips include a plurality of first semiconductor chips offset and stacked in a first offset direction and a plurality of second semiconductor chips offset and stacked above the first semiconductor chips in a second offset direction opposite to the first offset direction.

2. The semiconductor package according to claim 1, wherein A pitch of the plurality of landing pads is equal to a pitch of the first ends of the plurality of vertical interconnectors.

3. The semiconductor package according to claim 1, wherein: A center of the landing pad coincides with a center of the first end of the vertical interconnect.

4. The semiconductor package according to claim 1, wherein: A center of the second end of the vertical interconnect does not coincide with a center of each of the landing pads or a center of each of the first ends of the vertical interconnect.

5. The semiconductor package according to claim 1, wherein The width of the landing pad is equal to or greater than the width of the chip pad.

6. The semiconductor package according to claim 1, wherein A pitch of the plurality of landing pads is equal to a pitch of the first ends of the plurality of vertical interconnectors and a pitch of the plurality of chip pads, and The landing pad width has a value smaller than the pitch.

7. The semiconductor package according to claim 1, wherein: The package redistribution layer comprises: a first redistribution dielectric layer formed on the one surface of the mold layer to cover the landing pads and having a plurality of openings respectively exposing the landing pads; a plurality of redistribution conductive layers, the plurality of the redistribution conductive layers being formed on the first redistribution dielectric layer, and each of the redistribution conductive layers including a line portion having a relatively small width and a pad portion having a relatively large width and overlapping with each of the openings; and A second redistribution dielectric layer covers the first redistribution dielectric layer and the redistribution conductive layer.

8. The semiconductor package according to claim 7, wherein: A pitch of the plurality of landing pads, a pitch of the plurality of pad portions, a pitch of the first ends of the plurality of vertical interconnectors, and a pitch of the plurality of openings are equal to one another.

9. The semiconductor package according to claim 7, wherein: At least two selected from a center of the landing pad, a center of the pad portion, a center of the first end of the vertical interconnector, and a center of the opening coincide with each other.

10. The semiconductor package according to claim 1, wherein A portion of the second end of the vertical interconnect contacts each of the landing pads, and A width of the portion of the second end of the vertical interconnector is at least 2 / 3 of a width of the vertical interconnector.

11. The semiconductor package according to claim 1, wherein The vertical interconnects include bond wires.

12. The semiconductor package according to claim 7, wherein: The roughness of the one surface of the mold layer is greater than the roughness of one surface of the first redistribution dielectric layer facing the redistribution conductive layer.

13. The semiconductor package according to claim 12, wherein: The landing pad is in direct contact with the one surface of the molding layer, and The redistribution conductive layer is in direct contact with the one surface of the first redistribution dielectric layer.

14. The semiconductor package according to claim 1, wherein: The vertical interconnector connected to the uppermost semiconductor chip of the plurality of semiconductor chips of the chip stack includes a conductive bump, and The vertical interconnectors connected to the remaining semiconductor chips other than the uppermost semiconductor chip include bonding wires.

15. The semiconductor package according to claim 1, wherein: The plurality of semiconductor chips include an identical memory chip.

16. The semiconductor package according to claim 1, wherein The chip pad is formed in an edge region of the active surface, and The semiconductor chips are stacked with an offset in a direction away from the one edge region.

17. The semiconductor package according to claim 1, wherein: The chip pad of the first semiconductor chip is formed in an edge region of the active surface, wherein the chip pad of the second semiconductor chip is formed in another edge region of the active surface opposite to the one edge region, wherein the first semiconductor chips are stacked offset in a direction away from the one edge region, and The second semiconductor chips are stacked offset in a direction away from the other edge region.

18. The semiconductor package according to claim 1, wherein The second semiconductor chip has a state in which the first semiconductor chip is rotated 180 degrees around an axis parallel to the vertical direction.

19. The semiconductor package according to claim 1, wherein: Each of the plurality of semiconductor chips, except for at least the uppermost semiconductor chip, includes: an effective surface defined by two side surfaces in a first direction and two side surfaces in a second direction intersecting the first direction; a first one side chip pad disposed at an edge of the effective surface close to one side surface in the first direction; a first other side chip pad disposed at an edge of the effective surface close to another side surface in the first direction; and a first redistribution pad electrically connected to the first other side chip pad and disposed at an edge of the effective surface close to one side surface in the second direction, wherein the plurality of semiconductor chips are stacked offset toward one side in a third direction intersecting the first direction and the second direction, the one side being away from the one side surface in the first direction and the one side surface in the second direction so as to expose the first side chip pad and the first redistribution pad, Wherein, the first ends of the plurality of vertical interconnectors electrically connected to the plurality of semiconductor chips except the uppermost semiconductor chip are respectively connected to the first one-side chip pad and the first redistribution pad.

20. The semiconductor package according to claim 19, wherein The number of the first other-side chip pads is less than the number of the first one-side chip pads.

21. A semiconductor package, comprising: a plurality of first semiconductor chips stacked in a vertical direction; a plurality of second semiconductor chips stacked in the vertical direction above the first semiconductor chip; a plurality of vertical interconnectors, each of the vertical interconnectors having a first end connected to the plurality of first semiconductor chips and the plurality of second semiconductor chips, respectively, and extending in the vertical direction; a molding layer covering the plurality of first semiconductor chips, the plurality of second semiconductor chips, and the vertical interconnectors while exposing second ends of the vertical interconnectors; a plurality of landing pads formed over one surface of the molding layer to respectively contact the second ends of the vertical interconnectors, wherein the plurality of landing pads are conductive and respectively overlap the first ends of the vertical interconnectors, wherein a width of the landing pads is greater than a width of the vertical interconnectors; and a package redistribution layer electrically connected to the vertical interconnector through the landing pad, wherein each of the plurality of first semiconductor chips comprises: an effective surface defined by two side surfaces of the first semiconductor chip in a first direction and two side surfaces of the first semiconductor chip in a second direction intersecting the first direction; a first one side chip pad disposed at an edge of one side surface of the effective surface close to the first direction; a first other side chip pad disposed at an edge of the other side surface of the effective surface close to the first direction; and a first redistribution pad electrically connected to the first other side chip pad and disposed at an edge of one side surface of the effective surface close to the second direction, wherein the plurality of first semiconductor chips are stacked offset toward one side in a third direction intersecting the first direction and the second direction, the one side being away from the one side surface in the first direction and the one side surface in the second direction so as to expose the first side chip pad and the first redistribution pad, wherein the first ends of the plurality of vertical interconnectors connected to the first semiconductor chip are respectively connected to the first side chip pad and the first redistribution pad, wherein, except for at least the uppermost second semiconductor chip, the plurality of second semiconductor chips are in the same state as the state of the plurality of first semiconductor chips rotated 180 degrees around an axis parallel to the vertical direction, and each of the second semiconductor chips includes a second one side chip pad, a second other side chip pad, and a second redistribution pad located at a position opposite to the positions of the first one side chip pad, the first other side chip pad, and the first redistribution pad, wherein the plurality of second semiconductor chips are offset and stacked in a direction opposite to the offset and stacking direction of the plurality of first semiconductor chips so as to expose the second one-side chip pads and the second redistribution pads, and The first ends of the plurality of vertical interconnectors respectively electrically coupled to the plurality of second semiconductor chips except at least the uppermost second semiconductor chip are respectively connected to the second one-side chip pad and the second redistribution pad.

22. The semiconductor package according to claim 21, wherein The number of the first other-side chip pads is less than the number of the first one-side chip pads, and The number of the second other-side chip pads is less than the number of the second one-side chip pads.

23. A method for manufacturing a semiconductor package, the method comprising the steps of: stacking a plurality of semiconductor chips in a vertical direction on a substrate to form a chip stack; forming a plurality of vertical interconnectors extending in the vertical direction, wherein first ends of the plurality of vertical interconnectors are respectively connected to the plurality of semiconductor chips; forming a molding layer to cover the chip stack and the vertical interconnector while exposing a second end of the vertical interconnector; forming a plurality of landing pads over the mold layer to respectively contact the second ends of the vertical interconnectors, wherein the plurality of landing pads are conductive and respectively overlap the first ends of the vertical interconnectors, wherein a width of the landing pads is greater than a width of the vertical interconnectors; and forming a package redistribution layer electrically connected to the vertical interconnector through the landing pad, wherein each of the plurality of semiconductor chips comprises a chip pad formed on an effective surface facing the package redistribution layer, wherein the plurality of semiconductor chips are stacked offset to expose the chip pads of the plurality of semiconductor chips; wherein the first end of the vertical interconnector is connected to the chip pad, and The plurality of semiconductor chips include a plurality of first semiconductor chips offset and stacked in a first offset direction and a plurality of second semiconductor chips offset and stacked above the first semiconductor chips in a second offset direction opposite to the first offset direction.

24. The method according to claim 23, wherein: The step of forming the package redistribution layer further comprises the following steps: forming a first redistribution dielectric layer on one surface of the mold layer to cover the landing pad, and the first redistribution dielectric layer has a plurality of openings respectively exposing the landing pads; forming a plurality of redistribution conductive layers on the first redistribution dielectric layer, and each of the redistribution conductive layers includes a line portion having a relatively small width and a pad portion having a relatively large width and overlapping with each of the openings; and A second redistribution dielectric layer is formed to cover the first redistribution dielectric layer and the redistribution conductive layer.

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