Optimizing information requests to the memory system

Abstract

A system having a processing device and a controller, wherein the controller is operably connected to a memory subsystem via a communication channel to: store information identifying an amount of available capacity of a buffer of the memory subsystem; transmit one or more write commands to the memory subsystem via the communication channel to store data in a memory component of the memory subsystem, wherein the memory subsystem queues the one or more write commands in the buffer; update the information by deducting an amount of buffer capacity used by the one or more write commands from the amount of available capacity to generate an amount of current available capacity of the buffer; and determine whether to generate an information request to the memory subsystem based at least in part on the amount of current available capacity.

Description

[0001] Related Applications

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 16 / 058,645, filed on August 8, 2018, entitled “Optimize Information Requests to a Memory System,” the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory systems, and more particularly, to optimizing the frequency of information requests transmitted from a host system to a memory system. Background Art

[0004] The memory subsystem may be a storage system, such as a solid-state drive (SSD), or a memory module, such as a non-volatile dual in-line memory module (NVDIMM), and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components.

[0005] Standardized communication protocols allow the host system to communicate with the memory subsystem to store data and retrieve data.

[0006] For example, the JEDEC (Joint Electron Device Engineering Design Council) Solid State Technology Association has proposed a "DDR5 NVDIMM-P bus protocol" for communication between a host system and an NVDIMM-P memory module. This protocol is described in detail in JEDEC Committee Letter Ballot Committee: JC-45.6, Committee Item No. 2261.13D, Subject: "Proposed DDR5 NVDIMM-P Bus Protocol", which is hereby incorporated by reference in its entirety. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0008] Figure 1 An example computing system having a memory subsystem according to some embodiments of the present disclosure is described.

[0009] Figure 2 An example computing system including an information request manager according to some embodiments of the present disclosure is described.

[0010] Figure 3is a flow chart of an example method of optimizing information requests from a host system to a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 4 is a flowchart of a detailed example method of optimizing information requests according to some embodiments of the present disclosure.

[0012] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] At least some aspects of the present disclosure relate to optimizing information requests transmitted from a host system to a memory subsystem to reduce communication traffic and / or reduce power consumption. Alternatively, such optimization of requests can be used to increase responsiveness, or to create an intermediate point between responsiveness and traffic volume. The memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a memory module connected to a central processing unit (CPU) via a memory bus, such as a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), a non-volatile dual in-line memory module (NVDIMM), etc. Another example of a memory subsystem is a storage system, such as a solid-state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem that provides both memory functions and storage functions. In general, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored at the memory subsystem, and can request to retrieve data from the memory subsystem.

[0014] In some computer systems (e.g., a host system and a memory subsystem connected using an NVDIMM-P bus), a write command to store data in the memory subsystem may be buffered in the memory subsystem for execution within an unpredicted period of time. The host system may issue a command to request information from the memory subsystem, the information including information indicating the available capacity of the memory subsystem for accepting new write commands and their data. Such information indicating available capacity may be referred to as a write credit. In some cases, such as when the memory subsystem is not currently expected to have capacity that can be allocated to the host system to send a new write command, sending such a request may not produce useful results. Sending a request that produces a response that is unlikely to be useful may result in inefficient use of communication resources and / or may increase power consumption.

[0015] At least some aspects of the present disclosure address the above and other deficiencies by having a host system adjust the frequency of information requests based on statistics of the timing of past requests that have produced useful results.

[0016] Figure 1An example computing system 100 with a memory subsystem 110 according to some embodiments of the present disclosure is described. The memory subsystem 110 may include media, such as memory components 109A to 109N. The memory components 109A to 109N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem 110 is a memory module. Examples of memory modules include DIMMs, NVDIMMs, and NVDIMM-Ps. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. Typically, a computing environment may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0017] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 through a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may also utilize an NVM Express (NVMe) interface to access the memory components 109A to 109N. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 may access multiple memory subsystems through the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0018] The host system 120 includes a processing device 118 and a controller 116. The processing device 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 116 controls communication via a bus coupled between the host system 120 and the memory subsystem 110.

[0019] Typically, controller 116 may send commands or requests to memory subsystem 110 desiring access to memory components 109A-109N. Controller 116 may also include interface circuitry to communicate with memory subsystem 110. Interface circuitry may convert responses received from memory subsystem 110 into information for host system 120.

[0020] The controller 116 of the host system 120 may communicate with the controller 115 of the memory subsystem 110 to perform operations, such as reading data, writing data, or erasing data at the memory components 109A to 109N, and other such operations. In some cases, the controller 116 is integrated into the same package of the processing device 118. In other cases, the controller 116 is separate from the package of the processing device 118. The controller 116 and / or the processing device 118 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 116 and / or the processing device 118 may be a microcontroller, a dedicated logic circuit system (such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0021] Memory components 109A to 109N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 109A to 109N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more bits of data (e.g., a data block) used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 109A to 109N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 109A to 109N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, ferroelectric random access memory (FeTRAM), ferroelectric RAM (FeRAM), conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), nanowire-based nonvolatile memory, memory incorporating memristor technology, and cross-point arrays of nonvolatile memory cells. The cross-point array of the nonvolatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point nonvolatile memories can perform write-in-place operations, where nonvolatile memory cells can be programmed without pre-erasing the nonvolatile memory cells. In addition, the memory cells of memory components 109A-109N can be grouped into memory pages or data blocks, which can refer to units of a memory component used to store data.

[0022] The controller 115 of the memory subsystem 110 may communicate with the memory components 109A to 109N to perform operations, such as reading data, writing data, or erasing data at the memory components 109A to 109N, and other such operations (e.g., in response to commands dispatched by the controller 116 on a command bus). The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor. The controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines to control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a controller 115, and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0023] In general, the controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 109A to 109N. The controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 109A to 109N. The controller 115 may also include a host interface circuit system to communicate with the host system 120 through a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory components 109A to 109N, and convert responses associated with the memory components 109A to 109N into information for the host system 120.

[0024] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., a DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive an address from the controller 115 and decode the address to access the memory components 109A-109N.

[0025] The computing system 100 includes an information request manager 113 in the host system 120, which is configured to optimize the generation of information requests to the memory subsystem 110. In some embodiments, a controller 116 in the host system 120 includes at least a portion of the information request manager 113. For example, the controller 116 may include logic circuitry that implements the information request manager 113. For example, the controller 116 uses a processing device 118 (processor) configured to execute instructions stored in a local memory to perform the operations of the information request manager 113 described herein. In some embodiments, the information request manager 113 is part of an operating system, a device driver, or an application of the host system 120.

[0026] The information request manager 113 of the host system 120 controls the generation of information requests to improve the effectiveness of the requests and their responses. The information request may require the memory subsystem 110 to allocate available buffer capacity in the memory subsystem 110. Based on the allocated buffer capacity, the host system 120 may transmit a new write command and its data to the memory subsystem 110; and the memory subsystem 110 may store the new write command and its data in the allocated buffer capacity for execution at a time determined by the memory subsystem 110. The information request manager 113 may delay the generation of the information request based on the amount of currently allocated buffer capacity available at the host system 120 and / or the time interval after the previous communication about the allocation of buffer capacity. For example, if the currently allocated buffer capacity available at the host system 120 to send the write command is above a threshold, the information request manager 113 may delay the generation of the information request. For example, if the currently allocated buffer capacity available at the host system 120 for sending write commands is below a threshold, and the time that has elapsed since a previous buffer capacity allocation by the memory subsystem 110 is less than a threshold time period, the information request manager 113 may delay the generation of information requests until the elapsed time reaches the threshold time period. The threshold time period may be a predetermined time period, or a time period calculated based on the average speed at which the memory subsystem 110 can allocate buffer capacity for accepting new write commands. Controlling the generation of information requests in this manner may improve the efficiency of the use of communication resources, such as a bus between the host system 120 and the memory subsystem 110. In addition, increasing the effectiveness of information requests may reduce power consumption by eliminating and / or combining certain communications. Additional details regarding the operation of the information request manager 113 are described below.

[0027] Figure 2 An example computing system including an information request manager 113 is illustrated in accordance with some embodiments of the present disclosure.

[0028] describe Figure 2 For non-limiting illustrative purposes only, the controller 116 of the host system 120 is sometimes referred to as the memory controller 116 hereinafter, and the controller 115 of the memory subsystem 110 is sometimes referred to as the media controller 115 hereinafter.

[0029] exist Figure 2In the embodiment, the communication channel between the host system 120 and the memory subsystem 110 includes a command bus 121, a data bus 123, a transaction bus 125, and a metadata bus 127. The communication protocol used for the communication channel allows asynchronous access to the memory subsystem 110 for data storage and retrieval by the host system 120. For example, the memory subsystem 110 may be an NVDIMM; and the host system 120 may access the memory controller 116 according to the JEDEC NVDIMM-P bus protocol using the command bus 121, the data bus 123, the transaction bus 125, and the metadata bus 127.

[0030] For example, the memory controller 116 may issue a write command to store data in the memory subsystem 110. After a fixed and predetermined time window after transmitting the write command on the command bus 121, the memory controller 116 begins transmitting the data on the data bus 123. The memory subsystem 110 is not required to complete the operation of the write command within the predetermined time period. Examples of such write commands include XWRITE and PWRITE identified in the JEDEC NVDIMM-P bus protocol.

[0031] For example, the memory controller 116 may issue a read command to request information from the memory subsystem 110. The memory subsystem 110 is not required to generate a response within a predetermined time window after the read command. Examples of such read commands include XREAD and SREAD identified in the JEDEC NVDIMM-P bus protocol. XREAD may be given a predetermined read ID to indicate that it is an information request (status_read) that will return system status but will not directly access the media.

[0032] In response to the read command, the memory subsystem 110 prepares the data requested by the read command. For example, the media controller 115 may retrieve the data from the media (e.g., 109A, ..., or 109N) and buffer the retrieved data in the local memory 119 or another memory so that when such a transfer is requested, the data can be successfully transferred to the memory controller 116 within a predetermined time window.

[0033] When the requested data is ready for transmission, the memory subsystem 110 may provide a response signal in the transaction bus 125. When the memory controller 116 is informed that the memory subsystem 110 is ready to transmit certain data, the memory controller 116 may provide a send command to request the memory subsystem 110 to start transmitting the data on the data bus 123 within a predetermined time window from the start of the send command. When responding to the send command, the memory subsystem 115 may also send transaction status information, such as a read ID identifying the corresponding read command, write quota information as further discussed below, metadata corresponding to the transaction, and / or an error correction code (ECC). An example of such a send command is SEND identified in the JEDEC NVDIMM-P bus protocol.

[0034] The memory subsystem 110 may buffer in the local memory 119 or another memory the read and write commands received from the command bus 121. The media controller 115 may execute the buffered commands in an order different from the order in which the commands were received.

[0035] The memory subsystem 110 has a certain amount of capacity for buffering pending read and write commands and their associated data. The memory controller 116 and the media controller 115 may communicate with each other to prevent buffer overflows in the memory subsystem 110.

[0036] For example, write credits may be used to represent a unit of buffer capacity available for buffering a write command and its associated data of a predetermined size. In some cases, a write command may have data greater than a predetermined size; and such a write command requires multiple write credits for buffering the command and its data in the memory subsystem 110.

[0037] The memory controller 116 may maintain a count of the write credits it has available to transmit write commands to the memory subsystem 110 on the command bus 121. When a write command is sent over the command bus 121, the memory controller 116 deducts the write credits used for the write command. To avoid buffer overflow, the memory controller 116 should not transmit a write command when it does not have enough write credits to transmit the write command to the memory subsystem 110.

[0038] The media controller 115 may maintain a count of write credits that it may return to the memory controller 116 to complete a write command. After a write command buffered in the memory subsystem 110 is completed, the buffer space used by the write command may be freed to accept other write commands from the memory controller 116. The write credits used by the completed write commands may be added to the count of write credits that may be returned to the memory controller 116.

[0039] The memory subsystem 110 may use the metadata bus 127 to specify the number of write credits it returns to the memory controller 116. For example, after sending a response signal on the transaction bus 125 to enable the memory controller 116 to issue a send command, the media controller 115 may use the metadata bus 127 to transmit the number of write credits returned. The memory subsystem 110 may transmit such a response signal in response to a read command such as XREAD and SREAD identified in the JEDEC NVDIMM-P bus protocol. An example of a response signal is RSPx_n identified in the JEDEC NVDIMM-P bus protocol.

[0040] When the memory controller 116 uses a read command to request to retrieve data at a certain address, the memory controller 116 may place an address command immediately after the read command to specify the address. Similarly, when the memory controller 116 uses a write command to store data at a certain address, the memory controller 116 may place an address command immediately after the write command to specify the address. An example of such an address command is XADR identified in the JEDEC NVDIMM-P bus protocol.

[0041] The memory controller 116 of the host system 120 has a counter of a write quota at the host system 120 that represents the amount of buffer space known to be available in the memory subsystem 110 to buffer write commands transmitted from the host system 120 .

[0042] When the host system 120 transmits a write command to the memory subsystem, the memory controller 116 of the host system 120 reduces the counter of its write quota at the host system 120 by an amount corresponding to the buffer capacity occupied by the write command and its data. When the host system 120 does not have enough write quota to transmit the write command, the host system 120 does not transmit the command to avoid buffer overflow at the memory subsystem 110.

[0043] The media controller 115 of the memory subsystem 110 is operable to monitor a write buffer that may be located in the local memory 119 or another memory in the memory subsystem 110. The total count of write credits at the memory subsystem 110 identifies the total buffer capacity available for allocation to the host system 120 for transmitting write commands from the host system 120 to the memory subsystem 110. The total count of write credits at the memory subsystem 110 may be reduced by the write credits transmitted from the memory subsystem 110 to the host system 120. The transmitted write credits represent the amount of buffer capacity allocated for the host system 120 to use to send new write commands. After the write command is executed and the write command is cleared from the buffer, the total count of write credits may be increased by the amount of write credits corresponding to the amount of buffer space occupied by the write command in the buffer. When the write command is buffered, the amount of buffer space occupied by the write command in the buffer identifies the amount of write credits used by the write command. The amount of write credits may be determined based on the size of the data associated with the write command. The total count of write credits at the memory subsystem 110 may be reduced by the write credits transmitted from the memory subsystem 110 to the host system 120. The transmitted write credits represent the amount of buffer capacity allocated for use by the host system 120 to send new write commands. After executing a write command and / or flushing a write command from the buffer, the total count of write credits may be increased by the amount of write credits used by the write command.

[0044] The information request manager 113 of the host system 120 may generate an information request to receive a write quota from the memory subsystem 110; and the write quota in the host system 120 indicates the amount of buffer capacity allocated to the host system 120 to transmit a write command. Typically, the write quota is transmitted from the memory subsystem 110 to the host system 120 as a response to a read command from the host system 120, such as an information request (e.g., RSPx_n identified in the JEDEC NVDIMM-P bus protocol) or a request to retrieve data from a specific address (e.g., SREAD or XREAD identified in the JEDEC NVDIMM-P bus protocol).

[0045] Information request manager 113 determines whether host system 120 has more than a threshold number of write credits available to send write commands to memory subsystem 110. If the total count of write credits available at host system 110 is currently greater than the threshold number, information request manager 113 defers generating information requests for write credits.

[0046] When the total count of write credits available at the host system 110 is currently less than a threshold number, the information request manager 113 determines whether a time greater than a threshold period of time has elapsed since a write credit was previously transferred from the memory subsystem 110. The previous transfer of the write credit may have been in response to an information request for the write credit, or in response to a read command that retrieves data from a specified address associated with the read command.

[0047] The threshold time period may be a predetermined configuration parameter. Alternatively, the information request manager 113 may calculate the threshold time period as an average time interval at which the memory subsystem 110 transmits at least a threshold number of write credits (e.g., after the total count of write credits available at the host system 110 falls below a predetermined level) to the host system 110. The average time interval represents an average speed at which the memory subsystem 110 can execute buffered write commands to release write credits for new write commands. For example, based on an estimated speed at which write commands are executed at the memory subsystem 110, the information request manager 113 estimates or predicts the total write credits available at the memory subsystem 110 for transmission to the host system 120. When the estimated or predicted total write credits available at the memory subsystem 110 are above the threshold, the information request manager 113 may cause the memory controller 116 to transmit an information request that may cause the memory subsystem 110 to transmit the write credits.

[0048] Optionally, the information request manager 113 calculates a moving average of the time intervals between adjacent transfers of write credits from the memory subsystem 110 to the host system 120. The threshold time period may be dynamically adjusted based on the moving average of the time intervals.

[0049] Optionally, the information request manager 113 calculates an average speed at which write credits are generated in the memory subsystem 110 based on the time interval between two adjacent write credit transfers and the amount of write credits transferred at the end of the time interval. The average speed can be used to predict the time interval to the moment when the memory subsystem 110 has more than a threshold number of write credits that can be transferred to the host system 120; and the information request manager 113 can delay the generation of information requests based on the predicted time interval. In some cases, the information request manager 113 can calculate a moving average of the speed at which write credits are generated based on several recent time intervals of write credit transfers. The moving average can be used to calculate the threshold time period.

[0050] Optionally, the information request manager 113 may also defer the generation of information requests when the memory subsystem 110 has a pending read command from the host system 120. The memory subsystem 110 may communicate write credits to the host system 120 using responses to pending read commands.

[0051] Therefore, the information request manager 113 may combine and / or reduce communication traffic related to requests for allocation of buffer capacity for buffering write commands, and reduce power consumption associated with the reduced communication traffic.

[0052] Figure 3 is a flow chart of an example method of optimizing information requests from the host system 120 to the memory subsystem 110 according to some embodiments of the present disclosure. Figure 3 The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 3 The method is at least partly based on Figure 1 1 or 2. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0053] In block 301, the information request manager 113 stores information identifying the amount of available capacity in the buffer of the memory subsystem for write commands. For example, the buffer may be implemented in the local memory 119 or another memory. The amount of available capacity of the buffer has been allocated to the host system 120 for transmitting write commands and their data.

[0054] At block 303, the memory controller 116 transmits one or more write commands to the memory subsystem 110 to store data in the memory components 109A-109N of the memory subsystem 110. The memory subsystem 110 queues the one or more write commands in a buffer for execution at a time determined by the media controller 115 of the memory subsystem 110.

[0055] At block 305, the information request manager 113 deducts the amount of buffer capacity in the buffer for one or more write commands from the amount of available capacity to calculate the amount of currently available capacity in the buffer allocated to the host system 120 for transmitting the write command and its data.

[0056] At block 307, the information request manager 113 determines whether to generate an information request to the memory subsystem 110 based at least in part on the amount of currently available capacity. The information request may cause the memory subsystem 110 to allocate buffer capacity for the host system 120 to transmit new write commands.

[0057] For example, the information request manager 113 may defer generation of information requests until the amount of currently available buffer capacity is below a threshold. The amount of currently available / allocated buffer capacity is available at the host system 120 for transmitting write commands without causing buffer overflows in the memory subsystem 110.

[0058] Optionally, the information request manager 113 may defer the generation of the information request until a period of time longer than a certain time interval has elapsed since the previous communication of the allocated buffer capacity for transmission of write commands by the host system 120. By deferring according to the time interval, the information request is more likely to be transmitted at a time when the memory subsystem 110 has completed one or more write commands and freed up buffer capacity previously used by the completed write commands, so that the freed up capacity can be allocated and identified to the host system 120 for transmission of other write commands.

[0059] Optionally, the information request manager 113 may postpone the generation of an information request until the information request manager 113 predicts that the memory subsystem 110 has freed up write buffer capacity greater than a threshold amount by completing a previously received write command, such that the information request is sent at a time when the memory subsystem 110 can respond by identifying write buffer capacity greater than a threshold amount allocated to the host system 120 for transmitting a new write command and its data.

[0060] In some cases, the information request manager 113 may further defer generation of information requests, if desired, until the memory controller 116 of the host system 120 has received responses to all read commands previously transmitted to the memory subsystem 110. In conjunction with the response to any of the pending read commands, the memory subsystem may allocate write buffer capacity and transmit an indication of the amount of allocated buffer capacity.

[0061] Figure 4 is a flowchart of a detailed example method of optimizing information requests according to some embodiments of the present disclosure. Figure 4 The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 4 The method is at least partly based on Figure 11 or 2. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0062] At block 321, the memory controller 116 of the host system 120 receives a communication from the memory subsystem 110 to transfer a certain amount of write credits to the host system 120. For example, the communication protocol identified in the JEDEC NVDIMM-P bus protocol may be used to transfer the write credits. The amount of write credits may be communicated using the metadata bus 127 in response to the memory controller 116 placing a send command in the command bus 121. The memory controller 116 of the host system 120 may issue the send command in response to a response signal provided by the memory subsystem 110 on the transaction bus 125. An example of a response signal is RSPx_n identified in the JEDEC NVDIMM-P bus protocol. The response signal may be in response to a read command, such as XREAD or SREAD identified in the JEDEC NVDIMM-P bus protocol.

[0063] At block 323, the information request manager 113 adds the amount of write credits specified in the communication to the total amount of write credits available at the host system 120. The total amount represents the total allocated / available buffer space for buffering write commands from the host system 120. When the total amount of write credits is sufficient to allow the host system 120 to transmit one or more write commands, the method may proceed to block 325.

[0064] At block 325, the memory controller 116 transmits one or more write commands from the host system 120 to the memory subsystem 110. The memory subsystem 110 buffers the one or more write commands for execution at a time not controlled by the host system 120. Examples of write commands include WRITE and PWRITE identified in the JEDEC NVDIMM-P bus protocol.

[0065] At block 327, the information request manager 113 deducts the one or more write credits used by the one or more write commands from the total amount. By sending the one or more write commands, the host system 120 sends the write credits used by the one or more write commands to the memory subsystem 110.

[0066] At block 329, the information request manager 113 determines whether the total amount of write credits is now below a threshold. If the total amount is not below a threshold, the memory controller 116 may skip blocks 331, 333 to 335 and perform other operations, such as transmitting 325 other write commands. However, transmitting 325 one or more write commands does not require the total amount of write credits to be above a threshold. The write commands may be transmitted when the total amount of write credits is not below the write credit used by the write commands. Optionally, the memory controller 116 may also transmit a read command to retrieve data from the memory components 109A to 109N, such as an XREAD or SREAD in the JEDEC NVDIMM-P bus protocol. The memory subsystem 110 may optionally provide a write credit in conjunction with a response to a read command, and cause the memory controller 116 to receive 321 a write credit increment communication.

[0067] At block 331, if the total amount of write credits at the host system 120 is below a threshold, the information request manager 113 may delay for a period of time until more than a threshold period of time has passed since the most recent write credit communication. The threshold period of time allows the memory subsystem 110 to process buffered write commands and reclaim write credits used by completed write commands so that the reclaimed write credits can be communicated to the host system 120.

[0068] The threshold time period may be a predetermined time interval, or a time interval calculated by the information request manager 113 based on statistical data regarding the speed at which the memory subsystem 110 can reclaim write credits. For example, the time interval may be calculated as a running average of the time period between adjacent write credit communications (e.g., communications that transmit write credits greater than a predetermined level). For example, based on the time period between two adjacent write credit communications and the write credit provided in the latter of the two write credit communications, the information request manager 113 may calculate an estimated speed at which the memory subsystem 110 completes buffered write commands and reclaims write credits. For example, the information request manager 113 may calculate a running average of the estimated speed in multiple time intervals between adjacent write credit communications. The information request manager 113 may use the speed to determine the threshold time period. After the threshold time period after the previous write credit communication, the memory subsystem 110 predicts that a set of buffered write commands has been completed. The completed write commands allow the memory subsystem 110 to reclaim at least the predetermined level of write credits. The reclaimed write credits may be communicated to the host system 120 in a response to an information request sent after the threshold time period.

[0069] Figure 5An example machine illustrating a computer system 600 in which a set of instructions may be executed for causing the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 10), or may be used to perform operations of the information request manager 113 (e.g., execute instructions to perform operations corresponding to the reference Figure 1 , 2 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0070] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0071] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static random access memory (SRAM), and a data storage system 618, which communicate with each other via a bus 630 (which may include multiple buses).

[0072] Processing device 602 represents one or more general processing devices, such as a microprocessor, a central processing unit (CPU), etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a graphics processing unit (GPU), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may also include a network interface device 608 to communicate through a network 620.

[0073] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, with the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0074] In one embodiment, instructions 626 include implementing instructions corresponding to information request manager 113 (e.g., reference Figure 1 , 2 , 3 and 4). Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0075] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other skilled in the art. An algorithm is considered here and generally to be a self-consistent sequence of operations that produce a desired result. The operations are operations that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0076] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0077] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each medium coupled to a computer system bus.

[0078] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure described herein may be implemented using a variety of programming languages.

[0079] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0080] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It should be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A host system, comprising: Processing device; as well as A controller operatively connected to the memory subsystem via a communication channel to perform the following operations: storing information identifying an amount of available capacity of a buffer of the memory subsystem; transmitting one or more write commands to the memory subsystem over the communication channel to store data in a memory component of the memory subsystem, wherein the memory subsystem queues the one or more write commands in the buffer; updating the information by deducting the amount of buffer capacity used by the one or more write commands from the amount of available capacity to calculate an amount of current available capacity of the buffer; determining whether to generate an information request to the memory subsystem based at least in part on the amount of the currently available capacity; generating the information request based at least in part on a time interval; as well as Generating the information request is deferred until a time greater than the time interval has elapsed since a first communication between the host system and the memory subsystem regarding available capacity of the buffer.

2. The host system according to claim 1, wherein the controller further performs the following operations: Whether to generate the information request to the memory subsystem is determined based at least in part on whether the memory subsystem has responded to a read command transmitted from the host system to the memory subsystem.

3. The host system according to claim 2, wherein the controller further performs the following operations: Generating the information request is deferred until the amount of the current available capacity is less than a threshold value.

4. The host system according to claim 3, wherein the controller further performs the following operations: Generating the information request is deferred until the amount of the currently available capacity is less than a threshold and the memory subsystem has no read commands for which the memory subsystem has not provided a corresponding response to the host system.

5. The host system according to claim 1, wherein the controller further performs the following operations: The time interval is updated based on a time period between the first and second communications between the host system and the memory subsystem regarding available capacity of the buffer.

6. The host system of claim 5, wherein the time interval is updated further based on an amount of the buffer available capacity allocated to the host system in the first communication.

7. The host system according to claim 1, wherein the processing device further performs the following operations: predicting an amount of the buffer capacity in the memory subsystem available for allocation to the host system to transmit write commands; and Generating the information request is deferred until the predicted quantity is above a threshold value.

8. The host system of claim 1, wherein the memory component comprises a non-volatile memory; the communication channel between the host system and the memory subsystem comprises: a command bus for transmitting the one or more write commands; A data bus for transmitting the data requested to be stored by the one or more write commands; as well as A transaction bus is used to transmit a response signal to the information request from the memory system to the host system.

9. The host system of claim 8, wherein the write command, the information request, and the response signal conform to a communication protocol for a nonvolatile dual in-line memory module.

10. A method for a host system, the method comprising: storing information in the host system coupled to the memory subsystem via a communication channel, the information identifying an amount of available capacity of a buffer of the memory subsystem; transmitting one or more write commands to the memory subsystem via the communication channel to store data in a memory component of the memory subsystem, wherein the memory subsystem queues the one or more write commands in the buffer; updating the information by deducting the amount of buffer capacity used by the one or more write commands from the amount of available capacity to calculate an amount of current available capacity of the buffer; controlling generation of information requests to the memory subsystem based at least in part on a time interval and an amount of the currently available capacity; as well as The generating of the information request is deferred until a time elapsed after a previous communication between the host system and the memory subsystem is longer than the time interval and the amount of the current available capacity is less than a threshold value.

11. The method according to claim 10, further comprising: The time interval is updated based on a period of time between the previous communication and a communication between the host system and the memory subsystem regarding available capacity of the buffer prior to the previous communication.

12. The method of claim 11, wherein the time interval is updated further based on an amount of the buffer available capacity allocated to the host system in the previous communication.

13. The method according to claim 10, further comprising: predicting an amount of the buffer capacity in the memory subsystem available for allocation to the host system to transmit a write command; as well as Generating the information request is deferred until the predicted quantity is above a threshold value.

14. The method of claim 10, wherein the write command and the information request conform to a communication protocol for a non-volatile dual in-line memory module; and the communication channel between the host system and the memory subsystem comprises: a command bus for transmitting the one or more write commands; A data bus for transmitting the data requested to be stored by the one or more write commands; as well as A transaction bus is used to transmit a response signal to the information request from the memory system to the host system.

15. A non-transitory computer-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to: storing information in a host system coupled to a memory subsystem via a communication channel, the information identifying an amount of available capacity of a buffer of the memory subsystem, wherein the host system transmits one or more write commands to the memory subsystem via the communication channel to store data in a memory component of the memory subsystem, and wherein the memory subsystem queues the one or more write commands in the buffer; updating the information by deducting the amount of buffer capacity used by the one or more write commands from the amount of available capacity to calculate an amount of current available capacity of the buffer; predicting an amount of the buffer capacity in the memory subsystem available for allocation to the host system to transmit a write command; deferring generation of information requests to the memory subsystem until the predicted amount is above a threshold; calculating a time interval based on the predicted amount being above a threshold; and Wherein the generating of the information request is deferred until a time greater than the time interval has elapsed since a previous communication between the host system and the memory subsystem.

16. The non-transitory computer-readable storage medium of claim 15, wherein the instructions, when executed by the processing device, further cause the processing device to: The time interval is updated based on an amount of the buffer available capacity allocated to the host system in the previous communication.

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