Controller circuit and method for generating pulse width modulated (PWM) signals

Abstract

A controller circuit for generating a pulse width modulation (PWM) signal for activating a switching device of a switching power supply (SMPS) includes gap detection circuitry, pulse frequency modulation (PFM) circuitry, PWM circuitry, and logic circuitry. The gap detection circuitry is configured to generate a shift signal based on an indication of a voltage difference between a reference voltage and a feedback voltage corresponding to a voltage output by the SMPS. The PFM circuitry is configured to generate a hold signal indicative of a target PFM frequency of the PWM signal. The PWM circuitry is configured to shift a base current based on the shift signal to generate a shifted base current, and generate a peak signal indicative of a target PWM on-time of the PWM signal based on the shifted base current.

Description

Technical Field

[0001] This invention relates to techniques for reducing transient effects on switching power supplies (SMPS). Background Technology

[0002] The controller circuit can use a control loop to regulate the voltage output from the switching power supply (SMPS). For example, the controller circuit can use pulse frequency modulation (PFM) to regulate the voltage at the SMPS during periods of light load. Once a change in load at the SMPS from light to heavy is detected, the controller circuit can instead use pulse width modulation (PWM) to regulate the voltage at the SMPS. In this way, the controller circuit can select the control loop (e.g., PFM or PWM) based on operating factors (e.g., load, input voltage, etc.) to improve the operation (e.g., efficiency) of the SMPS. Summary of the Invention

[0003] Overall, the purpose of this disclosure is to provide techniques for helping to reduce or eliminate undervoltage generated by transients in switching power supplies (SMPS) (e.g., but not limited to DC-DC converters). Instead of operating the controller circuitry in open-loop control, the controller circuitry can be configured to generate a shift signal based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by the SMPS. In this example, the shift signal can drive the controller to select a control loop (e.g., pulse frequency modulation (PFM), pulse width modulation (PWM)) during transient conditions (e.g., a sudden increase in load). In this way, the controller circuitry can reduce transient effects on the SMPS.

[0004] In one example, a controller circuit for generating a PWM signal for activating a switching device of an SMPS includes: a gap detection circuit configured to generate a shift signal based on an indication of a voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output of the SMPS; a PFM circuit configured to generate a hold signal indicating a target PFM frequency of the PWM signal; a PWM circuit configured to generate a shift base current based on a shift base current of the shift signal, and to generate a peak signal indicating a target PWM on-time based on the shift base current; and a logic circuit configured to generate a PWM signal including a frequency corresponding to the target PFM frequency and an on-time corresponding to a minimum PFM on-time value in response to determining that the target PFM frequency is less than a PWM frequency value, and to generate a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time value in response to determining that the target PWM on-time is greater than the minimum PFM on-time value.

[0005] In another example, a method for generating a PWM signal for activating an SMPS includes: generating a shift signal based on an indication of a voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output of the SMPS; generating a hold signal indicating a target PFM frequency of the PWM signal; shifting a base current based on the shift signal to generate a shift base current; generating a peak signal indicating a target PWM on-time based on the shift base current; generating a PWM signal including a frequency corresponding to the target PFM frequency and an on-time corresponding to a minimum PFM on-time value in response to determining that the target PFM frequency is less than a PWM frequency value; and generating a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time value in response to determining that the target PWM on-time is greater than the minimum PFM on-time value.

[0006] In another example, a circuit for switching SMPS includes: a switching device configured to connect and disconnect based on a PWM signal; a gap detection circuit device configured to generate a shift signal based on an indication of a voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output of the SMPS; a PWM circuit device configured to shift a base current based on the shift signal to generate a shift base current, and to generate a peak signal indicating a target PWM on-time based on the shift base current; and a logic circuit device configured to generate a PWM signal including a frequency corresponding to a PWM frequency value and an on-time corresponding to the target PWM on-time in response to determining that the target PWM on-time is greater than a minimum on-time value.

[0007] Details of these and other examples are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example system for reducing transient effects according to one or more techniques of this disclosure.

[0009] Figure 2 This is a conceptual diagram illustrating a first controller circuit for reducing transient effects according to one or more techniques of this disclosure.

[0010] Figure 3 This is a circuit diagram illustrating an example gap detection circuit device according to one or more techniques of this disclosure.

[0011] Figure 4 This is a conceptual diagram illustrating the performance of pulse width modulation (PWM) for regulating voltage according to one or more techniques of this disclosure.

[0012] Figure 5 This is a conceptual diagram illustrating the performance of pulse frequency modulation (PFM) for voltage regulation according to one or more techniques of this disclosure.

[0013] Figure 6 This is a conceptual diagram illustrating the performance of a gap control for regulating voltage according to one or more techniques of this disclosure.

[0014] Figure 7 This is a conceptual diagram illustrating the mapping of compensation values ​​according to one or more techniques of this disclosure.

[0015] Figure 8 This is a conceptual diagram illustrating a first conversion from PFM to PWM according to one or more techniques according to this disclosure.

[0016] Figure 9 This is a conceptual diagram illustrating a second conversion from PFM to PWM according to one or more techniques according to this disclosure.

[0017] Figure 10 This is a conceptual diagram illustrating a second controller circuit for reducing transient effects according to one or more techniques of this disclosure.

[0018] Figure 11 This is a conceptual diagram illustrating a voltage-mode PWM according to one or more techniques of this disclosure.

[0019] Figure 12 This is a flowchart illustrating a process for reducing transient effects according to the present disclosure. Detailed Implementation

[0020] The purpose of this disclosure is to provide techniques for helping to reduce or eliminate undervoltage originating from transients in switching power supplies (SMPS) (e.g., but not limited to DC-DC converters). Some controller circuits separate control loops, which may result in only one loop being active during steady-state conditions (e.g., constant frequency modulation with on-time (“ton”) or frequency modulation with a constant ton). In systems where the controller circuitry uses multiple modulation schemes depending on the operating point (e.g., SMPS load, SMPS input voltage, etc.), one aspect is the transition between loops. For example, undervoltage may be caused by a transition between pulse frequency modulation (PFM) and pulse width modulation (PWM), where PFM uses a constant duty cycle or ton modulation and a variable frequency to control the SMPS, while PWM uses a constant frequency and a variable duty cycle or ton modulation to control the SMPS. During the transition, the controller circuitry may span a state where no loop is active (e.g., open-loop control). If the transition is associated with a severe transient (e.g., load transient), the controller circuitry may be unable to regulate the control quantity (e.g., output voltage) until transitioning to the correct control loop (e.g., PWM). Therefore, loss of control during these transient periods can lead to undesirable undervoltage, which can cause the circuit design requirements to fail.

[0021] Some systems use a higher setpoint when operating at low loads compared to operating at high loads. In this way, when the SMPS load increases from low to high load, the undervoltage is reduced compared to a system using only one setpoint.

[0022] According to the techniques described herein, controller circuitry can be configured to generate a shift signal to drive the controller circuitry to operate within a control loop. For example, the shift signal can be augmented with a compensation value to drive a PWM circuit to control the SMPS with an on-time (e.g., duty cycle) greater than a minimum on-time value. In this way, compared to systems that ignore the shift signal, the control circuitry can operate in a closed-loop manner to adapt to load increases without delay.

[0023] Figure 1 This is a block diagram illustrating an example system for reducing transient effects according to one or more techniques of this disclosure. Figure 1 As shown in the example, system 100 may include power supply 102, controller circuitry 104, and SMPS 106.

[0024] Power supply 102 may be configured to provide power to one or more other components of system 100. For example, power supply 102 may be configured to provide input power to SMPS 106. In some examples, power supply 102 may be a battery configured to store electrical energy. Examples of batteries may include, but are not limited to, nickel-cadmium, lead-acid, nickel-metal hydride, nickel-zinc, silver oxide, lithium-ion, lithium polymer, any other type of rechargeable battery, or any combination thereof. In some examples, power supply 102 may be the output of a power converter or power inverter. For example, power supply 102 may be the output of a DC-DC power converter, an AC-DC power converter, a DC-AC power inverter, etc. In some examples, power supply 102 may represent a connection to a power grid. In some examples, the input power signal provided by power supply 102 may be a DC input power signal. For example, power supply 102 may be configured to provide a DC input power signal in the range of ~5VDC to ~40VDC.

[0025] Controller circuit 104 may represent circuitry for generating a PWM signal for activating the switching mechanism of SMPS 106. Controller circuit 104 may include gap detection circuitry 112, PWM circuitry 114, PFM circuitry 116, and logic circuitry 118. Gap detection circuitry 112 may be configured to generate a shift signal based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by SMPS 106. PWM circuitry 114 may be configured to generate a peak signal indicating the target PWM on-time of the PWM signal. PFM circuitry 116 may be configured to generate a hold signal indicating the target PFM frequency of the PWM signal.

[0026] The logic circuit device 118 can be configured to generate a PWM signal for output to the SMPS 106 based on a peak signal output from the PWM circuit device 114 and a hold signal output from the PFM circuit device 116. For example, the logic circuit device 118 can be configured to generate a PWM signal including a frequency corresponding to the target PFM frequency and an on-time corresponding to a minimum PFM on-time value in response to determining that the target PFM frequency is less than the PWM frequency value. In some examples, the logic circuit device 118 can be configured to generate a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time value in response to determining that the target PWM on-time is greater than the minimum PFM on-time value.

[0027] SMPS106 can be configured to generate an output voltage (e.g., “VOUT+” to “VOUT-”) using a PWM signal output from controller circuit 104. SMPS106 may include switching devices. For example, SMPS106 can be configured to selectively switch the switching devices according to the PWM signal to regulate the voltage, current, or power output by SMPS106.

[0028] Examples of switching devices may include, but are not limited to, silicon-controlled rectifiers (SCRs), field-effect transistors (FETs), and bipolar junction transistors (BJTs). Examples of FETs may include, but are not limited to, junction field-effect transistors (JFETs), metal-oxide-semiconductor FETs (MOSFETs), dual-gate MOSFETs, FinFETs, insulated-gate bipolar transistors (IGBTs), any other type of FET, or any combination thereof. Examples of MOSFETs may include, but are not limited to, PMOS, NMOS, DMOS, or any other type of MOSFET, or any combination thereof. Examples of BJTs may include, but are not limited to, PNP, NPN, heterojunction, or any other type of BJT, or any combination thereof. Switching devices may be voltage-controlled and / or current-controlled. Examples of current-controlled switching devices may include, but are not limited to, gallium nitride (GaN) MOSFETs, BJTs, or other current-controlled elements.

[0029] Examples of SMPS106 may include, but are not limited to, flyback converters, buck-boost converters, buck converters, and boost converters. A converter or another switch-mode power converter. In some examples, the SMPS106 may receive a voltage and output a voltage different from the received voltage. For example, the SMPS106 may receive a battery voltage from power supply 102 and output a first voltage less than the battery voltage. More specifically, in some examples, the SMPS106 may be a buck converter that reduces (e.g., decreases) the voltage received from power supply 102.

[0030] According to the technology described herein, the gap detection circuit device 112 can generate a shift signal based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by the SMPS 106. The PFM circuit device 116 can generate a hold signal indicating the target PFM frequency of the PWM signal. The PWM circuit device 114 can shift a base current based on the shift signal to generate a shifted base current, and can generate a peak signal indicating the target PWM on-time of the PWM signal based on the shifted base current. The logic circuit device 118 can generate a PWM signal including a frequency corresponding to the target PFM frequency and an on-time corresponding to the minimum PFM on-time value in response to determining that the target PFM frequency is less than the PWM frequency value, and can generate a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time value in response to determining that the target PWM on-time is greater than the minimum PFM on-time value.

[0031] In this way, controller circuit 104 can effectively reduce the PWM compensation range during transients, which helps to reduce or eliminate the gap between PFM control and PWM control. Therefore, improved performance is achieved compared to systems that ignore the shift signal. Controller circuit 104 can be configured to automatically restore the separation (e.g., gap) between the two control loops (e.g., PFM and PWM) as system 100 approaches new steady-state conditions. Although the above examples involve PFM and PWM, other types of control loops may be used in other examples. In some examples, only one control loop may be used. For example, controller circuit 104 may include PWM circuitry 114 while ignoring PFM circuitry 116, may include PFM circuitry 116 while ignoring PWM circuitry 114, or may ignore both PWM circuitry 114 and PFM circuitry 116 and include another closed-loop control technique to temporarily “intrude” into the control loop, thereby minimizing output voltage undershoot / overshoot during transients.

[0032] Figure 2 This is a conceptual diagram illustrating a first controller circuit 204 for reducing transient effects according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figure 1 discuss Figure 2 As shown in the figure, the controller circuit 204 includes a PWM circuit device 214, a PFM circuit device 216, and a logic circuit device 218, which can be... Figure 1 Examples of PWM circuit device 114, PFM circuit device 116, and logic circuit device 118 are shown. As shown, the controller circuit 204 also includes a compensation element 221, a voltage divider 228, an amplifier 212, and an amplifier 220.

[0033] Voltage divider 228 can be configured to generate a feedback voltage corresponding to the voltage output by the SMPS. For example, voltage divider 228 may include a pair of resistors configured to decrease or increase the feedback voltage based on the ratio of the resistances between the pair of resistors.

[0034] Amplifier 212 can be configured to generate a shift signal based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by the SMPS. For example, amplifier 212 can generate a shift signal by applying a gain to the voltage difference between the reference voltage and the feedback voltage output by voltage divider 228.

[0035] Compensation element 221 can generate a compensation value based on the output of amplifier 212. For example, compensation element 221 can be charged by an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by the SMPS (i.e., the voltage output by amplifier 212). In some examples, compensation element 221 includes a capacitor. As used herein, the capacitor may include a single capacitor element or multiple capacitor elements arranged in series and / or parallel. For example, amplifier 212 can charge and / or discharge the capacitor of compensation element 221 using a voltage signal corresponding to the voltage difference between the reference voltage and the feedback voltage output by voltage divider 228.

[0036] Amplifier 220 can generate a compensation current (“i_comp”) based on the compensation value at compensation element 221. For example, amplifier 220 can draw a compensation current having an amplitude corresponding to the voltage at the capacitor of compensation element 221.

[0037] The PWM circuit arrangement 214 includes a base current source 222, a slope compensator 224, a current sensor 226, and a comparator 234. The base current source 222 can be configured to generate a base current corresponding to the minimum inductor current at the SMPS. As shown, the base current source 222 can be configured to receive a shift signal to drive the base current source 222 to output a shifted base current (“i_shifted pedestal”) based on the shift signal. For example, the base current source 222 can be configured to generate the shifted base current as the base current minus the shift signal. The slope compensator 224 can be configured to generate a slope compensation current that increases during the target PWM on-time and resets during the PWM off-time. For example, the slope compensator 224 can be configured to generate a triangular wave. The current sensor 226 can be configured to generate a sense current corresponding to the current output at the SMPS.

[0038] Comparator 234 can be configured to generate a peak signal (“PEAK SIGNAL”) to indicate when a first sum of the shifted base current (“i_shifted pedestal”) and the sensed current (“i_sense”) corresponding to the current output at the SMPS equals a second sum of the compensation current (“i_comp”) and the slope compensation current (“i_slope comp”). For example, comparator 234 can be configured to generate a PWM signal to transition from an on state to an off state in response to the peak signal indicating that the first sum equals the second sum.

[0039] PFM circuit device 216 includes a ramp generator 230 and a clock manager 232. The ramp generator 230 can be configured to increase a voltage ramp signal at a rate of change corresponding to the compensation value at compensation element 221. For example, amplifier 220 can generate a ramp current (“i_ramp”) that sets the rate of change corresponding to the compensation value at compensation element 221. In this example, the ramp current (“i_ramp”) charges capacitor 231 to set the rate of change after a minimum PFM on-time value. In this example, comparator 233 resets a hold signal (“HOLD SIGNAL”) in response to a voltage ramp signal greater than or equal to a voltage threshold (“Vref”). Clock manager 232 sets a minimum on-time value (“ton_min”). In some examples, clock manager 232 can discharge capacitor 231, for example, before the minimum PFM on-time.

[0040] Logic circuit device 218 can be configured to generate a PWM signal (“PWM”) based on a peak signal, a hold signal, and a minimum PFM on-time value. In some examples, logic circuit device 218 can be configured to operate with PWM circuit device 214 when the target PWM on-time indicated by the peak signal is greater than the minimum PFM on-time value. In some examples, logic circuit device 218 can be configured to operate with PFM circuit device 216 when the target PFM frequency is less than the PWM frequency value. Examples of control loops for logic circuit device 218 are shown in Table 1, where fsw is the frequency of the PWM signal, fpwm is the frequency of the PWM frequency value (e.g., a predetermined frequency value for the PWM control loop), ton is the target PWM on-time, and ton_min is the minimum PFM on-time value (e.g., a predetermined on-time value for the PFM control loop), PWM is the PWM control loop, PFM is the PFM control loop, and GAP is open-loop control.

[0041]

[0042] Table 1 - Example Control Loop

[0043] According to the techniques described herein, the shift signal can "steal" the base current to generate a shifted base current, which can reduce or eliminate gaps (e.g., open-loop control). Therefore, compared to systems that ignore the shift signal, logic circuitry 218 can use PWM circuitry 214 with a smaller compensation value at compensation element 221 to control the SMPS. This allows PWM circuitry 214 to output a peak signal indicating that the target PWM on-time (ton) is greater than the minimum PFM on-time (ton_min) to intrude into the control loop, thereby minimizing output voltage undershoot / overshoot during transients. In this way, transient effects can be minimized compared to systems that ignore the shift signal.

[0044] Figure 3 This is a circuit diagram illustrating an example gap detection circuit device 312 according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figure 1-2 discuss Figure 3 The gap detection circuit device 312 can represent Figure 1 An example of the gap detection circuit device 312. In some examples, the gap detection circuit device 312 may represent a mirror operational transconductance amplifier (OTA) error amplifier. Figure 3 Examples include a feedback (“fb”) voltage transistor 354, a reference (“ref”) voltage transistor 352, an fb current mirror 364, a ref current mirror 362, a first current mirror 366, and a second current mirror 368. The fb voltage sets the resistance of the fb voltage transistor 354, and the reference voltage sets the resistance of the ref voltage transistor 352. Therefore, the fb current mirror 364 generates an fb current (“i_fb”) corresponding to the feedback voltage, and the ref current mirror 362 generates a ref current (“i_ref”) corresponding to the reference voltage.

[0045] The first current mirror 366 can generate a current corresponding to the sum of the ref current (“i_ref”) and the threshold current (“i_thresh”) generated by the current source 370. The second current source 368 generates a shift signal corresponding to the feedback current minus the reference current minus the threshold current (“i_fb–i_ref–i_thresh”). In this way, when the voltage difference is greater than the threshold, the gap detection circuit device 312 can generate a shift signal to include a current proportional to the voltage difference between the reference voltage and the feedback voltage.

[0046] For example, under steady-state conditions (e.g., when the controller circuit 104 regulates the output voltage at the SMPS 106 to correspond to a reference voltage), the fb current and the ref current can be equal. During a transient (e.g., fb voltage < ref voltage), when above a defined threshold set by the current source 370, the error i_err = i_ref - i_fb can be greater than zero. In this way, the gap detection circuitry 312 can change the parameter that creates a gap between two loops (e.g., the PWM circuitry 114 and the PFM circuitry 116) to invade the control loop, thereby minimizing output voltage undershoot / overshoot during a transient.

[0047] Figure 4 is a conceptual diagram showing PWM performance for regulating voltage in accordance with one or more techniques of the present disclosure. For illustrative purposes only, reference Figures 1-3 discussion Figure 4 . Figure 4 The horizontal axis of Figure 4 represents time, while the vertical axis of

[0048] As Figure 4 shown, at time 420, the period is initialized such that the first sum 408 increases as the current in the inductor of the SMPS 106 increases, and the PWM signal is set to an active state. Additionally, at time 420, the ramp voltage 406 of the capacitor 231 has been reset. At time 422, the minimum PFM on-time value has passed, which causes the amplifier 220 to charge the capacitor 231 with a ramp current corresponding to the compensation value at the compensation element 221. At time 424, the first sum 408 of the shifted base current and the sense current corresponding to the current output at the SMPS 106 is equal to the second sum 410 of the compensation current and the slope compensation current, which causes the comparator 234 to set the peak signal 412 to an active state. In response to setting the peak signal 412 to an active state, the logic circuitry 218 generates the PWM signal 402 to transition from an on state to an off state. Since the controller circuit 104 operates using PWM, the logic circuitry 218 generates the PWM signal 402 to include a frequency corresponding to a PWM frequency value (“Tpwm”), and the process restarts at time 426.

[0049] Figure 5This is a conceptual diagram illustrating the performance of a voltage-regulating PFM according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figures 1-4 discuss Figure 5 . Figure 5 The horizontal axis represents time, while Figure 5 The vertical axis represents the voltage at PWM signal 502, the voltage at hold signal 504, the voltage at deep PFM 505, the ramp voltage 506 at capacitor 231, the current amplitude of the first sum 508 for shifting the base current and the sensed current corresponding to the current output at SMPS 106, the current amplitude of the second sum 510 for compensating current and slope compensating current, and the voltage at peak signal 512.

[0050] like Figure 5 As shown, at time 520, the period is initialized such that the first sum 508 increases with the increase of the current at the inductor of SMPS106, and the PWM signal is set to the active state. Furthermore, at time 520, the ramp voltage 506 of capacitor 231 has been reset. In this example, at time 522, the first sum 508 of the shift base current and the sensed current corresponding to the current output at SMPS106 equals the second sum 510 of the compensation current and the slope compensation current, causing comparator 234 to set the peak signal 512 to the active state. In response to setting the peak signal 512 to the active state before the minimum on-time, logic circuitry 218 suppresses the generation of the PWM signal 502 to transition from the on state to the off state. At time 524, the minimum PFM on-time value has passed, causing amplifier 220 to charge capacitor 231 with a ramp current corresponding to the compensation value at compensation element 221. In this example, at time 524, logic circuit device 218 generates PWM signal 502 to transition from the on state to the off state. At time 526, comparator 233 determines that ramp voltage 506 exceeds reference voltage (“Vth_vco”) and resets hold signal 504, and processing restarts.

[0051] Figure 6 This is a conceptual diagram illustrating the performance of a gap control for voltage regulation according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figures 1-5 discuss Figure 6 . Figure 6 The horizontal axis represents time, while Figure 6The vertical axis represents the voltage at PWM signal 602, the voltage at hold signal 604, the voltage at deep PFM 605, the ramp voltage 606 at capacitor 231, the current amplitude of the first sum 608 for shifting the base current and the sensed current corresponding to the current output at SMPS 106, the current amplitude of the second sum 610 for compensating current and slope compensating current, and the voltage at peak signal 612.

[0052] like Figure 6 As shown, at time 620, the period is initialized such that the first sum 608 increases with the increase of the current at the inductor of SMPS106, and the PWM signal is set to the active state. Furthermore, at time 620, the ramp voltage 606 of capacitor 231 has been reset. In this example, at time 622, the first sum 608 of the shift base current and the sensed current corresponding to the current output at SMPS106 equals the second sum 610 of the compensation current and the slope compensation current, causing comparator 234 to set the peak signal 612 to the active state. In response to setting the peak signal 612 to the active state before the minimum on-time, logic circuitry 218 suppresses the generation of the PWM signal 602 to transition from the on state to the off state. At time 624, the minimum PFM on-time value has passed, causing amplifier 220 to charge capacitor 231 with a ramp current corresponding to the compensation value at compensation element 221. In this example, at time 624, logic circuitry 218 generates a PWM signal 402 to transition from an on state to an off state. At time 626, comparator 233 determines that the ramp voltage 506 exceeds the reference voltage (“Vth_vco”). However, in response to determining that the target PFM frequency is not less than the PWM frequency value (e.g., Tpwm 630 is greater than the target period 632), logic circuitry 218 restarts processing at time 628.

[0053] Figure 7 This is a conceptual diagram illustrating the mapping of compensation values ​​according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figures 1-6 discuss Figure 7 . Figure 7 The horizontal axis represents the load current at SMPS106, while Figure 7 The vertical axis represents the voltage at power supply 102. Figure 7 In the example, controller circuit 104 operates using PFM compensation values ​​above line 702 and PWM compensation values ​​below line 702.

[0054] Figure 8 This is a conceptual diagram illustrating a first conversion from PFM to PWM according to one or more techniques according to this disclosure. Reference is made for illustrative purposes only. Figures 1-7discuss Figure 8 . Figure 8 The horizontal axis represents time, while Figure 8 The vertical axis represents the load 802 at SMPS106, the frequency 804 of the PWM signal, the on-time 806 of the PWM signal, the compensation value 808 at compensation element 221, and the output voltage 810 at SMPS106. Figure 8 In the example, controller circuit 104 may operate in gap mode in region 820, which would result in undervoltage at output voltage 810.

[0055] More specifically, such as Figure 8 As shown, a transition occurs when the load 802 overcomes a predetermined threshold. At this time, the controller circuit 104 may not be able to further increase the frequency 804, and the on-time 806 can be modulated by the PWM loop, but cannot be activated because the compensation value 808 is small. Therefore, the compensation value 808 can span a "gap" before activating the PWM loop. However, during this time interval, the output voltage 810 is not regulated. Consequently, a large undervoltage can occur at the output voltage 810. According to the technique described herein, the controller circuit 104 can use a shift signal to reduce or eliminate the gap before activating the PWM loop, which reduces or eliminates the undervoltage at the output voltage 810 in response to changes in the load 802.

[0056] Figure 9 This is a conceptual diagram illustrating a second conversion from PFM to PWM according to one or more techniques according to this disclosure. Reference is made for illustrative purposes only. Figures 1-8 discuss Figure 9 .like Figure 9 As shown, during steady-state operation, the controller circuit 104 operates using PFM due to the relatively low compensation value 902. Subsequently, during the transition cycle (e.g., load increase, voltage decrease at power supply 102, etc.), the shift signal drives the compensation value 904 faster and / or higher compared to a system that ignores the shift signal. Thus, the controller circuit 104 reduces or eliminates the gap during the transition cycle, for example, by operating in a PWM control loop. After the transition cycle, the shift signal decreases, resulting in a compensation value 906, and the controller circuit 104 operates in the PWM control loop. In this way, the controller circuit 104 can reduce or eliminate the gap compared to a system that ignores the shift signal without affecting steady-state operation (e.g., PFM, PWM, etc.).

[0057] Figure 10 This is a conceptual diagram illustrating a second system for reducing transient effects according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figures 1-9 discuss Figure 10 .like Figure 10As shown, the controller circuit 1004 includes a PWM circuit device 1014, a PFM circuit device 1016, and a logic circuit device 1018, which can be... Figure 1 Examples of PWM circuit device 114, PFM circuit device 216, and logic circuit device 118 are provided. Furthermore, the controller circuit 1004 may also include compensation element 1021, voltage divider 1028, amplifier 1012, and amplifier 1020, which may be substantially similar to... Figure 2 The compensation element 221, voltage divider 228, amplifier 212, and amplifier 220 are included. The PFM circuit device 1016 can be substantially similar to... Figure 2 The PFM circuit device 216. For example, the PFM circuit device 1016 may include a ramp generator 1030 and a clock manager 1032, which may be substantially similar to... Figure 2 The ramp generator 230 and the clock manager 232.

[0058] The PWM circuit 1014 may include a base current source 1022, a signal generator 1024, and a comparator 1034. As shown, the base current source 1022 may be configured to receive a shift signal to drive the base current source 1022 to output a shifted base current (“i_shifted pedestal”) based on the shift signal. For example, the base current source 1022 may be configured to generate the shifted base current as a base current minus the shift signal.

[0059] Amplifier 1012 can be configured to generate a modulated current based on a compensation value at compensation element 1021. Signal generator 1024 can be configured to generate a carrier current for each of multiple cycles, increasing the current at a rate of change. For example, signal generator 1024 can be configured to generate a triangular wave.

[0060] Comparator 1034 can be configured to generate a peak signal (“PEAK SIGNAL”) to indicate when the sum of the shift base current (“i_shifted pedestal”) and the carrier current (“i_carrier”) equals the modulation current (“i_modulating”). For example, comparator 1034 generates a peak signal to set when the sum of the shift base current (“i_shifted pedestal”) and the carrier current (“i_carrier”) equals the modulation current (“i_modulating”).

[0061] Logic circuit device 1018 can be configured to generate a PWM signal (“PWM”) based on a peak signal, a hold signal, and a minimum PFM on-time value. In some examples, logic circuit device 1018 can be configured to operate with PWM circuit device 1014 when the target PWM on-time indicated by the peak signal is greater than the minimum PFM on-time value. In some examples, logic circuit device 1018 can be configured to operate with PFM circuit device 1016 when the target PFM frequency is less than the PWM frequency value.

[0062] Figure 11 This is a conceptual diagram illustrating a voltage-mode PWM according to one or more techniques of this disclosure. Reference is made for illustrative purposes only. Figures 1-10 discuss Figure 11 . Figure 11 The horizontal axis represents time, while Figure 11 The vertical axis represents the current at carrier current 1102 output by signal generator 1024, the current amplitude at modulation current 1104 output by amplifier 1012, and the voltage at peak signal 1108 output by comparator 1034.

[0063] like Figure 11 As shown, at time 1120, the period is initialized such that the carrier current 1102, offset by the shifted base current output from the base current source 1022, increases as the current at the inductor of the SMPS 106 increases, and the PWM signal 1108 is set to the active state. At time 1122, in response to determining that the modulation current 1104 equals the carrier current 1102, the comparator 1034 resets the PWM signal 1108. Although Figure 11 The examples are discussed using current, but in some examples, voltage mode can also be used.

[0064] Figure 12 This is a flowchart illustrating a process for reducing transient effects according to this disclosure. Reference is made for illustrative purposes only. Figures 1-11 discuss Figure 12 .according to Figure 12 For example, gap detection circuit 112 generates a shift signal (1202) based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by SMPS 106. PFM circuit 116 generates a hold signal (1204) indicating the target PFM frequency of the PWM signal. PWM circuit 116 shifts the base current based on the shift signal to generate a shift base current (1206). PWM circuit 116 generates a peak signal (1208) based on the shift base current, indicating the target PWM on-time of the PWM signal.

[0065] Logic circuit device 118 determines whether the target PFM frequency is less than the PWM frequency value (1210). In response to determining that the target PFM frequency is less than the PWM frequency value ("Yes" in decision box 1210), logic circuit device 118 generates a PWM signal, which includes a frequency corresponding to the target PFM frequency and an on-time corresponding to the minimum PFM on-time value (1212). In response to determining that the target PFM frequency is not less than the PWM frequency value ("No" in decision box 1210), logic circuit device 118 determines whether the target PWM on-time is greater than the minimum PFM on-time value (1214).

[0066] In response to determining that the target PWM on-time is greater than the minimum PFM on-time value ("Yes" in decision box 1214), the logic circuit device 118 generates a PWM signal that includes a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time (1216). In response to determining that the target PWM on-time is not greater than the minimum PFM on-time value ("No" in decision box 1214), the logic circuit device 118 optionally generates a PWM signal that includes the PWM frequency value and the minimum PFM on-time value (1218).

[0067] The following examples may illustrate one or more aspects of this disclosure.

[0068] Example 1. A controller circuit for generating a pulse width modulation (PWM) signal for activating a switching device of a switching power supply (SMPS), the controller circuit comprising: a gap detection circuit configured to generate a shift signal based on an indication of a voltage difference between a reference voltage and a feedback voltage corresponding to a voltage output by the SMPS; a pulse frequency modulation (PFM) circuit configured to generate a hold signal indicating a target PFM frequency of the PWM signal; a PWM circuit configured to shift a base current based on the shift signal to generate a shifted base current, and to generate a peak signal indicating a target PWM on-time of the PWM signal based on the shifted base current; and a logic circuit configured to: in response to determining that the target PFM frequency is less than a PWM frequency value, generate a PWM signal including a frequency corresponding to the target PFM frequency and an on-time corresponding to a minimum PFM on-time value, and in response to determining that the target PWM on-time is greater than the minimum PFM on-time value, generate a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time.

[0069] Example 2. According to the controller circuit of Example 1, wherein the logic circuit device is configured to: in response to determining that the target PFM frequency is greater than or equal to the PWM frequency value and the target PWM on-time is less than or equal to the minimum PFM on-time value, generate a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the minimum PFM on-time value.

[0070] Example 3. A controller circuit according to any combination of Examples 1-2, wherein, in order to generate a shift signal, the gap detection circuit is configured to generate a shift signal comprising a current proportional to the voltage difference between the reference voltage and the feedback voltage when the voltage difference is greater than a threshold.

[0071] Example 4. A controller circuit according to any combination of Examples 1-3, wherein the gap detection circuit device includes an operational transconductance amplifier (OTA) having a first input coupled to a reference voltage, a second input coupled to a feedback voltage, and an output configured to output a shift signal.

[0072] Example 5. A controller circuit based on any combination of Examples 1-4, wherein the PWM circuit device is configured to generate a base current corresponding to the minimum inductor current of the SMPS.

[0073] Example 6. A controller circuit based on any combination of Examples 1-5, wherein, in order to shift the base current, the PWM circuit device is configured to subtract the shift signal from the base current.

[0074] Example 7. A controller circuit according to any combination of Examples 1-6, wherein, in order to generate a peak signal, the PWM circuitry is configured to: generate a compensation current based on a compensation value at a compensation element, wherein the compensation value is based on the voltage difference between a reference voltage and a feedback voltage; generate a slope compensation current that increases during the target PWM on-time; and generate a peak signal to indicate when a first sum of the shift base current and the sensed current corresponding to the current output at the SMPS equals a second sum of the compensation current and the slope compensation current.

[0075] Example 8. A controller circuit according to any combination of Examples 1-7, wherein, in order to generate a PWM signal, the PWM circuit device is configured to generate a PWM signal to transition from an on state to an off state in response to a peak signal indicating that a first sum equals a second sum.

[0076] Example 9. A controller circuit based on any combination of Examples 1-8, wherein the compensation value is further based on the shift signal.

[0077] Example 10. A controller circuit according to any combination of Examples 1-9, wherein, in order to generate a peak signal, the PWM circuit device is configured to: generate a carrier current or voltage that increases at a rate of change for each of a plurality of cycles; and generate a modulated current or voltage based on a compensation value at a compensation element, wherein the compensation value is based on the voltage difference between a reference voltage and a feedback voltage.

[0078] Example 11. A controller circuit according to any combination of Examples 1-10, wherein, in order to generate a PWM signal, the PWM circuit device is configured to generate a PWM signal to transition from an on state to an off state in response to the sum of the shift base current or voltage and the carrier current or voltage being equal to the modulation current or voltage.

[0079] Example 12. A controller circuit based on any combination of Examples 1-11, wherein the compensation value is further based on the shift signal.

[0080] Example 13. A controller circuit according to any combination of Examples 1-12, wherein, in order to generate a hold signal, the PFM circuit device is configured such that, for each cycle: after a minimum PFM on-time value, a voltage ramp signal is initiated and the hold signal is set to the on state, wherein the voltage ramp signal increases the voltage at a rate of change corresponding to a compensation value at the compensation element, wherein the compensation value is based on the voltage difference between the reference voltage and the feedback voltage; and in response to the voltage ramp signal being greater than or equal to a voltage threshold, the hold signal is reset to the off state.

[0081] Example 14. A method for generating a pulse width modulation (PWM) signal for activating a switching device of a switching power supply (SMPS), the method comprising: generating a shift signal based on an indication of a voltage difference between a reference voltage and a feedback voltage corresponding to a voltage output by the SMPS; generating a hold signal indicating a target pulse frequency modulation (PFM) frequency of the PWM signal; shifting a base current based on the shift signal to generate a shift base current; generating a peak signal based on the shift base current, the peak signal indicating a target PWM on-time of the PWM signal; generating a PWM signal including a frequency corresponding to the target PFM frequency and an on-time corresponding to a minimum PFM on-time value in response to determining that the target PFM frequency is less than a PWM frequency value; and generating a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time value in response to determining that the target PWM on-time is greater than the minimum PFM on-time value.

[0082] Example 15. The method according to Example 14 further includes: in response to determining that the target PFM frequency is greater than or equal to the PWM frequency value and the target PWM on-time is less than or equal to the minimum PFM on-time value, generating a PWM signal including a frequency corresponding to the PWM frequency value and an on-time corresponding to the minimum PFM on-time value.

[0083] Example 16. A method according to any combination of Examples 14-15, wherein generating the shift signal includes: generating a shift signal to include a current proportional to the voltage difference between the reference voltage and the feedback voltage when the voltage difference is greater than a threshold.

[0084] Example 17. The method according to any combination of Examples 14-16 further includes: generating a base current corresponding to the minimum inductor current of the SMPS.

[0085] Example 18. A method based on any combination of Examples 14-17, wherein the shift base current comprises: subtracting the shift signal from the base current.

[0086] Example 19. A circuit for switching power supplies (SMPS) comprising: a switching device configured to connect and disconnect based on a pulse width modulation (PWM) signal; a gap detection circuit configured to generate a shift signal based on an indication of a voltage difference between a reference voltage and a feedback voltage corresponding to a voltage output by the SMPS; a PWM circuit configured to shift a base current based on the shift signal to generate a shifted base current, and to generate a peak signal indicating a target PWM on-time based on the shifted base current; and a logic circuit configured to generate a PWM signal including a frequency corresponding to a PWM frequency value and an on-time corresponding to the target PWM on-time in response to determining that the target PWM on-time is greater than a minimum on-time value.

[0087] Example 20. The circuit according to Example 19, wherein the minimum on-time is a minimum pulse frequency modulation (PFM) on-time value, the circuit further includes: a PFM circuit means configured to generate a hold signal indicating a target PFM frequency of the PWM signal, wherein the logic circuit means is further configured to: in response to determining that the target PFM frequency is less than the PWM frequency value, generate a PWM signal including a frequency corresponding to the target PFM frequency and including an on-time corresponding to the minimum PFM on-time value.

[0088] This disclosure describes various aspects. These and other aspects are within the scope of the following claims.

Claims

1. A controller circuit for generating a pulse width modulation (PWM) signal, the PWM signal being used to activate the switching device of a switching power supply (SMPS), the controller circuit comprising: The gap detection circuit is configured to generate a shift signal based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by the SMPS. A pulse frequency modulation (PFM) circuit device is configured to generate a hold signal indicating a target PFM frequency of the PWM signal; A PWM circuit device is configured to shift a base current based on the shift signal to generate a shift base current, and to generate a peak signal indicating a target PWM on-time based on the shift base current; as well as The logic circuit device is configured as follows: In response to determining that the target PFM frequency is less than the PWM frequency value, a PWM signal is generated that includes a frequency corresponding to the target PFM frequency and an on-time corresponding to the minimum PFM on-time value; and In response to determining that the target PWM on-time is greater than the minimum PFM on-time value, a PWM signal is generated that includes a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time.

2. The controller circuit according to claim 1, wherein the logic circuit device is configured as follows: In response to determining that the target PFM frequency is greater than or equal to the PWM frequency value and the target PWM on-time is less than or equal to the minimum PFM on-time value, the PWM signal is generated, which includes a frequency corresponding to the PWM frequency value and an on-time corresponding to the minimum PFM on-time value.

3. The controller circuit according to claim 1, wherein, in order to generate the shift signal, the gap detection circuit device is configured as follows: When the voltage difference is greater than a threshold, the shift signal is generated to include a current proportional to the voltage difference between the reference voltage and the feedback voltage.

4. The controller circuit of claim 3, wherein the gap detection circuit device includes an operational transconductance amplifier OTA, the OTA including a first input coupled to the reference voltage, a second input coupled to the feedback voltage, and an output configured to output the shift signal.

5. The controller circuit according to claim 1, wherein the PWM circuit device is configured as follows: The base current is generated to correspond to the minimum inductor current of the SMPS.

6. The controller circuit of claim 1, wherein the PWM circuit arrangement is configured to: Subtract the shift signal from the base current.

7. The controller circuit of claim 1, wherein, in order to generate the peak signal, the PWM circuit device is configured as follows: A compensation current is generated based on the compensation value at the compensation element, wherein the compensation value is based on the voltage difference between the reference voltage and the feedback voltage; Generate an increased slope compensation current during the target PWM on-time; as well as The peak signal is generated to indicate when the first sum of the shift base current and the sensed current corresponding to the current output at the SMPS is equal to the second sum of the compensation current and the slope compensation current.

8. The controller circuit of claim 7, wherein, in order to generate the PWM signal, the PWM circuit device is configured as follows: In response to the peak signal indicating that the first sum is equal to the second sum, the PWM signal is generated to transition from the on state to the off state.

9. The controller circuit of claim 7, wherein the compensation value is further based on the shift signal.

10. The controller circuit of claim 1, wherein, in order to generate the peak signal, the PWM circuit device is configured to: Generate a carrier current or voltage, which increases at a rate of change for each of multiple cycles; and A modulation current or voltage is generated based on the compensation value at the compensation element, wherein the compensation value is based on the voltage difference between the reference voltage and the feedback voltage.

11. The controller circuit of claim 10, wherein, in order to generate the PWM signal, the PWM circuit device is configured to: In response to the sum of the shift base current or voltage and the carrier current or voltage being equal to the modulation current or voltage, the PWM signal is generated to transition from the on state to the off state.

12. The controller circuit of claim 10, wherein the compensation value is further based on the shift signal.

13. The controller circuit of claim 1, wherein, in order to generate the hold signal, the PFM circuit arrangement is configured such that, for each cycle: After the minimum PFM on-time value, a voltage ramp signal is initiated and the hold signal is set to the on state, wherein the voltage ramp signal increases the voltage at a rate of change corresponding to the compensation value at the compensation element, wherein the compensation value is based on the voltage difference between the reference voltage and the feedback voltage; and In response to the voltage ramp signal being greater than or equal to the voltage threshold, the holding signal is reset to the off state.

14. A method for generating a pulse width modulation (PWM) signal, the PWM signal being used to activate the switching device of a switching power supply (SMPS), the method comprising: A shift signal is generated based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by the SMPS; Generate a hold signal that indicates the target pulse frequency modulation PFM frequency of the PWM signal; The shift base current is generated based on the shift signal shift base current; A peak signal is generated based on the shifted base current, and the peak signal indicates the target PWM on-time of the PWM signal; In response to determining that the target PFM frequency is less than the PWM frequency value, a PWM signal is generated including a frequency corresponding to the target PFM frequency and an on-time corresponding to the minimum PFM on-time value; and In response to determining that the target PWM on-time is greater than the minimum PFM on-time value, a PWM signal is generated that includes a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time.

15. The method of claim 14, further comprising: In response to determining that the target PFM frequency is greater than or equal to the PWM frequency value and the target PWM on-time is less than or equal to the minimum PFM on-time value, the PWM signal is generated, which includes a frequency corresponding to the PWM frequency value and an on-time corresponding to the minimum PFM on-time value.

16. The method of claim 14, wherein generating the shift signal comprises: When the voltage difference is greater than a threshold, the shift signal is generated to include a current proportional to the voltage difference between the reference voltage and the feedback voltage.

17. The method of claim 16, further comprising: The base current is generated to correspond to the minimum inductor current of the SMPS.

18. The method of claim 14, wherein shifting the base current comprises: Subtract the shift signal from the base current.

19. A circuit for switching a switching power supply (SMPS), the circuit comprising: The switching device is configured to connect and disconnect based on a pulse width modulation (PWM) signal; The gap detection circuit is configured to generate a shift signal based on an indication of the voltage difference between a reference voltage and a feedback voltage corresponding to the voltage output by the SMPS; A PWM circuit device is configured to shift a base current based on the shift signal to generate a shift base current, and to generate a peak signal indicating a target PWM on-time based on the shift base current; as well as A logic circuit device is configured to generate the PWM signal, which includes a frequency corresponding to the PWM frequency value and an on-time corresponding to the target PWM on-time, in response to determining that the target PWM on-time is greater than the minimum pulse frequency modulation (PFM) on-time value.

20. The circuit of claim 19, wherein the circuit further comprises: The PFM circuitry is configured to generate a hold signal indicating the target PFM frequency of the PWM signal. The logic circuit device is further configured to: in response to determining that the target PFM frequency is less than the PWM frequency value, generate the PWM signal including a frequency corresponding to the target PFM frequency and an on-time corresponding to the minimum PFM on-time value.

Images