Apparatus and method for evaluating internal and external system processors by internal and external debugger devices

Abstract

Embodiments of this disclosure relate to an apparatus and method for evaluating internal and external system processors using internal and external debugger devices. An electronic device includes: a system processor (SP) region connectable to an SP; a main device region connectable to a first electronic device; and an auxiliary device region disposed between the SP device region and the main device region and connectable to a second electronic device. This embodiment further includes a debugger region comprising debugger units and disposed adjacent to the main device region and the auxiliary device region. This embodiment also includes: obtaining a debug selection, the debug selection including a debugger selection and a system processor (SP) selection; entering a first debug mode based on the determination that the debugger selection meets debugger criteria and the SP selection meets SP criteria; entering a second debug mode based on the determination that the debugger selection meets debugger criteria while the SP selection does not meet SP criteria; and entering a third debug mode based on the determination that the debugger selection does not meet debugger criteria.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 912490, filed October 8, 2019, entitled “Scalable architecture for microcontroller evaluation kits for mass-market ecosystem enablement,” the contents of which are incorporated herein by reference in their entirety for all purposes, and are as if fully and adequately set forth herein. Technical Field

[0003] This implementation generally relates to system processors, and more specifically to evaluating internal and external system processors using internal and external debugger devices. Background Technology

[0004] Traditional microcontroller evaluation kits lack sufficient capabilities to evaluate system processors using internal and external debugger devices. Furthermore, traditional microcontroller evaluation kits lack sufficient capabilities to evaluate internal and external system processors using debugger devices. Therefore, it is necessary to evaluate internal and external system processors using internal and external debugger devices. Summary of the Invention

[0005] This embodiment includes an electronic device having: a system processor (SP) region connectable to a SP; a main device region connectable to a first electronic device; and an auxiliary device region disposed between the SP device region and the main device region, and connectable to a second electronic device. This embodiment further includes a debugger region comprising a debugger unit and disposed adjacent to the main device region and the auxiliary device region. This embodiment also includes: obtaining a debug selection, the debug selection including a debugger selection and a system processor (SP) selection; determining to enter a first debug mode based on: the debugger selection meets debugger criteria and the SP selection meets SP criteria; determining to enter a second debug mode based on: the debugger selection meets debugger criteria while the SP selection does not meet SP criteria; and determining to enter a third debug mode based on: the debugger selection does not meet debugger criteria. Attached Figure Description

[0006] These and other aspects of this embodiment will become clear to those skilled in the art from the following description of specific embodiments in conjunction with the accompanying drawings.

[0007] Figure 1 An exemplary system according to this embodiment is illustrated.

[0008] Figure 2 An exemplary device according to this embodiment is illustrated.

[0009] Figure 3 The illustration shows operation in the exemplary first mode. Figure 2 An exemplary device.

[0010] Figure 4 The illustration shows operation in the exemplary second mode. Figure 2 An exemplary device.

[0011] Figure 5 The illustration shows operation in the exemplary third mode. Figure 2 An exemplary device.

[0012] Figure 6 An exemplary method according to this embodiment is illustrated.

[0013] Figure 7 The illustration shows about Figure 6 Further exemplary methods of the exemplary methods. Detailed Implementation

[0014] This embodiment will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of implementations to enable those skilled in the art to practice implementations and alternative forms that are obvious to them. It is worth noting that the following figures and examples are not intended to limit the scope of this embodiment to a single embodiment, but other embodiments are possible by exchanging some or all of the elements described or shown. Furthermore, where some elements of this embodiment may be implemented partially or wholly using known components, only those portions of these known components necessary for understanding this embodiment will be described, and detailed descriptions of other portions of these known components will be omitted so as not to obscure this embodiment. Unless otherwise specified herein, embodiments described as implemented in software should not be limited thereto, but may include embodiments implemented in hardware or a combination of software and hardware, and vice versa, as will be apparent to those skilled in the art. In this specification, the description of embodiments of a single component should not be considered limiting; rather, unless expressly stated otherwise, this disclosure is intended to cover other embodiments including multiple identical components, and vice versa. Furthermore, the applicant does not intend to assign any unusual or special meaning to any term in the specification or claims unless expressly stated otherwise. Furthermore, this embodiment covers current and future known equivalents of known components mentioned herein by way of example.

[0015] This embodiment can demonstrate one or more technical advantages, including standardized and flexible device and system layouts. Therefore, systems and devices according to this embodiment can be scaled and deployed to the market more quickly, thereby advantageously reducing overall development costs. Systems and devices according to this embodiment can further support a large number of auxiliary devices and associated capabilities by allowing easier connection to many expansion modules through the compatibility of flexible auxiliary devices. Systems and devices according to this embodiment can further provide multiple debugging options. Through a wide variety of debugging use cases (including but not limited to two-wire debugging and complex, near real-time trace capture), the multiple debugging modes according to this embodiment can advantageously reduce the user's ownership costs.

[0016] According to this embodiment, the system, apparatus, and method relate to an evaluation kit for system processor systems and apparatuses. According to this embodiment, in low-cost and experimental groups, the evaluation kit may include system processors and associated devices required for various applications. In some embodiments, the evaluation kit supports common layouts in which common and less common devices and functions are configured in a standardized manner to enable rapid prototyping and design modifications of the microcontroller system. Further, according to this embodiment, the evaluation kit may include support for debugging using onboard debug equipment capable of providing common debugging functions. Further, according to this embodiment, the evaluation kit may include support for debugging using external debug equipment capable of providing extended, uncommon, specialized, or similar debugging functions.

[0017] Figure 1 An exemplary system according to this embodiment is illustrated. Figure 1 As shown, the exemplary system 100 includes a system processor (SP) 102, a debugger device 104, a debugger input-output (I / O) interface 106, one or more master devices 108, a main I / O interface 110, one or more auxiliary devices 112, an auxiliary I / O interface 114, and an SP / IO interface 116.

[0018] SP 102 is operable to execute one or more instructions and interfaces with one or more external devices and I / O interfaces. In some embodiments, SP is an electronic processor, integrated circuit, etc., including one or more of digital logic, analog logic, digital sensors, analog sensors, communication buses, volatile memory, non-volatile memory, etc. In some embodiments, SP includes, but is not limited to, at least one microcontroller unit (MCU), microprocessor unit (MPU), central processing unit (CPU), graphics processing unit (GPU), physical processing unit (PPU), embedded controller (EC), etc. In some embodiments, SP 102 includes: a memory operable to store one or more instructions for operating components of SP 102; and an operating component operatively coupled to SP 102. In some embodiments, the one or more instructions include at least one of firmware, software, hardware, operating system, embedded operating system, etc. In some implementations, SP102 is operatively coupled to one or more of the following communication channels: debugger device 104, debugger input-output (I / O) interface 106, master device 108, master I / O interface 110, auxiliary device 112, auxiliary I / O interface 114, and microcontroller interface 116. It should be understood that communication channels 120, 122, 124, 126, and 128 can be implemented as different wires, conductors, traces, etc. It should further be understood that communication channels 120, 122, 124, 126, and 128 can be implemented as one or more wired or wireless digital or analog communication buses, etc. It should be understood that SP102 or system 100 typically includes at least one communication bus controller to influence communication between SP102 and other components of system 100 via communication channels 120, 122, 124, 126, and 128.

[0019] Debugger device 104 is operable to execute one or more instructions associated with the operation of SP 102. In some embodiments, debugger device 104 is an electronic processor, integrated circuit, etc., including a memory operable to store one or more instructions for operating components of debugger device 104 and operating components of SP 102. In some embodiments, the one or more instructions include at least one of firmware, software, hardware, operating system, embedded operating system, etc. In some embodiments, debugger device is a processor including instructions for operating any SP compatible with SP 102. In some embodiments, debugger device 104 includes instructions for monitoring the operation of SP 102. As an example, in response to various instructions being executed by SP 102 or receiving various instructions at SP 102, debugger device 104 can “track” changes in the state of the memory or other components of SP 102 to receive changes in the operating state of SP 102. In some embodiments, debugger device 104 includes instructions for modifying the operation of SP 102 by modifying, erasing, or adding instructions stored on SP. As an example, debugger device 104 can "flash" the memory of SP 102 to send operating system instructions or program instructions to SP 102.

[0020] System 100 includes one or more I / O interfaces to influence communication between devices within System 100 and external devices and the system. In some embodiments, the I / O interfaces include one or more of pin connections, via connections, clip connections, composite pin "board" or "head" connections, etc. Connections can operatively couple various digital, analog, electrical, electromechanical, electrostatic, wireless antenna, or similar devices to one or more devices of System 100. Debugger I / O interface 106 can operatively couple debugger device 104 to external devices including, but not limited to, debugger terminals. Main I / O interface 110 can operatively couple at least one master device to an external device. Auxiliary I / O interface 114 can operatively couple at least one auxiliary device to an external device. SP I / O interface 116 can operatively couple one or more components of SP 102 directly to an external device.

[0021] One or more master devices 108 from devices compatible with SP 102 and associated with the main functions of SP 102 or a device or system containing SP 102 may be included in system 100. In some embodiments, master device 108 is a device associated with basic functions such as SP 102, embedded system operation, etc. Master device 108 may include, but is not limited to, port controllers for serial, parallel, USB, DVI, or similar device ports. Master device 108 may further include, but is not limited to, expansion slots, power supply contacts, mounting vias, etc.

[0022] One or more auxiliary devices 112 from devices compatible with SP 102 and associated with auxiliary functions of SP 102 or devices or systems containing SP 102 may be included in system 100. In some embodiments, auxiliary device 108 is a device associated with advanced functions of SP 102, system 100, embedded system operation, etc. Auxiliary device 112 may include, but is not limited to, network interfaces, communication bus interfaces, sensor devices, memory devices, etc. Auxiliary device 112 may further include, but is not limited to, Ethernet interfaces, high-speed USB interfaces, flash memory devices, etc.

[0023] Figure 2 An exemplary device according to this embodiment is illustrated. For example... Figure 2 As shown, the exemplary device includes a system processor (SP) region 202, a debugger device region 204, a debugger I / O region 206, a main device region 208, a main I / O region 210, an auxiliary device region 212, an auxiliary I / O region 214, and an SP I / O region 216. In some embodiments, the device 200 includes an electronic circuit board, a printed circuit board, a conductive substrate, etc. In some embodiments, the electronic circuit board includes a first flat surface that engages with one or more electronic devices, and a second relatively flat surface that serves to secure one or more contacts between the electronic circuit board and one or more devices operatively coupled to the electronic circuit board. In some embodiments, the electronic circuit board of the device includes regions 202, 204, 206, 208, 210, 212, 214, and 216 disposed thereon. The device 200 can support various types of devices disposed in various locations to maximize variability in device functionality and consistency with operation with external devices.

[0024] SP region 202 is operable to accommodate SP 102 and operable to couple SP 102 to one or more of regions 204, 206, 208, 210, 212, 214, and 216, and to any device operable to the region. In some embodiments, SP region 202 includes a system processor pin interface compatible with multiple system processors (SPs) including SP 102. In some embodiments, each of the multiple compatible SPs includes different functionalities from each other. In some embodiments, each of the multiple compatible SPs includes a common pin assignment structure operable to couple with SP region 202. In some embodiments, alternatively, device 200 includes one of the multiple compatible SPs having different functionalities, thereby changing the functionality of device 200 through flexible exchange of SPs. In some embodiments, SP region 202 is disposed in a planar region on one or more edges of a printed circuit board remote from device 200.

[0025] Main device area 208 is operable to accommodate one or more of main devices 108 and operable to couple one or more of main devices 208 to one or more of areas 202, 204, 206, 210, 212, 214, and 216, as well as any devices operable to the area. In some embodiments, main device area 208 includes one or more of power supplies, power converters, power test loops, power LEDs, power buses, system control devices, and communication controller devices. In some embodiments, the main device area is operable to superimpose current by simultaneously receiving electrical power from multiple power supplies. In some embodiments, one or more of the multiple power supplies are located outside device 200. In some embodiments, power supplies or power converters compatible with or integrated with device 200 include low-dropout voltage regulators. In some embodiments, power test loops include power supplies for electronic device 200, SP102, SP area 202, any device or area of ​​device 200, or current clamping loops, voltage test loops, etc., operablely coupled to power supplies. System control devices include buttons, jumpers, etc., which are operable to affect one or more functions of electronic device 200, or any device or area of ​​electronic device 200, or operatively coupled to device or area of ​​electronic device 200. As an example, system control devices may be a system reset button, a power on / off switch, a startup configuration jumper, etc. Communication controller devices include electronic devices for receiving and transmitting communication signals according to one or more electrical or electronic communication protocols, conventions, modes, etc. As an example, communication control devices may be one or more of a serial communication integrated circuit and a USB communication integrated circuit. In some embodiments, the master device area 208 is only compatible with USB full-speed communication. In some embodiments, the master device area 208 is located on one or more edges of the printed circuit board remote from device 200 and in a planar area remote from SP area 202.

[0026] Auxiliary device region 212 is operable to accommodate one or more of auxiliary devices 112 and operable to couple one or more of auxiliary devices 112 to one or more of regions 202, 204, 206, 208, 210, 214, and 216, as well as any device operable to the region. In some embodiments, auxiliary device region 212 includes one or more auxiliary devices 112, including but not limited to communication interfaces and one or more electronic devices different from those associated with the main device region 208. As an example, auxiliary device region 212 may include an Ethernet port, an Ethernet communication integrated circuit, a high-speed USB communication integrated circuit, etc. As another example, auxiliary device region 212 may include a flash memory device, a flash memory communication integrated circuit, a magnetic memory controller, a multi-channel communication bus controller, etc. In some embodiments, alternatively, auxiliary device region 212 includes one or more of auxiliary devices 112 and SP 102 that are compatible with auxiliary device region 212, thereby changing the functionality of device 200 through flexible interchange of various auxiliary devices compatible with SP 102. In some embodiments, the auxiliary device region 208 is located in a planar region adjacent to one or more edges of a printed circuit board away from the device 200, and adjacent to the main device region 208 and the SP region 202.

[0027] Debugger device region 204 is operable to accommodate debugger 104 and is operable to couple debugger device 104 to one or more of regions 202, 206, 208, 210, 212, 214, and 216, and any device operable to the region. In some embodiments, debugger device region 204 includes debugger device 104 and one or more communication channels between debugger device 104 and SP 102. In some embodiments, debugger device 104 is operable to perform at least one debugging function with respect to SP 102. Debugging functions include, but are not limited to, monitoring the execution of one or more instructions executed on SP 102, controlling the execution of one or more instructions executed by SP 102, and modifying one or more instructions stored by SP 102 or any device operable to SP 102. In some embodiments, debugger device is operable to receive one or more debugging instructions from an external debugging terminal, send one or more debugging results to the debugging terminal, or perform a combination of such instructions in response to one or more debugging instructions received from the debugging terminal or any device operable to the debugging terminal. In some embodiments, monitoring and control execution includes monitoring and controlling the execution of instructions performed by SP 102 and associated with devices external to SP 102. Devices external to SP 102 include, but are not limited to, any device integrated or coupled to one or more of regions 202, 206, 208, 210, 212, 214, and 216, and any device operatively coupled to a region. Therefore, in some embodiments, debugger device region 204 provides a link between debugger device 104 and all devices and regions of electronic equipment 200 coupled to SP 102 via a debug-level interface with SP 102. In some embodiments, debugger device region 204 is located in a planar region adjacent to one or more edges of a printed circuit board remote from device 200, and adjacent to main device region 208, auxiliary device region 212, and SP region 202.

[0028] Main I / O region 210 is operable to couple one or more of main device 110 and main device region 208 to one or more external devices. In some embodiments, main I / O region 210 includes one or more connection interfaces to operablely couple electronic device 200 to one or more external microprocessors, external communication buses, etc. In some embodiments, main I / O region 210 includes one or more user I / O devices to receive information from and send information to the user of the device. In some embodiments, user I / O devices include user input buttons, user status LEDs, and disconnect traces for one or more regions and any devices operable to the region. In some embodiments, main I / O region 210 is disposed in a planar region adjacent to one or more edges of the printed circuit board of device 200 and adjacent to and at least partially surrounding main device region 208. In some embodiments, main I / O region 210 includes one or more connectors, interfaces, etc. operable to couple one or more external devices to electronic device 200. In some embodiments, main I / O region is operable to receive concurrent communication from multiple simultaneously connected devices. In some implementations, the simultaneously connected devices are serially connected to each other and connected to electronic devices via a "daisy-chain" or similar method. In some implementations, concurrent communication includes communication via one or more protocols, frameworks, etc., compatible with one or more embedded systems, or includes communication via one or more protocols, frameworks, etc., compatible with one or more embedded systems.

[0029] SP I / O region 216 is operable to couple one or more of SP 102 and SP region 202 to one or more external devices. In some embodiments, SP I / O region 216 includes one or more connection interfaces to operablely couple SP 102 to one or more external devices. In some embodiments, SP I / O region 216 includes one or more composite pin "board" or "header" connections. In some embodiments, SP I / O region 216 includes a graphics expansion port to operablely couple SP 102 to an external video output device or video display device. In some embodiments, SP I / O region 216 is disposed in a planar region adjacent to one or more edges of a printed circuit board remote from device 200, and adjacent to and at least partially surrounding SP region 202.

[0030] Auxiliary I / O region 212 is operable to couple one or more of auxiliary device 112 and auxiliary device region 210 to one or more external devices. In some embodiments, auxiliary I / O region 212 includes one or more connection interfaces to operablely couple electronic device 200 to one or more external microprocessors, external communication buses, etc. In some embodiments, auxiliary I / O region 212 is disposed in a planar region adjacent to one or more edges of the printed circuit board of device 200, adjacent to main I / O region 210, adjacent to auxiliary device region 212, and adjacent to SP I / O region 216.

[0031] Debugger I / O area 206 is operable to couple debugger device 104 and debugger device area 204 to one or more external devices. In some embodiments, auxiliary I / O area 212 includes one or more connection interfaces to operablely couple electronics device 200 to one or more external microprocessors, external communication buses, etc. In some embodiments, debugger I / O area 206 includes one or more connection interfaces or one or more LED devices. Exemplary connection interfaces include, but are not limited to, micro USB connectors coupled to debugger device 104. Exemplary connection interfaces further include, but are not limited to, one or more jumpers operable to select one or more debug modes. In some embodiments, jumpers are coupled to jumper pins in various combinations to select between multiple debug modes, including a first “onboard debug” mode, a second “external debugger” mode, and a third “external SP debug” mode of the electronics device. In various debug modes, debugger I / O area is operable to couple debugger device to electronics device 200, or operable to an external device of electronics device, or decouple debugger device from electronics device 200 or operable to an external device of electronics device. Exemplary LED devices include, but are not limited to, status LEDs for transmitting the status of debugger device 104, debugger operations performed by debugger device 104, etc.

[0032] Figure 3 The illustration shows operation in the exemplary first mode. Figure 2 An exemplary device. For example... Figure 3 As shown, the exemplary device 300 includes a component further operably coupled to the debugging terminal 310. Figure 2 An exemplary device. Exemplary device 300 is operably coupled by a debug terminal onboard I / O path 302 and a debugger onboard I / O path 304. Exemplary device 300 operates in a first "onboard debug" mode. In some embodiments, exemplary device 300 may selectively enter the "onboard debug" mode in response to a first jumper setting on debugger I / O area 206 corresponding to the "onboard debug" mode.

[0033] Debug terminal 310 is operatively coupled to exemplary device 300 to provide a user interface for debugging SP 102. In some embodiments, debug terminal 310 is a computing device, laptop computer, notebook computer, mobile device, handheld device, etc. In some embodiments, debug terminal includes one or more instructions for operatively coupling with debugger device 104. As an example, debug terminal 310 includes a graphical user interface and integrated development environment compatible with SP 102. As another example, debug terminal 310 includes one or more of a command-line interface, command recorder, input / output recorder, etc. Debug terminal onboard I / O path 302 operatively couples debug terminal 310 to debugger I / O area 206. In exemplary device 300, debugger I / O area 206 is operatively coupled to debugger area 204, and debugger area 204 is operatively coupled to debugger device 104 located together with, on, or similarly positioned within the area. The debugger onboard I / O path 304 operably couples the debugger region 204 to the SP region 202. In the exemplary device 300, the SP region 202 is operably coupled to SP 102. Therefore, the electronic device 300 is operable to perform debugging of SP 102 via the debugger device 104 and the debug terminal 310.

[0034] Figure 4 The illustration shows operation in the exemplary second mode. Figure 2 An exemplary device. For example... Figure 4 As shown, the exemplary device 400 includes a component further operably coupled to the debug terminal 310. Figure 2 The exemplary device 400 includes an external debugger 410. The exemplary device 400 is operatively coupled by a debug terminal external I / O path 402, an external debugger I / O path 404, and a debugger bypass I / O path 406. The exemplary device 400 operates in a second “external debugger” mode. In some embodiments, the exemplary device 400 selectively enters the “external debugger” mode in response to a second jumper setting on the debugger I / O area 206 corresponding to the “external debugger” mode.

[0035] External debugger 410 is operable to execute one or more instructions associated with the operation of SP 102. In some embodiments, external debugger 104 is an electronic processor, integrated circuit, etc., consistent with debugger device 104. In some embodiments, external debugger is operable to execute one or more debug operations different from the debug operations of debugger device. In some embodiments, exemplary external debugger 410 is operable to monitor instructions from or to one or more auxiliary devices 112 that are not monitored by debugger device 104. It should be understood that external debugger 410 is operable to execute instructions regarding monitoring, modification, or similar actions of SP 102 and devices operably coupled to external debugger, and is not limited to all functionalities differing between external debugger 410 and debugger device 104 as described herein. Debug terminal external I / O path 402 operablely couples debug terminal 310 to external debugger 410. External debugger I / O path 404 operablely couples external debugger 410 to main I / O area 210. The debugger bypass I / O path 406 operably couples the main I / O region 210 to the SP region 202. In the exemplary device 400, the SP region 202 is operably coupled to SP 102. Therefore, the electronic device 400 is operable to perform debugging of SP 102 via an external debugger 104 and a debug terminal 310.

[0036] Figure 5 The illustration shows operation in the exemplary third mode. Figure 2 An exemplary device. For example... Figure 5 As shown, the exemplary device 500 includes: Figure 2 Exemplary device, Figure 2 The exemplary device is further operably coupled to debug terminal 310; and external device 510, which includes external SP 520 and one or more master or auxiliary devices 530. Exemplary device 500 is operably coupled by debug terminal onboard I / O path 302, SP bypass I / O path 502 and external SP I / O path 504. External device 510 is operably coupled by external master-auxiliary device I / O path 506. Exemplary device 500 operates in a third “external SP debug” mode. In some embodiments, exemplary device 500 may selectively enter “external SP debug” mode in response to a third jumper setting on debugger I / O area 206 corresponding to the “external SP debug” mode.

[0037] External device 510 includes one or more devices and I / O interfaces corresponding to system 100. In some embodiments, external device 510 includes a printed circuit board, circuit board, etc., having the device and a subset of the I / O interfaces of system 100 disposed on or disposed with the device. In some embodiments, the printed circuit board of external device 510 is customized for a specific application including external SP 520. External SP 520 may operate correspondingly, identically, or similarly to SP 102. In some embodiments, external SP 502 is an electronic processor, integrated circuit, etc., consistent with SP 102.

[0038] An external master-slave device 530 from one or more devices compatible with master device 108 and slave device 112 may be included in external device 510. Depending on the specific application of external device 510, external device 510 may include one or more master devices 108, one or more slave devices 112, combinations thereof, or none of them. As an example, external device may include an Ethernet slave device for a network application, and may not include an Ethernet slave device for another application besides an Ethernet network. Corresponding to the debugger device 104 and debugger device region 204 operatively coupling debug terminal 310 to electronic device 300, debug terminal 310 is operatively coupled to debugger device 104 and debugger device region 204. SP bypass I / O path 502 operatively couples debugger device region 204 to main I / O region 210. External SP I / O path 504 operatively couples main I / O region 210 to external SP 420. In some embodiments, external SP I / O path 504 is operatively coupled directly to external SP 520 via main I / O area 210. Alternatively, in some embodiments, external SP I / O path 504 is operatively coupled indirectly to external SP 520 via external SP I / O interface, etc. Therefore, electronic device 500 is operable to perform debugging of external SP 520 via debugger device 104 and debug terminal 310. In some embodiments, external main-auxiliary device I / O path 506 is operatively coupled to external main-auxiliary device 530, wherein external SP 520 includes instructions for external SP 520.

[0039] Figure 6An exemplary method according to this embodiment is illustrated. In some embodiments, method 600 is performed on an exemplary system comprising at least one of system 100 and devices 200 to 500. In step 610, the exemplary system obtains a debug selection. In some embodiments, the exemplary system obtains the debug selection based on selectable jumper settings specified in debugger I / O area 206. Method 600 then proceeds to step 620.

[0040] In step 620, the exemplary system determines whether the obtained debug selection satisfies the "onboard debug" condition. In some embodiments, in response to selectable jumper settings, at least one of debugger device 104 and debugger I / O area 206 determines whether the obtained debug selection satisfies the "onboard debug" condition via a logic switch, selector, etc. Based on the determination that the obtained debug selection satisfies the "onboard debug" condition, method 600 proceeds to step 622. Alternatively, based on the determination that the obtained debug selection does not satisfy the "onboard debug" condition, method 600 proceeds to step 710. In step 622, the exemplary system couples debugger I / O area 206 to debug terminal 310. In some embodiments, the exemplary system couples debugger I / O area 206 to debug terminal 310 according to debug terminal onboard I / O path 302. Then method 600 proceeds to step 624. In step 624, the exemplary system couples debugger I / O area 206 to debugger area 204. Then method 600 proceeds to step 630.

[0041] In step 630, the exemplary system determines whether the obtained debug selection satisfies the "external SP debug" condition. In some embodiments, in response to selectable jumper settings, at least one of debugger device 104 and debugger I / O area 206 determines whether the obtained debug selection satisfies the "external SP debug" condition via a logic switch, selector, etc. Based on the determination that the obtained debug selection does not satisfy the "external SP debug" condition, method 600 proceeds to step 632. Alternatively, based on the determination that the obtained debug selection satisfies the "external SP debug" condition, method 600 proceeds to step 634. In step 632, the exemplary system couples debugger area 204 to SP area 202. In some embodiments, the exemplary system couples debugger I / O area 206 to debugger area 204 according to debugger-onboard I / O path 304. Then method 600 proceeds to step 640. In step 640, the exemplary system enters "onboard debug" mode. In some embodiments, method 600 ends at step 640.

[0042] In step 634, the exemplary system couples debugger region 204 to main I / O region 210. In some embodiments, the exemplary system couples debugger region 204 to main I / O region 210 according to SP bypass I / O path 502. Method 600 then proceeds to step 636. In step 636, the exemplary system couples main I / O region 210 to external SP 520. In some embodiments, the exemplary system couples main I / O region 210 to external SP 520 according to external SP I / O path 504. The method then proceeds to step 650. In step 650, the exemplary system enters "external SP debug" mode. In some embodiments, method 600 ends at step 650.

[0043] Figure 7 The illustration shows about Figure 6 An exemplary method of an exemplary method. In some embodiments, method 700 is performed according to an exemplary system of at least one of system 100 and devices 200 to 500. In step 710, method 700 continues from method 600. Method 700 then proceeds to step 712.

[0044] In step 712, the exemplary system couples the main I / O region 210 to the SP region 202. In some embodiments, the exemplary system couples the main I / O region 210 to the SP region 202 according to debugger bypass I / O path 406. Method 700 then proceeds to step 714. In step 714, the exemplary system couples the main I / O region 210 to the external debugger 410. In some embodiments, the exemplary system couples the main I / O region 210 to the external debugger 410 according to external debugger I / O path 404. Method 700 then proceeds to step 716. In step 716, the exemplary system obtains coupling from the external debugger 410 to the debug terminal 310. In some embodiments, the exemplary system obtains coupling from the external debugger 410 to the debug terminal 310 according to debug terminal external I / O path 402. In some implementations, the exemplary system acquires coupling by passively accepting a coupled state, or by successfully executing instructions to debug terminal 310 and receiving subsequent responses from debug terminal 310. Method 700 then proceeds to step 720. In step 720, the exemplary system enters "external debugger" mode. In some implementations, method 700 terminates at step 720.

[0045] The topics described herein sometimes illustrate different components contained in or connected to different other components. It should be understood that these described architectures are illustrative, and in reality, many other architectures can achieve the same functionality. Conceptually, any arrangement of components achieving the same functionality is effectively “associated” to achieve the desired functionality. Therefore, any two components combined herein to achieve a particular functionality can be considered “associated” with each other to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two components thus associated can also be considered “operably connected” or “operably coupled” with each other to achieve the desired functionality, and any two components capable of being thus associated can also be considered “operably coupled” with each other to achieve the desired functionality. Specific examples of operably coupled components include, but are not limited to, physically pairable and / or physically interactive components, and / or wirelessly interactive and / or logically interactive components.

[0046] Regarding the use of terms in plural and / or singular forms herein, those skilled in the art can convert from plural to singular and / or from singular to plural forms where appropriate for the context and / or application. For clarity, various arrangements of singular / plural forms may be explicitly stated herein.

[0047] Those skilled in the art will understand that, in general, the terms used herein, particularly in the appended claims (e.g., the body of the appended claims), are intended to be “open” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “at least having”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0048] While the accompanying drawings and descriptions may illustrate the specific order of the method steps, this order may differ from that depicted and described, unless otherwise specified above. Similarly, two or more steps may be performed simultaneously or partially simultaneously, unless otherwise specified above. For example, such variation may depend on the chosen software and hardware system and the designer's choices. All such variations are within the scope of this disclosure. Likewise, the software implementation of the described method can be accomplished using standard programming techniques that employ rule-based logic and other logic to accomplish the various connection steps, processing steps, comparison steps, and decision steps.

[0049] Those skilled in the art will further understand that if the specific number of claims listed is intentional, such intention will be explicitly stated in the claims, and if such a listing is not present, then such intention is not present. For example, to aid understanding, the appended claims below may contain the use of introductory phrases “at least one” and “one or more” to introduce the claim listing. However, the use of these phrases should not be construed as implying that the introduction of the claim listing by the indefinite article “a” or “an” will include any particular claim containing such an introduced claim listing, limited to inventions containing only one such listing, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” should generally be interpreted as “at least one” or “one or more”); this also applies when using definite articles for introducing the claim listing. Furthermore, even if the specific number of claims listed is explicitly stated, those skilled in the art will recognize that such a listing should generally be interpreted as meaning at least a number listed (e.g., a public listing of “two listings” without other modifiers generally means at least two listings or two or more listings).

[0050] Furthermore, in cases where conventions similar to "at least one of A, B, and C, etc." are used, generally, such a construction is intentional in the sense of the convention as understood by those skilled in the art (e.g., "a system having at least one of A, B, and C" includes, but is not limited to, systems having a single A, a single B, a single C, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). In cases where conventions similar to "at least one of A, B, and C, etc." are used, generally, such a construction is intentional in the sense of the convention as understood by those skilled in the art (e.g., "a system having at least one of A, B, or C" includes, but is not limited to, systems having a single A, a single B, a single C, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). Those skilled in the art will further understand that, in practice, any transitional words and / or phrases that propose two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one, any, or both of the terms. For example, the phrase “A or B” would be understood to include the possibility of “A” or “B” or “A and B”.

[0051] Furthermore, unless otherwise stated, the use of the words “approximately,” “about,” “probably,” “generally,” etc., refers to plus or minus ten percent.

[0052] For purposes of illustration and description, the foregoing description of illustrative embodiments has been presented. It is not intended to be exclusive or limiting with respect to the precise form disclosed, and modifications and variations based on the foregoing teachings are possible or can be obtained by practicing the disclosed embodiments. The scope of the invention is defined by the appended claims and their equivalents.

Claims

1. An electronic device, comprising: Electronic circuit board, the electronic circuit board comprising: An SP region that can be connected to the system processor SP, wherein the SP can be configured in multiple debugging modes according to debugger guidelines and SP guidelines; The main device area that can be connected to the first electronic device; and An auxiliary device area is located between the SP area and the main device area, and can be connected to a second electronic device. The electronic device mentioned above: Entering the first debugging mode is determined based on the following: the debugger selection meets the debugger criteria and the SP selection meets the SP criteria; and Entering the second debugging mode is determined based on the following: the debugger selection meets the debugger criteria while the SP selection does not meet the SP criteria; and Entering the third debugging mode is determined based on the following: the debugger selection does not meet the debugger criteria.

2. The electronic device according to claim 1, wherein the electronic circuit board further comprises: The debugger device area includes a debugger unit and is disposed adjacent to the main device area and the auxiliary device area.

3. The electronic device according to claim 2, wherein the electronic circuit board further comprises: The debugger input-output I / O area is located adjacent to the debugger device area.

4. The electronic device of claim 1, wherein the first electronic device can only be connected to the main device area.

5. The electronic device of claim 1, wherein the second electronic device can only be connected to the auxiliary device area.

6. The electronic device of claim 1, wherein the second electronic device is selectively connected to the auxiliary device region from among a plurality of electronic devices connectable to the auxiliary device region.

7. The electronic device of claim 6, wherein the plurality of electronic devices may be alternately connected to the auxiliary device area.

8. The electronic device of claim 6, wherein the plurality of electronic devices can be simultaneously connected to the auxiliary device area.

9. The electronic device according to claim 3, wherein the electronic circuit board further comprises: The main I / O area at least partially surrounds the main device area and is located adjacent to the debugger I / O area.

10. The electronic device of claim 9, wherein the electronic circuit board further comprises: The auxiliary I / O area is arranged adjacent to the debugger I / O area, the main I / O area, and the auxiliary device area.

11. The electronic device of claim 10, wherein the electronic circuit board further comprises: The SP I / O area at least partially surrounds the SP area and is disposed adjacent to the auxiliary I / O area.

12. An evaluation method for electronic devices, comprising: The electronic device obtains a debug selection, which includes debugger selection and system processor SP selection, wherein the electronic device includes a system processor SP, a debug processor, a debugger input-output I / O interface, and a main I / O interface; The electronic device determines to enter the first debugging mode based on the following: the debugger selects to meet the debugger criteria and the SP selects to meet the SP criteria. The electronic device enters the second debugging mode based on the following criteria: the debugger selects a mode that meets the debugger criteria while the SP selects a mode that does not meet the SP criteria. as well as The electronic device enters the third debugging mode based on the following criteria: the debugger selection does not meet the debugger criteria.

13. The method of claim 12, wherein entering the first debugging mode further comprises: Couple the debugger I / O interface to an external debugging terminal; and The debugger I / O interface is coupled to the debug processor.

14. The method of claim 13, wherein entering the first debugging mode further comprises: The debug processor is coupled to the SP.

15. The method of claim 14, wherein the debug processor, the SP, and the debugger I / O interface are integrated into an electronic device.

16. The method of claim 12, wherein entering the second debug mode further comprises: Couple the debugger I / O interface to an external debugging terminal; and The debugger I / O interface is coupled to the debug processor.

17. The method of claim 16, wherein entering the second debug mode further comprises: Couple the debug processor to the main I / O interface; and The main I / O interface is coupled to an external SP.

18. The method of claim 12, wherein entering the third debug mode further comprises: Couple the main I / O interface to the SP; and The main I / O interface is coupled to an external debug processor.

19. The method of claim 12, wherein the debug processor and the main I / O interface are integrated into an electronic device.

20. An evaluation method for electronic devices, comprising: The electronic device obtains a debug selection, which includes debugger selection and system processor SP selection, wherein the electronic device includes a system processor SP, a debug processor, a debugger input-output I / O interface, and a main I / O interface; The electronic device enters the first debug mode based on the following criteria: the debugger selection is to select the debug processor and the SP selection is to select the SP. The electronic device enters the second debug mode based on the following criteria: the debugger selection is to select the debug processor and the SP selection is not to select the SP. as well as The electronic device enters the third debugging mode based on the following: the debugger selection does not select the debug processor.

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