Methods of forming vertical field effect transistor (VFET) devices

Abstract

Methods of forming vertical field effect transistor (VFET) devices are provided. The methods can include forming an initial VFET on a substrate. The initial VFET can include a bottom source / drain region on the substrate, a channel region on the bottom source / drain region, a top source / drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source / drain region and the patterned sacrificial layer can be surrounded by the insulating layer. The methods can also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer via the contact opening, and forming a gate electrode in the cavity.

Description

Technical Field

[0001] This disclosure generally relates to the field of electronics, and more specifically to vertical field-effect transistor (VFET) devices. Background Technology

[0002] Due to the high scalability of VFET devices, various structures and fabrication processes for VFET devices have been studied. Therefore, it would be beneficial to develop fabrication processes that improve the performance and / or reliability of VFET devices. Summary of the Invention

[0003] According to some embodiments of the present invention, the gate electrode can be formed after the top source / drain region is formed. Therefore, the characteristics of the gate electrode can be unaffected by the process of forming the top source / drain region. Specifically, the gate electrode may not be oxidized or may not become damaged due to heat. In some embodiments, the gate electrode can be formed by a gate replacement process, which is performed through a gate contact opening in which a gate contact is subsequently formed. In some embodiments, the top source / drain region can be formed in an opening in the insulating layer and can be defined within that opening.

[0004] According to some embodiments of the present invention, a method of forming a VFET device may include forming an initial VFET on a substrate. The initial VFET may include a bottom source / drain region on the substrate, a channel region on the bottom source / drain region, a top source / drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The bottom source / drain region, the channel region, and the top source / drain region may be sequentially stacked on the substrate. The top source / drain region and the patterned sacrificial layer may be surrounded by the insulating layer. The method may further include: forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer; forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening; and forming a gate electrode in the cavity.

[0005] According to some embodiments of the present invention, a method of forming a VFET device may include: forming a mask layer on a substrate; etching the substrate using the mask layer as an etch mask to form a channel region; forming a bottom source / drain region on the substrate; forming a first liner extending on the side surface of the channel region and on the side and top surfaces of the mask layer; forming a patterned sacrificial layer on a lower portion of the side surface of the channel region; forming a top spacer on a upper portion of the side surface of the channel region; and forming an insulating layer on the substrate. The top spacer and the patterned sacrificial layer may be surrounded by the insulating layer. The method may further include: forming a top source / drain opening in the insulating layer by removing a portion of the top spacer and the mask layer; forming a top source / drain region in the top source / drain opening; forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer; and forming a gate electrode on a lower portion of the side surface of the channel region by replacing the patterned sacrificial layer with a gate electrode via the contact opening.

[0006] According to some embodiments of the present invention, a method of forming a VFET device may include forming a VFET on a substrate. The VFET may include a bottom source / drain region on the substrate, a channel region on the bottom source / drain region, a top source / drain region on the channel region, and a gate electrode on a side surface of the channel region. The bottom source / drain region, the channel region, and the top source / drain region may be sequentially stacked on the substrate. The gate electrode may include a work function layer and a metallic electrode sequentially stacked on the side surface of the channel region, and the work function layer may surround the metallic electrode in a cross-sectional view. Attached Figure Description

[0007] Figure 1 This is a flowchart illustrating a method for forming a VFET device according to some embodiments of the concept of the present invention.

[0008] Figure 2 This is a flowchart illustrating a method for forming a VFET device according to some embodiments of the concept of the present invention.

[0009] Figures 3 to 11 , Figures 13 to 16 , Figures 18 to 21 and Figure 23 This is a cross-sectional view illustrating a method for forming a VFET device according to some embodiments of the present invention.

[0010] Figure 12 , Figure 17 and Figure 22 This is a plan view illustrating a method for forming a VFET device according to some embodiments of the concept of the present invention.

[0011] Figures 24 to 28This is a cross-sectional view illustrating a method for forming a VFET device according to some embodiments of the present invention.

[0012] Figures 29 to 33 This is a cross-sectional view illustrating a method for forming a VFET device according to some embodiments of the present invention. Detailed Implementation

[0013] Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this disclosure, and therefore this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of this disclosure to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be enlarged. The same reference numerals always refer to the same elements.

[0014] Example embodiments of the inventive concept are described herein with reference to cross-sectional views, which are schematic diagrams of intermediate structures between idealized and example embodiments. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Consequently, the example embodiments of the inventive concept should not be construed as limited to the specific shapes shown herein, but rather include, for example, shape deviations caused by manufacturing processes.

[0015] Figure 1 This is a flowchart illustrating a method for forming a VFET device according to some embodiments of the concept proposed in this invention. (Refer to...) Figure 1 This method may include forming an initial VFET (e.g. Figure 13 The VFET shown in the diagram (box 100) is then sequentially formed with contact openings (e.g., Figure 14 The contact opening 62 (box 200) and the formation of the gate electrode (e.g. Figure 18 Gate electrode 74 in (box 300). The initial VFET may include a top source / drain region (e.g., Figure 18 The top source / drain region 52 in the middle, so the gate electrode can be formed after the top source / drain region is formed.

[0016] The initial VFET may also include a bottom source / drain region (e.g. Figure 13 The bottom source / drain region 22) and the channel region (e.g.) Figure 13 The channel region 12), patterned sacrificial layer (e.g.) Figure 13 The patterned sacrificial layer 33P in the middle) and the insulating layer (e.g. Figure 13 The second insulating layer 46 and the first insulating layer 36 are in the middle. The bottom source / drain region, the channel region and the top source / drain region are sequentially stacked on the substrate (e.g., the second insulating layer 46 and the first insulating layer 36). Figure 13On the substrate 10).

[0017] Figure 2 This is a flowchart illustrating a method for forming a VFET device according to some embodiments of the concept according to the present invention. Specifically, Figure 2 This is a flowchart illustrating the process of forming part of the initial VFET. Figures 3 to 11 , Figures 13 to 16 , Figures 18 to 21 and Figure 23 This is a cross-sectional view illustrating a method for forming a VFET device according to some embodiments of the present invention. Figure 12 , Figure 17 and Figure 22 This is a plan view illustrating a method for forming a VFET device according to some embodiments of the concept of the present invention. Figure 13 and Figure 18 They are respectively along Figure 12 and Figure 17 The sectional view taken by line A-A'. Figure 14 and Figure 19 They are respectively along Figure 12 and Figure 17 The sectional view taken by line B-B'. Figure 23 It is along Figure 22 The sectional view taken by line B-B'. Figure 20 yes Figure 18 A magnified view of region C. Figure 21 yes Figure 19 A magnified view of region D.

[0018] Reference Figure 2 and Figure 3 Forming the initial VFET may include forming a bottom source / drain region 22 and a channel region 12 on the substrate 10. In some embodiments, forming the channel region 12 may include forming a mask layer 14 on the substrate 10 (box 110) and forming the channel region 12 by etching the substrate 10 using the mask layer 14 as an etching mask (box 120). For example, the mask layer 14 may be a hard mask layer comprising SiN and / or SiON. The channel region 12 may protrude from the substrate 10 in a third direction D3. The third direction D3 may be vertical and may be perpendicular to the upper surface 10u of the substrate 10.

[0019] The substrate 10 may include one or more semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the substrate 10 may be a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. Figure 3As shown, two channel regions 12 can be formed on the substrate 10. The two channel regions 12 can be spaced apart from each other in a first horizontal direction D1. The first horizontal direction D1 can be parallel to the upper surface 10u of the substrate 10.

[0020] The bottom source / drain region 22 can be formed on the substrate 10 before or after the formation of the channel region 12. In some embodiments, the bottom source / drain region 22 can be formed by implanting impurity elements (e.g., B, P, and / or As) into the substrate 10. In some embodiments, the bottom source / drain region 22 can be formed by forming an epitaxial layer including impurity elements (e.g., B, P, and / or As) on the substrate 10. The epitaxial layer of the bottom source / drain region 22 can be formed by performing an epitaxial growth process using the substrate 10 as a seed layer.

[0021] Bottom spacer 24 may be formed on bottom source / drain region 22 such that bottom source / drain region 22 is adjacent to components subsequently formed on bottom source / drain region 22 (e.g., Figure 18 The gate electrode 74 is electrically isolated. The bottom spacer 24 may include an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride).

[0022] like Figure 3 As shown, a first liner 26 can be formed on the upper surface of the bottom spacer 24, the side surface of the channel region 12, and the side and upper surfaces of the mask layer 14. Figure 2 (See box 130 in the image). A first liner 26 can be formed to protect the channel region 12 during subsequent processes. In some embodiments, the first liner 26 can have a uniform thickness along the side surfaces of the channel region 12 and the side and top surfaces of the mask layer 14, such as... Figure 3 As shown. The first liner 26 may comprise a material different from the channel region 12, such that the first liner 26 can be selectively removed from the side surface of the channel region 12. For example, the first liner 26 may be a silicon oxide layer. Throughout the specification, removal layer X may refer to layer X etched using a wet etching process and / or a dry etching process. Although Figure 3 The first liner 26 is shown as a single layer, but in some embodiments, the first liner 26 may include multiple stacked layers sequentially stacked on the side surface of the channel region 12.

[0023] Reference Figure 4 The method may include sequentially forming an initial sacrificial layer 32 and an initial second liner 34 on a first liner 26. Each of the initial sacrificial layer 32 and the initial second liner 34 may have a uniform thickness, such as Figure 4As shown. For example, the initial sacrificial layer 32 may be a silicon layer (e.g., an amorphous silicon layer and / or a polycrystalline silicon layer) and / or a metallic layer (e.g., a TiN layer and / or a Ti layer). For example, the initial second substrate 34 may be a layer comprising an insulating material (e.g., a silicon layer comprising oxides and / or nitrides).

[0024] Reference Figure 5 The method may further include forming a first insulating layer 36 on the lower portion of the side surface of the channel region 12. The side surface of the channel region 12 may include an upper portion and a lower portion between the upper portion of the channel region 12 and the substrate 10. The first insulating layer 36 may include an insulating material (e.g., a silicon layer comprising oxides and / or nitrides or a low dielectric layer having a lower dielectric constant than silicon dioxide). The first insulating layer 36 is formed only on the lower portion of the side surface of the channel region 12, and the first insulating layer 36 exposes the portion of the initial sacrificial layer 32 above the first insulating layer 36 and the portion of the initial second liner 34 above the first insulating layer 36.

[0025] Reference Figure 6 The portion of the initial sacrificial layer 32 above the first insulating layer 36 and the portion of the initial second liner 34 above the first insulating layer 36 can be removed to form a sacrificial layer 33 and a second liner 35. The sacrificial layer 33 and the second liner 35 can be formed on the lower portion of the side surface of the channel region 12, such as... Figure 6 As shown. In some embodiments, the portion of the initial sacrificial layer 32 above the first insulating layer 36 and the portion of the initial second liner 34 above the first insulating layer 36 may be removed until the underlying first liner 26 is exposed. A portion of the channel region 12 and the mask layer 14 may protrude beyond the upper surface of the sacrificial layer 33 and the upper surface of the second liner 35 in the third direction D3, as shown. Figure 6 As shown.

[0026] Reference Figure 7 A top spacer layer 42 can be formed on the mask layer 14, sacrificial layer 33, second liner 35, and first insulating layer 36. The top spacer layer 42 can directly contact the upper surfaces of the first liner 26, sacrificial layer 33, second liner 35, and first insulating layer 36, such as... Figure 7 As shown. In some embodiments, the top spacer layer 42 may have a uniform thickness along the mask layer 14, such as Figure 7 As shown. For example, the top spacer layer 42 may include an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride). In some embodiments, the top spacer layer 42 may be a SiN layer. In some embodiments, the top spacer layer 42 may be multiple stacked layers.

[0027] Reference Figure 8A portion of the top spacer layer 42 can be removed until the underlying first insulating layer 36 is exposed. A portion of the top spacer layer 42 on the upper surface of the mask layer 14 can also be removed, thereby forming a top spacer 44. In some embodiments, the top spacer 44 may overlap with the upper surface of the sacrificial layer 33 and the upper surface of the second liner 35, such as... Figure 8 As shown.

[0028] Reference Figure 9 The portion of the first insulating layer 36, the portion of the second liner 35, and the portion of the sacrificial layer 33 can be as follows: Figure 9 The mask layer 14, the first liner 26, and the top spacer 44 are collectively used as an etching mask to remove the substrate, thereby forming a patterned sacrificial layer 33P and a patterned second liner 35P. The first insulating layer 36, the second liner 35, and the sacrificial layer 33 can be removed until the portion of the first liner 26 extending over the bottom spacer 24 is exposed. In some embodiments, portions of the first insulating layer 36 may remain on the side surfaces of the patterned second liner 35P, such as... Figure 9 As shown.

[0029] Reference Figure 10 A second insulating layer 46 can be formed on the substrate 10. A top spacer 44, a patterned sacrificial layer 33P, and a patterned second liner 35P can be within the second insulating layer 46. The portion of the first insulating layer 36 on the side surface of the patterned second liner 35P and the second insulating layer 46 can be collectively referred to as the insulating layer. The second insulating layer 46 may include an insulating material (e.g., a silicon layer comprising oxides and / or nitrides or a low-dielectric layer). In some embodiments, the second insulating layer 46 and the first insulating layer 36 may include the same material, and the interface between the second insulating layer 46 and the first insulating layer 36 may be invisible. In some embodiments, the upper surface of the second insulating layer 46, the upper surface of the top spacer 44, and the upper surface of the first liner 26 may be coplanar with each other, such as... Figure 10 As shown.

[0030] Reference Figure 11 The portions of the top spacer 44 above the channel region 12, the mask layer 14 above the channel region 12, and the portions of the first liner 26 above the channel region 12 can be removed, thereby forming a top source / drain opening 48 in the second insulating layer 46. A portion of the second insulating layer 46 defines the top source / drain opening 48 above the channel region 12, as... Figure 11 As shown. The top source / drain opening 48 can expose the top spacer 44 and the channel region 12. After the top source / drain opening 48 is formed, the first liner 26 can be retained between the top spacer 44 and the channel region 12 and can separate the top spacer 44 from the channel region 12.

[0031] Reference Figure 12 and Figure 13 The top source / drain region 52 can be formed in the top source / drain opening 48. For simplicity of illustration, Figure 12 Not shown Figure 13 and Figure 14 All components are shown in the diagram. For example, the top source / drain region 52 can be formed by performing an epitaxial growth process using the channel region 12 as a seed layer. The epitaxial growth process for forming the top source / drain region 52 can be performed at high temperatures (e.g., from about 400°C to about 700°C). The top source / drain region 52 can contact the underlying top spacer 44 and the channel region 12. In some embodiments, a third insulating layer 56 can be formed in the top source / drain opening 48 and on the top source / drain region 52. Since the top source / drain region 52 is formed in the top source / drain opening 48, a patterning process for patterning the top source / drain region 52 may not be performed.

[0032] Reference Figure 12 and Figure 14 The bottom source / drain region 22 can be formed in the field isolation layer 11. In some embodiments, the bottom source / drain region 22 can be the upper part of the active region formed on the substrate 10. Therefore, the active region can be on the side surface of the field isolation layer 11, and the field isolation layer 11 can surround the active region. Each channel region 12 can extend longitudinally in a second horizontal direction D2. The second horizontal direction D2 can be parallel to the upper surface of the substrate 10 (e.g., Figure 3 (10u in the text). In some embodiments, the second horizontal direction D2 may be perpendicular to the first horizontal direction D1. In some embodiments, the field isolation layer 11 may surround the bottom source / drain region 22, such as... Figure 12 As shown.

[0033] The contact opening 62 may be formed to extend through the second insulating layer 46. The contact opening 62 may also extend through a portion of the patterned sacrificial layer 33P extending on the field isolation layer 11 and a portion of the patterned second liner 35P extending on the field isolation layer 11. In some embodiments, the portion of the first liner 26 extending on the field isolation layer 11 may be removed when forming the contact opening 62, and the contact opening 62 may expose the field isolation layer 11, such as... Figure 14 As shown. In some embodiments, the portion of the first liner 26 extending on the field isolation layer 11 may not be removed when the contact opening 62 is formed, and the contact opening 62 may expose the portion of the first liner 26 extending on the field isolation layer 11.

[0034] The contact opening 62 may overlap with the field isolation layer 11 and may be spaced apart from the channel region 12 in the second horizontal direction D2. The patterned sacrificial layer 33P may have a first thickness T1 on the side surface of the channel region 12, and may also have a first thickness T1 on the field isolation layer 11, such as... Figure 14 As shown.

[0035] Reference Figure 15 and Figure 16 The patterned sacrificial layer 33P can be removed through the contact opening 62, thereby forming a cavity 64 between the channel region 12 and the second insulating layer 46. For example, etchant for removing the patterned sacrificial layer 33P can be supplied through the contact opening 62. In some embodiments, the cavity 64 may be defined by a first liner 26, a patterned second liner 35P, and a second insulating layer 46.

[0036] Reference Figure 16 Cavity 64 may include a portion extending onto field isolation layer 11. The etchant used to remove the patterned sacrificial layer 33P may not remove the first liner 26 extending over channel region 12, such that channel region 12 can be protected by the first liner 26 when the patterned sacrificial layer 33P is removed. Cavity 64 may have a width equal to the first thickness T1 of the patterned sacrificial layer 33P. Cavity 64 may be connected to contact opening 62.

[0037] Reference Figure 17 , Figure 18 and Figure 19 Gate insulator 72 and gate electrode 74 can be sequentially formed in cavity 64 through contact opening 62. For the sake of illustration, Figure 17 Not shown Figure 18 and Figure 19 All components are shown in the diagram. Each of the gate insulator 72 and the gate electrode 74 can be formed by performing an atomic layer deposition (ALD) process. The gate insulator 72 can be conformally formed in the cavity 64, as shown in the diagram. Figure 18 and Figure 19 As shown. The gate insulator 72 can have a uniform thickness, such as... Figure 18 and Figure 19 As shown. In some embodiments, the gate insulator 72 can be, for example, Figure 18 The cross-sectional view shown surrounds the gate electrode 74. The gate insulator 72 may include silicon oxide and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide).

[0038] Gate electrode 74 may be formed in cavity 64. For example, gate electrode 74 may include a metallic layer (e.g., W, Ti, Cu, and / or Co). Before forming gate electrode 74, first liner 26 may be selectively removed from the side surface of channel region 12. After forming gate electrode 74, a portion of first liner 26 may remain between top spacer 44 and channel region 12.

[0039] Figure 20 yes Figure 18 A magnified view of region C. (Refer to...) Figure 20 The gate electrode 74 may include a work function layer 75 and a metallic electrode 77. The work function layer 75 and the metallic electrode 77 may be sequentially formed on the gate insulator 72. In some embodiments, the work function layer 75 may be formed as follows: Figure 20 The cross-sectional view shown surrounds the metallic electrode 77. The work function layer 75 can be used to adjust the work function of the gate electrode 74 and may include metal nitrides (e.g., TiN, TiAlN, TaAlN), TiAl, TaC, TiC, and / or HfSi. Although Figure 20 The work function layer 75 is shown as a single layer, but it can be multiple stacked layers. The work function layer 75 can have a uniform thickness along the surface of the gate insulator 72, such as... Figure 20 As shown.

[0040] The metallic electrode 77 may comprise a metal (e.g., Al, W, and / or Cu). In some embodiments, the metallic electrode 77 may be formed by repeatedly depositing atomic layers on the surface of the work function layer 75 until the metallic electrode 77 has a second thickness T2. The metallic electrode 77 may include gaps 78 spaced uniformly from the surface of the work function layer 75 at a distance (i.e., the second thickness T2). In some embodiments, the gaps 78 of the metallic electrode 77 may be visible.

[0041] Figure 21 yes Figure 19 A magnified view of region D. (Refer to...) Figure 19 The gate insulator 72 may have portions spaced apart from each other on a third direction D3, and the gate electrode 74 may be formed between these portions of the gate insulator 72. The gap 78 of the metallic electrode 77 may be spaced apart from the work function layer 75 by a uniform distance (i.e., a second thickness T2).

[0042] In some embodiments, the gate insulator 72 and the gate electrode 74 may be formed on the side surface 46s of the defined contact opening 62 of the second insulating layer 46 and then removed.

[0043] For the sake of simplicity in the illustration, Figure 22 It was not shown Figure 23 All components are shown in the image. (Refer to...) Figure 22and Figure 23 The gate electrode 74 may include a self-aligned portion 74s formed on the bottom source / drain region 22 and a field gate portion 74f extending on the field isolation layer 11. A gate contact 82 may be formed in the contact opening 62. The gate contact 82 may overlap with the field isolation layer 11 and may contact the field gate portion 74f of the gate electrode 74. In some embodiments, the gate insulator 72 may be, for example... Figure 22 The plan view shown surrounds the lower part of the gate contact 82, and the lower part of the gate contact 82 can be as follows: Figure 23 As shown in gate electrode 74. Gate contact 82 may include a conductive material (e.g., a doped semiconductor material and / or a metallic material).

[0044] In some implementations, when the VFET device is operating, a gate voltage can be applied to the gate electrode 74 through the gate contact 82. The gate contact 82 can electrically connect the gate electrode 74 to the word line of the VFET device.

[0045] Figures 24 to 28 This is a cross-sectional view illustrating a method for forming a VFET device according to some embodiments of the concept of the present invention. (Refer to...) Figure 24 In some implementations, the gate insulator 72 may be used to form the initial sacrificial layer (e.g., Figure 4 The initial sacrificial layer 32) and the initial second liner (e.g.) Figure 4 The initial second liner 34) is formed before this. (Refer to reference) Figures 4 to 19 The processes described can be performed after the formation of gate insulator 72, thereby forming Figure 25 and Figure 26 The structure shown. Figure 25 and Figure 26 It corresponds to Figure 18 and Figure 19 The view.

[0046] Reference Figure 25 The gate insulator 72 may not surround the gate electrode 74. The gate insulator 72 may be disposed between the channel region 12 and the gate electrode 74, and between the bottom spacer 24 and the gate electrode 74. However, other surfaces of the gate electrode 74 may not have the gate insulator 72. In some embodiments, the first liner 26 may be disposed between the channel region 12 and the gate insulator 72, and on the bottom spacer 24, such as... Figure 25 As shown. (Refer to...) Figure 26 The contact opening 62 may not extend through a portion of the gate insulator 72.

[0047] Figure 27 yes Figure 25 A magnified view of region E. Figure 28 yes Figure 26A magnified view of region F. The gate electrode 74 may include a work function layer 75 and a metallic electrode 77. The work function layer 75 may surround the metallic electrode 77, such as... Figure 27 As shown. The metallic electrode 77 can be formed to have a second thickness T2, and the gap 78 can be formed to be spaced uniformly from the work function layer 75 in the first horizontal direction D1 (e.g., the second thickness T2). Figure 28 As shown, the portion of the metallic electrode 77 extending on the field isolation layer 11 can be formed to have a second thickness T2, and the gap 78 can be formed to be spaced at a uniform distance (e.g., the second thickness T2) from the work function layer 75 in the third direction D3.

[0048] Figures 29 to 33 This is a cross-sectional view illustrating a method for forming a VFET device according to some embodiments of the concept of the present invention. (Refer to...) Figures 29 to 33 Initial sacrifice layer (e.g.) Figure 4 The initial sacrificial layer 32) and the initial second liner (e.g.) Figure 4 The initial second liner 34) can be formed in the first insulating layer (e.g. Figure 5 The first insulating layer 36) is patterned beforehand to form a patterned initial sacrificial layer 32P and a patterned initial second substrate 34P. The initial sacrificial layer and the initial second substrate can be patterned using a mask pattern (e.g., a photoresist pattern) as an etching mask.

[0049] Reference Figure 30 The first insulating layer 36 can be formed on the patterned initial sacrificial layer 32P and the patterned initial second liner 34P. Then, the portion of the patterned initial sacrificial layer 32P above the first insulating layer 36 and the portion of the patterned initial second liner 34P above the first insulating layer 36 can be removed to form the patterned sacrificial layer 33P and the patterned second liner 35P.

[0050] Reference Figures 31 to 33 It can be executed and referenced. Figure 8 , Figure 10 and Figure 11 The processes described are similar to those described. The first insulating layer 36 and the second insulating layer 46 can be sequentially stacked on the bottom spacer 24, as... Figure 33 As shown. The first insulating layer 36 and the second insulating layer 46 can be collectively referred to as insulating layers.

[0051] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and not as having an idealized or overly formal meaning, unless expressly stated herein.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” and / or “containing,” when used in this specification, specify the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0053] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the inventive concept, a first element may be referred to as a second element.

[0054] It should also be noted that in some alternative implementations, the functions / actions mentioned in the flowchart boxes herein may not occur in the order shown in the flowchart. For example, two boxes shown consecutively may be executed substantially simultaneously, or the boxes may sometimes be executed in reverse order, depending on the functions / actions involved. Moreover, the function of a given box in the flowchart and / or block diagram may be divided into multiple boxes, and / or the functions of two or more boxes in the flowchart and / or block diagram may be at least partially integrated. Finally, additional boxes may be added / inserted between the shown boxes, and / or boxes / operations may be omitted without departing from the scope of the inventive concept.

[0055] The subject matter disclosed above is to be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments falling within the actual spirit and scope of the inventive concept. Therefore, to the maximum extent permitted by law, the scope will be determined by the widest permissible interpretation of the following claims and their equivalents, and should not be limited or restricted by the foregoing detailed description.

[0056] This application claims priority to U.S. Provisional Application Serial No. 62 / 913868, filed on October 11, 2019, entitled “Vertical FET Structure with Through-Gate Contact (THROUGH-CB) Replaced Metal Gate and Method of Forming Thereof,” and U.S. Application Serial No. 16 / 794358, filed on February 19, 2020, entitled “Vertical Field-Effect Transistor (VFET) Device and Method of Forming Thereof,” the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A method for forming a vertical field-effect transistor device, the method comprising: An initial vertical field-effect transistor is formed on a substrate, wherein the initial vertical field-effect transistor comprises: The bottom source / drain region on the substrate; The channel region on the bottom source / drain region; A top source / drain region on the channel region, wherein the bottom source / drain region, the channel region, and the top source / drain region are sequentially stacked on the substrate; A patterned sacrificial layer on the side surface of the channel region; and An insulating layer, wherein the top source / drain region and the patterned sacrificial layer are surrounded by the insulating layer; A contact opening is formed extending through the insulating layer, wherein the contact opening exposes a portion of the patterned sacrificial layer, and the contact opening is separated from the channel region by the patterned sacrificial layer and the insulating layer; A cavity is formed between the channel region and the insulating layer by removing the patterned sacrificial layer via the contact opening; and A gate electrode is formed in the cavity.

2. The method of claim 1, further comprising forming a gate contact in the contact opening after forming the gate electrode, wherein the gate contact contacts the gate electrode.

3. The method of claim 2, further comprising forming an active region and a field isolation layer on the substrate. The active region is located on the side surface of the field isolation layer, the channel region is formed on the active region, and the gate contact overlaps with the field isolation layer.

4. The method of claim 1, further comprising forming a gate insulator in the cavity before forming the gate electrode in the cavity, The gate insulator is described in cross-sectional view as surrounding the gate electrode.

5. The method of claim 1, wherein forming the gate electrode comprises sequentially forming a functional layer and a metallic electrode in the cavity. The work function layer surrounds the metallic electrode in the cross-sectional view.

6. The method of claim 1, wherein the initial vertical field-effect transistor further comprises: Top spacers separate the patterned sacrificial layer from the top source / drain regions; and A first liner separates the channel region from the patterned sacrificial layer and the top spacer.

7. The method of claim 6, wherein the first liner comprises a silicon oxide layer.

8. The method of claim 1, wherein forming the initial vertical field-effect transistor comprises: A mask layer is formed on the substrate; The channel region is formed by etching the substrate using the mask layer as an etching mask; A first liner is formed on the side surface of the channel region and extends on the side and top surfaces of the mask layer; And then The patterned sacrificial layer is formed on the lower portion of the side surface of the channel region and a top spacer is formed on the upper portion of the side surface of the channel region, wherein the first liner separates the channel region from the patterned sacrificial layer and the top spacer.

9. The method of claim 1, wherein forming the initial vertical field-effect transistor comprises: The bottom source / drain region and the channel region are formed on the substrate; The patterned sacrificial layer is formed on the side surface of the channel region; A top spacer is formed on the patterned sacrificial layer; The insulating layer is formed on the substrate, wherein the top spacer and the patterned sacrificial layer are surrounded by the insulating layer, and the insulating layer includes a top source / drain opening above the top spacer; as well as The top source / drain region is formed in the top source / drain opening.

10. The method of claim 9, wherein forming the top source / drain region comprises performing an epitaxial growth process using the channel region as a seed layer.

11. The method of claim 10, wherein the top source / drain region contacts a portion of the insulating layer that defines the top source / drain opening.

12. The method of claim 1, further comprising forming an active region and a field isolation layer on the substrate, wherein the active region is on a side surface of the field isolation layer, and the channel region is formed on the active region. The portion of the patterned sacrificial layer overlaps with the field isolation layer.

13. A method for forming a vertical field-effect transistor device, the method comprising: A mask layer is formed on the substrate; The substrate is etched by using the mask layer as an etching mask to form a trench region; A bottom source / drain region is formed on the substrate; A first liner is formed on the side surface of the channel region and extends on the side and top surfaces of the mask layer; A patterned sacrificial layer is formed on the lower part of the side surface of the channel region; A top spacer is formed on the upper part of the side surface of the channel region; An insulating layer is formed on the substrate, wherein the top spacer and the patterned sacrificial layer are surrounded by the insulating layer; By removing a portion of the top spacer and the mask layer, a top source / drain opening is formed in the insulating layer; A top source / drain region is formed in the top source / drain opening; Forming contact openings that extend through the insulating layer, wherein the contact openings expose portions of the patterned sacrificial layer; as well as The gate electrode is formed on the lower portion of the side surface of the channel region by replacing the patterned sacrificial layer with a gate electrode via the contact opening.

14. The method of claim 13, further comprising: An active region and a field isolation layer are formed on the substrate, wherein the active region is surrounded by the field isolation layer, and the channel region is formed on the active region; as well as After the gate electrode is formed, a gate contact is formed in the contact opening, wherein the gate contact contacts the gate electrode and overlaps with the field isolation layer.

15. The method of claim 13, wherein after the gate electrode is formed, the first liner is between the upper portion of the side surface of the channel region and the top spacer.

16. The method of claim 13, wherein forming the gate electrode comprises: A cavity is formed between the channel region and the insulating layer by removing the patterned sacrificial layer via the contact opening; as well as A gate insulator and a gate electrode are sequentially formed in the cavity, wherein the gate insulator surrounds the gate electrode in a cross-sectional view.

17. A method for forming a vertical field-effect transistor device, the method comprising: A vertical field-effect transistor is formed on a substrate, wherein the vertical field-effect transistor comprises: The bottom source / drain region on the substrate; The channel region on the bottom source / drain region; A top source / drain region on the channel region, wherein the bottom source / drain region, the channel region, and the top source / drain region are sequentially stacked on the substrate; A gate electrode on a side surface of the channel region, wherein the gate electrode comprises a work function layer and a metallic electrode sequentially stacked on the side surface of the channel region, and the work function layer surrounds the metallic electrode in a cross-sectional view; and A gate contact, wherein the portion of the gate electrode on the side surface of the channel region is separated from the gate contact by an insulating layer.

18. The method of claim 17, wherein the vertical field-effect transistor further comprises a gate insulator extending between the side surface of the channel region and the gate electrode, and the gate insulator surrounds the gate electrode in the cross-sectional view.

19. The method of claim 17, further comprising: An active region and a field isolation layer are formed on the substrate, wherein the active region is on a side surface of the field isolation layer, the channel region is on the active region, and the gate electrode includes a field gate portion extending on the field isolation layer. as well as The gate contact is formed in the field gate portion that contacts the gate electrode.

20. The method of claim 19, wherein the lower portion of the gate contact is in the field gate portion of the gate electrode.

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