Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device with high reliability. A semiconductor device includes a first oxide, a second oxide over the first oxide, a first insulator over the second oxide, a first conductor over the first insulator, a second conductor over the second oxide, and a third conductor, wherein the second conductor includes a first region and a second region, the third conductor includes a third region and a fourth region, the second region is positioned above the first region, the fourth region is positioned above the third region, the second conductor and the third conductor each contain tantalum and nitrogen, the atomic ratio of nitrogen to tantalum in the first region is higher than the atomic ratio of nitrogen to tantalum in the second region, and the atomic ratio of nitrogen to tantalum in the third region is higher than the atomic ratio of nitrogen to tantalum in the fourth region.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Furthermore, another aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, or storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the aforementioned technical fields. One aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, another aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Background Technology

[0004] The technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. In addition, oxide semiconductors have also garnered attention as other materials.

[0005] In oxide semiconductors, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single crystals nor amorphous, have been discovered (see Non-Patent Literature 1 and Non-Patent Literature 2).

[0006] Non-patent document 1 and non-patent document 2 disclose a technique for manufacturing transistors using an oxide semiconductor having a CAAC structure.

[0007] [Preliminary Technology Documents]

[0008] [Non-patent literature]

[0009] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186

[0010] [Non-Patent Literature 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10 Summary of the Invention

[0011] The technical problem that the invention aims to solve

[0012] One objective of this invention is to provide a semiconductor device with high reliability. Furthermore, one objective of this invention is to provide a semiconductor device with good electrical characteristics. Furthermore, one objective of this invention is to provide a semiconductor device with a large on-state current. Furthermore, one objective of this invention is to provide a semiconductor device that can be miniaturized or highly integrated. Furthermore, one objective of this invention is to provide a semiconductor device with low power consumption.

[0013] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above will be readily apparent from the description in the specification, drawings, claims, etc., and can be extracted from that description.

[0014] means of solving technical problems

[0015] One aspect of the present invention is a semiconductor device comprising a first oxide, a second oxide on the first oxide, a first insulator on the second oxide, a first conductor on the first insulator, a second conductor on the second oxide, and a third conductor, wherein the second conductor comprises a first region and a second region, and the third conductor comprises a third region and a fourth region, the second region being located above the first region, the fourth region being located above the third region, and both the second and third conductors comprising tantalum and nitrogen, wherein the atomic ratio of nitrogen to tantalum in the first region is higher than that in the second region, and the atomic ratio of nitrogen to tantalum in the third region is higher than that in the fourth region.

[0016] In the aforementioned semiconductor device, preferably, the second conductor includes a fifth region in addition to the first and second regions, and the third conductor includes a sixth region in addition to the third and fourth regions. The fifth region is located above the second region, and the sixth region is located above the fourth region. The atomic ratio of nitrogen to tantalum in the fifth region is higher than that in the second region, and the atomic ratio of nitrogen to tantalum in the sixth region is higher than that in the fourth region.

[0017] In the above-described semiconductor device, a second insulator is preferably provided on the second conductor and the third conductor.

[0018] Another aspect of the present invention is a semiconductor device comprising a first oxide, a second oxide on the first oxide, a first insulator on the second oxide, a first conductor on the first insulator, a second and a third conductor on the second oxide, a fourth conductor on the second conductor, and a fifth conductor on the third conductor, wherein the second and third conductors are made of conductive materials having the properties of extracting hydrogen and being resistant to oxidation, and the conductivity of the fourth and fifth conductors is higher than that of the second and third conductors.

[0019] In the aforementioned semiconductor device, it is preferred that both the second conductor and the third conductor contain tantalum and nitrogen.

[0020] In the above-mentioned semiconductor device, it is preferable to provide a second insulator on the fourth conductor and the fifth conductor.

[0021] In the aforementioned semiconductor device, it is preferable that a sixth conductor is disposed on a fourth conductor and a seventh conductor is disposed on a fifth conductor, wherein the sixth and seventh conductors are made of conductive materials that have the properties of extracting hydrogen and are not easily oxidized.

[0022] In the aforementioned semiconductor device, it is preferred that the second conductor, the third conductor, the sixth conductor, and the seventh conductor all contain tantalum and nitrogen.

[0023] In the aforementioned semiconductor device, it is preferable to provide a second insulator on the sixth and seventh conductors.

[0024] In the aforementioned semiconductor device, the first oxide preferably comprises indium, element M (M being aluminum, gallium, yttrium, or tin), and zinc.

[0025] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising an oxide, an insulator, and a conductor. The oxide includes a first oxide, the insulator includes a first insulator in contact with the first oxide, and the conductor includes a first conductor in contact with the insulator, a second conductor in contact with the first oxide, and a third conductor in contact with the first oxide. The manufacturing method includes: a first step of forming a first oxide; a second step of forming a conductive film on the first oxide; a third step of processing the conductive film to form the second and third conductors; and a fourth step of forming a first insulator and a first conductor on the first oxide, the second conductor, and the third conductor. In the second step, the first conductive film and the second conductive film are formed sequentially as conductive films under a nitrogen atmosphere, and the ratio of nitrogen flow rate in the total gas flow rate during the formation of the first conductive film is higher than the ratio of nitrogen flow rate in the total gas flow rate during the formation of the second conductive film.

[0026] In the above-mentioned semiconductor device manufacturing method, sputtering is preferably used to form a conductive film.

[0027] In the above-mentioned semiconductor device manufacturing method, ion sputtering is preferably used to form the conductive film.

[0028] In the above-mentioned method for manufacturing semiconductor devices, it is preferable to use a tantalum target to form a conductive film.

[0029] Invention Effects

[0030] According to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high on-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0031] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not require achieving all of the above-described effects. Effects other than those described above are readily apparent from the description in the specification, drawings, claims, etc., and can be extracted from that description. Attached Figure Description

[0032] Figure 1A This is a top view of a semiconductor device according to one aspect of the present invention. Figures 1B to 1D This is a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0033] Figure 2A and Figure 2BThis is a cross-sectional view of a semiconductor device according to one aspect of the present invention.

[0034] Figure 3A and Figure 3B This is a diagram illustrating the computational model after structural optimization.

[0035] Figure 4A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 4B and Figure 4C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0036] Figure 5A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 5B and Figure 5C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0037] Figure 6A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 6B and Figure 6C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0038] Figure 7A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 7B and Figure 7C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0039] Figure 8A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 8B and Figure 8C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0040] Figure 9A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 9B and Figure 9C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0041] Figure 10A This is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 10B and Figure 10C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0042] Figure 11AThis is a top view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. Figure 11B and Figure 11C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to one aspect of the present invention.

[0043] Figure 12 This is a cross-sectional view showing the structure of a storage device according to one aspect of the present invention.

[0044] Figure 13 This is a cross-sectional view showing the structure of a storage device according to one aspect of the present invention.

[0045] Figure 14A and Figure 14B This is a block diagram illustrating an example of the structure of a storage device according to one aspect of the present invention.

[0046] Figures 15A to 15H This is a circuit diagram illustrating a structural example of a storage device according to one aspect of the present invention.

[0047] Figure 16A and Figure 16B This is a schematic diagram of a semiconductor device according to one aspect of the present invention.

[0048] Figures 17A to 17E This is a schematic diagram of a storage device according to one aspect of the present invention.

[0049] Figures 18A to 18H This is a diagram illustrating an electronic device according to one aspect of the present invention.

[0050] Figures 19A to 19E This is a graph illustrating the results of the XRD spectrum of the sample according to the embodiment.

[0051] Figures 20A to 20E This is a diagram illustrating a cross-sectional STEM image of a sample according to an embodiment.

[0052] Figure 21 This is a graph illustrating the calculated results of the thickness and resistivity of the oxide film and layer of the sample according to the embodiment. Detailed Implementation

[0053] The embodiments will now be described with reference to the accompanying drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0054] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, ideal examples are schematically illustrated in the drawings, and the invention is not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting redundant descriptions. Furthermore, the same shading lines are sometimes used when indicating parts with the same function, without additional reference numerals.

[0055] Furthermore, especially in top views (also known as plan views) or perspective views, descriptions of some constituent elements are sometimes omitted to facilitate understanding of the invention. Additionally, descriptions of some hidden lines, etc., are sometimes omitted.

[0056] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," etc., are added for convenience, but they do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for description. In addition, the ordinal numbers described in this specification and other documents are sometimes inconsistent with the ordinal numbers used to specify one aspect of the present invention.

[0057] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate configuration, referring to the accompanying drawings to illustrate the positional relationships of the constituent elements. Furthermore, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0058] For example, in this specification, when it is explicitly stated as "X and Y are connected," it means the following: X and Y are electrically connected; X and Y are functionally connected; X and Y are directly connected. Therefore, connection relationships other than those shown in the drawings or text are disclosed in the drawings or text, not limited to those specified therein. Here, X and Y refer to objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0059] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as the channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), through which current can flow between the source and the drain. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0060] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may sometimes be interchanged.

[0061] Note that channel length, for example, refers to the distance between the overlapping region of the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor, or between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel-forming region. Furthermore, the channel length in a transistor is not necessarily the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum, minimum, or average value in the channel-forming region.

[0062] The channel width, for example, refers to the length of the region perpendicular to the channel length direction in the overlapping area of ​​the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and the gate electrode in a top view of the transistor. Furthermore, the channel width in a transistor is not necessarily the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value in the channel forming region.

[0063] In this specification, depending on the transistor structure, the actual channel width (hereinafter referred to as "effective channel width") in the region forming the channel sometimes differs from the channel width shown in the top view of the transistor (hereinafter referred to as "apparent channel width"). For example, when the gate electrode covers the side of the semiconductor, the effect cannot be ignored because the effective channel width is greater than the apparent channel width. For example, in miniature transistors where the gate electrode covers the side of the semiconductor, the ratio of channel formation regions formed on the side of the semiconductor is sometimes increased. In this case, the effective channel width is greater than the apparent channel width.

[0064] In the aforementioned situations, it can sometimes be difficult to estimate the effective channel width through actual measurements. For example, estimating the effective channel width based on design values ​​requires the assumption that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is uncertain, it is difficult to accurately determine the effective channel width.

[0065] In this specification, when simply described as "channel width," it sometimes refers to the apparent channel width. Alternatively, in this specification, when simply referred to as "channel width," it sometimes refers to the actual channel width. Note that the values ​​of channel length, channel width, actual channel width, apparent channel width, etc., can be determined by analyzing cross-sectional TEM images, etc.

[0066] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity of the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Additionally, oxygen vacancies can sometimes form in the oxide semiconductor due to the incorporation of impurities.

[0067] Note that in this specification, silicon oxynitride refers to a substance with an oxygen content greater than its nitrogen content. Furthermore, silicon oxynitride refers to a substance with a nitrogen content greater than its oxygen content.

[0068] Note that in this specification, etc., "insulator" may be replaced with "insulating film" or "insulating layer". Additionally, "conductor" may be replaced with "conductive film" or "conductive layer". Furthermore, "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer".

[0069] In this specification, "parallel" refers to a state where the angle between two straight lines is -10 degrees or more and less than 10 degrees. Therefore, it also includes a state where the angle is -5 degrees or more and less than 5 degrees. Furthermore, "approximately parallel" refers to a state where the angle between two straight lines is -30 degrees or more and less than 30 degrees. Additionally, "perpendicular" refers to a state where the angle between two straight lines is 80 degrees or more and less than 100 degrees. Therefore, it also includes a state where the angle is 85 degrees or more and less than 95 degrees. "Approximately perpendicular" refers to a state where the angle between two straight lines is 60 degrees or more and less than 120 degrees.

[0070] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when a metal oxide is used as the semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing either a metal oxide or an oxide semiconductor.

[0071] Note that in this specification, "normally off" means that the drain current flowing through the transistor per channel width of 1 μm is 1 × 10⁻⁶ at room temperature when no gate potential is applied or when a ground potential is applied to the gate. -20 Below A, at 85℃, it is 1×10 -18 Below A, or 1×10 at 125℃ -16 Below A.

[0072] (Implementation Method 1)

[0073] In this embodiment, an example of a semiconductor device including a transistor 200 according to one aspect of the present invention is described.

[0074] <Examples of semiconductor device structures>

[0075] Figures 1A to 1D This is a top view and a cross-sectional view of a semiconductor device including a transistor 200 according to one aspect of the present invention. Figure 1A This is a top view of the semiconductor device. Figures 1B to 1D This is a cross-sectional view of the semiconductor device. Here, Figure 1B It is along Figure 1A The cross-sectional view of the section marked with dotted lines A1-A2 is also a cross-sectional view along the channel length of transistor 200. Additionally, Figure 1C It is along Figure 1A The cross-sectional view of the section marked with dotted lines A3-A4 is also a cross-sectional view of the channel width direction of transistor 200. Additionally, Figure 1D It is along Figure 1A A cross-sectional view of the section marked with dashed lines A5-A6. Figure 1A In the top view, some constituent elements are omitted for clarity.

[0076] One embodiment of the semiconductor device of the present invention includes a transistor 200, and insulators 214, 216, 280, 274, and 281 serving as interlayer films. Additionally, the semiconductor device includes conductors 240 (conductors 240a and 240b) electrically connected to the transistor 200 and serving as a connector. Furthermore, insulators 241 (insulators 241a and 241b) are disposed in contact with the side surfaces of the conductors 240 serving as connectors.

[0077] [Transistor 200]

[0078] like Figures 1A to 1D As shown, transistor 200 is disposed on a substrate (not shown) and includes a conductor 205 buried in an insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, an insulator 224 disposed on the insulator 222, oxides 230 (oxides 230a, 230b, and 230c) disposed on the insulator 224, an insulator 250 disposed on the oxide 230c, and a conductor 260 disposed on the insulator 250. (Conductor 260a and conductor 260b), conductor 242a (conductor 242a1 and conductor 242a2) and conductor 242b (conductor 242b1 and conductor 242b2) in contact with a portion of the top surface of oxide 230b, and insulator 254 in contact with a portion of the top surface of insulator 224, the side surface of oxide 230a, the side surface of oxide 230b, the side surface and top surface of conductor 242a, and the side surface and top surface of conductor 242b.

[0079] Oxide 230 preferably includes oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b, at least a portion of which is in contact with the top surface of oxide 230b. When oxide 230a is disposed under oxide 230b, the diffusion of impurities from the structure formed under oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed on oxide 230b, the diffusion of impurities from the structure formed above oxide 230c to oxide 230b can be suppressed.

[0080] In transistor 200, oxide 230 is stacked with three layers: oxide 230a, oxide 230b, and oxide 230c. However, the present invention is not limited to this. For example, oxide 230 may also have a single-layer structure of oxide 230b, a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers. Furthermore, each of oxide 230a, oxide 230b, and oxide 230c may also have a stacked structure.

[0081] Conductors 242a (conductor 242a1 and conductor 242a2) and conductor 242b (conductor 242b1 and conductor 242b2) are disposed on oxide 230b.

[0082] Conductor 260 is used as the first gate (also called top gate) electrode of transistor 200, and conductors 242a and 242b are used as the source electrode or drain electrode of transistor 200, respectively.

[0083] Figure 2A Show Figure 1B An enlarged view of the area surrounded by the dotted line. (See example...) Figure 2A As shown, oxide 230 includes region 234, which is used as a channel forming region of transistor 200, and region 231 (regions 231a and 231b), which are used as source or drain regions.

[0084] Although Figure 2A The structure of regions 231 and 234 formed in oxide 230b is shown, but is not limited thereto. For example, regions 231 or 234 may be formed in oxides 230a and 230b, or in oxides 230b and 230c, or in oxides 230a, 230b and 230c.

[0085] In addition, Figure 2A In this embodiment, the boundary between regions 231 and 234 is approximately perpendicular to the top surface of oxide 230b, but this embodiment is not limited to this. For example, region 234 may sometimes have the following shape: protruding toward the conductor 240 near the surface of oxide 230b and narrowing near the bottom surface of oxide 230b.

[0086] Preferably, in transistor 200, the metal oxide (hereinafter also referred to as oxide semiconductor) used as a semiconductor is used in oxide 230 including the channel formation region. By using oxide semiconductor in the channel formation region of the transistor, a transistor with high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized.

[0087] As the aforementioned metal oxide, a metal oxide with a band gap of 2.0 eV or more is preferred, and a metal oxide with a band gap of 2.5 eV or more is more preferable. Thus, by using a metal oxide with a wider band gap in oxide 230, the off-state current of the transistor can be reduced. By employing such a transistor, a low-power semiconductor device can be provided.

[0088] Since the transistor 200, which uses oxide semiconductors in the channel formation region, has extremely low leakage current in the non-conducting state, it can provide a low-power semiconductor device. Furthermore, since oxide semiconductors can be formed using methods such as sputtering, they can be used to construct transistors 200 that form highly integrated semiconductor devices.

[0089] For example, as oxide 230, an In-M-Zn oxide containing indium (In), element M, and zinc (Zn) is preferably used (element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). In particular, aluminum, gallium, yttrium, or tin is preferably used as element M. Furthermore, In-M oxide, In-Zn oxide, and M-Zn oxide can also be used as oxide 230.

[0090] Metal oxides with low carrier concentrations are preferably used in transistors. To reduce the carrier concentration of the metal oxide, the impurity concentration in the metal oxide is reduced to lower the defect state density. In this specification, the state with low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0091] In particular, hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies in the metal oxide. When oxygen vacancies are present in the channel formation region of the metal oxide, the transistor sometimes exhibits always-on characteristics. Furthermore, sometimes oxygen vacancies containing hydrogen are used as donors, generating electrons as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to have always-on characteristics.

[0092] Therefore, when using metal oxides in oxide 230, it is preferable to minimize the amount of hydrogen in the metal oxide. Specifically, in the metal oxide, the hydrogen concentration, as measured by secondary ion mass spectrometry (SIMS), is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3By using metal oxides with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0093] Furthermore, when a metal oxide is used for oxide 230, when conductors 242 (conductors 242a and 242b) come into contact with oxide 230, oxygen from oxide 230 sometimes diffuses into conductor 242, thereby oxidizing conductor 242. When conductor 242 is oxidized, the conductivity of conductor 242 is likely to decrease. This phenomenon of oxygen from oxide 230 diffusing into conductor 242 can be described as conductor 242 absorbing oxygen from oxide 230.

[0094] Furthermore, when oxygen in oxide 230 diffuses into conductor 242 (conductors 242a and 242b), another layer sometimes forms between conductor 242a and oxide 230b, and between conductor 242b and oxide 230b. This other layer contains more oxygen than conductor 242, and therefore can be considered to have insulating properties. Here, the three-layer structure of conductor 242, this other layer, and oxide 230b can be regarded as a three-layer structure composed of metal-insulator-semiconductor, sometimes referred to as a MIS (Metal-Insulator-Semiconductor) structure.

[0095] Note that the aforementioned additional layer is not limited to being formed between conductor 242 and oxide 230b. For example, sometimes the aforementioned additional layer is formed between conductor 242 and oxide 230c, or between conductor 242 and oxide 230b and between conductor 242 and oxide 230c.

[0096] Furthermore, when oxygen diffuses from oxide 230 to conductor 242, an oxygen-deficient region may sometimes form between another layer and oxide 230b or in oxide 230b near another layer. This region contains multiple oxygen vacancies. In this region, impurities (such as hydrogen) entering the oxygen vacancies are used as donors, increasing the carrier concentration, and sometimes partially forming a low-resistance region.

[0097] Note that regions 231a and 231b both include at least a portion of the aforementioned regions. Therefore, region 231 is a low-resistivity region with high carrier concentration. Region 234 is a region with a lower carrier concentration than region 231.

[0098] The greater the thickness of the other layer, the higher the likelihood that carrier movement between the conductor 242 and the oxide 230 will be suppressed. Furthermore, the greater the thickness of this other layer, the larger the region of oxygen-deficient states becomes. Therefore, the possibility of non-uniformity in transistor electrical characteristics or a decrease in transistor reliability is higher.

[0099] Therefore, the conductor 242 (conductor 242a and conductor 242b) preferably has a stacked structure of two or more layers. For example, such as Figure 1B and Figure 2A As shown, the conductor 242 preferably has the following two-layer stacked structure: conductor 242a1 and conductor 242b1 are disposed on the side in contact with oxide 230b, and conductor 242a2 and conductor 242b2 are disposed on conductor 242a1 and conductor 242b1 respectively.

[0100] The lower layer of conductor 242 (conductors 242a1 and 242b1) is preferably made of a conductive material that readily absorbs (extracts) hydrogen and is not easily oxidized. Furthermore, the lower layer of conductor 242 is more preferably made of a conductive material that readily diffuses hydrogen from oxide 230 into this layer and does not readily diffuse oxygen from oxide 230 into this layer. This allows hydrogen from oxide 230 to diffuse into this layer, reducing the hydrogen concentration of oxide 230 and enabling the transistor 200 to have stable electrical characteristics. Furthermore, oxidation of conductor 242, which would otherwise decrease its conductivity, can be suppressed.

[0101] The upper layer of conductor 242 (conductors 242a2 and 242b2) is preferably made of a conductive material with higher conductivity than the lower layer of conductor 242 (conductors 242a1 and 242b1). Alternatively, the upper layer of conductor 242 is preferably made of a conductive material with lower resistivity than the lower layer of conductor 242. This allows for the manufacture of a semiconductor device in which wiring delay is suppressed.

[0102] Furthermore, the upper layer of conductor 242 can have the characteristic of readily absorbing hydrogen. Consequently, the hydrogen absorbed by the lower layer of conductor 242 diffuses back to the upper layer of conductor 242, further reducing the hydrogen concentration in oxide 230. Therefore, transistor 200 can possess stable electrical characteristics.

[0103] Here, conductive materials with the same constituent elements but different chemical compositions are preferably used as the lower layer (conductor 242a1 and conductor 242b1) and the upper layer (conductor 242a2 and conductor 242b2) of conductor 242. In this case, the lower and upper layers of conductor 242 can be continuously formed without exposure to the atmospheric environment. By forming a film without exposure to the atmospheric environment, impurities or moisture from the atmospheric environment can be prevented from adhering to the surface of the lower layer of conductor 242, thereby maintaining the cleanliness of the area near the interface between the lower and upper layers of conductor 242.

[0104] As the aforementioned conductive material, conductive metal nitrides are preferably used, for example. Examples of such metal nitrides include tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, tantalum and aluminum nitrides, and titanium and aluminum nitrides. In one aspect of the invention, tantalum nitrides are particularly preferred. The tantalum nitride preferably satisfies the composition TaNx (x is a real number greater than 0 and less than 1.67). Furthermore, tantalum nitrides may also contain oxygen. Thus, tantalum nitrides include metallic tantalum, tantalum nitride, tantalum oxynitride, tantalum oxynitride, etc.

[0105] By reducing the atomic ratio of nitrogen to tantalum in the tantalum-containing nitride, the resistivity of the nitride can be reduced. Therefore, it is preferable to use this nitride as the upper layer of the conductor 242. This allows the fabrication of a semiconductor device with suppressed wiring delay.

[0106] Furthermore, by increasing the atomic ratio of nitrogen to tantalum in the tantalum-containing nitride, the oxidation of the nitride can be suppressed. In addition, the oxidation resistance of the nitride can be improved. Furthermore, oxygen diffusion into the nitride can be suppressed. Therefore, it is preferable to use this nitride as the lower layer of the conductor 242. This prevents the formation of another layer between the lower layer of the conductor 242 and the oxide 230, or reduces the thickness of the other layer. The oxidation resistance of this nitride will be explained later.

[0107] Since tantalum-containing nitrides are conductive materials that readily absorb hydrogen (hydrogen diffuses easily), they are suitable for conductor 242. By using tantalum-containing nitrides in conductor 242, hydrogen in oxide 230 can diffuse into conductor 242 during heat treatment in a process following the formation of the conductive film that will become conductor 242, thereby reducing the hydrogen concentration in oxide 230. Furthermore, the formation of another layer between conductor 242 and oxide 230 can be prevented, or the thickness of the other layer can be suppressed. Moreover, even during heat treatment, the extraction of oxygen from oxide 230b can be suppressed, thus giving transistor 200 stability against the high temperatures (so-called thermal budget) in the manufacturing process.

[0108] Furthermore, by using a tantalum-containing nitride in the conductor 242, hydrogen in the oxide 230 diffuses from region 231 of the oxide 230 to the conductor 242, thereby reducing the hydrogen concentration in region 231. When the hydrogen concentration in region 231 decreases, hydrogen in region 234 diffuses into region 231. Additionally, sometimes hydrogen in region 234 diffuses into the conductor 242 through oxide 230c. This further reduces the hydrogen concentration in region 234.

[0109] Furthermore, the aforementioned oxygen-deficient region contains multiple oxygen vacancies. In oxide 230 containing metal oxides, hydrogen in oxygen vacancies tends to diffuse less readily than hydrogen bonded to oxygen atoms or hydrogen present between crystal lattice elements. Therefore, region 231, which includes the oxygen-deficient region, contains more hydrogen that is less prone to diffusion than region 234. In other words, hydrogen in region 234 diffuses more readily to the conductor 242 than hydrogen in region 231. Consequently, the hydrogen concentration in region 234 is sometimes lower than that in region 231.

[0110] Note that sometimes hydrogen diffused into conductor 242 remains within conductor 242. In other words, sometimes hydrogen in oxide 230 is absorbed by conductor 242. In particular, when hydrogen diffuses into tantalum-containing nitrides with a high nitrogen atom ratio relative to tantalum, the hydrogen bonds with nitrogen and sometimes tends to remain in the nitride. Furthermore, sometimes hydrogen in oxide 230 is released through conductor 242 to the exterior of structures or transistor 200 disposed around conductor 242.

[0111] This reduces the hydrogen concentration in oxide 230, thus enabling transistor 200 to possess good electrical characteristics and reliability.

[0112] Note that in conductor 242, the boundary between the upper and lower layers can sometimes be difficult to clearly observe. When a tantalum-containing nitride is used in conductor 242, the concentrations of tantalum and nitrogen detected in each layer do not necessarily need to vary in stages for each layer; they can also vary gradually in the region between the upper and lower layers (also known as gradation). That is, in conductor 242, the closer the region is to region 231, the higher the atomic ratio of nitrogen relative to tantalum. Therefore, the atomic ratio of nitrogen relative to tantalum in the region below conductor 242 is preferably higher than that in the region above conductor 242.

[0113] In addition, an example is shown here in which the lower layer (conductor 242a1 and conductor 242b1) and the upper layer (conductor 242a2 and conductor 242b2) of conductor 242 are made of conductive materials with the same constituent elements but different chemical compositions. However, it is not limited to this, and the lower layer and the upper layer of conductor 242 may also be formed of different conductive materials.

[0114] In addition, such as Figure 2BAs shown, the conductor 242 can also have the following three-layer stacked structure: a conductor 242a1 and a conductor 242b1 are provided on the side in contact with the oxide 230b, a conductor 242a2 and a conductor 242b2 are respectively provided on the conductor 242a1 and the conductor 242b1, and a conductor 242a3 and a conductor 242b3 are respectively provided on the conductor 242a2 and the conductor 242b2.

[0115] Similar to conductors 242a1 and 242b1, conductors 242a3 and 242b3 are preferably made of a conductive material that readily absorbs (extracts) hydrogen and is not easily oxidized. Furthermore, it is preferable to use a tantalum-containing nitride with a higher ratio of nitrogen atoms to tantalum atoms compared to conductors 242a2 and 242b2. This suppresses oxidation of conductor 242 caused by oxygen in the oxide located above it.

[0116] In addition, the conductor 242 may be made of a conductive material that has the property that hydrogen in the oxide 230 can easily diffuse into the conductor 242, and another layer may be formed between the conductor 242 and the oxide 230.

[0117] By using a tantalum-containing nitride in the conductor 242, a thin additional layer can be formed. Specifically, the thickness of the additional layer is preferably 0.1 nm or more and 4 nm or less, more preferably 0.5 nm or more and 3 nm or less. As a result, hydrogen in the oxide 230 diffuses into the conductor 242 through the additional layer, thereby reducing the hydrogen concentration in region 234.

[0118] For example, the thickness of the other layer can be defined as the difference between the position of the interface between the other layer and oxide 230b and the position of the interface between the bottom surface of conductor 242a (conductor 242b) and the other layer. In this case, the thickness of the other layer can sometimes be determined by observing the cross-sectional shape of the other layer and its surroundings using a transmission electron microscope (TEM).

[0119] Furthermore, the thickness of the aforementioned other layer can sometimes be calculated by performing linear analysis of the composition of the other layer and its surroundings using energy dispersive X-ray diffraction (EDX). As a method for calculating the thickness of the other layer, firstly, linear analysis of the other layer and its surroundings using EDX is performed with the stacking direction of conductor 242, the other layer, and oxide 230b (e.g., the direction perpendicular to the substrate surface) as the depth direction. Next, in the distribution of quantitative values ​​for each element in the depth direction obtained through the above analysis, the depth (position) of the interface between the other layer and oxide 230b is half the quantitative value of the metal that is the main component of oxide 230b and a non-main component of conductor 242a (conductor 242b). Furthermore, the depth (position) of the interface between the bottom surface of conductor 242a (conductor 242b) and the other layer is half the quantitative value of oxygen in oxide 230b. Thus, the thickness of the aforementioned other layer can be calculated.

[0120] Furthermore, since the other layer contains tantalum and oxygen, it sometimes possesses insulating properties. In this case, the conductor 242, the other layer, and the oxide 230 form a MIS structure. By employing this structure, the conductor 242 and the oxide 230 do not come into contact, thereby suppressing the degradation of the interface between the conductor 242 and the oxide 230 due to heat treatment. Moreover, because the other layer is thin, current can easily flow between the conductor 242 and the oxide 230, thereby improving the reliability of the transistor.

[0121] Furthermore, when the hydrogen permeability of the other layer is low, for example, hydrogen in region 234 may sometimes diffuse to conductor 242 through oxide 230c and insulator 254, or through oxide 230c, insulator 280, and insulator 254. In other words, the conductive material constituting conductor 242 preferably has the characteristic of extracting hydrogen from oxide 230, in addition to the characteristic of extracting hydrogen from at least one structure disposed around conductor 242. This can sometimes reduce the hydrogen concentration in region 234.

[0122] Furthermore, in order to reduce the hydrogen concentration of oxide 230 and suppress the formation of another layer between conductor 242 and oxide 230, it is preferable that conductor 242 is made of a conductive material having the characteristic that hydrogen in oxide 230 can easily diffuse into conductor 242, and that a layer having the function of suppressing oxidation of conductor 242 is provided between conductor 242 and oxide 230. By providing this layer, conductor 242 and oxide 230 do not come into contact, thereby suppressing the absorption of oxygen from oxide 230 by conductor 242.

[0123] For example, it is preferable to place an oxide that inhibits oxygen permeation between the conductor 242 (conductor 242a and conductor 242b) and the oxide 230b. By placing an oxide that inhibits oxygen permeation between the conductor 242, which is used as a source electrode or drain electrode, and the oxide 230b, the resistance between the conductor 242 and the oxide 230b can be reduced, which is therefore preferred. By adopting this structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0124] As the aforementioned oxide, a metal oxide containing element M can also be used. In particular, aluminum, gallium, yttrium, or tin is preferably used as element M. The concentration of element M in the aforementioned oxide is preferably higher than that in oxide 230b. Furthermore, gallium oxide can also be used as the aforementioned oxide. In addition, metal oxides such as In-M-Zn oxide can also be used as the aforementioned oxide. Specifically, the atomic ratio of element M relative to In in the metal oxide used for the aforementioned oxide is preferably greater than the atomic ratio of element M relative to In in the metal oxide used for oxide 230b. Furthermore, the thickness of the aforementioned oxide is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. Furthermore, the aforementioned oxide is preferably crystalline. When the aforementioned oxide is crystalline, the release of oxygen in oxide 230 can be effectively suppressed. For example, when the aforementioned oxide has a hexagonal crystal structure or the like, the release of oxygen in oxide 230 can sometimes be suppressed.

[0125] When the above-mentioned oxide is provided, it is preferable that the upper layer (conductor 242a2 and conductor 242b2) of conductor 242 is made of a conductive material that has the characteristics of easily absorbing hydrogen and not easily oxidizing, and that the lower layer (conductor 242a1 and conductor 242b1) of conductor 242 is made of a conductive material with higher conductivity than the upper layer of conductor 242.

[0126] By adopting the above structure, the hydrogen concentration of oxide 230 can be reduced. Therefore, transistor 200 can have good electrical characteristics and reliability.

[0127] Therefore, a highly reliable semiconductor device can be provided. Furthermore, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device that can be miniaturized or highly integrated can be provided. Furthermore, a semiconductor device with low power consumption can be provided.

[0128] <Oxidation resistance of tantalum-containing nitrides>

[0129] The following section discusses nitrides containing tantalum (TaN). xThe oxidation resistance of the nitride with different compositions (x) will be explained. Here, the oxidation resistance of the nitride will be evaluated based on the ease with which oxygen atoms are present in the nitride. Specifically, the ease with which oxygen atoms are present in the nitride will be evaluated by calculating the formation energy.

[0130] In this calculation, six calculation models (crystallization model of tantalum nitride and crystallization model of metallic tantalum (Ta)) are prepared as shown in Table 1. Here, tantalum nitride with a chemical composition of tantalum and nitrogen of A:B is denoted as Ta. A N B Alternatively, tantalum nitride with a nitrogen atom ratio of x to tantalum is denoted as TaN. x Note that the value of x is equal to the value of B / A.

[0131] [Table 1]

[0132]

[0133] The number of atoms shown in Table 1 represents the number of each element included in each computational model. Furthermore, the k-point grid shown in Table 1 is the k-point grid set when performing calculations using each model.

[0134] Next, an oxygen atom is added to the interlattice sites of each computational model shown in Table 1, and the structure of each model is optimized using first-principles calculations. Then, the total energy E(TaN) of each model after structure optimization is derived. x :O int Table 2 shows the calculation conditions. VASP (Vienna Ab initio Simulation Package) was used as the software. The PBE (Perdew-Burke-Ernzerhof) type generalized gradient approximation (GGA) was used as the exchange-correlation functional, and the PAW (Projector Augmented Wave) method was used as the ion pseudopotential. The cutoff energy was set to 800 eV.

[0135] [Table 2]

[0136] software VASP functional GGA-PBE pseudopotential PAW Cut-off energy 800eV The overall charge of the system neutral

[0137] Formation energy (E) in each calculation model form (O int E can be calculated using the following formula (1). It can be assumed that: E form (O int The larger the value of E, the less likely oxygen atoms are to exist at interlattice sites in this computational model. In other words, it can be considered that: E form (Oint The higher the value of ), the higher the oxidation resistance.

[0138] [Equation 1]

[0139] E form (O int )=E(TaN x :O int )-E(TaN x )-μ(O) (1)

[0140] In the above formula, E(TaN) x ) refers to the total energy of the computational model without adding oxygen atoms to the interlattice sites, and μ(O) refers to the chemical potential of the oxygen atom. Here, the value of μ(O) is half the value of the total energy of the oxygen molecule.

[0141] Table 3 shows the formation energy (E) of each computational model calculated using formula (1). form (O int )).

[0142] [Table 3]

[0143]

[0144] According to Table 3, the E in the crystallization model of tantalum nitride form (O int The value of ) is greater than E in the crystallization model of tantalum metal. form (O int The value of ) is given. Therefore, nitrides containing tantalum can be considered to have oxidation resistance.

[0145] Figure 3A and Figure 3B The computational model after structural optimization is shown. Figure 3A The diagram shows the configuration of the oxygen atom and its surrounding atoms after structural optimization of a crystal model of tantalum nitride (TaN) with an additional oxygen atom. Figure 3B The diagram shows the configuration of the oxygen atom and its surrounding atoms after structural optimization of a crystal model of tantalum nitride (Ta3N5) with an additional oxygen atom.

[0146] according to Figure 3A In the crystallization model of tantalum nitride (TaN), a short distance was observed between oxygen and tantalum atoms, while a long distance was observed between oxygen and nitrogen atoms. This suggests that a bond has formed between oxygen and tantalum atoms. Furthermore, according to... Figure 3B It can be assumed that, similar to the crystallization model of tantalum nitride (TaN), the crystallization model of tantalum nitride (Ta3N5) also involves the formation of bonds between oxygen atoms and tantalum atoms.

[0147] Therefore, it can be assumed that the oxygen atom in the tantalum-containing nitride forms a bond with the tantalum atom.

[0148] <Detailed Structure of Semiconductor Devices>

[0149] The detailed structure of a semiconductor device including a transistor 200 according to one aspect of the present invention will now be described.

[0150] The insulator 214 is preferably used as an insulating barrier film to suppress the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. Therefore, the insulator 214 is preferably an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0151] In this specification, "the function of inhibiting the diffusion of impurities or oxygen" refers to the function of inhibiting the diffusion of any one or all of the aforementioned impurities or oxygen. Furthermore, membranes with the function of inhibiting the diffusion of hydrogen or oxygen are sometimes referred to as membranes that are not easily permeable to hydrogen or oxygen, membranes with low hydrogen or oxygen permeability, membranes that block hydrogen or oxygen, or barrier membranes for hydrogen or oxygen. Additionally, when the barrier membrane is conductive, it is sometimes referred to as a conductive barrier membrane.

[0152] For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. This suppresses the diffusion of impurities such as water and hydrogen from the side closer to the substrate than the insulator 214 to the transistor 200 side. Furthermore, it suppresses the diffusion of oxygen contained in the insulator 224, etc., to the side closer to the substrate than the insulator 214. Moreover, the insulator 214 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material; a stacked structure formed of different materials can also be used. For example, a stack of aluminum oxide and silicon nitride can be used.

[0153] For example, silicon nitride formed by sputtering is preferably used as the insulator 214. This reduces the hydrogen concentration in the insulator 214 and suppresses the diffusion of impurities such as water and hydrogen from the side closer to the substrate than the insulator 214 to the transistor 200 side.

[0154] The dielectric constant of the insulator 216, which is used as the interlayer film, is preferably lower than that of the insulator 214. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen added, and porous silicon oxide are suitable as insulator 216.

[0155] Furthermore, the insulator 216 preferably includes a region with a low hydrogen concentration and an excess of oxygen compared to the stoichiometric composition (hereinafter also referred to as "excess oxygen region") or contains oxygen removed by heating (hereinafter also referred to as "excess oxygen"). For example, silicon oxide formed by sputtering is preferably used as the insulator 216. This suppresses hydrogen incorporation into the oxide 230, or supplies oxygen to the oxide 230 to reduce oxygen vacancies. Therefore, a transistor with improved reliability can be provided while suppressing variations in electrical characteristics to achieve stable electrical properties.

[0156] Furthermore, the insulator 216 may also have a laminated structure. For example, it may be possible to use a structure identical to that of the insulator 214, where at least the portion of the insulator 216 in contact with the side of the conductor 205 is provided. By employing this structure, oxygen oxidation of the conductor 205 contained within the insulator 216 can be suppressed. Alternatively, the reduction in the amount of oxygen contained within the insulator 216 due to the conductor 205 can be suppressed.

[0157] Conductor 205 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential supplied to conductor 205 without linking it to the potential supplied to conductor 260. In particular, by supplying a negative potential to conductor 205, the Vth of transistor 200 can be increased and the off-state current can be reduced. Therefore, compared with not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential supplied to conductor 260 is 0V.

[0158] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Alternatively, the conductor 205 is preferably disposed within the insulator 214 or the insulator 216.

[0159] In addition, such as Figure 1B As shown, the conductor 205 is preferably larger than the channel formation region of the oxide 230. In particular, as Figure 1C As shown, conductor 205 preferably extends to the region outside the end of oxide 230 that intersects the channel width direction. That is, conductor 205 and conductor 260 preferably overlap with an insulator on the outer side of the side of oxide 230 in the channel width direction. Alternatively, by providing a larger conductor 205, localized charging (also known as charge up) can sometimes be mitigated during plasma processing in manufacturing steps after the formation of conductor 205. Note that one aspect of the invention is not limited to this. Conductor 205 overlaps at least with oxide 230 located between conductors 242a and 242b.

[0160] With the above structure, a region can be formed around the channel of oxide 230 by the electric field of the conductor 260 used as the first gate and the electric field of the conductor 205 used as the second gate.

[0161] In addition, such as Figure 1D As shown, the side surface and periphery of the oxide 230b, which contacts the conductors 242a and 242b used as source and drain electrodes, are in contact with the insulator 254. When an oxide is used as the insulator 254, oxygen in the insulator 254 is sometimes supplied to the aforementioned side surface and periphery. Alternatively, oxygen in the aforementioned side surface and periphery is sometimes prevented from diffusing into the insulator 254. Therefore, the aforementioned side surface and periphery may become Type I, the same as the channel forming region. In this specification, Type I can be considered the same as the aforementioned high-purity intrinsic property.

[0162] In this specification, a transistor structure having a channel-forming region formed by the electric fields of the first and second gates, and the sides and periphery of the oxide 230 in contact with the conductors 242a and 242b used as source and drain electrodes having the same type I characteristics as the channel-forming region, is referred to as a surrounded channel (S-channel) structure. Note that the S-channel structure disclosed in this specification differs from the Fin-type structure and the planar structure. By employing the S-channel structure, transistors with improved tolerance to short-channel effects can be realized; in other words, transistors that are less prone to short-channel effects can be realized.

[0163] In addition, such as Figure 1C As shown, conductor 205 is extended for use as wiring. However, the invention is not limited to this; conductors used for wiring may also be provided under conductor 205. Furthermore, it is not necessary to provide a conductor 205 in each transistor. For example, conductor 205 can be shared among multiple transistors.

[0164] Although a first conductor and a second conductor of conductor 205 are stacked in transistor 200, the present invention is not limited thereto. For example, conductor 205 may also have a single-layer structure or a stacked structure of three or more layers. In addition, when the structure has a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for differentiation.

[0165] Here, as the first conductor of conductor 205, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0166] When a conductive material with the function of inhibiting oxygen diffusion is used as the first conductor of conductor 205, the oxidation of the second conductor of conductor 205, which would otherwise lead to a decrease in conductivity, can be prevented. For example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used as the conductive material with the function of inhibiting oxygen diffusion. Therefore, a single layer or a stack of the above-mentioned conductive materials can be used as the first conductor of conductor 205. For example, the first conductor of conductor 205 can be a stack of tantalum, tantalum nitride, ruthenium, or ruthenium oxide with titanium or titanium nitride.

[0167] Furthermore, as the second conductor of conductor 205, a conductive material with tungsten, copper, or aluminum as its main components is preferably used. In the accompanying drawings, the second conductor of conductor 205 is illustrated as a single layer, but the second conductor of conductor 205 may also have a multilayer structure, for example, it may be a multilayer of titanium or titanium nitride with the aforementioned conductive material.

[0168] Insulators 222 and 224 are used as gate insulators.

[0169] Insulator 222 preferably has the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, insulator 222 preferably has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, compared to insulator 224, insulator 222 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen.

[0170] The insulator 222 is preferably an insulator containing one or both of aluminum and hafnium as the insulating material. Aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as this insulator. When this material is used to form the insulator 222, the insulator 222 serves as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inner side of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. Furthermore, the reaction between the conductor 205 and the oxygen contained in the insulator 224 or the oxide 230 can be suppressed.

[0171] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Furthermore, the insulator may be nitrided. Additionally, silicon oxide, silicon oxynitride, or silicon nitride may be laminated onto the insulator 222.

[0172] Furthermore, as the insulator 222, insulators comprising so-called high-k materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST) can be used, either as a single layer or in a stack. When miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0173] The insulator 224 in contact with the oxide 230 is preferably heated to remove oxygen. For example, silicon oxide, silicon oxynitride, etc., can be appropriately used as the insulator 224. By providing an oxygen-containing insulator in a manner that contacts the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0174] Specifically, as the insulator 224, an oxide material that allows a portion of the oxygen to be removed by heating is preferably used. An oxide film that allows oxygen to be removed by heating refers to an oxide film in which the amount of oxygen molecules removed by TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10⁻⁶. 18 molecules / cm 3 The preferred value is 1.0 × 10⁴. 19 molecules / cm 3 The above is further preferred to be 2.0×10 19 molecules / cm 3 Above, or 3.0 × 10 20 molecules / cm 3 The above-mentioned oxide film. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0175] Additionally, it is preferable that the insulator 224 has a low hydrogen concentration and that the insulator 224 includes or contains excess oxygen regions, for example, it can be formed using the same material as the insulator 216.

[0176] Alternatively, insulators 222 and 224 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0177] Oxide 230 preferably has a stacked structure of oxides with different chemical compositions. Specifically, the atomic ratio of element M relative to the main metal element in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Furthermore, the atomic ratio of element M relative to In in the metal oxide used for oxide 230a is preferably greater than that in the metal oxide used for oxide 230b. Additionally, the atomic ratio of In relative to element M in the metal oxide used for oxide 230b is preferably greater than that in the metal oxide used for oxide 230a. Furthermore, oxide 230c can use a metal oxide that can be used for either oxide 230a or oxide 230b.

[0178] Furthermore, oxides 230b and 230c preferably have crystallinity. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, the extraction of oxygen from oxide 230b from the source electrode or drain electrode can be suppressed. Thus, even with heat treatment, the extraction of oxygen from oxide 230b can be reduced, and the transistor 200 has stability against the high temperatures (so-called thermal budget) in the manufacturing process.

[0179] Furthermore, CAAC-OS is preferably used as oxide 230c, and the c-axis of the crystals contained in oxide 230c is preferably oriented in a direction substantially perpendicular to the formed surface or top surface of oxide 230c. CAAC-OS has the characteristic of readily moving oxygen in a direction perpendicular to the c-axis. Therefore, the oxygen contained in oxide 230c can be supplied to oxide 230b with high efficiency.

[0180] Preferably, the conduction band bottoms of oxides 230a and 230c are closer to the vacuum level than the conduction band bottom of oxide 230b. In other words, the electron affinity of oxides 230a and 230c is preferably lower than that of oxide 230b. In this case, oxide 230c is preferably a metal oxide that can be used for oxide 230a. At this time, the dominant carrier pathway is oxide 230b.

[0181] Here, at the junction of oxides 230a, 230b, and 230c, the conduction band bottom changes gradually. In other words, the above situation can also be expressed as the conduction band bottom at the junction of oxides 230a, 230b, and 230c changing continuously or continuously joined. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxides 230a and 230b, and at the interface between oxides 230b and 230c.

[0182] Specifically, by including common elements as main components other than oxygen in oxides 230a and 230b, and in oxides 230b and 230c, a mixed layer with low defect state density can be formed. For example, when oxide 230b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can be used as oxides 230a and 230c.

[0183] Specifically, for oxide 230a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or 1:1:0.5 (atomic ratio) can be used. Furthermore, for oxide 230b, a metal oxide with an In:Ga:Zn ratio of 1:1:1 or 4:2:3 (atomic ratio) can be used. Furthermore, for oxide 230c, a metal oxide with an In:Ga:Zn ratio of 1:3:4, 4:2:3, 2:1, or 2:5 (atomic ratio) can be used.

[0184] Note that when metal oxides are formed by sputtering, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, but can also refer to the atomic ratio of the sputtering target used in the formation of the metal oxide.

[0185] By equipping oxides 230a and 230c with the aforementioned structures, the defect state density at the interfaces between oxides 230a and 230b, and between oxides 230b and 230c, can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, resulting in transistor 200 exhibiting high on-state current and high frequency characteristics.

[0186] Alternatively, oxide 230c may have a stacked structure of two or more layers. For example, it may include a first oxide of oxide 230c and a second oxide of oxide 230c disposed on the first oxide of oxide 230c.

[0187] The first oxide of oxide 230c preferably contains at least one of the metal elements constituting the metal oxide for oxide 230b, and more preferably contains all of the aforementioned metal elements. For example, In-Ga-Zn oxide is preferably used as the first oxide of oxide 230c, and In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide is used as the second oxide of oxide 230c. This reduces the defect state density at the interface between oxide 230b and the first oxide of oxide 230c. Compared to the first oxide of oxide 230c, the second oxide of oxide 230c is preferably a metal oxide that can suppress oxygen diffusion or permeation. By providing the second oxide of oxide 230c between insulator 250 and the first oxide of oxide 230c, oxygen contained in insulator 280 can be prevented from diffusing to insulator 250. Therefore, oxygen can be readily supplied to oxide 230b through the first oxide of oxide 230c.

[0188] Preferably, the conduction band bottom of the second oxides of oxides 230a and 230c is closer to the vacuum level than the conduction band bottom of the first oxides of oxides 230b and 230c. In other words, the electron affinity of the second oxides of oxides 230a and 230c is preferably less than that of the first oxides of oxides 230b and 230c. In this case, the second oxide of oxide 230c is preferably a metal oxide that can be used for oxide 230a, and the first oxide of oxide 230c is preferably a metal oxide that can be used for oxide 230b. At this time, the main pathway of charge carriers is sometimes the first oxide of oxides 230b and 230c.

[0189] Specifically, the first oxide of oxide 230c can be a metal oxide with an In:Ga:Zn ratio of 4:2:3 (atomic ratio), and the second oxide can be a metal oxide or gallium oxide with an In:Ga:Zn ratio of 1:3:4 (atomic ratio), Ga:Zn ratio of 2:1 (atomic ratio), or Ga:Zn ratio of 2:5 (atomic ratio). This reduces the defect state density at the interface between the first and second oxides of oxide 230c.

[0190] Furthermore, when the atomic ratio of In to the main metal element in the metal oxide of the second oxide used in oxide 230c is less than the atomic ratio of In to the main metal element in the metal oxide of the first oxide used in oxide 230c, In diffusion to the insulator 250 side can be suppressed. Insulator 250 is used as a gate insulator, so when In mixes into insulator 250, it leads to poor transistor characteristics. Therefore, by employing a stacked structure in oxide 230c, a highly reliable semiconductor device can be provided.

[0191] As the conductor 242, a metal nitride with the aforementioned conductivity is preferably used. Examples of metal nitrides include tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, tantalum and aluminum nitrides, and titanium and aluminum nitrides. Tantalum nitrides are particularly preferred. Furthermore, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel can also be used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even after absorbing oxygen.

[0192] like Figure 1B As shown, insulator 254 preferably contacts the top and side surfaces of conductor 242a, the top and side surfaces of conductor 242b, the side surface of oxide 230a, the side surface of oxide 230b, and a portion of the top surface of insulator 224. With this structure, insulator 280 is separated from insulator 224, oxide 230a, and oxide 230b by insulator 254.

[0193] Similar to insulator 222, insulator 254 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen. For example, compared with insulator 224 and insulator 280, insulator 254 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen. Thus, the diffusion of hydrogen contained in insulator 280 to oxides 230a and 230b can be suppressed. Furthermore, by surrounding insulator 224, oxide 230, etc., with insulator 222 and insulator 254, the diffusion of impurities such as water and hydrogen from the outside to insulator 224 and oxide 230 can be suppressed. Therefore, transistor 200 can have good electrical characteristics and reliability.

[0194] The insulator 254 is preferably formed by sputtering. By forming the insulator 254 using sputtering in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region where the insulator 224 contacts the insulator 254. Oxygen can then be supplied from this region to the oxide 230 through the insulator 224. Here, by making the insulator 254 have the function of suppressing oxygen diffusion upwards, oxygen diffusion from the oxide 230 to the insulator 280 can be prevented. Furthermore, by making the insulator 222 have the function of suppressing oxygen diffusion downwards, oxygen diffusion from the oxide 230 to the substrate side can be prevented. Thus, oxygen is supplied to the channel formation region of the oxide 230. This reduces oxygen vacancies in the oxide 230 and suppresses the constant-on state of the transistor.

[0195] As the insulator 254, an insulator comprising one or both of aluminum and hafnium oxides can be formed, for example. In this case, atomic layer deposition (ALD) is preferred for forming the insulator 254. Because ALD is a film-forming method with good coverage, it can prevent breakage caused by unevenness of the insulator 254.

[0196] Furthermore, an insulator containing aluminum nitride, for example, can be used as the insulator 254. Therefore, a film with high insulation and high thermal conductivity can be formed, thereby improving the heat dissipation generated when driving the transistor 200. Alternatively, silicon nitride or silicon oxynitride can also be used.

[0197] Alternatively, gallium-containing oxides can be used as insulators 254, for example. Gallium-containing oxides are preferred because they sometimes have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Gallium oxide, zinc gallium oxide, indium gallium zinc oxide, etc., can be used as gallium-containing oxides. When indium gallium zinc oxide is used as insulator 254, a large ratio of gallium atoms to indium is preferred. By increasing this atomic ratio, the insulating properties of the oxide can be improved.

[0198] Furthermore, the insulator 254 can have a multilayer structure with two or more layers. When the insulator 254 has a two-layer stacked structure, the methods described above can be used to form the lower and upper layers of the insulator 254. Moreover, the same or different methods can be used to form the lower and upper layers of the insulator 254. For example, the lower layer of the insulator 254 can be formed by sputtering in an oxygen-containing atmosphere, and then the upper layer of the insulator 254 can be formed by ALD (Alternating Layer Deposition). Because ALD is a film-forming method with good coverage, it can prevent breakage due to unevenness in the first layer.

[0199] Furthermore, the aforementioned materials can be used as the lower and upper layers of the insulator 254, and the materials of the lower and upper layers of the insulator 254 can be the same or different. For example, a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride with an insulator that has the function of suppressing impurities such as hydrogen and oxygen permeation can be used. As an insulator that has the function of suppressing impurities such as hydrogen and oxygen permeation, for example, an insulator containing one or both of aluminum and hafnium oxides can be used.

[0200] Insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with at least a portion of oxide 230c. Insulator 250 may be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, etc. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0201] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as insulator 250 in contact with at least a portion of oxide 230c, oxygen can be efficiently supplied to the channel formation region of oxide 230b, thereby reducing oxygen vacancies in the channel formation region of oxide 230b. Therefore, a transistor with improved reliability can be provided while suppressing variations in electrical characteristics to achieve stable electrical characteristics. Furthermore, similar to insulator 224, it is preferable to reduce the concentration of impurities such as water and hydrogen in insulator 250. The thickness of insulator 250 is preferably 1 nm or more and 20 nm or less.

[0202] Alternatively, a metal oxide can be disposed between the insulator 250 and the conductor 260. This metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By disposing of a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 caused by oxygen in the insulator 250 can be suppressed.

[0203] Furthermore, the aforementioned metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, a metal oxide that is a high-k material with a high relative permittivity is preferably used as the aforementioned metal oxide. By making the gate insulator have a stacked structure of insulator 250 and the aforementioned metal oxide, a stacked structure with thermal stability and a high relative permittivity can be formed. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0204] Specifically, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, insulators containing oxides of one or both of aluminum and hafnium are preferred.

[0205] Alternatively, the aforementioned metal oxide can also be used as part of the first gate electrode. For example, an oxide semiconductor that can be used as oxide 230 can be used as the aforementioned metal oxide. In this case, by forming the conductor 260 using a sputtering method, the resistance value of the aforementioned metal oxide can be reduced, making it a conductor.

[0206] By incorporating the aforementioned metal oxide, the on-state current of transistor 200 can be increased without reducing the influence of the electric field from conductor 260. Furthermore, by maintaining the distance between conductor 260 and oxide 230 using the physical thickness of insulator 250 and the aforementioned metal oxide, leakage current between conductor 260 and oxide 230 can be suppressed. Additionally, by providing a stacked structure of insulator 250 and the aforementioned metal oxide, the physical distance between conductor 260 and oxide 230, as well as the electric field strength applied from conductor 260 to oxide 230, can be easily adjusted.

[0207] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed in a manner that surrounds the bottom surface and side surface of the conductor 260b.

[0208] The conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0209] Furthermore, when the conductor 260a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used, for example.

[0210] Furthermore, since conductor 260 is also used for wiring, it is preferable to use a conductor with high conductivity. For example, conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main components. Alternatively, conductor 260b can also adopt a multilayer structure, such as a multilayer structure of titanium, titanium nitride, and the aforementioned conductive materials.

[0211] Although Figure 1B and Figure 1CThe intermediate conductor 260 has a two-layer structure of conductor 260a and conductor 260b, but it can also have a single-layer structure or a stacked structure of three or more layers.

[0212] Furthermore, in transistor 200, conductor 260 is formed in a self-aligned manner by filling the openings formed in insulator 280, etc. By forming conductor 260 in this way, conductor 260 can be reliably positioned in the region between conductor 242a and conductor 242b without alignment.

[0213] In addition, such as Figure 1B As shown, the top surface of the conductor 260 is roughly the same as the top surface of the insulator 250 and the top surface of the oxide 230c.

[0214] In addition, such as Figure 1C As shown, in the channel width direction of transistor 200, the bottom surface of conductor 260 in the region where conductor 260 does not overlap with oxide 230b is preferably lower than the bottom surface of oxide 230b. By employing a structure in which conductor 260, used as a gate electrode, covers the side and top surfaces of the channel formation region of oxide 230b via insulator 250 or the like, the electric field of conductor 260 can easily act on the entire channel formation region of oxide 230b. This increases the on-state current of transistor 200 and improves frequency characteristics. When the bottom surface of insulator 222 is used as a reference, and the difference between the height of the bottom surface of conductor 260 and the height of the bottom surface of oxide 230b in the region where oxide 230a and oxide 230b do not overlap with conductor 260 is denoted as T1, this T1 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0215] The insulator 280 is preferably disposed on the insulator 224, oxide 230a, oxide 230b and conductor 242, with the insulator 254 in between. In addition, the top surface of the insulator 280 may also be planarized.

[0216] Preferably, the insulator 280 used as the interlayer film has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably formed, for example, using the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Especially, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen that has been released through heating.

[0217] The concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. Furthermore, it is preferable that insulator 280 has a low hydrogen concentration and includes or contains excess oxygen regions; for example, it can be formed using the same material as insulator 216. Additionally, insulator 280 may also have a multilayer structure with two or more layers.

[0218] Similar to insulator 214, insulator 274 is preferably used as an insulating barrier film to inhibit the diffusion of impurities such as water and hydrogen from above into insulator 280. Furthermore, similar to insulator 214, it is preferable that insulator 274 has a low hydrogen concentration and that it has the function of inhibiting hydrogen diffusion.

[0219] In addition, such as Figure 1B As shown, insulator 274 is preferably in contact with the top surface of conductor 260, insulator 250, and oxide 230c. This suppresses the incorporation of impurities such as hydrogen contained in insulator 281 into insulator 250. Consequently, negative impacts on the electrical characteristics and reliability of the transistor can be suppressed.

[0220] Preferably, an insulator 281, which serves as an interlayer film, is provided on insulator 274. Similar to insulator 216, insulator 281 preferably has a low dielectric constant. Similar to insulator 224, the concentration of impurities such as water and hydrogen in insulator 281 is preferably reduced.

[0221] Furthermore, conductors 240a and 240b are disposed in openings formed in insulators 281, 274, 280, and 254. Conductors 240a and 240b are arranged opposite each other with conductor 260 sandwiched between them. Additionally, the top surfaces of conductors 240a and 240b can be located on the same plane as the top surface of insulator 281.

[0222] Additionally, an insulator 241a is provided in contact with the sidewalls of the openings of insulators 281, 274, 280, and 254, and a conductor 240a is formed in contact with the side of the insulator 241a. A conductor 242a is located at least a portion of the bottom of the opening, and the conductor 240a is in contact with the conductor 242a. Similarly, an insulator 241b is provided in contact with the sidewalls of the openings of insulators 281, 274, 280, and 254, and a conductor 240b is formed in contact with the side of the insulator 241b. A conductor 242b is located at least a portion of the bottom of the opening, and the conductor 240b is in contact with the conductor 242b.

[0223] Conductors 240a and 240b are preferably made of conductive materials with tungsten, copper or aluminum as the main components.

[0224] Furthermore, conductors 240a and 240b may also have a stacked structure. Although conductors 240a and 240b in transistor 200 have a two-layer stacked structure, the present invention is not limited thereto. For example, conductor 240 may also have a single-layer structure or a stacked structure of three or more layers.

[0225] When conductors 240a and 240b have a stacked structure, a conductive material that suppresses the permeation of impurities such as water and hydrogen is preferably used as the conductor that contacts conductor 242 and contacts insulators 254, 280, 274, and 281 through insulator 241. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide are preferred. The conductive material that suppresses the permeation of impurities such as water and hydrogen can be used as a single layer or in a stacked manner. By using this conductive material, oxygen added to insulator 280 can be prevented from being absorbed into conductors 240a and 240b. Furthermore, impurities such as water and hydrogen contained in the layer above insulator 281 can be prevented from diffusing through conductors 240a and 240b to oxide 230.

[0226] As insulators 241a and 241b, insulators suitable for insulators 214, 254, etc., can be used. Because insulators 241a and 241b are disposed in contact with insulator 254, impurities such as water and hydrogen contained in insulator 280 can be suppressed from diffusing to oxide 230 via conductors 240a and 240b. Furthermore, it can prevent the absorption of oxygen contained in insulator 280 by conductors 240a and 240b.

[0227] Although not shown, the conductors used for wiring can be configured to contact the top surfaces of conductors 240a and 240b. The conductors used for wiring are preferably made of conductive materials with tungsten, copper, or aluminum as their main components. Furthermore, the conductors can have a multilayer structure, for example, a multilayer structure of titanium, titanium nitride, and the aforementioned conductive materials. Additionally, the conductors can be embedded in openings provided in an insulator.

[0228] Furthermore, although not illustrated, it is preferable to set its resistivity to 1.0 × 10⁻⁶ in a manner that covers the aforementioned conductor. 13 Ωcm or more and 1.0×10 15 Below Ωcm, preferably 5.0 × 10 13 Ωcm or more and 5.0×10 14An insulator with a resistivity of Ωcm or less. By providing an insulator with the above resistivity on the conductor, the insulator can not only maintain insulation, but also disperse the charge accumulated between the transistor 200 and the wiring of the conductor, thereby suppressing malfunctions or electrostatic damage to the transistor or electronic device having the transistor caused by the charge, and is therefore preferred.

[0229] <Materials Constituting Semiconductor Devices>

[0230] The following describes the constituent materials that can be used in semiconductor devices.

[0231] Substrate

[0232] For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates for forming the transistor 200. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples of insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators can also be used. Alternatively, substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0233] Insulators

[0234] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0235] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a relatively low permittivity as the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0236] In addition, examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0237] In addition, examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide or resin with pores.

[0238] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator (such as insulator 214, insulator 222, insulator 254, and insulator 274) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in a stack. Specifically, as an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0239] Furthermore, the insulator used as the gate insulator is preferably an insulator having regions containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having regions containing oxygen that has been removed by heating is contacted with oxide 230, oxygen vacancies contained in oxide 230 can be filled.

[0240] Conductors

[0241] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. Alternatively, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicides can also be used.

[0242] Alternatively, multiple conductive layers formed from the above-described materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Alternatively, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0243] Furthermore, when using oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0244] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Or, hydrogen entering from external insulators or the like can sometimes be trapped.

[0245] Metal Oxides

[0246] As oxide 230, a metal oxide that is used as an oxide semiconductor is preferred. Hereinafter, metal oxides that can be used in oxide 230 according to the present invention will be described.

[0247] The metal oxide preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Additionally, it preferably contains gallium, yttrium, tin, etc. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0248] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M.

[0249] Note that in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0250] [Structure of metal oxides]

[0251] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0252] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, resulting in a distorted crystal structure. Note that distortion refers to the portion of the lattice orientation that changes between regions with consistent lattice arrangement and other regions with consistent lattice arrangement within the region where multiple nanocrystals are linked.

[0253] Although nanocrystals are primarily hexagonal, they are not limited to regular hexagons and can be non-regular hexagonal. Furthermore, pentagonal, heptagonal, and other lattice arrangements sometimes exist in the distortion. Additionally, in CAAC-OS, clear grain boundaries (also known as grain boundaries) are difficult to observe even near the distortion. That is, it can be seen that the lattice arrangement distortion can suppress grain boundary formation. This is because CAAC-OS can contain the distortion due to the low density of oxygen atoms along the ab plane or the change in interatomic bonding distance caused by the substitution of metal elements.

[0254] Furthermore, CAAC-OS tends to have a layered crystal structure (also called a layered structure) consisting of layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers). Additionally, indium and element M can substitute for each other; when element M in a (M, Zn) layer is replaced by indium, the layer can also be represented as an (In, M, Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0255] CAAC-OS is a highly crystalline metal oxide. Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Additionally, the crystallinity of metal oxides can sometimes decrease due to the introduction of impurities or the formation of defects; therefore, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides containing CAAC-OS possess high heat resistance and high reliability.

[0256] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the overall film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0257] Furthermore, In-Ga-Zn oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is in the form of nanocrystals as described above. In particular, IGZO tends to not readily grow crystals in the atmosphere, so it may be structurally stable when IGZO is in the form of small crystals (e.g., the aforementioned nanocrystals) compared to when IGZO is in the form of large crystals (here, crystals a few mm or a few cm).

[0258] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0259] Oxide semiconductors (metal oxides) have various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0260] [Impurities]

[0261] Here, we will explain the effects of various impurities in metal oxides.

[0262] When impurities are incorporated into oxide semiconductors, they sometimes form defect levels or oxygen vacancies. Therefore, when impurities are present in the channel formation region of an oxide semiconductor, the electrical characteristics of transistors using oxide semiconductors are prone to change, and sometimes their reliability decreases. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor tends to exhibit always-on characteristics.

[0263] Furthermore, sometimes the aforementioned defect levels include trap levels. The charge trapped in a metal oxide trap level takes a long time to dissipate, sometimes acting like a fixed charge. Therefore, transistors containing metal oxides with high trap state densities in the channel formation region sometimes exhibit unstable electrical characteristics.

[0264] Furthermore, the presence of impurities in the channel formation region of an oxide semiconductor can sometimes reduce the crystallinity of the channel formation region. Additionally, the crystallinity of the oxide in contact with the channel formation region can sometimes decrease. When the crystallinity of the channel formation region is low, there is a tendency for the stability or reliability of the transistor to decrease. Moreover, when the crystallinity of the oxide in contact with the channel formation region is low, interfacial energy levels may sometimes form, leading to a decrease in the stability or reliability of the transistor.

[0265] Therefore, reducing the impurity concentration in and around the channel formation region of an oxide semiconductor is effective in improving the stability or reliability of transistors. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0266] Specifically, in and around the channel formation region of the oxide semiconductor, the concentration of the aforementioned impurities, as measured by SIMS, is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 Alternatively, in the channel formation region and vicinity of the oxide semiconductor, the concentration of the aforementioned impurities, as measured by elemental analysis using EDX, is 1.0 atomic% or less. Furthermore, when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the aforementioned impurities relative to element M in the channel formation region and vicinity of the oxide semiconductor is less than 0.10, preferably less than 0.05. Here, the concentration of element M used in calculating the aforementioned concentration ratio can be either the concentration in the same region where the impurity concentration is calculated, or the concentration in the oxide semiconductor itself.

[0267] In addition, metal oxides with reduced impurity concentrations have lower defect state densities, so the trap state density sometimes also becomes lower.

[0268] <Methods for Manufacturing Semiconductor Devices>

[0269] Next, refer to Figures 4A to 11C The instructions include Figures 1A to 1D The method for manufacturing a semiconductor device of transistor 200 according to one aspect of the present invention is shown.

[0270] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A A top view is shown. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B Showing along Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A The cross-sectional view of the section with dotted lines A1-A2 in the figure corresponds to a cross-sectional view of the transistor 200 along the channel length direction. Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C Showing along Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A The cross-sectional view of the section marked with dashed lines A3-A4 corresponds to a cross-sectional view of transistor 200 along the channel width direction. For clarity, in Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A Some constituent elements are omitted in the top view.

[0271] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed using sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD.

[0272] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD), thermal CVD (TCVD), and photo-CVD. Furthermore, CVD methods can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0273] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a film deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices sometimes experience charge buildup due to receiving charge from plasma. This accumulated charge can sometimes damage these wiring, electrodes, and components. On the other hand, thermal CVD, which does not use plasma, avoids this plasma damage, thus improving the yield of semiconductor devices. Additionally, since thermal CVD does not generate plasma damage during film deposition, films with fewer defects can be obtained.

[0274] Furthermore, the ALD method leverages the self-regulating nature of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects like pinholes, films with excellent coverage, and films formed at low temperatures. In addition, the ALD method includes PEALD (Plasma Enhanced ALD), which utilizes plasma. By using plasma, film deposition can be performed at even lower temperatures, making it sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0275] Unlike film formation methods that deposit particles released from a target or similar material, CVD and ALD methods form films based on reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed using ALD exhibit excellent step coverage and thickness uniformity, making ALD suitable for applications requiring coverage of surfaces with high aspect ratio openings. Note that ALD has a relatively slow film formation rate, so it is sometimes preferable to combine it with other film formation methods with faster rates, such as CVD.

[0276] CVD and ALD methods allow for control of the film composition by adjusting the source gas flow rate ratio. For example, when using CVD or ALD, films with arbitrary compositions can be formed by adjusting the source gas flow rate ratio. Furthermore, for instance, when using CVD and ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio while forming the film. When forming a film while changing the source gas flow rate ratio, the time required for pressure adjustment and transmission is eliminated, thus shortening the film formation time compared to using multiple deposition chambers. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0277] In this embodiment, aluminum oxide is formed by sputtering as the insulator 214. The insulator 214 may also have a multilayer structure.

[0278] Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, silicon oxynitride is formed as the insulator 216 using CVD.

[0279] Next, an opening leading to insulator 214 is formed in insulator 216. The opening may include, for example, a groove or a slit. Furthermore, the area where the opening is formed is sometimes referred to as the opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. As insulator 214, it is preferable to select an insulator that serves as an etch stop film when etching insulator 216 to form a groove. For example, when silicon oxynitride is used as insulator 216 for forming the groove, silicon nitride, aluminum oxide, or hafnium oxide are preferably used as insulator 214.

[0280] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used. The CCP etching apparatus including parallel planar electrodes can also employ a structure in which a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of the same frequency are applied to each of the parallel planar electrodes can be used. Alternatively, a structure in which high-frequency voltages of different frequencies are applied to each of the parallel planar electrodes can be used. Alternatively, a dry etching apparatus having a high-density plasma source can also be used. For example, as a dry etching apparatus having a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used.

[0281] After the opening is formed, a conductive film is formed, which will become the first conductor 205. This conductive film preferably contains a conductor that inhibits oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc., can be used. Alternatively, a laminated film of a conductor that inhibits oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. This conductive film can be formed using sputtering, CVD, MBE, PLD, ALD, etc.

[0282] In this embodiment, the conductive film that will serve as the first conductor of the conductor 205 is a tantalum nitride film formed by sputtering or a film formed by laminating titanium nitride on tantalum nitride. By using this metal nitride as the first conductor of the conductor 205, even if a metal that easily diffuses, such as copper, is used as the second conductor of the conductor 205 (described later), the diffusion of this metal from the first conductor of the conductor 205 to the outside can be suppressed.

[0283] Next, a second conductive film, which will also become a conductor 205, is formed on the conductive film that will become the first conductor 205. This conductive film can be formed using methods such as plating, sputtering, CVD, MBE, PLD, and ALD. In this embodiment, tungsten is formed as the conductive film.

[0284] Next, by performing CMP (Chemical Mechanical Polishing), the conductive film that will become the first conductor of conductor 205 and a portion of the conductive film that will become the second conductor of conductor 205 are removed, exposing the insulator 216. As a result, only the conductive film that will become the first conductor of conductor 205 and the conductive film that will become the second conductor of conductor 205 remain at the opening. Thus, a conductor 205 comprising the first conductor of conductor 205 and the second conductor of conductor 205, with a flat top surface, can be formed (see reference). Figures 4A to 4C ).

[0285] Alternatively, after forming the conductor 205, the following steps can be performed: removing a portion of the second conductor of the conductor 205, forming a trench in the second conductor of the conductor 205, forming a conductive film on the conductor 205 and the insulator 216 by filling the trench, and performing CMP treatment. This CMP treatment removes a portion of the conductive film, exposing the insulator 216. It is preferable to use a dry etching method or similar technique to remove the portion of the second conductor of the conductor 205.

[0286] Through the above-described process, a conductor 205 comprising the aforementioned conductive film with a flat top surface can be formed. By improving the flatness of the top surfaces of the insulator 216 and the conductor 205, the crystallinity of oxides 230a, 230b, and 230c can be improved. The same material as the first conductor or the second conductor of the conductor 205 can be used as the conductive film.

[0287] The following will describe a method for forming the conductor 205 that differs from the above.

[0288] A conductive film, which will become a conductor 205, is formed on the insulator 214. The conductive film can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Furthermore, the conductive film can be a multilayer film. For example, tungsten can be formed as the conductive film.

[0289] Next, the conductive film that will become the conductor 205 is processed using photolithography to form the conductor 205.

[0290] In photolithography, a photoresist is first exposed through a mask. Then, a developer is used to remove or leave the exposed areas, forming a photoresist mask. Next, etching is performed through this photoresist mask to process conductors, semiconductors, insulators, etc., into the desired shape. For example, a photoresist mask can be formed by exposing the photoresist with KrF stimulated excimer laser, ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion lithography can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Note that a mask is not required when using electron or ion beams. Furthermore, when removing the photoresist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0291] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating or conductive film that serves as the hard mask material can be formed on the conductive film that will become the conductor 205, and a photoresist mask can be formed on top of it. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the conductive film that will become the conductor 205 can be performed either after removing the photoresist mask or without removing it. In the latter case, the photoresist mask may sometimes disappear during etching. Alternatively, the hard mask can be removed by etching after etching the conductive film that will become the conductor 205. On the other hand, it is not necessary to remove the hard mask if the hard mask material does not affect subsequent processes or can be used in subsequent processes.

[0292] Next, an insulating film, which will become insulator 216, is formed on insulator 214 and conductor 205. This insulating film is formed in contact with the top and side surfaces of conductor 205. The insulating film can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods.

[0293] Here, the thickness of the insulating film that will become the insulator 216 is preferably greater than or equal to the thickness of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film is 1 or more and 3 or less.

[0294] Next, a portion of the insulating film, which will become the insulator 216, is removed by CMP treatment, exposing the surface of the conductor 205. Thus, a conductor 205 and an insulator 216 with flat top surfaces can be formed. This is another method for forming the conductor 205.

[0295] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. The insulator 222 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, hafnium oxide or aluminum oxide is formed as the insulator 222 using the ALD method.

[0296] Next, a heat treatment is preferably performed. The heat treatment is performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, heat treatment can be performed in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0297] In this embodiment, as a heat treatment, after the insulator 222 is formed, it is treated at 400°C for 1 hour in a nitrogen atmosphere, followed by continuous treatment at 400°C for 1 hour in an oxygen atmosphere. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Alternatively, the heat treatment can be performed after the insulator 224 is formed, or at other times.

[0298] Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed using sputtering, CVD, MBE, PLD, ALD, or other methods. In this embodiment, a silicon oxynitride film is formed as the insulator 224 using CVD.

[0299] To create an excess oxygen region in the insulator 224, an oxygen-containing plasma treatment can be performed under reduced pressure. The oxygen-containing plasma treatment preferably employs a device including a power supply for generating high-density plasma using microwaves. Alternatively, a power supply applying RF (Radio Frequency) to one side of the substrate can also be used. High-density oxygen radicals can be generated using high-density plasma, and applying RF to one side of the substrate allows the oxygen radicals generated by the high-density plasma to be efficiently introduced into the insulator 224. Alternatively, an oxygen-containing plasma treatment can be performed after a plasma treatment containing an inert gas using such a device to replenish the detached oxygen. Furthermore, by appropriately selecting the conditions of this plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, heating treatment may not be necessary.

[0300] Here, an aluminum oxide film can be formed on the insulator 224, for example, by sputtering, and the aluminum oxide can be subjected to CMP treatment until it reaches the insulator 224. This CMP treatment can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing CMP treatment, the endpoint of the CMP treatment can be easily detected. Furthermore, sometimes the thickness of the insulator 224 may become thinner due to polishing of a portion of the insulator 224 through CMP treatment, but this can be corrected by adjusting the thickness during film formation on the insulator 224. Planarizing and smoothing the surface of the insulator 224 can sometimes prevent a decrease in the coverage of the oxide film to be formed underneath and prevent a decrease in the yield of the semiconductor device. Furthermore, it is preferable to add oxygen to the insulator 224 by sputtering an aluminum oxide film on the insulator 224.

[0301] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (refer to...). Figure 4B and Figure 4C Preferably, oxide films 230A and 230B are formed continuously without exposure to the atmospheric environment. By forming the oxide films in a manner that does not expose them to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to oxide film 230A, thus keeping the area near the interface between oxide film 230A and oxide film 230B clean.

[0302] Oxide film 230A and oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD and other methods.

[0303] For example, when forming oxide films 230A and 230B using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. Furthermore, when forming the aforementioned oxide films using sputtering, the aforementioned In-M-Zn oxide target can be used, for example.

[0304] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas is sometimes supplied to the insulator 224. Therefore, the oxygen content in the sputtering gas can be 70% or more, preferably 80% or more, and more preferably 100%.

[0305] When forming the oxide film 230B using sputtering, an oxygen-excess oxide semiconductor can be formed by forming the film under conditions where the oxygen content in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%. Transistors using oxygen-excess oxide semiconductors in the channel formation region can have high reliability. However, the invention is not limited to this. When forming the oxide film 230B using sputtering, an oxygen-deficient oxide semiconductor is formed when the film is formed under conditions where the oxygen content in the sputtering gas is set to more than 1% and less than 30%, preferably more than 5% and less than 20%. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can have high field-effect mobility. Furthermore, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved.

[0306] In this embodiment, an oxide film 230A is formed using an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 1:3:4 (atomic ratio) via sputtering. Additionally, an oxide film 230B is formed using an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic ratio) via sputtering. The deposition conditions and atomic ratios for each oxide film can be appropriately selected based on the desired characteristics of the oxide 230.

[0307] Here, it is preferable to form insulator 222, insulator 224, oxide film 230A, and oxide film 230B in a manner that does not expose them to the atmosphere. For example, a multi-chamber film-forming apparatus is preferred.

[0308] Next, a heat treatment can be performed. The aforementioned heat treatment conditions can be used as the conditions for this heat treatment. By performing this heat treatment, impurities such as water and hydrogen in the oxide films 230A and 230B can be removed. In this embodiment, the treatment is performed at 400°C for 1 hour under a nitrogen atmosphere, followed by a continuous treatment at 400°C for 1 hour under an oxygen atmosphere.

[0309] Next, conductive films 242A1 and 242A2 are sequentially formed on the oxide film 230B. Conductive films 242A1 and 242A2 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. (see reference). Figures 4B to 4C ).

[0310] More preferably, conductive films 242A1 and 242A2 are formed using ionization sputtering. In ionization sputtering, a high-density plasma is formed between the target and the substrate. Sputtered particles sputtered from the target collide with electrons in this high-density plasma region, thereby positively ionizing them. Furthermore, by applying a negative bias voltage to the substrate side, the positively ionized particles can be introduced to the substrate side, thereby achieving a good interface between the oxide film 230B and the conductive film 242A1. For example, by forming conductive films 242A1 and 242A2 using ionization sputtering, the contact resistance between them and the oxide film 230B can be reduced. Moreover, by forming conductive films 242A1 and 242A2 using ionization sputtering, even if there are irregularities on the surface of the oxide film 230B, these irregularities can be filled in; in other words, the coverage can be improved.

[0311] Alternatively, a heat treatment can be performed before forming the conductive film 242A1. This heat treatment can be performed under reduced pressure, and the conductive films 242A1 and 242A2 can be formed continuously without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide films 230A and 230B can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is 200°C.

[0312] Furthermore, in this embodiment, conductive films 242A1 and 242A2 are formed in a nitrogen atmosphere using a sputtering apparatus such that the ratio of nitrogen flow rate in the total gas flow rate when forming conductive film 242A1 is greater than the ratio of nitrogen flow rate in the total gas flow rate when forming conductive film 242A2. Examples of gases that can be used to form conductive films 242A1 and 242A2 include nitrogen, helium, argon, xenon, and krypton. It is particularly preferred to use film-forming gases of nitrogen and argon to form conductive films 242A1 and 242A2.

[0313] Furthermore, the substrate temperature during the formation of conductive films 242A1 and 242A2 can be room temperature, or the substrate can be heated. For example, the substrate temperature during the formation of conductive films 242A1 and 242A2 can be above room temperature and below 350°C.

[0314] Furthermore, when tantalum nitride films with different compositions are formed as conductive films 242A1 and 242A2, by setting the film formation conditions other than the film-forming gas to common conditions, conductive films 242A1 and 242A2 can be continuously formed without exposure to the atmospheric environment. By forming the films without exposure to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to conductive film 242A1, thus maintaining the cleanliness of the interface between conductive films 242A1 and 242A2. Moreover, when tantalum nitride films with different compositions are formed as conductive films 242A1 and 242A2, the implementer can arbitrarily change the film formation conditions other than the film-forming gas (e.g., pressure, power, time, substrate temperature, etc.). However, to maintain the cleanliness of the interface between conductive films 242A1 and 242A2, it is preferable to form them continuously in a vacuum.

[0315] Next, oxide films 230A, 230B, conductive films 242A1, and 242A2 are processed into island shapes to form oxides 230a, 230b, conductive layers 242B1, and 242B2. Note that in this process, the thickness of the region in insulator 224 that does not overlap with oxide 230a may sometimes become thinner (see reference). Figures 5A to 5C ).

[0316] Here, oxides 230a and 230b, and conductive layers 242B (conductive layers 242B1 and 242B2) are formed such that at least a portion overlaps with the conductor 205. Furthermore, the side surfaces of oxides 230a, 230b, and conductive layers 242B are preferably substantially perpendicular to the top surface of the insulator 224. When the side surfaces of oxides 230a, 230b, and conductive layers 242B are substantially perpendicular to the top surface of the insulator 224, a smaller area and higher density can be achieved when multiple transistors 200 are provided. Alternatively, a structure with a lower angle between the side surfaces of oxides 230a, 230b, and conductive layers 242B and the top surface of the insulator 224 can be used. In this case, the angle between the side surfaces of oxides 230a, 230b, and conductive layers 242B and the top surface of the insulator 224 is preferably 60 degrees or more and less than 70 degrees. By adopting this shape, the coverage of insulators such as 254 can be improved in the following processes, and defects such as voids can be reduced.

[0317] Furthermore, a curved surface is provided between the side surface and the top surface of the conductive layer 242B (conductive layers 242B1 and 242B2). That is, the ends of the side surface and the top surface are preferably curved. For example, at the ends of the conductive layer 242B, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, more preferably 5 nm or more and 6 nm or less. When the ends do not have corners, the film coverage in subsequent film deposition processes can be improved.

[0318] Furthermore, the oxide films 230A and 230B, and the conductive films 242A (conductive films 242A1 and 242A2) can be processed using photolithography. Alternatively, this processing can be performed using dry etching or wet etching. Dry etching is suitable for microfabrication. Moreover, the processing conditions for the oxide films 230A, 230B, and 242A can differ from one another.

[0319] Next, an insulating film 254A (see reference) is formed on insulator 224, oxide 230a, oxide 230b and conductive layer 242B (conductive layer 242B1 and conductive layer 242B2). Figure 6B and Figure 6C ).

[0320] The insulating film 254A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. Preferably, the insulating film 254A is an insulating film that inhibits oxygen permeation. For example, silicon nitride, silicon oxide, or aluminum oxide can be formed by sputtering.

[0321] Next, an insulating film that will become the insulator 280 is formed on the insulating film 254A. This insulating film can be formed using methods such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a silicon oxide film is formed using CVD or sputtering as the insulating film. Alternatively, a heat treatment can be performed before forming the insulating film. This heat treatment can also be performed under reduced pressure to continuously form the insulating film without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adhering to the surface of the insulating film 254A can be removed, and the moisture and hydrogen concentrations in oxides 230a, 230b, and the insulating film 254A can be reduced. The aforementioned heat treatment conditions can be used in the heat treatment.

[0322] Furthermore, the insulating film that will become the insulator 280 can have a multilayer structure. For example, a silicon oxide film can be formed by sputtering, and a silicon oxide film can be formed on the silicon oxide film by CVD.

[0323] Next, the insulating film that will become insulator 280 is subjected to CMP treatment to form insulator 280 with a flat top surface (see reference). Figure 6B and Figure 6C ).

[0324] Next, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B (conductive layer 242B1 and conductive layer 242B2) are processed to form an opening reaching the oxide 230b. This opening is preferably formed in a manner that overlaps with the conductor 205. By forming this opening, conductors 242a (conductors 242a1 and 242a2), conductors 242b (conductors 242b1 and 242b2), and the insulator 254 are formed. At this time, sometimes the thickness of the region of oxide 230b overlapping with the opening becomes thinner (see reference). Figures 7A to 7C ).

[0325] Furthermore, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B can be processed under different conditions. For example, a portion of the insulator 280 can be processed by dry etching, a portion of the insulating film 254A can be processed by wet etching, and a portion of the conductive layer 242B can be processed by dry etching.

[0326] Here, it is preferable to remove impurities adhering to the surfaces of oxides 230a, oxides 230b, etc., or those diffused into their interior. Examples of such impurities include components contained in the insulator 280, insulating film 254A, and conductive layer 242B; components contained in the components used in the apparatus for forming the aforementioned opening; components contained in the gas or liquid used for etching; and so on. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0327] To remove the aforementioned impurities, washing treatment can also be performed. Washing methods include wet washing using detergents, plasma treatment using plasma, and washing using heat treatment; combinations of these methods are also possible.

[0328] As a wet washing process, washing can be performed using aqueous solutions of ammonia, oxalic acid, phosphoric acid, or hydrofluoric acid diluted with carbonated water or pure water, or pure water or carbonated water. Alternatively, ultrasonic washing can be performed using these aqueous solutions, pure water, or carbonated water. Furthermore, a combination of the above washing methods can be appropriately combined.

[0329] Next, a heat treatment may be performed. This heat treatment is preferably carried out in an oxygen-containing atmosphere. Alternatively, the heat treatment may be carried out under reduced pressure, wherein an oxide film is continuously formed at 230°C (refer to) without exposure to the atmosphere. Figures 8A to 8CThis treatment removes moisture and hydrogen adhering to the surface of oxide 230b, and reduces the moisture and hydrogen concentrations in oxides 230a and 230b. The heat treatment temperature is preferably 100°C or higher and 400°C or lower. In this embodiment, the heat treatment temperature is 200°C.

[0330] The oxide film 230C can be formed using sputtering, CVD, MBE, PLD, ALD, and other methods. The oxide film 230C can be formed using the same film-forming method as oxide film 230A or oxide film 230B, depending on the desired properties of the oxide film 230C. In this embodiment, the oxide film 230C is formed using an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 1:3:4 or 4:2:4.1 [atomic ratio] via sputtering. Alternatively, as the oxide film 230C, an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 4:2:4.1 [atomic ratio] is used to form a film via sputtering, and an In-Ga-Zn oxide target with an In:Ga:Zn ratio of 1:3:4 [atomic ratio] is used to form a film thereon.

[0331] In particular, during the formation of oxide film 230C, a portion of the oxygen contained in the sputtering gas is sometimes supplied to oxides 230a and 230b. Therefore, the oxygen content in the sputtering gas of oxide film 230C can be 70% or more, preferably 80% or more, and more preferably 100%.

[0332] Next, heat treatment can also be performed. The heat treatment can also be carried out under reduced pressure, wherein an insulating film 250A (refer to) is continuously formed without exposure to the atmosphere. Figures 9A to 9C This treatment removes moisture and hydrogen adhering to the surface of the oxide film 230C, and reduces the moisture and hydrogen concentrations in oxides 230a, 230b, and the oxide film 230C. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0333] The insulating film 250A can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, silicon oxynitride is formed using CVD as the insulating film 250A. The film-forming temperature for forming the insulating film 250A is preferably 350°C or higher and lower than 450°C, and particularly preferably around 400°C. By forming the insulating film 250A at a temperature of 400°C, an insulating film with fewer impurities can be formed.

[0334] Next, conductive films 260A and 260B are formed sequentially. Conductive films 260A and 260B can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. In this embodiment, conductive film 260A is formed using the ALD method, and conductive film 260B is formed using the CVD method (see reference). Figures 10A to 10C ).

[0335] Next, the oxide film 230C, insulating film 250A, conductive film 260A, and conductive film 260B are polished using CMP treatment until the insulator 280 is exposed, forming oxide 230c, insulator 250, and conductor 260 (conductor 260a and conductor 260b) (see reference). Figures 11A to 11C Therefore, oxide 230c is disposed in such a way that it covers the inner wall (side wall and bottom surface) of the opening reaching oxide 230b. Insulator 250 is disposed in such a way that it covers the inner wall of the opening, separated by oxide 230c. In addition, conductor 260 is disposed in such a way that it fills the opening, separated by oxide 230c and insulator 250.

[0336] Next, heat treatment can also be performed. In this embodiment, the treatment is carried out at 400°C for 1 hour under a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in insulators 250 and 280.

[0337] Next, an insulator 274 is formed on oxide 230c, insulator 250, conductor 260, and insulator 280. The insulator 274 can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. For example, an alumina film or a silicon nitride film is preferably formed by sputtering as the insulator 274. By forming an alumina film or silicon nitride film using sputtering, the diffusion of hydrogen contained in the insulator 281 into the oxide 230 can be suppressed. Furthermore, forming the insulator 274 in contact with the conductor 260 can suppress the oxidation of the conductor 260, which is therefore preferred.

[0338] Furthermore, oxygen can be supplied to insulator 280 by sputtering to form an alumina film as insulator 274. The oxygen supplied to insulator 280 is sometimes supplied to the channel-forming region of oxide 230b via oxide 230c. Additionally, when oxygen is supplied to insulator 280, the oxygen contained in insulator 280 before the formation of insulator 274 is sometimes supplied to the channel-forming region of oxide 230b via oxide 230c.

[0339] The insulator 274 can also have a multilayer structure. For example, it can be a structure in which an aluminum oxide film is formed by sputtering, and a silicon nitride film is formed on the aluminum oxide film by sputtering.

[0340] Next, a heat treatment can be performed. The aforementioned heat treatment conditions can be used as the conditions for this heat treatment. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulator 280. Furthermore, oxygen contained in the insulator 274 can be injected into the insulator 280.

[0341] Alternatively, before forming the insulator 274, the following steps can be performed: First, an alumina film is formed on the insulator 280, etc., by sputtering; then, heat treatment is performed using the aforementioned heat treatment conditions; and finally, the alumina film is removed by CMP treatment. This process can create more excess oxygen regions in the insulator 280. Note that in this process, sometimes a portion of the insulator 280, a portion of the conductor 260, a portion of the insulator 250, and a portion of the oxide 230c are removed.

[0342] Alternatively, an insulator can be provided between insulator 280 and insulator 274. For example, silicon oxide formed by sputtering can be used as this insulator. By providing this insulator, an excess oxygen region can be formed in insulator 280.

[0343] Next, insulator 281 can also be formed on insulator 274. Insulator 281 can be formed using sputtering, CVD, MBE, PLD, ALD, etc. (see reference) Figure 11B and Figure 11C ).

[0344] Next, openings leading to conductors 242a (conductors 242a1 and 242a2) and 242b (conductors 242b1 and 242b2) are formed in insulators 254, 280, 274, and 281. These openings are formed using photolithography.

[0345] Next, an insulating film that will become insulator 241 is formed, and the insulating film is anisotropically etched to form insulator 241. This insulating film can be formed using sputtering, CVD, MBE, PLD, ALD, or similar methods. As the insulating film, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, an aluminum oxide film is preferably formed by ALD. Alternatively, a silicon nitride film can be formed by ALD or CVD. Furthermore, anisotropic etching, for example, dry etching, can be performed. By giving the sidewall portion of the opening this structure, the permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed next can be prevented. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from conductors 240a and 240b to the outside.

[0346] Next, a conductive film is formed that will become conductors 240a and 240b. This conductive film preferably employs a multilayer structure containing conductors that suppress the diffusion of impurities such as water and hydrogen. For example, it can be a multilayer of tantalum nitride, titanium nitride, tungsten, molybdenum, copper, etc. This conductive film can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD.

[0347] Next, a portion of the conductive film that will become conductors 240a and 240b is removed by CMP processing, exposing the insulator 281. As a result, the conductive film remains only at the aforementioned opening, thereby forming conductors 240a and 240b with flat top surfaces (see reference). Figure 1A and Figure 1B Note that sometimes a portion of insulator 281 is removed due to this CMP process.

[0348] Through the above processes, it is possible to manufacture including Figures 1A to 1D The semiconductor device shown is transistor 200.

[0349] According to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high on-state current can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0350] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments and examples.

[0351] (Implementation Method 2)

[0352] In this embodiment, refer to Figure 12 and Figure 13 One method of describing a semiconductor device is described.

[0353] [Storage Device 1]

[0354] Figure 12An example of a semiconductor device (memory device) using a semiconductor device as an embodiment of the present invention is shown. In the semiconductor device of one embodiment of the present invention, transistor 200 is disposed above transistor 300, and capacitor 100 is disposed above transistor 200. At least a portion of capacitor 100 or transistor 300 preferably overlaps transistor 200. This reduces the area occupied by capacitor 100, transistor 200, and transistor 300 in top view, enabling miniaturization or high integration of the semiconductor device according to this embodiment. The semiconductor device according to this embodiment can be applied, for example, to logic circuits represented by CPU (Central Processing Unit) or GPU (Graphics Processing Unit), or to memory circuits represented by DRAM (Dynamic Random Access Memory) or NVM (Non-Volatile Memory).

[0355] Note that the transistor 200 described in the above embodiments can be used as transistor 200. Therefore, regarding transistor 200 and the layer including transistor 200, please refer to the description of the above embodiments.

[0356] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200 has a small off-state current, its use in storage devices allows for long-term retention of stored data. In other words, since refresh operations are unnecessary or occur at extremely low frequencies, the power consumption of the storage device can be significantly reduced. Furthermore, compared to transistors using silicon as the semiconductor layer, transistor 200 exhibits superior electrical characteristics at high temperatures. For example, transistor 200 maintains good electrical characteristics even within a temperature range of 125°C to 150°C. Moreover, within this temperature range, transistor 200 has a conduction-to-cutoff ratio exceeding ten digits. In other words, compared to transistors using silicon as the semiconductor layer, transistor 200 possesses characteristics such as improved on-state current and frequency response at higher temperatures, typical of transistors.

[0357] exist Figure 12In the semiconductor device shown, wiring 1001 is electrically connected to the source of transistor 300, wiring 1002 is electrically connected to the drain of transistor 300, and wiring 1007 is electrically connected to the gate of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Moreover, the other of the source and drain of transistor 200 is electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0358] Figure 12 The semiconductor device shown has the characteristic that the charge in one electrode of the capacitor 100 can be maintained by switching the transistor 200, thus enabling data writing, retention, and reading. Furthermore, the transistor 200 is a device that has a back gate in addition to the source, gate (top gate), and drain. That is, compared to two-terminal devices such as MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), and Phase-change memory, which utilize MTJ (Magnetic Tunnel Junction) characteristics, the four-terminal transistor 200 has the characteristic of easily enabling independent control of input and output. Moreover, MRAM, ReRAM, and Phase-change memory sometimes undergo atomic-level structural changes when rewriting information. On the other hand, Figure 12 The semiconductor device shown operates by charging or discharging electrons in transistors and capacitors when rewriting information, thus exhibiting good rewrite durability and minimal structural changes.

[0359] In addition, by Figure 12 The semiconductor devices shown are arranged in a matrix, which can form a memory cell array. In this case, transistors 300 can be used as readout circuits or drive circuits connected to the memory cell array, etc. Furthermore, Figure 12 The semiconductor device shown is configured as a memory cell array as described above. Figure 12 When the semiconductor device shown is used as a storage element, for example, it can achieve an operating frequency of over 200 MHz under conditions of a driving voltage of 2.5V and an evaluation ambient temperature range of -40°C to 85°C.

[0360] <Transistor 300>

[0361] The transistor 300 is disposed on the substrate 311 and includes: a conductor 316 used as a gate electrode, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311, and low-resistance regions 314a and 314b used as source or drain regions.

[0362] Here, an insulator 315 is disposed on the semiconductor region 313, and a conductor 316 is disposed on the insulator 315. Furthermore, the transistor 300 formed in the same layer is electrically separated by an insulator 312, which serves as an element separation insulating layer. The same insulator as the insulator 326 described later can be used as the insulator 312. The transistor 300 can be a p-channel or an n-channel type.

[0363] In the substrate 311, the region of the semiconductor region 313 where the channel is formed or the region near it, the low-resistance region 314a and the low-resistance region 314b used as the source or drain region, preferably contain a semiconductor such as silicon, and more preferably contain single-crystal silicon. Alternatively, materials containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc., can also be used. Silicon, by applying stress to the crystal lattice and changing the interplanar spacing to control the effective quality, can be used. Furthermore, the transistor 300 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0364] In the low resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements such as arsenic and phosphorus that impart n-type conductivity or elements such as boron that impart p-type conductivity are also included.

[0365] The conductor 316 used as the gate electrode can be a conductive material such as silicon, a semiconductor material, a metal material, an alloy material, or a metal oxide material, which contains elements that impart n-type conductivity, such as arsenic or phosphorus, or elements that impart p-type conductivity, such as boron.

[0366] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as conductors. In order to combine conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, especially tungsten, which is preferred in terms of heat resistance.

[0367] Here, in Figure 12In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductor 316 is provided such that it covers the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Alternatively, an insulator serving as a mask for forming the convex portion may be provided in contact with the upper surface of the convex portion. Furthermore, although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0368] Notice, Figure 12 The structure of transistor 300 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0369] In addition, such as Figure 12 As shown, the semiconductor device is provided with a stack of transistors 300 and 200. For example, transistor 300 can be formed using a silicon-based semiconductor material, and transistor 200 can be formed using an oxide semiconductor material. Thus, Figure 12 The semiconductor device shown can have silicon-based semiconductor materials and oxide semiconductors formed in different layers, respectively. Furthermore, Figure 12 The semiconductor device shown can be manufactured using the same processes as those used in manufacturing equipment employing silicon-based semiconductor materials, and can achieve high integration.

[0370] <Capacitor>

[0371] The capacitor 100 includes an insulator 114 on an insulator 160, an insulator 140 on an insulator 114, a conductor 110 disposed in an opening formed in the insulator 114 and the insulator 140, a conductor 130 on the conductor 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130. Here, at least a portion of the conductor 110, the insulator 130, and the conductor 120 are disposed in the opening formed in the insulator 114 and the insulator 140.

[0372] Conductor 110 is used as the lower electrode of capacitor 100, conductor 120 is used as the upper electrode of capacitor 100, and insulator 130 is used as the dielectric of capacitor 100. Capacitor 100 has a structure in which the upper and lower electrodes are opposed by a dielectric material not only on the bottom surface but also on the side surfaces within the openings of insulators 114 and 140, thus increasing the electrostatic capacitance per unit area. The deeper the opening, the greater the electrostatic capacitance of capacitor 100. In this way, by increasing the electrostatic capacitance per unit area of ​​capacitor 100, miniaturization or high integration of semiconductor devices can be advanced.

[0373] As insulators 114 and 150, an insulator that can be used as insulator 280 can be used. In addition, insulator 140 is preferably used as an etch stop layer when forming an opening in insulator 114, and an insulator that can be used for insulator 214 can be used.

[0374] Furthermore, the top-view shape of the openings formed in insulators 114 and 140 can be a quadrilateral, a polygon other than a quadrilateral, a polygon with rounded corners, or a circular shape such as an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. By adopting this structure, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0375] The conductor 110 is disposed in contact with an opening formed in the insulator 140 and the insulator 114. The top surface of the conductor 110 preferably coincides substantially with the top surface of the insulator 140. Furthermore, the bottom surface of the conductor 110 contacts the conductor 152 disposed on the insulator 160. The conductor 110 is preferably formed by an ALD method or a CVD method, for example, using a conductor suitable for conductor 205.

[0376] The insulator 130 is configured to cover both the conductor 110 and the insulator 140. For example, the insulator 130 is preferably formed by an ALD or CVD method. As the insulator 130, for example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride, etc., can be used, and a multilayer or single-layer structure can be employed. For example, as the insulator 130, an insulating film sequentially stacked with zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0377] For example, the insulator 130 is preferably made of a material with high dielectric strength, such as silicon oxynitride, or a material with a high dielectric constant (high-k). Alternatively, a multilayer structure of materials with high dielectric strength or high dielectric constant (high-k) can also be used.

[0378] Note that insulators that are high-k materials (materials with relatively high dielectric constants) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such a high-k material, even if the insulator 130 is thickened, the electrostatic capacitance of the capacitor 100 can be sufficiently ensured. By thickening the insulator 130, leakage current generated between the conductor 110 and the conductor 120 can be suppressed.

[0379] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, and resins. For example, an insulating film consisting of silicon nitride formed by the ALD method, silicon oxide formed by the PEALD method, and silicon nitride formed by the ALD method can be used in sequence. By using such an insulator with high dielectric strength, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0380] Conductor 120 is disposed in such a way that it fills the openings formed in insulator 140 and insulator 114. Furthermore, conductor 120 is electrically connected to wiring 1005 via conductor 112 and conductor 153. Conductor 120 is preferably formed by ALD or CVD methods, for example, a conductor suitable for conductor 205 can be used.

[0381] Furthermore, the transistor 200 has a structure using oxide semiconductor, thus providing good matching with the capacitor 100. Specifically, the off-state current of the transistor 200 using oxide semiconductor is small, thereby allowing the stored content to be retained for a long period of time by combining the transistor 200 with the capacitor 100.

[0382] <Wiring Layer>

[0383] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductors used as plugs or wiring, multiple structures are sometimes represented by the same reference numeral. Additionally, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of a conductor is sometimes used as wiring, and a portion of a conductor is sometimes used as a plug.

[0384] For example, in transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to conductors 153 used as terminals, are embedded within insulators 320, 322, 324, and 326. Additionally, conductors 328 and 330 are used as plugs or wiring.

[0385] Furthermore, the insulator used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of insulator 322, its top surface can also be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0386] Furthermore, a wiring layer can also be formed on the insulator 326 and the conductor 330. For example, in Figure 12 In the structure, insulators 350, 352, and 354 are stacked sequentially. Furthermore, a conductor 356 is formed within insulators 350, 352, and 354. The conductor 356 is used as a plug or wiring.

[0387] Insulators 210, 212, 214, and 216 are sequentially stacked on insulators 354 and conductors 356. Furthermore, conductors 218 and conductors constituting transistor 200 (conductor 205) are embedded within insulators 210, 212, 214, and 216. Conductor 218 serves as a plug or wiring for electrical connection with transistor 300.

[0388] Furthermore, conductor 112 and conductors constituting capacitor 100 (conductor 120, conductor 110) are embedded in insulators 114, 140, 130, 150, and 154. Conductor 112 is used as a plug or wiring to electrically connect capacitor 100, transistor 200, or transistor 300 to conductor 153, which is used as a terminal.

[0389] Additionally, a conductor 153 is provided on the insulator 154, and the conductor 153 is covered by the insulator 156. Here, the conductor 153 is in contact with the top surface of the conductor 112 and is used as a terminal of the capacitor 100, transistor 200, or transistor 300.

[0390] Note that insulating materials suitable for use as interlayer films include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides, all possessing insulating properties. For example, by using a material with a low relative permittivity as the insulator for the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0391] For example, insulators 320, 322, 326, 352, 354, 212, 114, 150, and 156 are preferably insulators with a low relative permittivity. For example, the insulator preferably comprises silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, porous silicon oxide, resin, etc. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorinated silicon oxide, carbon-added silicon oxide, silicon oxide with carbon and nitrogen, or porous silicon oxide and resin. Because silicon oxide and silicon oxynitride are thermally stable, a thermally stable laminated structure with a low relative permittivity can be achieved by combining them with resin. Examples of resins include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins.

[0392] Additionally, the resistivity of the insulator disposed on or below conductor 152 or conductor 153 is 1.0 × 10⁻⁶. 12 Ωcm or more and 1.0×10 15 Below Ωcm, preferably 5.0 × 10 12 Ωcm or more and 1.0×10 14 Below Ωcm, more preferably 1.0 × 10 13 Ωcm or more and 5.0×10 13 Below Ωcm. By setting the resistivity of the insulator disposed on or below conductor 152 or conductor 153 to the above-mentioned range, the insulator can maintain insulation and disperse the charge accumulated between the wiring of transistor 200, transistor 300, capacitor 100, and conductor 152, etc., thereby suppressing the malfunction or electrostatic damage caused by the charge to the transistor and the semiconductor device including the transistor, and is therefore preferred. Silicon nitride or silicon oxynitride can be used as such an insulator. For example, the resistivity of insulator 160 or insulator 154 can be set to the above-mentioned range.

[0393] By surrounding a transistor using an oxide semiconductor with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, insulators such as insulator 324, insulator 350, and insulator 210 can be insulators that suppress the permeation of impurities such as hydrogen and oxygen.

[0394] As an insulator that suppresses impurities such as hydrogen and oxygen permeation, single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator that suppresses impurities such as hydrogen and oxygen permeation, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, as well as silicon oxynitride or silicon nitride, can be used.

[0395] The preferred conductor for use in wiring and plugs is a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, highly conductive semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0396] For example, conductors 328, 330, 356, 218, 112, 152, and 153 can be conductive materials such as metallic materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above-mentioned materials, either in single layers or in layers. Specifically, high-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. By using low-resistance conductive materials, wiring resistance can be reduced.

[0397] <Wires or connectors with oxide semiconductor layers>

[0398] Note that when an oxide semiconductor is used in a transistor 200, an insulator with an excess oxygen region is sometimes provided near the oxide semiconductor. In this case, it is preferable to provide a barrier insulator between the insulator with the excess oxygen region and the conductor provided in the insulator with the excess oxygen region.

[0399] For example, in Figure 12 In this configuration, it is preferable to place an insulator 241 between an insulator 280 containing excess oxygen and a conductor 240. Because the insulator 241 is arranged in contact with an insulator 274, a structure in which the conductor 240 and the transistor 200 are sealed by a barrier insulator can be achieved.

[0400] In other words, by providing insulator 241, the absorption of excess oxygen contained in insulator 280 by conductor 240 can be suppressed. Furthermore, by having insulator 241, the diffusion of hydrogen as an impurity through conductor 240 to transistor 200 can be suppressed.

[0401] Here, conductor 240 has the function of a plug or wiring that is electrically connected to transistor 200 or transistor 300.

[0402] The above is an explanation of the structural examples. By adopting this structure, miniaturization or high integration of semiconductor devices using transistors containing oxide semiconductors can be achieved. Furthermore, in semiconductor devices using transistors containing oxide semiconductors, variations in electrical characteristics can be suppressed and reliability improved. Additionally, a transistor containing oxide semiconductors with a large on-state current can be provided. Furthermore, a transistor containing oxide semiconductors with a small off-state current can be provided. Furthermore, a semiconductor device with low power consumption can be provided.

[0403] [Storage Device 2]

[0404] Figure 13 An example of a memory device using a semiconductor device as an embodiment of the present invention is shown. Figure 13 The storage device shown includes, in addition to Figure 12 In addition to the semiconductor devices shown, transistors 200, 300, and capacitor 100, transistor 400 is also included. Figure 13 The storage device shown is related to Figure 12 The differences in the storage device shown are as follows: capacitor 100 is planar; and transistors 200 and 300 are electrically connected.

[0405] In one embodiment of the storage device of the present invention, transistor 200 is disposed above transistor 300, and capacitor 100 is disposed above transistors 300 and 200. At least a portion of capacitor 100 or transistor 300 preferably overlaps transistor 200. This reduces the area occupied by capacitor 100, transistor 200, and transistor 300 in a top-view configuration, enabling miniaturization or high integration of the storage device of this embodiment.

[0406] Transistor 400 can control the second gate voltage of transistor 200. For example, a structure can be adopted in which the first and second gates of transistor 400 are connected to a source diode, and the source of transistor 400 is connected to the second gate of transistor 200. When the second gate of transistor 200 is maintained at a negative potential in this structure, the voltage between the first gate and source of transistor 400 and the voltage between the second gate and source of transistor 400 become 0V. In transistor 400, since the drain current is very small when the second gate voltage and the first gate voltage are 0V, the negative potential of the second gate of transistor 200 can be maintained for a long time even if no power is supplied to transistors 200 and 400. Therefore, a storage device including transistors 200 and 400 can retain stored content for a long period.

[0407] Therefore, in Figure 13 In this configuration, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the first gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Wiring 1006, 1007, 1008, and 1009 are also electrically connected.

[0408] Sometimes, the node where the gate of transistor 300, the source of transistor 200, and the drain of transistor 300 are connected to one of the electrodes of capacitor 100 is called node FG. Figure 13 The semiconductor device shown has the characteristic that the potential of the gate (node ​​FG) of transistor 300 can be maintained by switching transistor 200, thus enabling data writing, holding and reading.

[0409] In addition, by Figure 13 The storage device shown is Figure 12 The illustrated memory device is also configured in a matrix shape, which can form a memory cell array. Note that one transistor 400 can control the second gate voltage of multiple transistors 200. Therefore, it is preferable that the number of transistors 400 is less than the number of transistors 200.

[0410] Transistors 200 and 300 can be used as described in the above-described storage device 1. Therefore, for information regarding transistors 200, 300, and the layers comprising them, please refer to the description of storage device 1 above.

[0411] Conductor 218 is embedded in insulators 210, 212, 214, and 216. Conductor 218 is used as a plug or wiring for electrical connection to capacitor 100, transistor 200, transistor 300, or transistor 400. For example, conductor 218 is electrically connected to conductor 316, which is used as the gate electrode of transistor 300.

[0412] Conductor 240 is used as a plug or wiring for electrical connection to capacitor 100, transistor 200, transistor 300 or transistor 400. For example, conductor 240 electrically connects conductor 242b, which is used as another of the source and drain electrodes of transistor 200, and conductor 110, which is used as an electrode of capacitor 100.

[0413] Additionally, a planar capacitor 100 may be disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric. Note that the conductor 110, conductor 120, and insulator 130 may use the constituent elements described in the storage device 1 above.

[0414] In addition, although Figure 13 An example of using a planar capacitor as capacitor 100 is shown, but the semiconductor device shown in this embodiment is not limited to this. For example, capacitor 100 can be... Figure 12 The cylinder-shaped capacitor 100 is shown.

[0415] <Transistor 400>

[0416] Transistor 400 is formed on the same layer as transistor 200, thereby allowing them to be manufactured simultaneously. Transistor 400 includes: conductors 460 (conductors 460a and 460b) serving as a first gate; conductor 405 serving as a second gate; insulators 222 and 450 serving as gate insulators; oxide 430c including a channel forming region; conductors 442a, oxide 431b, and oxide 431a serving as a source; conductors 442b, oxide 432b, and oxide 432a serving as a drain; and conductors 440 (conductors 440a and 440b) serving as a connector.

[0417] Conductor 405 and conductor 205 are formed in the same layer. Oxides 431a and 432a are formed in the same layer as oxide 230a, and oxides 431b and 432b are formed in the same layer as oxide 230b. Conductors 442a and 442b are formed in the same layer as conductor 242. Oxide 430c and oxide 230c are formed in the same layer. Insulator 450 and insulator 250 are formed in the same layer. Conductor 460 and conductor 260 are formed in the same layer.

[0418] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing an oxide film that will become oxide 230c.

[0419] Similar to oxide 230, the oxide 430c used as the active layer of transistor 400 has fewer oxygen vacancies and impurities such as hydrogen and water. Therefore, the threshold voltage of transistor 400 can be increased, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are both 0V can be made very small.

[0420] <cut line>

[0421] The following describes the dicing lines (also called dividing lines, severing lines, or cut-off lines) used when dividing a large-area substrate into multiple semiconductor devices in the shape of a chip by dividing each semiconductor element. As a dicing method, for example, sometimes a groove (dicing line) for dividing the semiconductor element is first formed in the substrate, and then the substrate is cut off at the dicing line to obtain multiple semiconductor devices that have been divided (segmented).

[0422] Here, for example, such as Figure 13 As shown, it is preferable to design the area in contact with insulator 254 and insulator 222 as a cut line. That is, an opening is provided in insulator 224 near the area that forms a cut line with the edges of the memory cells including the plurality of transistors 200 and the transistors 400. Furthermore, insulator 254 is provided in such a way that it covers the sides of insulator 224.

[0423] In other words, insulator 222 and insulator 254 are in contact within the opening provided in insulator 224. For example, insulator 222 and insulator 254 can be formed using the same material and the same method. By using the same material and the same method to form insulator 222 and insulator 254, the tightness can be improved. For example, alumina is preferably used.

[0424] By employing this structure, insulators 222 and 254 can surround insulator 224, transistor 200, and transistor 400. Since insulators 222 and 254 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips to form the circuit region of the semiconductor element as shown in this embodiment, impurities such as hydrogen and water can be prevented from mixing in from the side direction of the truncated substrate and diffusing into transistor 200 or transistor 400.

[0425] By employing this structure, excess oxygen in insulator 224 can be prevented from diffusing to the outside through insulators 254 and 222. Therefore, excess oxygen in insulator 224 is efficiently supplied to the oxide forming the channel in transistor 200 or transistor 400. This oxygen reduces oxygen vacancies in the oxide forming the channel in transistor 200 or transistor 400. Consequently, the oxide forming the channel in transistor 200 or transistor 400 can become an oxide semiconductor with low defect state density and stable characteristics. In other words, reliability can be improved while suppressing variations in the electrical characteristics of transistor 200 or transistor 400.

[0426] This embodiment can be implemented by appropriately combining the structures described in other embodiments and examples.

[0427] (Implementation Method 3)

[0428] In this embodiment, refer to Figure 14A , Figure 14B as well as Figures 15A to 15H The following describes a storage device (hereinafter sometimes referred to as an OS storage device) using an oxide-based semiconductor transistor (hereinafter sometimes referred to as an OS transistor) and a capacitor, according to one embodiment of the present invention. An OS storage device is a storage device comprising at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of an OS transistor is extremely small, an OS storage device has excellent retention characteristics and can therefore be used as a non-volatile memory.

[0429] <Example of storage device structure>

[0430] Figure 14A An example of the structure of an OS storage device is shown. Storage device 1400 includes peripheral circuitry 1411 and a storage cell array 1470. Peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0431] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470, and its details are described below. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Furthermore, the row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and can select the row to be accessed.

[0432] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives external control signals (CE, WE, RE), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0433] The control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0434] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column configuration and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0435] In addition, although Figure 14A An example is shown where the peripheral circuitry 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited thereto. For example, as Figure 14B As shown, the memory cell array 1470 can also be arranged overlapping a portion of the peripheral circuitry 1411. For example, the readout amplifier can also be arranged overlapping the memory cell array 1470.

[0436] exist Figures 15A to 15H The text describes a structural example of a memory cell that can be used in the aforementioned memory cell MC.

[0437] [DOSRAM]

[0438] Figures 15A to 15C An example of the circuit structure of a DRAM memory cell is shown. In this specification and other materials, DRAM using a 1000 transistors and 1 capacitor type memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Figure 15AThe memory cell 1471 shown includes a transistor M1 and a capacitor CA. Furthermore, the transistor M1 includes a gate (sometimes referred to as the top gate) and a back gate.

[0439] The first terminal of transistor M1 is connected to the first terminal of capacitor CA. The second terminal of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0440] Wiring BIL is used as the bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. During data writing and reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0441] Here, Figure 15A The storage cell 1471 shown corresponds to Figure 12 The storage device shown is as follows: That is, transistor M1 corresponds to transistor 200, capacitor CA corresponds to capacitor 100, wiring BIL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, and wiring CAL corresponds to wiring 1005. Note that... Figure 12 The transistor 300 described corresponds to the one set in Figure 14B The transistors of the peripheral circuit 1411 of the storage device 1400 shown.

[0442] Furthermore, the memory cell MC is not limited to memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also adopt... Figure 15B The transistor M1 in the illustrated memory cell 1472 has a back gate that is not connected to wiring BGL, but to wiring WOL. Furthermore, for example, the memory cell MC can also be as follows: Figure 15C The memory cell shown is a memory cell 1473, which is composed of a single-gate transistor, i.e., a transistor M1 excluding the back gate.

[0443] When the semiconductor device shown in the above embodiment is used in memory cell 1471, transistor 200 can be used as transistor M1, and capacitor 100 can be used as capacitor CA. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be minimized. In other words, since the written data can be held by transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, the memory cell refresh operation can be eliminated. In addition, since the leakage current is minimal, multi-valued data or analog data can be stored in memory cells 1471, 1472, and 1473.

[0444] Furthermore, in DOSRAM, when the read amplifier is arranged in a manner overlapping the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cells.

[0445] [NOSRAM]

[0446] Figures 15D to 15G This illustrates an example of a gain-cell type memory cell with two transistors and one capacitor. Figure 15D The illustrated memory cell 1474 includes transistor M2, transistor M3, and capacitor CB. Furthermore, transistor M2 includes a top gate (sometimes simply referred to as the gate) and a back gate. In this specification and the like, a memory device that includes a gain-cell type memory cell using an OS transistor for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0447] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; transistor M2's gate is connected to wiring WOL; and transistor M2's back gate is connected to wiring BGL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0448] Wiring WBL is used as the write bit line, wiring RBL is used as the read bit line, and wiring WOL is used as the word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CB. It is preferable to apply a low-level potential to wiring CAL during data writing, holding, and reading. Wiring BGL is used to apply a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0449] Here, Figure 15DThe storage cell 1474 shown corresponds to Figure 13 The storage device shown is as follows: transistor M2 corresponds to transistor 200, capacitor CB corresponds to capacitor 100, transistor M3 corresponds to transistor 300, wiring WBL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, wiring CAL corresponds to wiring 1005, wiring RBL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0450] Furthermore, the memory cell MC is not limited to memory cell 1474, and its circuit structure can be appropriately modified. For example, the memory cell MC can also adopt... Figure 15E The transistor M2 in the illustrated memory cell 1475 has its back gate connected to the wiring BGL, but not to the wiring WOL. Furthermore, for example, the memory cell MC can also be as follows: Figure 15F The memory cell 1476 shown is a memory cell composed of a single-gate transistor, i.e., a transistor M2 excluding the back gate. Furthermore, for example, the memory cell MC may also have... Figure 15G The storage cell 1477 shown has a structure that combines wiring WBL and wiring RBL into a wiring BIL.

[0451] When the semiconductor device shown in the above embodiment is used in memory cell 1474, transistor 200 can be used as transistor M2, transistor 300 can be used as transistor M3, and capacitor 100 can be used as capacitor CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be minimized. Therefore, since the written data can be held by transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. Furthermore, memory cell refresh operations can be eliminated. Moreover, due to the minimal leakage current, multi-valued data or analog data can be stored in memory cell 1474. The same applies to memory cells 1475 to 1477.

[0452] Furthermore, transistor M3 can also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of a Si transistor can be n-channel or p-channel. The field-effect mobility of a Si transistor is sometimes higher than that of an OS transistor. Therefore, a Si transistor can also be used as the readout transistor M3. Furthermore, by using a Si transistor in transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the footprint of the memory cell and enabling high integration of the memory device.

[0453] Furthermore, transistor M3 can also be an OS transistor. When OS transistors are used for transistors M2 and M3, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0454] also, Figure 15H An example of a gain-cell type memory cell with 3 transistors and 1 capacitor is shown. Figure 15H The illustrated memory cell 1478 includes transistors M4 through M6 and capacitor CC. Capacitor CC can be appropriately configured. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0455] Transistor M4 is an OS transistor that includes a back gate, which is electrically connected to wiring BGL. Alternatively, the back gate and gate of transistor M4 can be electrically connected to each other. Or, transistor M4 may not include a back gate.

[0456] Furthermore, transistors M5 and M6 can each be either n-channel or p-channel Si transistors. Alternatively, transistors M4 through M6 can all be OS transistors. In this case, only n-type transistors can be used to construct the circuit in the memory cell array 1470.

[0457] When the semiconductor device shown in the above embodiment is used in the memory cell 1478, transistor 200 can be used as transistor M4, transistor 300 can be used as transistors M5 and M6, and capacitor 100 can be used as capacitor CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 can be minimized.

[0458] Note that the structure of the peripheral circuit 1411, the memory cell array 1470, etc., shown in this embodiment is not limited to the structure described above. Furthermore, the configuration or function of these circuits and the wiring and circuit elements connected to them can be changed, removed, or added as needed.

[0459] The structure shown in this embodiment can be used in appropriate combinations with structures described in other embodiments, examples, etc.

[0460] (Implementation Method 4)

[0461] In this embodiment, refer to Figure 16A and Figure 16BAn example of a chip 1200 in which the semiconductor device of the present invention is mounted is described. Multiple circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a System on Chip (SoC).

[0462] like Figure 16A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0463] A bump (not shown) is provided on chip 1200, and the bump is as follows: Figure 16B It is connected to the first side of the printed circuit board (PCB) 1201 as shown. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, which are connected to the motherboard 1203.

[0464] Alternatively, storage devices such as DRAM 1221 and flash memory 1222 can be provided on the motherboard 1203. For example, the DOSRAM shown in the above embodiment can be applied to the DRAM 1221. Furthermore, for example, the NOSRAM shown in the above embodiment can be applied to the flash memory 1222.

[0465] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Additionally, CPU 1211 and GPU 1212 may each have a memory for temporary data storage. Alternatively, a memory shared by both CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned NOSRAM or DOSRAM can be used in this memory. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations. By incorporating an image processing circuit or product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and product operations can be performed with low power consumption.

[0466] Furthermore, since the CPU1211 and GPU1212 are located on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation result from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed at high speed.

[0467] The analog arithmetic unit 1213 includes one or both of an analog-to-digital (A / D) conversion circuit and a digital-to-analog (D / A) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog arithmetic unit 1213.

[0468] The storage controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0469] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, imaging devices, and controllers. Controllers include mice, keyboards, and game console controllers. Universal Serial Bus (USB) and High-Definition Multimedia Interface (HDMI) (registered trademark) can be used as the interface.

[0470] Network circuit 1216 includes network circuits such as those for local area networks (LANs). Additionally, it may include network security circuits.

[0471] The aforementioned circuit (system) can be formed on chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, no additional manufacturing process is required, and chip 1200 can be manufactured at low cost.

[0472] The motherboard 1203, which includes a PCB 1201 with a chip 1200 having a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0473] The GPU module 1204 can reduce its size due to the presence of the chip 1200 using SoC technology. Furthermore, the GPU module 1204, with its high image processing capabilities, is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Moreover, by utilizing the product-sum operation circuitry of the GPU 1212, deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be executed, thereby enabling the chip 1200 to be used as an AI chip, or the GPU module to be used as an AI system module.

[0474] The structure shown in this embodiment can be appropriately combined with the structures shown in other embodiments, examples, etc.

[0475] (Implementation Method 5)

[0476] In this embodiment, an application example of a storage device using the semiconductor device described in the above embodiments is explained. The semiconductor device described in the above embodiments can be applied, for example, to the storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book reader terminals, digital cameras (including camcorders), video recording devices, navigation systems, etc.). Note that here, "computer" includes tablet computers, notebook computers, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiments can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB storage devices, and SSDs (solid-state drives). Figures 17A to 17E Several structural examples of removable storage devices are illustrated schematically. For example, the semiconductor devices shown in the above embodiments are fabricated into packaged memory chips and used in various storage devices or removable memories.

[0477] Figure 17A This is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1105, etc.

[0478] Figure 17B This is a schematic diagram of the SD card's appearance. Figure 17C This is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a frame 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the frame 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, data can be read from and written to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The semiconductor device described in the above embodiment can be assembled onto the memory chip 1114, etc.

[0479] Figure 17D This is a schematic diagram of the SSD's appearance. Figure 17EThis is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled onto the memory chip 1154, etc.

[0480] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0481] (Implementation Method 6)

[0482] The semiconductor device according to one aspect of the present invention can be applied to processors or chips such as CPUs and GPUs. Figures 18A to 18H Specific examples of electronic devices having a processor or chip such as a CPU or GPU according to one aspect of the present invention are shown.

[0483] <Electronic Devices and Systems>

[0484] The GPU or chip according to one aspect of the present invention can be installed in a wide variety of electronic devices. Examples of electronic devices include, in addition to television sets, displays for laptop information terminals, digital signage, and large-screen game consoles such as pinball machines, digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. Furthermore, by incorporating the GPU or chip according to one aspect of the present invention into an electronic device, the electronic device can possess artificial intelligence.

[0485] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0486] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0487] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, animated images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc. Figures 18A to 18H Examples of electronic devices are shown.

[0488] [Information Terminal]

[0489] Figure 18A A mobile phone (smartphone) is shown as one of the information terminals. The information terminal 5100 includes a housing 5101 and a display unit 5102. The display unit 5102 has a touch panel as an input interface, and buttons are provided on the housing 5101.

[0490] By applying a chip according to one aspect of the present invention to an information terminal 5100, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include applications that identify a session and display the content of that session on a display unit 5102, applications that identify text or graphics input by a user to a touch panel provided with the display unit 5102 and display that text or graphics on the display unit 5102, and applications that perform biometric identification such as fingerprints or voiceprints.

[0491] Figure 18B A notebook-type information terminal 5200 is shown. The notebook-type information terminal 5200 includes an information terminal body 5201, a display unit 5202, and a keyboard 5203.

[0492] Similar to the aforementioned information terminal 5100, by applying a chip according to one aspect of the present invention to the notebook information terminal 5200, applications utilizing artificial intelligence can be executed. Examples of such applications utilizing artificial intelligence include design support software, document proofreading software, and automatic menu generation software. Furthermore, by using the notebook information terminal 5200, novel artificial intelligence technologies can be developed.

[0493] Note that in the example above, Figure 18A and Figure 18B Examples of smartphones and laptops as electronic devices are shown, but other information terminals besides smartphones and laptops can also be applied. Examples of information terminals other than smartphones and laptops include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0494] [Game console]

[0495] Figure 18C A portable game console 5300 is shown as an example of a game console. The portable game console 5300 includes a frame 5301, a frame 5302, a frame 5303, a display unit 5304, a connector 5305, and operation keys 5306. Frames 5302 and 5303 can be detached from frame 5301. By attaching the connector 5305 provided in frame 5301 to another frame (not shown), the image output to display unit 5304 can be output to another video display device (not shown). At this time, frames 5302 and 5303 can each be used as controllers. Thus, multiple players can play games simultaneously. Chips, etc., as shown in the above embodiment, can be embedded in the substrates provided in frames 5301, 5302, and 5303.

[0496] in addition, Figure 18D The image shows a stationary game console 5400, one of the game consoles. The stationary game console 5400 is connected to a controller 5402 wirelessly or via a wired connection.

[0497] By applying a GPU or chip according to one aspect of the present invention to game consoles such as the portable game console 5300 and the stationary game console 5400, a low-power game console can be achieved. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat generation on the circuitry itself, peripheral circuits, and modules.

[0498] Furthermore, by applying a GPU or chip according to one aspect of the present invention to a portable game console 5300, a portable game console 5300 with artificial intelligence can be realized.

[0499] The progress of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are normally governed by the game's programming. However, by applying artificial intelligence to the portable game console 5300, it is possible to achieve performances that are not limited to the game's programming. For example, it is possible to display the content of the player's questions, the progress of the game, the time elapsed, and changes in the behavior of characters appearing in the game.

[0500] Furthermore, when playing games that require multiple players using the portable game console 5300, artificial intelligence can be used to create human-like game players, allowing one person to play a game that can be played by multiple people.

[0501] Although Figure 18C and Figure 18DPortable and stationary game consoles are shown as examples of game consoles, but game consoles using GPUs or chips according to one aspect of the present invention are not limited to these. Examples of game consoles using GPUs or chips according to one aspect of the present invention include arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0502] [Mainframe Computer]

[0503] A GPU or chip based on one aspect of this invention can be applied to large-scale computers.

[0504] Figure 18E The image shows the Supercomputer 5500 as an example of a large computer. Figure 18F The image shows the rack-mount computer 5502 included in the supercomputer 5500.

[0505] The supercomputer 5500 includes a rack 5501 and multiple rack-mounted computers 5502. Note that the multiple computers 5502 are housed in the rack 5501. Additionally, each computer 5502 has multiple substrates 5504 on which the GPU or chip described in the above embodiments can be mounted.

[0506] The Supercomputer 5500 is primarily a large-scale computer suitable for scientific computing. Scientific computing requires massive calculations at high speeds, resulting in high power consumption and significant chip heat generation. By applying a GPU or chip according to one aspect of this invention to the Supercomputer 5500, a low-power supercomputer can be realized. Furthermore, the low power consumption reduces heat generation from the circuitry, thereby minimizing the negative impacts of heat on the circuitry itself, peripheral circuits, and modules.

[0507] exist Figure 18E and Figure 18F The example shown is a supercomputer, but the supercomputer using a GPU or chip according to one aspect of the present invention is not limited to this. Examples of supercomputers using a GPU or chip according to one aspect of the present invention include service-providing computers (servers), large general-purpose computers (hosts), etc.

[0508] [Moving Object]

[0509] One embodiment of the present invention, the GPU or chip, can be applied to a car as a moving body and the area around the driver's seat of the car.

[0510] Figure 18G This is a diagram showing the perimeter of the windshield inside a car interior, illustrating an example of a moving object. Figure 18GDisplay panels 5701, 5702, and 5703 are shown mounted on the dashboard, and display panel 5704 is mounted on the support column.

[0511] Display panels 5701 to 5703 can provide various information by displaying speedometer, tachometer, distance traveled, fuel gauge, gear position, and air conditioning settings. Furthermore, users can appropriately change the displayed content and layout of the display panels according to their preferences, enhancing design flexibility. Display panels 5701 to 5703 can also be used as lighting devices.

[0512] By displaying images captured by a camera (not shown) installed in the vehicle on display panel 5704, blind spots (obstructions to the view) can be filled. In other words, by displaying images captured by a camera installed on the exterior of the vehicle, blind spots can be filled, thereby improving safety. Furthermore, by displaying images that supplement areas that are not visible, safety can be confirmed more naturally and comfortably. Display panel 5704 can also be used as a lighting device.

[0513] Because the GPU or chip of one aspect of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an autonomous driving system for automobiles. The chip can also be used in systems for navigation, hazard prediction, etc. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0514] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies, and the chip of one aspect of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0515] [Electrical Products]

[0516] Figure 18H An example of an electrical appliance is shown: an electric refrigerator / freezer 5800. The electric refrigerator / freezer 5800 includes a frame 5801, a refrigerator door 5802, and a freezer door 5803, etc.

[0517] By applying a chip according to one aspect of the present invention to an electric refrigerator / freezer 5800, an electric refrigerator / freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator / freezer 5800 can have the function of automatically generating a menu based on the food stored in the electric refrigerator / freezer 5800 or the consumption period of the food, and automatically adjusting the temperature of the electric refrigerator / freezer 5800 according to the stored food.

[0518] Electric refrigerators and freezers are one example of electrical appliances, but other electrical appliances that can be cited include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners (including air conditioners with heating and cooling), washing machines, dryers, and audio-visual equipment.

[0519] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and their effects can be implemented by appropriately combining them with descriptions of other electronic devices.

[0520] This embodiment can be implemented by appropriately combining the structures described in other embodiments, examples, etc.

[0521] [Example]

[0522] In this embodiment, the ease of forming another layer at the interface between the metal oxide and tantalum nitride in the stacked structure of metal oxide and tantalum nitride, the oxidation resistance of tantalum nitride, and the conductivity of tantalum nitride are evaluated. Specifically, various analyses are performed on samples (samples 1A to 5A) in which a tantalum nitride film is formed on a metal oxide film and samples (samples 1B to 5B) in which a tantalum nitride film is formed on a metal oxide film and subjected to heat treatment, and the thickness of the oxide film formed on the surface of the tantalum nitride film, the thickness of the layer formed at the interface between the metal oxide film and the tantalum nitride film, and the resistivity of the tantalum nitride film are calculated.

[0523] The manufacturing methods of samples 1A to 5A are described below.

[0524] A silicon-containing substrate was heat-treated in a hydrogen chloride (HCl) atmosphere to form a 100 nm thick silicon oxide film. Next, a 15 nm thick metal oxide film was formed on the silicon oxide film using sputtering. The following conditions were used for forming the metal oxide film: an oxide target with an In:Ga:Zn ratio of 4:2:4.1 (atomic ratio); oxygen gas at 45 sccm; a film-forming pressure of 0.7 Pa; a film-forming power of 0.5 kW; a substrate temperature of 200 °C; and a distance of 60 mm between the oxide target and the substrate.

[0525] Next, a tantalum nitride film with a thickness of 100 nm was formed on the aforementioned metal oxide film using a sputtering method. The following conditions were used when forming the tantalum nitride film: a tantalum metal target was used; the film formation pressure was 0.6 Pa; the film formation power was 1 kW; the substrate temperature was room temperature (RT); and the distance between the target and the substrate was 60 mm.

[0526] The differences among Sample 1A to Sample 5A lie in the flow rates of the film-forming gases used during the formation of the above tantalum nitride film. Specifically, in Sample 1A, 55 sccm of argon gas and 5 sccm of nitrogen gas are used. In Sample 2A, 50 sccm of argon gas and 10 sccm of nitrogen gas are used. In Sample 3A, 40 sccm of argon gas and 20 sccm of nitrogen gas are used. In Sample 4A, 30 sccm of argon gas and 30 sccm of nitrogen gas are used. In Sample 5A, 10 sccm of argon gas and 50 sccm of nitrogen gas are used.

[0527] Thus, Sample 1A to Sample 5A are manufactured.

[0528] Here, the higher the ratio of the flow rate of nitrogen gas to the flow rate of the above film-forming gas, the higher the atomic number ratio of nitrogen to tantalum in the tantalum nitride film. Therefore, the atomic number ratio of nitrogen to tantalum in the tantalum nitride film is high in the order of Sample 5A, Sample 4A, Sample 3A, Sample 2A, and Sample 1A.

[0529] Next, the manufacturing methods of Sample 1B to Sample 5B will be described. In the manufacturing methods of Sample 1B to Sample 5B, the steps until the formation of the tantalum nitride film are the same as those of the manufacturing methods of Sample 1A to Sample 5A.

[0530] Then, a heat treatment is performed. As this heat treatment, a treatment is carried out at a temperature of 400 °C for 1 hour in an oxygen atmosphere. Sample 1B is a sample obtained by performing this heat treatment on a sample having the same structure as Sample 1A. Sample 2B is a sample obtained by performing this heat treatment on a sample having the same structure as Sample 2A. Sample 3B is a sample obtained by performing this heat treatment on a sample having the same structure as Sample 3A. Sample 4B is a sample obtained by performing this heat treatment on a sample having the same structure as Sample 4A. Sample 5B is a sample obtained by performing this heat treatment on a sample having the same structure as Sample 5A.

[0531] Thus, Sample 1B to Sample 5B are manufactured.

[0532] Similar to Sample 1A to Sample 5A, the atomic number ratio of nitrogen to tantalum in the tantalum nitride film is high in the order of Sample 5B, Sample 4B, Sample 3B, Sample 2B, and Sample 1B.

[0533] <X-ray Diffraction Analysis>

[0534] Next, the results of X-ray diffraction (XRD: X-Ray Diffraction) measurement on Sample 1A to Sample 5A will be described.

[0535] In this embodiment, the Bruker D8 DISCOVER Hybrid XRD device was used. The measurement conditions were as follows: θ / 2θ scanning was performed using the out-of-plane method, with a scanning range of 15 degrees to 80 degrees, a step width of 0.02 degrees, and a cumulative time of 0.1 seconds for each point.

[0536] Figures 19A to 19E The results of the XRD spectrum obtained by out-of-plane measurement are shown. Figure 19A This is the XRD spectrum of sample 1A. Figure 19B This is the XRD spectrum of sample 2A. Figure 19C This is the XRD spectrum of sample 3A. Figure 19D This is the XRD spectrum of sample 4A. Figure 19E This is the XRD spectrum of sample 5A. Figures 19A to 19E In the diagram, the horizontal axis represents 2θ [deg.], and the vertical axis represents intensity [au]. Furthermore, the dashed lines shown near 2θ = 35deg. and 2θ = 40deg. indicate the peak positions showing the crystallinity of tantalum nitride.

[0537] according to Figures 19A to 19E It can be seen that the tantalum nitride films of samples 1A to 5A all have crystallinity.

[0538] <Cross-sectional STEM images and EDX analysis>

[0539] Next, the results of observations of samples 1B to 5B using scanning transmission electron microscopy (STEM) and the results of analysis using energy dispersive X-ray spectroscopy (EDX) will be described.

[0540] In this embodiment, the "HD-2700" manufactured by Hitachi High Technology Corporation was used to capture cross-sectional STEM images with an accelerating voltage of 200kV and to perform compositional linear analysis using EDX.

[0541] Linear compositional analysis using EDX was performed to calculate the thickness of the layer formed at the interface between the metal oxide film and the tantalum nitride film. Here, the thickness of this layer is defined as the difference between the location of the interface between this layer and the metal oxide film and the location of the interface between the bottom surface of the tantalum nitride film and this layer. Specifically, linear EDX analysis was performed on the layer and its surrounding area with the depth direction perpendicular to the substrate surface. Then, in the distribution of the quantitative values ​​of each element relative to the depth direction obtained through the above analysis, the depth (location) of the interface between this layer and the metal oxide film was defined as the depth where the quantitative value of the metal (gallium in this embodiment), a major component of the metal oxide film, is half of the quantitative value of the non-major component of the tantalum nitride film. Furthermore, the depth (location) of the interface between the bottom surface of the tantalum nitride film and this layer was defined as the depth where the quantitative value of oxygen in the metal oxide film is half of the quantitative value. Thus, the thickness of this layer can be calculated.

[0542] Figures 20A to 20E The image shown is a cross-sectional STAEM image. Figure 20A This is a cross-sectional STEM image of sample 1B. Figure 20B This is a cross-sectional STEM image of sample 2B. Figure 20C This is a cross-sectional STEM image of sample 3B. Figure 20D This is a cross-sectional STEM image of sample 4B. Figure 20E This is a cross-sectional STEM image of sample 5B. Note that... Figures 20A to 20E The cross-sectional STEM image shown is a phase-contrast image (TE image). Using... Figures 20A to 20E The cross-sectional STEM image shown measures the thickness of the oxide film formed on the surface of the tantalum nitride film.

[0543] Figure 21 The calculated thickness of the oxide film formed on the surface of the tantalum nitride film is shown. Figure 21 In the diagram, the bar chart on the left side of each sample represents the thickness of the oxide film [nm]. The thickness of the oxide film in sample 1B is 11.9 nm, in sample 2B it is 4.6 nm, in sample 3B it is 4.0 nm, in sample 4B it is 3.6 nm, and in sample 5B it is 5.3 nm.

[0544] Thus, the following tendency was confirmed: in tantalum nitride films, the greater the atomic ratio of nitrogen to tantalum, the thinner the oxide film. Therefore, it can be considered that in tantalum nitride films, the greater the atomic ratio of nitrogen to tantalum, the less likely an oxide film is to form on the surface of the tantalum nitride film; in other words, the greater the atomic ratio of nitrogen to tantalum in the tantalum nitride film, the less likely the tantalum nitride film is to oxidize.

[0545] in addition, Figure 21 The calculated thickness of the layer formed at the interface between the metal oxide film and the tantalum nitride film is shown. Figure 21 In the image, the bar chart on the right side of each sample represents the thickness of the layer [nm]. The thickness of the layer in sample 1B is 7.4 nm, the thickness in sample 2B is 3.4 nm, the thickness in sample 3B is 2.0 nm, the thickness in sample 4B is 1.4 nm, and the thickness in sample 5B is 0.8 nm.

[0546] Thus, the following tendency was confirmed: in tantalum nitride films, the greater the atomic ratio of nitrogen to tantalum, the smaller the thickness of the aforementioned layer. Therefore, it can be considered that in tantalum nitride films, the greater the atomic ratio of nitrogen to tantalum, the less likely a layer is to form between the tantalum nitride film and the metal oxide.

[0547] <Resistivity>

[0548] Next, the resistivity of the tantalum nitride film in samples 1B to 5B was calculated. Specifically, the sheet resistance was measured at five points on each surface of samples 1B to 5B, and the average sheet resistance measured at the five points was calculated. This average value was then converted to 100 nm (the target thickness) to calculate the resistivity of the tantalum nitride film. A resistivity meter (trade name: Σ-10) manufactured by NPS Corporation was used for the measurement.

[0549] Figure 21 The calculated resistivity of the tantalum nitride film is shown. Figure 21 In the diagram, the circles represent the resistivity [Ω·cm] of the tantalum nitride film. The resistivity of the tantalum nitride film in sample 1B is 2.9 × 10⁻⁶. -4 The resistivity of the tantalum nitride film in sample 2B is 4.6 × 10 Ω·cm. -4 The resistivity of the tantalum nitride film in sample 3B is 1.5 × 10 Ω·cm. -3 The resistivity of the tantalum nitride film in sample 4B is 6.5 × 10 Ω·cm. -3 The resistivity of the tantalum nitride film in sample 5B is 1.1 × 10 Ω·cm. -2 Ω·cm.

[0550] Thus, the following tendency was confirmed: in tantalum nitride films, the smaller the atomic ratio of nitrogen to tantalum, the lower the resistivity of the tantalum nitride film. Therefore, it can be considered that in tantalum nitride films, the smaller the atomic ratio of nitrogen to tantalum, the higher the conductivity of the tantalum nitride film.

[0551] At least a portion of the structures, methods, etc. shown in this embodiment can be implemented in appropriate combinations with the embodiments described in this specification.

[0552] [Symbol Explanation]

[0553] 100: Capacitor, 110: Conductor, 112: Conductor, 114: Insulator, 120: Conductor, 130: Insulator, 140: Insulator, 150: Insulator, 152: Conductor, 153: Conductor, 154: Insulator, 156: Insulator, 160: Insulator, 200: Transistor, 205: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 231: Region, 231a: Region, 231b: Region, 234: Region, 240: Conductor, 240a: Conductor, 240b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor, 242a: Conductor, 242a1: Conductor, 242a2: Conductor, 242a3: Conductor, 242A: Conductive film, 242A1: Conductive film, 242A2: Conductive film, 242b: Conductor, 242b1: Conductor, 242b2: Conductor, 242b3: Conductor, 242B: Conductive layer, 242B1: Conductive layer, 242B2: Conductive layer, 250: Insulator, 250A: Insulating film, 254: Insulator, 254A: Insulating film, 260: Conductor, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 274: Insulator, 280: Insulator, 281: Insulator, 300: Transistor, 311: Substrate, 312: Insulator, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 3 54: Insulator, 356: Conductor, 400: Transistor, 405: Conductor, 430c: Oxide, 431a: Oxide, 431b: Oxide, 432a: Oxide, 432b: Oxide, 440: Conductor, 440a: Conductor, 440b: Conductor, 442a: Conductor, 442b: Conductor, 450: Insulator, 460: Conductor, 460a: Conductor, 460b: Conductor, 1001: Wiring, 1002: Wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring, 1007: Wiring, 1008: Wiring, 1009: Wiring, 1010: Wiring.

Claims

1. A semiconductor device, comprising: First oxide; The second oxide on the first oxide; The first insulator on the second oxide; The first conductor on the first insulator; as well as The second and third conductors on the second oxide, The second conductor includes a first region and a second region. The third conductor includes a third region and a fourth region. The second region is located above the first region. The fourth region is located above the third region. Both the second conductor and the third conductor contain tantalum and nitrogen. The nitrogen-to-tantalum atomic ratio in the first region is higher than that in the second region. The nitrogen-to-tantalum atomic ratio in the third region is higher than that in the fourth region. The second conductor also includes a fifth region. The third conductor also includes a sixth region. The fifth region is located above the second region. The sixth region is located above the fourth region. The nitrogen-to-tantalum atomic ratio in the fifth region is higher than that in the second region. Furthermore, the ratio of nitrogen to tantalum atoms in the sixth region is higher than that in the fourth region.

2. The semiconductor device according to claim 1, A second insulator is provided on the second conductor and the third conductor.

3. A semiconductor device, comprising: First oxide; The second oxide on the first oxide; The first insulator on the second oxide; The first conductor on the first insulator; The second conductor and the third conductor on the second oxide; The fourth conductor on the second conductor; as well as The fifth conductor on the third conductor. The second and third conductors are made of conductive materials that have the properties of extracting hydrogen and are not easily oxidized. The conductivity of the fourth and fifth conductors is higher than that of the second and third conductors. The second conductor includes a first region and a second region. The third conductor includes a third region and a fourth region. The second region is located above the first region. The fourth region is located above the third region. Each of the second and third conductors comprises tantalum and nitrogen. The nitrogen-to-tantalum atomic ratio in the first region is higher than that in the second region. The nitrogen-to-tantalum atomic ratio in the third region is higher than that in the fourth region. The second conductor also includes a fifth region. The third conductor also includes a sixth region. The fifth region is located above the second region. The sixth region is located above the fourth region. The nitrogen-to-tantalum atomic ratio in the fifth region is higher than that in the second region. Furthermore, the ratio of nitrogen to tantalum atoms in the sixth region is higher than that in the fourth region.

4. The semiconductor device according to claim 3, A second insulator is provided on the fourth conductor and the fifth conductor.

5. The semiconductor device according to claim 1 or 3, The first oxide comprises indium, element M, and zinc, wherein M is aluminum, gallium, yttrium, or tin.

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