Display panel and display device

Abstract

The present invention discloses a display panel and a display device, which relate to the field of display technology. The display panel comprises: a driving circuit, the driving circuit comprises N-stage shift registers cascaded to each other, N≥2; the shift register comprises: a first control unit; a second control unit; a third control unit; a fourth control unit, the fourth control unit is used to receive a third voltage signal and a fourth voltage signal, and generate an output signal in response to a signal of a second node and a signal of a fourth node; wherein the third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal; the potential of the first voltage signal is higher than the potential of the third voltage signal, and / or the potential of the second voltage signal is lower than the potential of the fourth voltage signal. The present invention solves the problem in the prior art that the shift register cannot meet the different voltage requirements of the pixel circuit for different signals.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a display panel and a display device. Background Art

[0002] At present, display technology is widely used in televisions, mobile phones and public information display, bringing great convenience to people's daily life and work. In the prior art, a display panel used to display images needs to use a scanning driving circuit to provide a driving signal to a pixel circuit to control the display panel to implement the scanning function, so that the image data input to the display panel can be refreshed in real time, thereby realizing dynamic display.

[0003] However, the existing scan driving circuit cannot meet the different voltage requirements of the pixel circuit for different signals. Summary of the invention

[0004] In view of this, the present invention provides a display panel and a display device to solve the problem in the prior art that the shift register cannot meet the different voltage requirements of the pixel circuit for different signals.

[0005] The present invention provides a display panel, comprising: a driving circuit, the driving circuit comprising N-stage shift registers cascaded with each other, N≥2; the shift register comprising: a first control unit, the first control unit is used to receive an input signal and control the signal of a first node in response to a first clock signal; a second control unit, the second control unit is used to receive a first voltage signal and a second voltage signal, and control the signal of the second node in response to the signal of the first node, the first clock signal, and the second clock signal; a third control unit, the third control unit is used to receive the first voltage signal and the second voltage signal, and control the signal of a fourth node in response to the signal of the second node and the signal of the third node, wherein the third node is connected to the first node, the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal; a fourth control unit, the fourth control unit is used to receive the third voltage signal and the fourth voltage signal, and generate an output signal in response to the signal of the second node and the signal of the fourth node; wherein the third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal; the potential of the first voltage signal is higher than the potential of the third voltage signal, and / or the potential of the second voltage signal is lower than the potential of the fourth voltage signal.

[0006] Based on the same concept, the present invention further provides a display device, which includes the above-mentioned display panel.

[0007] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0008] In the display panel provided by the present invention, the first control unit, the second control unit and the third control unit control the signal of the second node and the signal of the fourth node based on the input signal, the first clock signal, the second clock signal, the first voltage signal and the second voltage signal, and the fourth control unit is used to receive the third voltage signal and the fourth voltage signal, and generate an output signal in response to the signal of the second node and the signal of the fourth node controlled by the first control unit, the second control unit and the third control unit, that is, the first control unit, the second control unit and the third control unit are the control parts in the shift register, which play a control role. The fourth control unit is the output part in the shift register, which is used to generate an output signal. The voltage signal (the third voltage signal and the fourth voltage signal) received by the fourth control unit is set separately from the voltage signal (the first voltage signal and the second voltage signal) received by the first control unit, the second control unit and the third control unit, that is, the voltage signal of the control part in the shift register is set separately from the voltage signal of the output part, so that the voltage signal received by the fourth control unit can be set according to the requirements of the pixel circuit in the display panel for different signals, and the required signal can be selectively output, thereby improving the flexibility of the signal output by the driving circuit.

[0009] Furthermore, since the potential of the first voltage signal is higher than the potential of the third voltage signal, and / or the potential of the second voltage signal is lower than the potential of the fourth voltage signal, the waveform stability of the output signal generated by the fourth control unit can be improved, thereby improving the stability of the signal output by the driving circuit.

[0010] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0011] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0013] Figure 1 is a plan view schematic diagram of a display panel provided by the present invention;

[0014] Figure 2 It is a structural schematic diagram of a driving circuit provided by the present invention;

[0015] Figure 3 It is a schematic diagram of the framework structure of a shift register provided by the present invention;

[0016] Figure 4 It is a circuit diagram of a shift register provided by the present invention;

[0017] Figure 5 It is a circuit diagram of another shift register provided by the present invention;

[0018] Figure 6 It is a circuit diagram of another shift register provided by the present invention;

[0019] Figure 7 It is a circuit diagram of another shift register provided by the present invention;

[0020] Figure 8 It is a circuit diagram of another shift register provided by the present invention;

[0021] Fig. 9 It is a circuit diagram of another shift register provided by the present invention;

[0022] Fig.10 It is a circuit diagram of another shift register provided by the present invention;

[0023] Fig.11 It is a circuit diagram of another shift register provided by the present invention;

[0024] Fig.12 It is a driving timing diagram of the shift register provided by the present invention;

[0025] Fig.13 is another driving timing diagram of the shift register provided by the present invention;

[0026] Fig.14 is a structural schematic diagram of another driving circuit provided by the present invention;

[0027] Fig.15 is a structural schematic diagram of another driving circuit provided by the present invention;

[0028] Fig.16 is a circuit schematic diagram of a pixel circuit provided by the present invention;

[0029] Fig.17 is a circuit schematic diagram of another pixel circuit provided by the present invention;

[0030] Fig.18 is a plan view schematic diagram of another display panel provided by the present invention;

[0031] Fig.19 is a plan view schematically showing another display panel provided by the present invention;

[0032] Fig. 20 It is a plan schematic diagram of a display device provided by the present invention. DETAILED DESCRIPTION

[0033] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0034] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0035] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0036] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0037] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0038] Figure 1 is a schematic plan view of a display panel provided by the present invention, with reference to Figure 1 This embodiment provides a display panel, including: a driving circuit 100 and a plurality of pixels 200, each pixel 200 having a pixel circuit 210. The driving circuit 100 is connected to the pixel circuit 210 via a signal line to provide a driving signal to the pixel circuit 210, so that the pixel circuit 210 drives the pixel 200 to emit light and display a picture.

[0039] It should be noted that Figure 1 In the following, only one display panel structure is used as an example for explanation. Figure 1 It is exemplarily shown that the driving circuit 200 is located on one side of the display panel. In other embodiments of the present invention, the driving circuit 200 may also be located on both sides of the display panel, which will not be described in detail herein.

[0040] Figure 2 is a schematic diagram of the structure of a driving circuit provided by the present invention, Figure 3 is a schematic diagram of the framework structure of a shift register provided by the present invention, with reference to Figure 2 and Figure 3 In the embodiment of the present invention, the driving circuit 100 in the display panel includes N stages of shift registers 110 cascaded to each other, where N≥2;

[0041] The shift register 110 in the driving circuit 100 includes a first control unit 10 , a second control unit 20 , a third control unit 30 and a fourth control unit 40 .

[0042] The first control unit 10 is used to receive an input signal IN and control a signal of the first node N1 in response to a first clock signal CK;

[0043] The second control unit 20 is used to receive the first voltage signal VGH1 and the second voltage signal VGL1, and control the signal of the second node N2 in response to the signal of the first node N1, the first clock signal CK, and the second clock signal XCK;

[0044] The third control unit 30 is used to receive the first voltage signal VGH1 and the second voltage signal VGL1, and control the signal of the fourth node N4 in response to the signal of the second node N2 and the signal of the third node N3, wherein the third node N3 is connected to the first node N1, the first voltage signal VGH1 is a high level signal, and the second voltage signal VGL1 is a low level signal;

[0045] The fourth control unit 40 is used to receive the third voltage signal VGH2 and the fourth voltage signal VGL2, and generate an output signal OUT in response to the signal of the second node N2 and the signal of the fourth node N4; wherein the third voltage signal VGH2 is a high-level signal, and the fourth voltage signal VGL2 is a low-level signal; the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and / or the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2.

[0046] Specifically, in the embodiment of the present invention, the first control unit 10, the second control unit 20 and the third control unit 30 control the signal of the second node N2 and the signal of the fourth node N4 based on the input signal IN, the first clock signal CK, the second clock signal XCK, the first voltage signal VGH1 and the second voltage signal VGL1, and the fourth control unit 40 is used to receive the third voltage signal VGH2 and the fourth voltage signal VGL2, and respond to the signal of the second node N2 and the signal of the fourth node N4 controlled by the first control unit 10, the second control unit 20 and the third control unit 30, and generate the output signal OUT, that is, the first control unit 10, the second control unit 20 and the third control unit 30 are the control part of the shift register 110, and play a control role. The fourth control unit 40 is the output part of the shift register 110, and is used to generate an output signal. The voltage signal (the third voltage signal VGH2 and the fourth voltage signal VGL2) received by the fourth control unit 40 is separately set from the voltage signal (the first voltage signal VGH1 and the second voltage signal VGL1) received by the first control unit 10, the second control unit 20 and the third control unit 30, that is, the voltage signal of the control part and the voltage signal of the output part in the shift register 110 are separately set, so that the voltage signal received by the fourth control unit 40 can be set according to the requirements of the pixel circuit in the display panel for different signals, and can selectively output the required signal, thereby improving the flexibility of the signal output by the driving circuit 100.

[0047] Moreover, since the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and / or the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2, the waveform stability of the output signal OUT generated by the fourth control unit 40 can be improved, thereby improving the stability of the signal output by the driving circuit 100.

[0048] Figure 4 is a circuit diagram of a shift register provided by the present invention, with reference to Figure 4 , Optionally, the fourth control unit 40 includes a first transistor M1 and a second transistor M2;

[0049] The first transistor M1 receives the third voltage signal VGH2 , and the second transistor M2 receives the fourth voltage signal VGL2 to generate an output signal OUT.

[0050] Specifically, the fourth control unit 40 includes a first transistor M1 and a second transistor M2. The first transistor M1 receives a third voltage signal VGH2, and the second transistor M2 receives a fourth voltage signal VGL2 to generate an output signal OUT. The output signal OUT is controlled by the first transistor M1 and the second transistor M2 respectively. When the first transistor M1 is turned on, the output signal OUT is the third voltage signal VGH2. When the second transistor M2 is turned on, the output signal OUT is the fourth voltage signal VGL2.

[0051] Continue to refer Figure 4 , optionally, wherein the first transistor M1 and the second transistor M2 are both PMOS transistors;

[0052] The first transistor M1 has a source connected to the third voltage signal VGH2, a drain connected to the output signal OUT, and a gate connected to the fourth node N4;

[0053] The second transistor M2 has a source connected to the fourth voltage signal VGL2 , a drain connected to the output signal OUT, and a gate connected to the second node N2 .

[0054] Specifically, when the fourth node N4 is at a low level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the fourth node N4 is at a high level, the first transistor M1 is turned off. When the second node N2 is at a low level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. When the second node N2 is at a high level, the second transistor M2 is turned off. That is, the high level of the output signal OUT is determined by the fourth node N4, and the low level of the output signal OUT is determined by the second node N2.

[0055] Figure 5 is a circuit diagram of another shift register provided by the present invention, referring to Figure 5 , optionally, wherein the first transistor M1 and the second transistor M2 are both NMOS transistors;

[0056] The first transistor M1 has a source connected to the third voltage signal VGH2, a drain connected to the output signal OUT, and a gate connected to the second node N2;

[0057] The second transistor M2 has a source connected to the fourth voltage signal VGL2 , a drain connected to the output signal OUT, and a gate connected to the fourth node N4 .

[0058] Specifically, when the second node N2 is at a low level, the first transistor M1 is turned off. When the second node N2 is at a high level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the fourth node N4 is at a low level, the second transistor M2 is turned off. When the fourth node N4 is at a high level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. That is, the high level of the output signal OUT is determined by the second node N2, and the low level of the output signal OUT is determined by the fourth node N4.

[0059] Figure 6 is a circuit diagram of another shift register provided by the present invention, referring to Figure 6 , optionally, wherein the first transistor M1 and the second transistor M2 are both PMOS transistors;

[0060] The first transistor M1 has a source connected to the third voltage signal VGH2, a drain connected to the output signal OUT, and a gate connected to the second node N2;

[0061] The second transistor M2 has a source connected to the fourth voltage signal VGL2 , a drain connected to the output signal OUT, and a gate connected to the fourth node N4 .

[0062] Specifically, when the second node N2 is at a low level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the second node N2 is at a high level, the first transistor M1 is turned off. When the fourth node N4 is at a low level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. When the fourth node N4 is at a high level, the second transistor M2 is turned off. That is, the high level of the output signal OUT is determined by the second node N2, and the low level of the output signal OUT is determined by the fourth node N4.

[0063] Figure 7 is a circuit diagram of another shift register provided by the present invention, referring to Figure 7 , optionally, wherein the first transistor M1 and the second transistor M2 are both NMOS transistors;

[0064] The first transistor M1 has a source connected to the third voltage signal VGH2, a drain connected to the output signal OUT, and a gate connected to the fourth node N4;

[0065] The second transistor M2 has a source connected to the fourth voltage signal VGL2 , a drain connected to the output signal OUT, and a gate connected to the second node N2 .

[0066] Specifically, when the fourth node N4 is at a low level, the first transistor M1 is turned off. When the fourth node N4 is at a high level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the drain of the first transistor M1 to generate the output signal OUT. When the second node N2 is at a low level, the second transistor M2 is turned off. When the second node N2 is at a high level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the drain of the second transistor M2 to generate the output signal OUT. That is, the high level of the output signal OUT is determined by the fourth node N4, and the low level of the output signal OUT is determined by the second node N2.

[0067] Based on any of the above embodiments, in some embodiments of the present invention, in order to ensure the stability of the potentials of the second node N2 and the fourth node N4 and the stability of the output signal OUT, optionally, the fourth control unit 40 further includes a first capacitor C1 and a second capacitor C2.

[0068] Figure 8 is a circuit diagram of another shift register provided by the present invention, referring to Figure 8 The first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL2.

[0069] Fig. 9 is a circuit diagram of another shift register provided by the present invention, referring to Fig. 9 The first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the third voltage signal VGH2.

[0070] Fig.10 is a circuit diagram of another shift register provided by the present invention, referring to Fig. 9 and Fig.10 The first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the third voltage signal VGH2.

[0071] Fig.11 is a circuit diagram of another shift register provided by the present invention, referring to Fig.11The first plate of the first capacitor C1 is connected to the second voltage signal VGL1, and the second plate of the first capacitor C1 is connected to the fourth node N4. The first plate of the second capacitor C2 is connected to the second node N2, and the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL2.

[0072] In other embodiments of the present application, the second plate of the first capacitor C1 is connected to the fourth node N4, the connection method of the first plate of the first capacitor C1 can be adjusted, the first plate is connected to one of the first voltage signal VGH1, the second voltage signal VGL1, the third voltage signal VGH2, the fourth voltage signal VGL2 and the output signal OUT, and the potential of the fourth node N4 is stabilized by a fixed potential or an output signal.

[0073] The first plate of the second capacitor C2 is connected to the second node N2, and the connection method of the second plate of the second capacitor C2 can be adjusted. The second plate is connected to one of the first voltage signal VGH1, the second voltage signal VGL1, the third voltage signal VGH2, the fourth voltage signal VGL2 and the output signal OUT, and the potential of the second node N2 is stabilized by a fixed potential or an output signal.

[0074] Based on any of the above embodiments, Figures 8 to 11 As shown, optionally, the first control unit 10 includes: a fifth transistor M5, a source of the fifth transistor M5 is connected to the input signal IN, a drain is connected to the first node N1, and a gate is connected to the first clock signal CK.

[0075] The second control unit 20 includes: a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a fifth capacitor C5, wherein the source of the sixth transistor M6 is connected to the first node N1, the drain is connected to the drain of the seventh transistor M7, and the gate is connected to the second clock signal XCK; the source of the seventh transistor M7 is connected to the first voltage signal VGH1, the drain is connected to the drain of the sixth transistor M6, and the gate is connected to the fifth node N5; the source of the eighth transistor M8 is connected to the first clock signal CK, the drain is connected to the fifth node N5, and the gate is connected to the first node N1; The source of the transistor M9 is connected to the second clock signal XCK, the drain is connected to the fifth node N5, and the gate is connected to the first clock signal CK; the source of the tenth transistor M10 is connected to the second clock signal XCK, the drain is connected to the sixth node N6, and the gate is connected to the fifth node N5; the source of the eleventh transistor M11 is connected to the sixth node N6, the drain is connected to the second node N2, and the gate is connected to the second clock signal XCK; the source of the twelfth transistor M12 is connected to the first voltage signal VGH1, the drain is connected to the second node N2, and the gate is connected to the third node N3; the first electrode of the fifth capacitor C5 is connected to the fifth node N5, and the second electrode of the fifth capacitor C5 is connected to the sixth node N6.

[0076] Based on any of the above embodiments, Figures 8 to 11 As shown, optionally, the second control unit 20 further includes a thirteenth transistor M13 and a fourteenth transistor M14.

[0077] Among them, the source of the thirteenth transistor M13 is connected to the fifth node N5, the drain is connected to the gate of the tenth transistor M10, and the gate is connected to the second voltage signal VGL1; the source of the fourteenth transistor M14 is connected to the first node N1, the drain is connected to the third node N3, and the gate is connected to the second voltage signal VGL1.

[0078] Based on any of the above embodiments, Figures 8 to 11 As shown, optionally, the third control unit 30 includes a third transistor M3 and a fourth transistor M4.

[0079] The source of the third transistor M3 is connected to the first voltage signal VGH1, the drain is connected to the fourth node N4, and the gate is connected to the second node N2; the source of the fourth transistor M4 is connected to the second voltage signal VGL1, the drain is connected to the fourth node N4, and the gate is connected to the third node N3.

[0080] Since the first transistor M1 and the second transistor M2 are output transistors, in order to ensure the stability of the output signal OUT, the requirements for the output performance of the first transistor M1 and the second transistor M2 are higher. Therefore, in some embodiments of the present invention, in order to improve the output performance of the first transistor M1 and the second transistor M2, the width-to-length ratio of the channel region of the first transistor M1 is greater than the width-to-length ratio of the channel region of the third transistor M3, and / or the width-to-length ratio of the channel region of the second transistor M2 is greater than the width-to-length ratio of the channel region of the fourth transistor M4.

[0081] Based on any of the above embodiments, Figures 8 to 11 As shown, optionally, the third control unit 30 further includes a third capacitor C3 and a fourth capacitor C4.

[0082] Among them, the first plate of the third capacitor C3 is connected to the first voltage signal VGH1, and the second plate of the third capacitor C3 is connected to the second node N2; the first plate of the fourth capacitor C4 is connected to the second clock signal XCK or the second voltage signal VGL1, and the second plate of the fourth capacitor C4 is connected to the third node N3.

[0083] Since the first capacitor C1 and the second capacitor C2 are used to stabilize the potentials of the second node N2 and the fourth node N4, and thus stabilize the output signal OUT, the capacitances of the first capacitor C1 and the second capacitor C2 need to be large enough to ensure that the potentials of the second node N2 and the fourth node N4 do not fluctuate easily.

[0084] Based on this, in some embodiments of the present invention, the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are greater than the capacitance value of the third capacitor C3, and greater than the capacitance value of the fourth capacitor C4. Of course, the present invention is not limited to this. In other embodiments, in order to simplify the manufacturing process, the capacitance value of the first capacitor C1, the capacitance value of the second capacitor C2, the capacitance value of the third capacitor C3 and the capacitance value of the fourth capacitor C4 can also be equal.

[0085] Optionally, in some other embodiments of the present invention, in order to ensure the stability of the potential of the second node N2 and the fourth node N4, the capacitance value of the fifth capacitor C5 can also be made smaller than the capacitance value of the first capacitor C1, and smaller than the capacitance value of the second capacitor C2. And because the stability of the second node N2 and the fourth node N4 will affect the stability of the output signal OUT, and the stability of the fifth node N5 has little effect on the stability of the output signal OUT, therefore, the fifth capacitor C5 can be set smaller to save space.

[0086] Optionally, in some other embodiments of the present invention, the capacitance value of the fifth capacitor C5 is smaller than the capacitance value of the third capacitor C3 and smaller than the capacitance value of the fourth capacitor C4. The fifth capacitor C5 can be further set to be smaller to save space.

[0087] The working process of the shift register of the present invention is described below in conjunction with the timing diagram of each signal in the shift register.

[0088] Fig.12 This is a driving timing diagram of the shift register provided by the present invention. Figure 8 and Fig.12 .

[0089] In the T1 stage, the input signal IN is at a high level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, so that the fifth node N5 is at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 maintains a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the twelfth transistor M12 is turned off, the second node N2 maintains a high level, the second transistor M2 is turned off, the third transistor M3 is turned off, the third node N3 maintains a high level, the fourth transistor M4 is turned off, the fourth node N4 maintains a low level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the output end, so that the output signal OUT is a high level.

[0090] In the T2 stage, the input signal IN is at a high level, the first clock signal CK is at a high level, the fifth transistor M5 is turned off, the ninth transistor M9 is turned off, the first node N1 maintains a high level, the second clock signal XCK is at a low level, the sixth transistor M6 is turned on, the eighth transistor M8 is turned off, the fifth node N5 maintains a low level, the tenth transistor M10 is turned on, and the second clock signal XCK is transmitted to the sixth node N6, so that the sixth node N6 is at a low level, the eleventh transistor M11 is turned on, and the signal of the sixth node N6 is transmitted to the second node N2, so that the second node N2 is at a low level, the third transistor M3 is turned on, the first voltage signal VGH1 is transmitted to the fourth node N4, so that the fourth node N4 is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the output end, so that the output signal OUT is at a low level.

[0091] In the T3 stage, the input signal IN is at a high level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is at a high level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, so that the fifth node N5 is at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 maintains a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, the twelfth transistor M12 is turned off, the third transistor M3 is turned off, the third node N3 maintains a high level, the fourth transistor M4 is turned off, the fourth node N4 maintains a high level, the first transistor M1 is turned off, the second node N2 maintains a low level, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the output end, so that the output signal OUT is a low level.

[0092] In the T4 stage, the input signal IN is at a low level, the first clock signal CK is at a high level, the fifth transistor M5 is turned off, the ninth transistor M9 is turned off, the first node N1 maintains a high level, the second clock signal XCK is at a low level, the sixth transistor M6 is turned on, the eighth transistor M8 is turned off, the fifth node N5 maintains a low level, the tenth transistor M10 is turned on, and the second clock signal XCK is transmitted to the sixth node N6, so that the sixth node N6 is at a low level, the eleventh transistor M11 is turned on, and the signal of the sixth node N6 is transmitted to the second node N2, so that the second node N2 is at a low level, the third transistor M3 is turned on, the first voltage signal VGH1 is transmitted to the fourth node N4, so that the fourth node N4 is at a high level, the first transistor M1 is turned off, the second transistor M2 is turned on, and the fourth voltage signal VGL2 is transmitted to the output end, so that the output signal OUT is at a low level.

[0093] In the T5 phase, the input signal IN is at a low level, the first clock signal CK is at a low level, the fifth transistor M5 is turned on, the input signal IN is transmitted to the first node N1, so that the first node N1 is at a low level, the ninth transistor M9 is turned on, the second voltage signal VGL1 is transmitted to the fifth node N5, so that the fifth node N5 is at a low level, the tenth transistor M10 is turned on, the second clock signal XCK is at a high level, the sixth node N6 maintains a high level, the sixth transistor M6 is turned off, the eleventh transistor M11 is turned off, and the first node N1 controls the twelfth transistor M12 to conduct. The first transistor M1 is turned on, the first voltage signal VGH1 is transmitted to the second node N2, so that the second node N2 is at a high level, the third transistor M3 is turned off, the second transistor M2 is turned off, the fourteenth transistor M14 is turned on, the signal of the first node N1 is transmitted to the third node N3, the third node N3 is at a low level, the third node N3 controls the fourth transistor M4 to be turned on, the second voltage signal VGL1 is transmitted to the fourth node N4, so that the fourth node N4 is at a low level, the first transistor M1 is turned on, and the third voltage signal VGH2 is transmitted to the output end, so that the output signal OUT is at a high level.

[0094] Fig. 9 In the shift register shown, although the types of the first transistor M1 and the second transistor M2 are the same as Figure 8 The first transistor M1 and the second transistor M2 in the shift register shown are of different types. However, in the stages T1 to T5, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are the same as those in the above process. Fig. 9 The voltage signal of the first transistor M1 input is Figure 8 The voltage signal input to the first transistor M1 is different. Fig. 9 The voltage signal of the second transistor M2 input is Figure 8 The voltage signal input to the second transistor M2 is also different, therefore, Fig. 9 The level of the output signal OUT is Figure 8 The level of the output signal OUT is the same. Fig. 9 The timing diagram of the signals at each node in the shift register shown is also as shown in Fig.12 shown.

[0095] Fig.10 In the shift register shown in FIG. 1 , only the connection node between the first transistor M1 and the second transistor M2 is connected to the Figure 8 The connection nodes shown are different, therefore, in the stages T1 to T5, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are the same as in the above process, and the only difference is the level of the output signal OUT. Fig.12 As shown, the level change state of the output signal OUT is the same as the level change state of the second node N2. Fig.13 This is another driving timing diagram of the shift register provided by the present invention. Fig.10 and Fig.13 , the level change state of the output signal OUT is the same as the level change state of the fourth node N4.

[0096] Fig.11 In the shift register shown, although the types of the first transistor M1 and the second transistor M2 are the same as Fig.10 The first transistor M1 and the second transistor M2 in the shift register shown are of different types. However, in the stages T1 to T5, the levels of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are the same as those in the above process. Fig.11 The voltage signal of the first transistor M1 input is Fig.10 The voltage signal input to the first transistor M1 is different. Fig.11 The voltage signal of the second transistor M2 input is Fig.10 The voltage signal input to the second transistor M2 is also different, therefore, Fig.11 The level of the output signal OUT is Fig.10 The level of the output signal OUT is the same. Fig.11 The timing diagram of the signals at each node in the shift register shown is also as shown in Fig.13 shown.

[0097] It should be noted that, since the first transistor M1 and the second transistor M2 generate the output signal OUT under the control of the fourth node N4 and the second node N2, respectively, and the high level signal and the low level signal of the second node N2 and the fourth node N4 are respectively the first voltage signal VGH1 and the second voltage signal VGL1, that is, the control signal of the fourth control unit 40 is the first voltage signal VGH1 and the second voltage signal VGL1, and the receiving signal of the fourth control unit 40 is the third voltage signal VGH2 and the fourth voltage signal VGL2, therefore, when the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and / or the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2, the control signal of the fourth control unit 40 can have a higher level or a lower level than the receiving signal.

[0098] When the first transistor M1 and the second transistor M2 are PMOS transistors, when receiving a low level, when the level of the control signal is lower than the received low level signal, it is possible to ensure that the PMOS transistor operates in a relatively saturated state, thereby ensuring the stability of the output signal OUT and reducing the tailing phenomenon of the signal output. In addition, when the control signal is a higher high level, if the level received by the PMOS transistor is also a high level, it is possible to fully ensure that the PMOS transistor is turned off, and fully reduce the risk of leakage. Therefore, in the embodiment of the present invention, the stability of the output waveform can be fully improved, and the occurrence of problems such as tailing and leakage current can be avoided.

[0099] Similarly, when the first transistor M1 and the second transistor M2 are NMOS transistors, when receiving a high level, when the level of the control signal is higher than the received high level signal, it is possible to ensure that the NMOS transistor operates in a relatively saturated state, thereby ensuring the stability of the output signal OUT and reducing the tailing phenomenon of the signal output. In addition, when the control signal is a lower low level, if the level received by the NMOS transistor is also a low level, it is possible to fully ensure that the NMOS transistor is turned off, and the risk of leakage is fully reduced. Therefore, in the embodiment of the present invention, the stability of the output waveform can be fully improved, and the occurrence of problems such as tailing and leakage current can be avoided.

[0100] exist Figure 8 and Fig.10 Based on the shift register shown, optionally, the width-to-length ratio of the channel region of the second transistor M2 is greater than or equal to the width-to-length ratio of the channel region of the first transistor M1.

[0101] Specifically, since the second transistor M2 is a transistor connected to the fourth voltage signal VGL2, when the fourth voltage signal VGL2 is transmitted to the output end so that the output signal OUT is at a low level, the potential of the second node N2 is a low potential. For the PMOS transistor, when the source and the gate are both at a low potential, in order to ensure the stability of the low-level signal output by the PMOS transistor, that is, the output signal OUT, it is necessary to improve the output capacity of the PMOS transistor as much as possible. Since the larger the width-to-length ratio of the channel region of the PMOS transistor, the stronger the output capacity of the PMOS transistor, therefore, it is necessary to appropriately increase the width-to-length ratio of the channel region of the PMOS transistor.

[0102] As for the first transistor M1, the third voltage signal VGH2 connected thereto is a high level signal. When the fourth node N4 is at a low level, the PMOS transistor operates in a relatively saturated state and is fully turned on. Therefore, the requirement for its output capacity is smaller than that of the second transistor M2, and its width-to-length ratio can be appropriately set to be smaller.

[0103] Based on this, in some embodiments of the present invention, the width-to-length ratio of the channel region of the second transistor M2 can be greater than the width-to-length ratio of the channel region of the first transistor M1. Similarly, in order to simplify the manufacturing process, the width-to-length ratio of the channel region of the second transistor M2 can also be equal to the width-to-length ratio of the channel region of the first transistor M1.

[0104] Of course, in Fig. 9 and Fig.11 Based on the shift register shown, in some embodiments of the present invention, the width-to-length ratio of the channel region of the second transistor M2 may also be greater than or equal to the width-to-length ratio of the channel region of the first transistor M1. The reasons are similar to the above reasons and will not be repeated here.

[0105] exist Figure 8 Based on the shift register shown, optionally, the capacitance value of the first capacitor C1 is less than or equal to the capacitance value of the second capacitor C2.

[0106] Since the second plate of the second capacitor C2 is connected to the fourth voltage signal VGL2, the first plate of the second capacitor C2 is connected to the second node N2, the source of the second transistor M2 is connected to the fourth voltage signal VGL2, and the gate is connected to the second node N2, when the second transistor M2 is a PMOS transistor, when the second node N2 is a low level signal, the output of the second transistor M2 is unstable. By increasing the capacitance value of the second capacitor C2, the stability of the potential of the second node N2 can be improved. At this time, the capacitance value of the first capacitor C1 can be set to be less than the capacitance value of the second capacitor C2. Of course, in order to simplify the production process, the capacitance value of the first capacitor C1 can also be set to be equal to the capacitance value of the second capacitor C2.

[0107] exist Figure 9-11 Based on the shift register shown, in some embodiments of the present invention, the capacitance value of the first capacitor C1 may also be less than or equal to the capacitance value of the second capacitor C2, which will not be described in detail herein.

[0108] Continue to refer Figure 1 , Figure 2 and Figure 8 , Optionally, the driving circuit includes N-stage shift registers, that is, N cascaded shift registers ASG1 to ASGN. In the N-stage shift registers of the driving circuit, the signal of the fourth node N4 of the M-stage shift register is connected to the input signal terminal of the M+1-stage shift register as the input signal of the M+1-stage shift register, wherein 1≤M≤N.

[0109] Specifically, in the driving circuit, the signal Next of the fourth node N4 of the previous shift register is used as the input signal IN of the next shift register, and the output signal OUT of each shift register is input into the pixel circuit as the driving signal. However, the present invention is not limited to this. In other embodiments, such as Fig.13 As shown, when the output signal OUT is in the same change state as the fourth node N4, the output signal OUT of the Mth stage shift register can also be used as the input signal IN of the M+1th stage shift register, and the signal Next of the fourth node N4 can be input into the pixel circuit as a driving signal.

[0110] Continue to refer Figure 1 and Figure 2 , optionally, the display panel further comprises:

[0111] A first voltage signal line XVGH1, providing a first voltage signal VGH1 to the driving circuit;

[0112] A second voltage signal line XVGL1, providing a second voltage signal VGL1 to the driving circuit;

[0113] A third voltage signal line XVGH2, providing a third voltage signal VGH2 to the driving circuit;

[0114] The fourth voltage signal line XVGL2 provides a fourth voltage signal VGL2 to the driving circuit.

[0115] Since the third voltage signal VGH2 and the fourth voltage signal VGL2 are used to generate the output signal OUT, and the output signal OUT is used to provide a driving signal for the pixel circuit 210 of the display area AA of the display panel, in order to save the space of the driving circuit 100 as much as possible and avoid excessive wiring, the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 can be set on the side close to the display area AA.

[0116] Based on this, in some embodiments of the present invention, at least one of the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 is located on a side of at least one of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 facing the display area of ​​the display panel.

[0117] Continue to refer Figure 2, Optionally, the first voltage signal line XVGH1, the second voltage signal line XVGL1, the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 are all located on the side of the driving circuit 100 away from the display area AA of the display panel. In addition, the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 are both located on the side of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 close to the display area AA or facing the display area AA of the display panel, so as to save the space of the driving circuit 100 to the maximum extent and shorten the wiring length.

[0118] Of course, the present invention is not limited to this, and optionally, Fig.14 As shown, Fig.14 It is a structural schematic diagram of another driving circuit provided by the present invention, wherein the first voltage signal line XVGH1 and the second voltage signal line XVGL1 are located on the side of the driving circuit away from the display area AA of the display panel; the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2 are located on the side of the driving circuit toward the display area AA of the display panel, so as to further save the space of the driving circuit 11 and shorten the wiring length.

[0119] Since the potential of the first voltage signal VGH1 is higher than the potential of the third voltage signal VGH2, and / or the potential of the second voltage signal VGL1 is lower than the potential of the fourth voltage signal VGL2, the voltage value carried by the first voltage signal line XVGH1 and the second voltage signal line XVGL1 is larger. If the line width is smaller, the resistance is larger and the voltage loss thereon will be greater. Therefore, optionally, the line width of at least one of the first voltage signal line XVGH1 and the second voltage signal line XVGL1 is larger than the line width of at least one of the third voltage signal line XVGH2 and the fourth voltage signal line XVGL2.

[0120] Since the first transistor M1 and the second transistor M2 generate the output signal OUT in the shift register, the first transistor M1 and the second transistor M2 are generally transistors with a relatively large width-to-length ratio. Therefore, in order to further reduce the frame of the display panel and reduce the space of the driving circuit 100, optionally, reference Fig.15 , Fig.15 It is a structural diagram of another driving circuit provided by the present invention, wherein the shift registers 110 are cascaded with each other along the first direction X1, the first transistor M1 and the second transistor M2 are arranged along the second direction X2, wherein the first direction X1 is parallel to the second direction X2.

[0121] Continue to refer Figure 1 , optionally, the display panel includes a pixel circuit 210, and the driving circuit 100 provides a first driving signal to the pixel circuit 210 through a first driving signal line 120, and the first driving signal is an output signal OUT.

[0122] Fig.16 is a circuit diagram of a pixel circuit provided by the present invention, Fig.17 is a circuit diagram of another pixel circuit provided by the present invention, referring to Fig.16 and Fig.17 , the pixel circuit includes a driving transistor T0. Wherein, Fig.16 The driving transistor T0 in is a PMOS transistor. Fig.17 The driving transistor T0 in the pixel driving circuit is an NMOS transistor. Of course, the pixel driving circuit also includes other transistors T1 to T6 and other signal input terminals, which will not be described in detail in the present invention.

[0123] The gate of the driving transistor T0 is coupled to the first driving signal line 120 , and the first driving signal, ie, the output signal OUT of the shift register, is used to selectively reset the gate of the driving transistor T0 , so that the gate of the driving transistor T0 is initialized.

[0124] The output signal OUT of the shift register is Fig.16 When the transistor T5 and the transistor T2 are turned on, the output signal OUT of the shift register, namely V0 (Vref / Vbias), is transmitted to the gate of the driving transistor T0 to reset the gate of the driving transistor T0.

[0125] The output signal OUT of the shift register is Fig.17 When the transistor T4 and the transistor T2 are turned on, the output signal OUT of the shift register, namely Vobs / Vini, is transmitted to the gate of the driving transistor T0 to reset the gate of the driving transistor T0.

[0126] When the driving transistor T0 is a PMOS transistor, the gate reset mainly gives the gate a low level signal. However, in order to achieve high-frequency refresh of the display panel, the gate reset signal should not be too low to shorten the Fig.16 The charging time of the N1' node in the data writing phase, therefore, the voltage absolute value V GL2 The absolute value of the voltage of the third voltage signal VGH2 needs to be set smaller. GH2 The corresponding non-reset stage requires a relatively high level to ensure that the gate of the driving transistor T0 is not affected by the signal during the non-reset stage. Therefore, for the PMOS transistor, V GH2 It can be set higher appropriately. For NMOS transistors, the level situation is just the opposite, but the principle is the same.

[0127] Based on this, optionally, the absolute value of the voltage of the first voltage signal VGH1 is V GH1 , the absolute value of the voltage of the second voltage signal VGL1 is V GL1 , the absolute value of the voltage of the third voltage signal VGH2 is V GH2 The absolute value of the voltage of the fourth voltage signal VGL2 is V GL2 ; Wherein, when the driving transistor T0 is a PMOS transistor, |V GH1 -V GH2 |≤|V GL1 -V GL2 |; or, when the driving transistor T0 is an NMOS transistor, |V GH1 -V GH2 |≥|V GL1 -V GL2 |.

[0128] Furthermore, for a PMOS transistor, if |V GL1 -V GL2 |≥V GL2 , such as V GH1 9V, V GL2 is only 4V, then |V GL1 -V GL2 |V GL2 If the voltage is still large, the potential of the gate of the driving transistor T0 will not be too low during the reset phase, thereby ensuring the stable operation of the driving transistor T0. For NMOS transistors, the voltage level is just the opposite, but the principle is the same.

[0129] Based on this, optionally, when the driving transistor T0 is a PMOS transistor, |V GH1 -V GH2 |≤V GH2 , and |V GL1 -V GL2 |≥V GL2 ; or, when the driving transistor is an NMOS transistor, |V GH1 -V GH2 |≥V GH2 , and |V GL1 -V GL2 |≤V GL2 .

[0130] Continue to refer Fig.16 and Fig.17 , Optionally, the pixel circuit includes a data writing module 211, a compensation module 212, and a reset module 213;

[0131] The data writing module 211 is connected to the source of the driving transistor T0;

[0132] The compensation module 212 is connected between the gate and the drain of the driving transistor T0;

[0133] The reset module 213 is connected to the drain of the driving transistor T0;

[0134] The working process of the pixel circuit includes a reset stage and a bias stage. In the reset stage, the reset module 213 and the compensation module 212 are both turned on, and the gate of the driving transistor T0 receives the reset signal; in the bias stage, the reset module 213 is turned on, and the compensation module 212 is turned off, and the drain of the driving transistor T0 receives the bias signal.

[0135] Specifically, when the output signal OUT of the shift register is Fig.16 When V0(Vref / Vbias) is equal to V0(Vref / Vbias), in the reset phase, the output signal OUT, i.e., the reset signal, is used to reset the gate of the driving transistor T0; in the bias phase, the reset module 213 is turned on, and the output signal OUT, i.e., the bias signal, is used to reset the gate of the driving transistor T0. Fig.16 The N3' node in the Fig.16 The potential of the N3' node in Fig.16 The potential of the N1' node is prevented from flowing from the N1' node to the N3' node in the driving transistor T0, which causes the potential of the N1' node to drop and affects the display of the display panel.

[0136] When the output signal OUT of the shift register is Fig.17 When Vobs / Vini is equal to 1, in the reset phase, the output signal OUT, i.e., the reset signal, is used to reset the gate of the driving transistor T0; in the bias phase, the output signal OUT, i.e., the bias signal, is used to Fig.17 The potential of the N3' node is adjusted to make Fig.17 The potential of the N3' node in Fig.17 The potential of the N1' node in Fig.16 The difference is that the levels of the reset signal and the bias signal are different.

[0137] Continue to refer Fig.16 , optionally, the reset signal is the fourth voltage signal VGL2, and the bias signal is the third voltage signal VGH2, or in other words, the reset signal is the output signal OUT generated by the fourth voltage signal VGL2, and the bias signal is the output signal OUT generated by the third voltage signal VGH2.

[0138] Specifically, in Fig.16In the light-emitting stage of the pixel circuit shown, there may be a situation where the potential of the gate N1' node of the driving transistor T0 is higher than the potential of the drain N3' node, for example, the N2' node is 4.6V, the N1' node is 3V, and the N3' node may be 2V. For the PMOS transistor, after a long time, the stability of the PMOS transistor will be affected. Therefore, it is necessary to set a bias stage in the non-light-emitting stage, and raise the potential of the N3' node through the bias signal to eliminate the above-mentioned influence in the light-emitting stage. In order to fully realize this process, the high-level signal VGH2 of the bias signal needs to be as high as possible, and the low-level signal VGL2 of the reset signal does not need to be set too low. Therefore, |V GH1 -V GH2 |≤|V GL1 -V GL2 |.

[0139] Or, continue to refer to Fig.17 , the driving transistor is an NMOS transistor, the reset signal is the third voltage signal VGH2, and the bias signal is the fourth voltage signal VGL2. In other words, the reset signal is the output signal OUT generated by the third voltage signal VGH2, and the bias signal is the output signal OUT generated by the fourth voltage signal VGL2.

[0140] Specifically, in Fig.17 In the light-emitting stage of the pixel circuit shown, there may be a situation where the potential of the gate N1' node of the driving transistor T0 is lower than the potential of the drain N3' node, for example, the N3' node is 4.6V and the N1' node is 3V. For the NMOS transistor, after a long time, the stability of the NMOS transistor will be affected. Therefore, it is necessary to set a bias stage in the non-light-emitting stage, and pull down the potential of the N3' node through the bias signal to eliminate the above-mentioned influence in the light-emitting stage. In order to fully realize this process, the low-level signal VGL2 of the bias signal needs to be as low as possible, and the high-level signal VGH2 of the reset signal does not need to be set too low. Therefore, |V GH1 -V GH2 |≥|V GL1 -V GL2 |.

[0141] Fig.18 is a plan view of another display panel provided by the present invention, referring to Fig.18 Optionally, the display panel further includes a light emitting element 220, the light emitting element 220 includes a cathode, an anode and a light emitting layer located between the cathode and the anode. The driving circuit 100 provides a second driving signal to the pixel circuit 210 through a second driving signal line 130, and the second driving signal is an output signal OUT; wherein,

[0142] The anode of the light emitting element 220 is coupled to the second driving signal line 130 , and the second driving signal, ie, the output signal OUT, is used to selectively reset the light emitting element 220 .

[0143] Specifically, the output signal OUT of the shift register is Fig.16 When the transistor T4 is turned on, the output signal OUT of the shift register, namely, Vini, is transmitted to the anode of the light-emitting element 220, and the anode of the light-emitting element 220 is reset.

[0144] Alternatively, the output signal OUT of the shift register is Fig.17 When the transistor T5 is turned on, the output signal OUT of the shift register, namely VAR, is transmitted to the anode of the light emitting element 220, and the anode of the light emitting element 220 is reset.

[0145] In the embodiment of the present invention, the absolute value of the voltage of the first voltage signal VGH1 is V GH1 , the absolute value of the voltage of the second voltage signal VGH2 is V GL1 , the absolute value of the voltage of the third voltage signal VGH3 is V GH2 , the absolute value of the fourth voltage signal VGH4 is V GL2 Since the reset signal of the anode of the light emitting element 220 is generally at a low level, it is optional that |V GH1 -V GH2 |≤|V GL1 -V GL2 |.

[0146] Furthermore, in some application scenarios, the potential of the reset signal cannot be too low. Therefore, it is optional that, wherein |V GH1 -V GH2 |≤V GH2 , and |V GL1 -V GL2 |≥V GL2 .

[0147] In the above embodiment, the display panel includes only one driving circuit, but the present invention is not limited thereto. Fig.19 is a plan view of another display panel provided by the present invention, referring to Fig.19 , optionally, the display panel includes a first driving circuit 140 and a second driving circuit 150, the first driving circuit 140 includes N1-level shift registers cascaded to each other, and the second driving circuit 150 includes N2-level shift registers cascaded to each other, N1≥2, N2≥2.

[0148] Among them, the potential of at least one of the third voltage signal in the first driving circuit 140 and the third voltage signal in the second driving circuit 150 is higher than the potential of the other; and / or, the potential of at least one of the fourth voltage signal in the first driving circuit 140 and the fourth voltage signal in the second driving circuit 150 is lower than the potential of the other, so that the voltage of the output signal of the first driving circuit 140 and the output signal of the second driving circuit 150 are different, so as to meet the different voltage requirements of different signals in the pixel circuit 210.

[0149] Continue to refer Fig.19 , Optionally, the display panel further includes a pixel circuit 210, the first drive circuit 140 provides a third drive signal for the pixel circuit 210, and the second drive circuit 150 provides a fourth drive signal for the pixel circuit 210, that is, the output signal of the first drive circuit 140 is the third drive signal of the pixel circuit 210, and the output signal of the second drive circuit 150 is the fourth drive signal of the pixel circuit 210. The third drive signal and the fourth drive signal are different drive signals, such as reset signals with different voltages, to meet different voltage requirements of different signals in the pixel circuit 210. Of course, the present invention is not limited to this, and in other embodiments, the third drive signal and the fourth drive signal can also be signals with different timings to provide two signals with different timings to the pixel circuit 210. For example, one of the third drive signal and the fourth drive signal is a reset signal, and the other is a scan signal.

[0150] In some alternative embodiments, please refer to Fig. 20 , Fig. 20 1 is a schematic plan view of a display device provided by the present invention. The display device 1000 provided by this embodiment includes the display panel 000 provided by the above embodiment of the present invention. Fig. 20 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device 1000 provided in the embodiment of the present invention can also be a computer, a television, a car display device or other display device 1000 with a display function, and the present invention does not specifically limit this. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention. For details, please refer to the specific description of the display panel 1000 in the above embodiments, and this embodiment will not be repeated here.

[0151] It can be seen from the above embodiments that the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0152] In the display panel provided by the present invention, the first control unit, the second control unit and the third control unit control the signal of the second node and the signal of the fourth node based on the input signal, the first clock signal, the second clock signal, the first voltage signal and the second voltage signal, and the fourth control unit is used to receive the third voltage signal and the fourth voltage signal, and generate an output signal in response to the signal of the second node and the signal of the fourth node controlled by the first control unit, the second control unit and the third control unit, that is, the first control unit, the second control unit and the third control unit are the control parts in the shift register, which play a control role. The fourth control unit is the output part in the shift register, which is used to generate an output signal. The voltage signal (the third voltage signal and the fourth voltage signal) received by the fourth control unit is set separately from the voltage signal (the first voltage signal and the second voltage signal) received by the first control unit, the second control unit and the third control unit, that is, the voltage signal of the control part in the shift register is set separately from the voltage signal of the output part, so that the voltage signal received by the fourth control unit can be set according to the requirements of the pixel circuit in the display panel for different signals, and the required signal can be selectively output, thereby improving the flexibility of the signal output by the driving circuit.

[0153] Furthermore, since the potential of the first voltage signal is higher than the potential of the third voltage signal, and / or the potential of the second voltage signal is lower than the potential of the fourth voltage signal, the waveform stability of the output signal generated by the fourth control unit can be improved, thereby improving the stability of the signal output by the driving circuit.

[0154] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that: include: A driving circuit, the driving circuit comprising N stages of shift registers cascaded to each other, N≥2; The shift register comprises: a first control unit configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, the second control unit being configured to receive the first voltage signal and the second voltage signal, and to control the signal of the second node in response to the signal of the first node, the first clock signal, and the second clock signal; a third control unit, the third control unit being configured to receive the first voltage signal and the second voltage signal, and to control the signal of a fourth node in response to the signal of the second node and the signal of the third node, wherein the third node is connected to the first node, the first voltage signal is a high level signal, and the second voltage signal is a low level signal; a fourth control unit, the fourth control unit being configured to receive the third voltage signal and the fourth voltage signal, and generate an output signal in response to the signal of the second node and the signal of the fourth node; wherein, The third voltage signal is a high level signal, and the fourth voltage signal is a low level signal; The potential of the first voltage signal is higher than the potential of the third voltage signal, and / or The potential of the second voltage signal is lower than the potential of the fourth voltage signal.

2. The display panel according to claim 1, characterized in that: The fourth control unit includes a first transistor and a second transistor; The first transistor receives the third voltage signal, and the second transistor receives the fourth voltage signal to generate the output signal.

3. The display panel according to claim 2, characterized in that: The first transistor and the second transistor are both PMOS transistors; The source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the fourth node; The second transistor has a source connected to the fourth voltage signal, a drain connected to the output signal, and a gate connected to the second node.

4. The display panel according to claim 2, characterized in that: The first transistor and the second transistor are both NMOS transistors; The source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the second node; The second transistor has a source connected to the fourth voltage signal, a drain connected to the output signal, and a gate connected to the fourth node.

5. The display panel according to claim 2, characterized in that: The first transistor and the second transistor are both PMOS transistors; The source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the second node; The second transistor has a source connected to the fourth voltage signal, a drain connected to the output signal, and a gate connected to the fourth node.

6. The display panel according to claim 2, characterized in that: The first transistor and the second transistor are both NMOS transistors; The source of the first transistor is connected to the third voltage signal, the drain is connected to the output signal, and the gate is connected to the fourth node; The second transistor has a source connected to the fourth voltage signal, a drain connected to the output signal, and a gate connected to the second node.

7. The display panel according to claim 2, characterized in that: The fourth control unit also includes a first capacitor and a second capacitor; The first plate of the first capacitor is connected to one of the first voltage signal, the second voltage signal, the third voltage signal or the fourth voltage signal, and the second plate of the first capacitor is connected to the fourth node; The first plate of the second capacitor is connected to the second node, and the second plate of the second capacitor is connected to the output signal or one of the first voltage signal, the second voltage signal, the third voltage signal or the fourth voltage signal.

8. The display panel according to claim 7, characterized in that: The capacitance value of the first capacitor is less than or equal to the capacitance value of the second capacitor.

9. The display panel according to claim 2, characterized in that: A width-to-length ratio of a channel region of the second transistor is greater than or equal to a width-to-length ratio of a channel region of the first transistor.

10. The display panel according to claim 1, characterized in that: Among the N-stage shift registers of the driving circuit, the signal of the fourth node of the M-th stage shift register is connected to the input signal terminal of the M+1-th stage shift register as the input signal of the M+1-th stage shift register, wherein 1≤M≤N.

11. The display panel according to claim 1, characterized in that: The display panel includes a pixel circuit, and the driving circuit provides a first driving signal to the pixel circuit through a first driving signal line, and the first driving signal is the output signal; wherein, The pixel circuit includes a driving transistor, a gate of the driving transistor is coupled to the first driving signal line, and the first driving signal is used to selectively reset the gate of the driving transistor.

12. The display panel according to claim 11, characterized in that: The absolute value of the voltage of the first voltage signal is V GH1 , the absolute value of the voltage of the second voltage signal is V GL1 , the voltage absolute value of the third voltage signal is V GH2 , the voltage absolute value of the fourth voltage signal is V GL2 ;in, The driving transistor is a PMOS transistor, then |V GH1 -V GH2 |≤|V GL1 -V GL2 |; or, The driving transistor is an NMOS transistor, then |V GH1 -V GH2 |≥|V GL1 -V GL2 |.

13. The display panel according to claim 12, characterized in that: The driving transistor is a PMOS transistor. ∣V GH1 -V GH2 |≤V GH2 , and |V GL1 -V GL2 |≥V GL2 ;or, The driving transistor is an NMOS transistor. ∣V GH1 -V GH2 |≥V GH2 , and |V GL1 -V GL2 |≤V GL2 .

14. The display panel according to claim 11, characterized in that: The pixel circuit includes a data writing module, a compensation module, and a reset module; The data writing module is connected to the source of the driving transistor; The compensation module is connected between the gate and the drain of the driving transistor; The reset module is connected to the drain of the driving transistor; The working process of the pixel circuit includes a reset stage and a bias stage. In the reset stage, the reset module and the compensation module are both turned on, and the gate of the driving transistor receives a reset signal; in the bias stage, the reset module is turned on, and the compensation module is turned off, and the drain of the driving transistor receives a bias signal.

15. The display panel according to claim 14, characterized in that: The driving transistor is a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal; or, The driving transistor is an NMOS transistor, the reset signal is the third voltage signal, and the bias signal is the fourth voltage signal.

16. The display panel according to claim 1, characterized in that: The display panel further includes a pixel circuit and a light-emitting element, the driving circuit provides a second driving signal to the pixel circuit via a second driving signal line, and the second driving signal is the output signal; wherein, The anode of the light emitting element is coupled to the second driving signal line, and the second driving signal is used to selectively reset the light emitting element.

17. The display panel according to claim 16, characterized in that: The absolute value of the voltage of the first voltage signal is V GH1 , the absolute value of the voltage of the second voltage signal is V GL1 , the voltage absolute value of the third voltage signal is V GH2 , the absolute value of the fourth voltage signal is V GL2 ;in, ∣V GH1 -V GH2 |≤|V GL1 -V GL2 |。 18. The display panel according to claim 16, characterized in that: ∣V GH1 -V GH2 |≤V GH2 , and |V GL1 -V GL2 |≥V GL2 .

19. The display panel according to claim 1, characterized in that: The display panel includes a first driving circuit and a second driving circuit, the first driving circuit includes N1 stages of shift registers cascaded to each other, and the second driving circuit includes N2 stages of shift registers cascaded to each other, N1≥2, N2≥2; wherein, At least one of the third voltage signal in the first driving circuit and the third voltage signal in the second driving circuit has a potential higher than the other; and / or, At least one of the fourth voltage signal in the first driving circuit and the fourth voltage signal in the second driving circuit has a potential lower than that of the other.

20. The display panel according to claim 19, characterized in that: The display panel further includes a pixel circuit, the first driving circuit provides a third driving signal for the pixel circuit, the second driving circuit provides a fourth driving signal for the pixel circuit, and the third driving signal and the fourth driving signal are different driving signals.

21. The display panel according to claim 2, characterized in that: The shift registers are cascaded with each other along a first direction, and the first transistors and the second transistors are arranged along a second direction, wherein the first direction is parallel to the second direction.

22. The display panel according to claim 1, characterized in that: The display panel further includes: A first voltage signal line, providing a first voltage signal to the driving circuit; A second voltage signal line, providing a second voltage signal to the driving circuit; A third voltage signal line, providing a third voltage signal to the driving circuit; The fourth voltage signal line provides a fourth voltage signal to the driving circuit; wherein, At least one of the third voltage signal line and the fourth voltage signal line is located at a side of at least one of the first voltage signal line and the second voltage signal line facing the display area of ​​the display panel.

23. The display panel according to claim 22, characterized in that: The third voltage signal line and the fourth voltage signal line are both located at a side of the first voltage signal line and the second voltage signal line facing the display area of ​​the display panel.

24. The display panel according to claim 22, characterized in that: The first voltage signal line and the second voltage signal line are located on a side of the driving circuit away from a display area of ​​the display panel; The third voltage signal line and the fourth voltage signal line are located at a side of the driving circuit facing the display area of ​​the display panel.

25. The display panel according to claim 22, characterized in that: The first voltage signal line, the second voltage signal line, the third voltage signal line and the fourth voltage signal line are all located at a side of the driving circuit away from the display area of ​​the display panel.

26. The display panel according to claim 22, characterized in that: A line width of at least one of the first voltage signal line and the second voltage signal line is greater than a line width of at least one of the third voltage signal line and the fourth voltage signal line.

27. The display panel according to claim 7, characterized in that: The third control unit comprises: a third transistor, wherein a source of the third transistor is connected to the first voltage signal, a drain of the third transistor is connected to the fourth node, and a gate of the third transistor is connected to the second node; a fourth transistor, wherein the source of the fourth transistor is connected to the second voltage signal, the drain is connected to the fourth node, and the gate is connected to the third node; wherein, The width-to-length ratio of the channel region of the first transistor is greater than the width-to-length ratio of the channel region of the third transistor, or the width-to-length ratio of the channel region of the second transistor is greater than the width-to-length ratio of the channel region of the fourth transistor.

28. The display panel according to claim 27, characterized in that: The third control unit also includes: a third capacitor, wherein a first plate of the third capacitor is connected to the first voltage signal, and a second plate of the third capacitor is connected to the second node; a fourth capacitor, wherein a first plate of the fourth capacitor is connected to the second clock signal or the second voltage signal, and a second plate of the fourth capacitor is connected to the third node; wherein, The capacitance value of the first capacitor and the capacitance value of the second capacitor are greater than the capacitance value of the third capacitor, and greater than the capacitance value of the fourth capacitor.

29. The display panel according to claim 28, characterized in that: The first control unit comprises: a fifth transistor, wherein a source of the fifth transistor is connected to the input signal, a drain of the fifth transistor is connected to the first node, and a gate of the fifth transistor is connected to the first clock signal; The second control unit comprises: a sixth transistor, wherein a source of the sixth transistor is connected to the first node, a drain of the sixth transistor is connected to the drain of the seventh transistor, and a gate of the sixth transistor is connected to the second clock signal; a seventh transistor, wherein a source of the seventh transistor is connected to the first voltage signal, a drain of the seventh transistor is connected to the drain of the sixth transistor, and a gate of the seventh transistor is connected to the fifth node; an eighth transistor, wherein a source of the eighth transistor is connected to the first clock signal, a drain of the eighth transistor is connected to the fifth node, and a gate of the eighth transistor is connected to the first node; a ninth transistor, wherein a source of the ninth transistor is connected to the second clock signal, a drain of the ninth transistor is connected to the fifth node, and a gate of the ninth transistor is connected to the first clock signal; a tenth transistor, wherein a source of the tenth transistor is connected to the second clock signal, a drain of the tenth transistor is connected to the sixth node, and a gate of the tenth transistor is connected to the fifth node; an eleventh transistor, wherein a source of the eleventh transistor is connected to the sixth node, a drain of the eleventh transistor is connected to the second node, and a gate of the eleventh transistor is connected to the second clock signal; a twelfth transistor, wherein a source of the twelfth transistor is connected to the first voltage signal, a drain of the twelfth transistor is connected to the second node, and a gate of the twelfth transistor is connected to the third node; A fifth capacitor, wherein a first electrode of the fifth capacitor is connected to the fifth node, and a second electrode of the fifth capacitor is connected to the sixth node.

30. The display panel according to claim 29, characterized in that: The capacitance value of the fifth capacitor is smaller than the capacitance value of the first capacitor, and smaller than the capacitance value of the second capacitor.

31. The display panel according to claim 30, characterized in that: The capacitance value of the fifth capacitor is smaller than the capacitance value of the third capacitor, and smaller than the capacitance value of the fourth capacitor.

32. The display panel according to claim 29, characterized in that: The second control unit comprises: a thirteenth transistor, wherein a source of the thirteenth transistor is connected to the fifth node, a drain of the thirteenth transistor is connected to the gate of the tenth transistor, and a gate of the thirteenth transistor is connected to the second voltage signal; A fourteenth transistor, wherein the source of the fourteenth transistor is connected to the first node, the drain is connected to the third node, and the gate is connected to the second voltage signal.

33. A display device, characterized in that: A display panel comprising any one of claims 1-32.

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