Display device and method of manufacturing the same

Abstract

The present application relates to a display device and a method of manufacturing the same. The display device includes a substrate having a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface; a thin film transistor disposed above the top surface and including a semiconductor layer; a display element connected to the thin film transistor; a top conductive pattern disposed between the substrate and the thin film transistor and overlapping the semiconductor layer of the thin film transistor; a bottom conductive pattern disposed on the bottom surface and connected to the top conductive pattern through the first contact hole; and a bottom planarization layer disposed on the bottom surface, the bottom planarization layer being disposed on the bottom conductive pattern.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0131393, filed with the Korean Intellectual Property Office on October 22, 2019, the entire contents of which are incorporated herein by reference. Technical field

[0003] One or more embodiments of the present disclosure relate to a display device including wirings under a substrate, and a method of manufacturing the display device. Background art

[0004] As the information - oriented society is developing, the demand for display devices for displaying different images in various ways has increased. Display devices have rapidly changed from large - volume cathode ray tubes (CRTs) to slender and lightweight flat - panel display devices (FPDs) with large display areas. Flat - panel display devices include liquid crystal display devices (LCDs), plasma display panels (PDPs), organic light - emitting display devices (OLEDs), and electrophoretic display devices (EPDs).

[0005] A display device may include a substrate including a display area and a non - display area; and various wirings for transmitting an electrical signal to the display area.

[0006] It should be understood that this background - art section is partly intended to provide a useful background for understanding the technology. However, this background - art section may also include ideas, concepts, or understandings that are not part of what was known or appreciated by a person of ordinary skill in the relevant art before the effective filing date of the corresponding subject matter disclosed herein. Summary of the invention

[0007] One or more embodiments may include a display device including a conductive pattern on a bottom surface of a substrate; and a method of manufacturing the display device.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of the present disclosure.

[0009] According to one or more embodiments, a display device may include a substrate having a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface. The display device may include a thin film transistor disposed above the top surface and including a semiconductor layer; a display element connected to the thin film transistor; a top conductive pattern disposed between the substrate and the thin film transistor and overlapping with the semiconductor layer of the thin film transistor; a bottom conductive pattern disposed on the bottom surface and connected to the top conductive pattern through the first contact hole; and a bottom planarization layer disposed on the bottom conductive pattern above the bottom surface.

[0010] The display device may include a buffer layer disposed above the top conductive pattern and including a second hole. The semiconductor layer may be connected to the top conductive pattern through the second contact hole.

[0011] The first contact hole may be disposed to be spaced apart from the second contact hole in a second direction intersecting a first direction perpendicular to the top surface.

[0012] The display device may further include a bottom buffer layer between the substrate and the bottom conductive pattern.

[0013] The display device may further include a connecting electrode between the thin film transistor and the display element, wherein the thin film transistor may be connected to the display element through the connecting electrode.

[0014] The substrate may include a base layer including a polymer resin; and a barrier layer including an inorganic material, wherein the base layer and the barrier layer may be alternately stacked.

[0015] The semiconductor layer may include a step difference.

[0016] The thin film transistor may include a gate electrode disposed above the semiconductor layer, and the gate electrode may be connected to a first bottom electrode through a third contact hole in the substrate, the first bottom electrode being disposed between the substrate and the bottom planarization layer.

[0017] The display device may further include a bottom insulating layer below the bottom planarization layer; and a second bottom electrode between the bottom planarization layer and the bottom insulating layer, the second bottom electrode corresponding to the first bottom electrode.

[0018] The top conductive pattern may include a first layer including a conductive oxide; and a second layer including a metal.

[0019] The first layer and the pixel electrode of the display element may include the same metal.

[0020] The thin film transistor may include a source electrode and a drain electrode, each of the source electrode and the drain electrode being connected to a semiconductor layer disposed on a top surface, and at least one of the source electrode and the drain electrode may be connected to a top conductive pattern through a fourth contact hole.

[0021] According to one or more embodiments, a display device may include a substrate including a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface. The display device may include a thin film transistor including a semiconductor layer, a source electrode, and a drain electrode each disposed above the top surface; a display element connected to the thin film transistor and disposed above the top surface; a bottom conductive pattern disposed on the bottom surface and connected to at least one of the source electrode and the drain electrode through the first contact hole; and a bottom planarization layer disposed on the bottom conductive pattern.

[0022] The display device may further include a conductive pattern corresponding to the first contact hole and contacting at least one of the source electrode and the drain electrode, wherein the bottom conductive pattern may be connected to the conductive pattern through the first contact hole.

[0023] According to one or more embodiments, a method of manufacturing a display device may include: forming a display layer including a display element on a top surface of a substrate disposed on a first carrier substrate; detaching the first carrier substrate from the bottom surface of the substrate; attaching a second carrier substrate such that the second carrier substrate faces the top surface of the substrate; forming a first contact hole in the substrate; and forming a bottom conductive pattern on the bottom surface, the bottom conductive pattern corresponding to the first contact hole.

[0024] The formation of the display layer may include forming a top conductive pattern corresponding to a portion of the substrate where the first contact hole may be formed. The method may include connecting the bottom conductive pattern to the top conductive pattern through the first contact hole.

[0025] The formation of the top conductive pattern may include: forming a first layer including a conductive oxide, and forming a second layer including a metal.

[0026] The formation of the display layer may include: forming a buffer layer on the top conductive pattern; and forming a thin film transistor including a semiconductor layer disposed on the buffer layer, the semiconductor layer overlapping with the top conductive pattern, wherein the method may include connecting the top conductive pattern to the semiconductor layer through a second contact hole in the buffer layer.

[0027] The method may further include: forming a bottom buffer layer on the bottom surface of the substrate before the formation of the first contact hole.

[0028] The method may further include forming a bottom planarization layer disposed on the bottom conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a schematic plan view of a display device according to an embodiment;

[0031] Figure 2 is a schematic circuit diagram of a pixel included in the display device according to an embodiment;

[0032] Figure 3 is a schematic cross-sectional view of a display device according to an embodiment;

[0033] Figure 4 is a schematic cross-sectional view of a pixel of a display device according to an embodiment;

[0034] Figure 5 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0035] Figure 6 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0036] Figure 7 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0037] Figure 8 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0038] Figure 9 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0039] Figure 10 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0040] Figure 11 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0041] Figure 12 is a schematic cross-sectional view of a pixel of a display device according to another embodiment;

[0042] Figures 13A to 13G is a schematic cross-sectional view for showing a method of manufacturing a display device according to an embodiment; and

[0043] Figure 14Aand Figure 14B is a schematic cross-sectional view for showing a method of manufacturing a display device according to another embodiment. Detailed Embodiments

[0044] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Repeated descriptions may be omitted. In this regard, the embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the figures to explain the described aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms "and" and "or" may be used in the conjunctive or disjunctive sense and may be understood as equivalent to "and / or". Throughout the present disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. For example, referring to at least one of a source electrode and a drain electrode indicates only the source electrode, only the drain electrode, both the source electrode and the drain electrode, or variations thereof.

[0045] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. Such terms are only used to distinguish one component from another.

[0046] As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0047] It should be further understood that terms such as "comprises", "comprising", "has", "having", and / or "including" indicate the presence of the recited features or components, but do not preclude the presence or addition of one or more other features or components.

[0048] It should be understood that when a layer, region, or component is referred to as being "on" or "formed on" another layer, region, or component, it may be directly or indirectly on or directly or indirectly formed on another layer, region, or component. For example, there may be intermediate layers, regions, or components.

[0049] For ease of explanation, the dimensions of elements in the drawings may be enlarged. In other words, since the dimensions and thicknesses of components in the drawings are arbitrarily shown for ease of explanation, the embodiments are not limited thereto.

[0050] Embodiments can be implemented differently. For example, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the recited order.

[0051] It should be understood that when a layer, region, or component is referred to as being "connected" to another layer, region, or component, it can be "directly connected" to another layer, region, or component and / or can be "indirectly connected" to another layer, region, or component, with another layer, region, or component interposed therebetween. It should also be understood that "connected" can refer to "electrically connected". It should be understood that when a layer, region, or component is referred to as being "electrically connected" to another layer, region, or component, it can be "directly electrically connected" to another layer, region, or component and / or can be "indirectly electrically connected" to other layers, regions, or components, with another layer, region, or component interposed therebetween.

[0052] Terms such as "overlap" can include laminating, stacking, facing or facing, extending over, covering or partially covering, or any other suitable terms known and understood by those of ordinary skill in the art.

[0053] For ease of description, spatial relative terms, such as "beneath", "below", "under", "bottom", "above", "on", "top", etc., may be used herein to describe the relationship of one element to another element(s) as shown in the figures. Changing the orientation of the device incorporating such elements may change the spatial relative orientation of the elements to another element(s), but this will still be understood to be within the scope of the present disclosure.

[0054] Figure 1 FIG. is a schematic plan view of a display device 1 according to an embodiment.

[0055] Reference Figure 1 , the display device 1 may include a display area DA and a non-display area NDA. The display area DA may display an image, and the non-display area NDA may not display an image. The display device 1 may display an image by using light emitted from pixels P that can be provided in the display area DA. Each pixel P may emit red light, green light, blue light, or white light.

[0056] The display device 1 may be a device capable of displaying an image and may include a game console, a multimedia device, or a mobile device, such as an ultra-small personal computer. The display device 1 may be a device capable of displaying an image and may have various technologies, for example, a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface conduction electron emission display, a quantum dot display, a plasma display, or a cathode ray display. Hereinafter, although the display device according to an embodiment may be described as an organic light-emitting display device as an example, the embodiments may use various types of display device technologies described above.

[0057] The pixel P can be electrically connected to the scan line SLn and the data line DLm. The scan line SLn can extend in the x direction and the data line DLm can extend in the y direction.

[0058] Figure 2 It is a schematic circuit diagram of a pixel included in a display device according to an embodiment.

[0059] Reference Figure 2 , the pixel P can include a pixel circuit PC and an organic light-emitting diode OLED, and the organic light-emitting diode OLED is a display element connected to the pixel circuit PC.

[0060] The pixel circuit PC can include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. Each pixel P can emit, for example, red light, green light, or blue light, or emit red light, green light, blue light, or white light through the organic light-emitting diode OLED.

[0061] The switching thin-film transistor T2 can be connected to the scan line SLn and the data line DLm, and based on the switching voltage SLV input from the scan line SLn, transmit the data voltage DLV input from the data line DLm to the driving thin-film transistor T1. The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the driving voltage line PL, and can store a voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor T2 and the first power supply voltage ELVDD supplied to the driving voltage line PL.

[0062] The driving thin-film transistor T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with brightness by using the driving current. The opposite electrode (e.g., the cathode) of the organic light-emitting diode OLED can receive the second power supply voltage ELVSS.

[0063] Although Figure 2 it may be shown that the pixel circuit PC includes two thin-film transistors and one storage capacitor, the embodiment is not limited thereto. The number of thin-film transistors and the number of storage capacitors can be changed differently depending on the design of the pixel circuit PC. For example, in addition to two thin-film transistors, the pixel circuit PC can further include one or more thin-film transistors.

[0064] Figure 3 It is a schematic cross-sectional view of a display device 1 according to an embodiment.

[0065] Reference Figure 3, the display layer DL can be disposed on the top surface 101U of the substrate 101 of the display device 1. The display layer DL can include a pixel circuit layer PCL and a display element layer DEL. The pixel circuit layer PCL can include pixel circuits and an insulating layer, and the display element layer DEL can include display elements on the pixel circuit layer PCL. A bottom buffer layer 102 and a bottom planarization layer 103 can be disposed on the bottom surface 101D of the substrate 101.

[0066] The substrate 101 can include glass or a polymer resin, such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or a combination thereof.

[0067] The bottom buffer layer 102 can be disposed on the bottom surface 101D of the substrate 101. The bottom buffer layer 102 can include an inorganic insulating material or an organic insulating material. In an embodiment, the bottom buffer layer 102 can include an inorganic insulating material, such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), or a combination thereof. In another embodiment, the bottom buffer layer 102 can include an organic insulating material, which includes general polymers, such as imide-based polymers, polymethyl methacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, or a combination thereof. Hereinafter, for convenience of description, the case where the bottom buffer layer 102 includes an inorganic insulating material will be described.

[0068] The bottom planarization layer 103 can be disposed below the bottom buffer layer 102. Similar to the bottom buffer layer 102, the bottom planarization layer 103 can include an inorganic insulating material or an organic insulating material. Hereinafter, for convenience of description, the case where the bottom planarization layer 103 includes an organic insulating material will be described.

[0069] In an embodiment, a bottom insulating layer (not shown) can be further disposed below the bottom planarization layer 103.

[0070] The display element layer DEL can include display elements. For example, the display element layer DEL can include the organic light-emitting diode OLED described above. The pixel circuit layer PCL can include pixel circuits and an insulating layer each connected to each organic light-emitting diode OLED. The pixel circuit layer PCL can include transistors, storage capacitors, and an insulating layer between the transistors and the storage capacitors.

[0071] The display element may be covered by a packaging member, such as a thin film encapsulation layer TFE.

[0072] In an embodiment, the thin film encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer each covering the display element layer DEL. The inorganic encapsulation layer may include at least one inorganic material among the following: aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), silicon oxide (SiO2), silicon nitride (SiN x ) and silicon oxynitride (SiON). The organic encapsulation layer may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, polyimide, polyethylene, or a combination thereof. In an embodiment, the organic encapsulation layer may include an acrylate.

[0073] In another embodiment, the thin film encapsulation layer TFE may have a structure in which the substrate 101 can be coupled to a top substrate (which may be a transparent member) by using a sealing member such that the internal space between the substrate 101 and the top substrate can be sealed. A moisture absorbent or a filling material may be disposed in the internal space. The sealing member may be a sealant. In another embodiment, the sealing member may include a material that can be hardened by laser. For example, the sealing member may be a frit. Specifically, the sealing member may include a urethane resin, an epoxy resin, or an acrylic resin that may be an organic sealant, silicone that may be an inorganic sealant, or a combination thereof. As the urethane resin, for example, urethane acrylate etc. may be used. As the acrylic resin, for example, butyl acrylate, 2-ethylhexyl acrylate, etc., or a combination thereof may be used. The sealing member may include a material that can be hardened by heat.

[0074] Hereinafter, a case where the thin film encapsulation layer TFE includes at least one inorganic encapsulation layer and at least one organic encapsulation layer may be described.

[0075] An input sensing layer TSL including a touch electrode may be disposed on the thin film encapsulation layer TFE. An optical function layer OFL may be disposed on the input sensing layer TSL. The input sensing layer TSL may obtain coordinate information corresponding to an external input (e.g., a touch event). The optical function layer OFL may reduce the reflectance of light (external light) incident on the display device 1 from the outside and / or improve the color purity of the light emitted from the display device 1. In an embodiment, the optical function layer OFL may include a retarder and a polarizer. The retarder may include a film type retarder or a liquid crystal type retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may include a film type polarizer or a liquid crystal type polarizer. The film type polarizer may include a stretchable synthetic resin film, and the liquid crystal type polarizer may include liquid crystals arranged in a certain arrangement. Each of the retarder and the polarizer may further include a protective film.

[0076] In another embodiment, the optical function layer OFL may include a black matrix and a color filter. The color filter may be set by considering the colors of multiple light beams respectively emitted from the pixels of the display device 1. Each color filter may include red, green, or blue pigments or dyes. In another example, in addition to the pigments or dyes, each color filter may further include quantum dots. In another example, some color filters may not include pigments or dyes and may include scattering particles such as titanium oxide.

[0077] In another embodiment, the optical function layer OFL may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers respectively. The first reflected light and the second reflected light respectively reflected by the first reflective layer and the second reflective layer may generate destructive interference and thus may reduce the reflectance of external light.

[0078] An adhesive member may be disposed between the input sensing layer TSL and the optical function layer OFL. The adhesive member may employ general members known in the art without limitation. The adhesive member may include a pressure-sensitive adhesive (PSA).

[0079] Figure 4 It is a schematic cross-sectional view of a pixel of a display device according to an embodiment. In Figure 4 Since the same reference numerals as those in Figure 3 represent the same elements, their repeated descriptions may be omitted.

[0080] Referring to Figure 4 , the display layer DL and the thin film encapsulation layer TFE may be disposed on the top surface 101U of the substrate 101. The display layer DL may include a pixel circuit layer PCL and a display element layer DEL. The pixel circuit layer PCL may include a pixel circuit and an insulating layer, and the display element layer DEL may include display elements. The display element layer DEL may include display elements, for example, the organic light-emitting diode OLED described above. The pixel circuit layer PCL may include pixel circuits respectively connected to each organic light-emitting diode OLED and an insulating layer. The pixel circuit layer PCL may include transistors, storage capacitors, and an insulating layer between the transistors and the storage capacitors.

[0081] The bottom buffer layer 102 and the bottom planarization layer 103 may be disposed on the bottom surface 101D of the substrate 101.

[0082] In an embodiment, the substrate 101 may have a multilayer structure including a polymer resin. For example, as shown in Figure 4 , the substrate 101 may include a first base layer 101a, a first barrier layer 101b, a second base layer 101c, and a second barrier layer 101d that can be stacked (e.g., sequentially stacked).

[0083] The first base layer 101a and the second base layer 101c may each include a polymer resin. For example, the first base layer 101a and the second base layer 101c may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, or a combination thereof.

[0084] The first barrier layer 101b and the second barrier layer 101d may be barrier layers that prevent penetration of external foreign substances, and may include a single layer or multiple layers, the single layer or multiple layers including an inorganic material such as silicon nitride (SiN x ) and silicon oxide (SiO2).

[0085] In another embodiment, the substrate 101 may include glass. Hereinafter, for convenience of description, a case where the substrate 101 includes a first base layer 101a, a first barrier layer 101b, a second base layer 101c, and a second barrier layer 101d that can be stacked (e.g., sequentially stacked) will be described.

[0086] In an embodiment, the substrate 101 may include a first contact hole CNT1 that penetrates the top surface 101U and the bottom surface 101D. Specifically, the first contact hole CNT1 may penetrate the first base layer 101a, the first barrier layer 101b, the second base layer 101c, and the second barrier layer 101d. In another example, the first contact hole CNT1 may include contact holes formed in the first base layer 101a, the first barrier layer 101b, the second base layer 101c, and the second barrier layer 101d and overlapping each other. The first contact hole CNT1 may be formed by etching the substrate 101 in a direction from the bottom surface 101D to the top surface 101U of the substrate 101. A method of manufacturing the first contact hole CNT1 is described.

[0087] In an embodiment, a top conductive pattern UM may be disposed on the top surface 101U of the substrate 101. The top conductive pattern UM may be disposed between the substrate 101 and the thin film transistor TFT. The top conductive pattern UM may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). In an embodiment, the top conductive pattern UM may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO), or a combination thereof, and may include a single layer or multiple layers including the above materials.

[0088] In an embodiment, the top conductive pattern UM may be disposed to correspond to the first contact hole CNT1. Accordingly, the first contact hole CNT1 of the substrate 101 may be shielded by the top conductive pattern UM.

[0089] In an embodiment, the bottom buffer layer 102 may be disposed on the bottom surface 101D of the substrate 101. The bottom buffer layer 102 may include a bottom contact hole CNTC corresponding to the first contact hole CNT1. The bottom contact hole CNTC may be connected to the first contact hole CNT1.

[0090] In an embodiment, the bottom conductive pattern DM may be disposed on the bottom surface 101D of the substrate 101. In other words, the bottom conductive pattern DM may be disposed on a surface opposite to the top surface 101U. Specifically, the bottom conductive pattern DM may be disposed under the bottom buffer layer 102.

[0091] In an embodiment, the bottom conductive pattern DM may be connected to the top conductive pattern UM through the first contact hole CNT1. The bottom conductive pattern DM may be disposed to correspond to the first contact hole CNT1. Specifically, the bottom conductive pattern DM may be connected to the top conductive pattern UM through the first contact hole CNT1 and the bottom contact hole CNTC.

[0092] The bottom conductive pattern DM may include a conductive material including Al, Cu, Ti, or a combination thereof, and the bottom conductive pattern DM may include a single layer or multiple layers including the above materials. In an embodiment, the bottom conductive pattern DM may have a multilayer structure of Ti / Al / Ti.

[0093] The bottom planarization layer 103 may be disposed under the bottom buffer layer 102. The bottom planarization layer 103 may planarize the bottom surface 101D of the substrate 101. In an embodiment, the bottom planarization layer 103 may cover the bottom conductive pattern DM.

[0094] The pixel circuit layer PCL may be disposed on the top surface 101U of the substrate 101. The pixel circuit layer PCL may include a buffer layer 111, a thin film transistor TFT, a first gate insulating layer 113a, a second gate insulating layer 113b, a first interlayer insulating layer 115a, and a second interlayer insulating layer 115b.

[0095] The buffer layer 111 may cover the top conductive pattern UM. The buffer layer 111 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x )), silicon oxynitride (SiON), or a combination thereof, and may include a single layer or multiple layers including the inorganic insulating material.

[0096] In an embodiment, the buffer layer 111 may include a second contact hole CNT2. The second contact hole CNT2 may be disposed on the top conductive pattern UM. The second contact hole CNT2 may be disposed to be spaced apart from the first contact hole CNT1. Specifically, the first contact hole CNT1 may be disposed to be spaced apart from the second contact hole CNT2 in a second direction (e.g., the x direction) intersecting a first direction (e.g., the z direction) perpendicular to the top surface 101U of the substrate 101.

[0097] In the case where the first contact hole CNT1 may be disposed to correspond to the second contact hole CNT2, moisture or the like introduced through the first contact hole CNT1 may be easily introduced into the second contact hole CNT2, and the semiconductor layer 112 may be exposed to moisture.

[0098] In an embodiment, since the first contact hole CNT1 may be disposed to be spaced apart from the second contact hole CNT2 in the second direction, moisture or the like introduced through the first contact hole CNT1 can be prevented from being introduced into the semiconductor layer 112 through the second contact hole CNT2. Accordingly, the semiconductor layer 112 can be prevented from being exposed to external moisture or the like.

[0099] The thin film transistor TFT may include a semiconductor layer 112. At least a part of the semiconductor layer 112 may overlap with the top conductive pattern UM. In an embodiment, a part of the semiconductor layer 112 may overlap with the top conductive layer UM. The semiconductor layer 112 may include a step difference. In another embodiment, the semiconductor layer 112 may completely overlap with the top conductive pattern UM.

[0100] In an embodiment, the semiconductor layer 112 may be connected to the top conductive pattern UM through the second contact hole CNT2. Specifically, the semiconductor layer 112 may overlap with at least a part of the top conductive pattern UM. Since the semiconductor layer 112 may be disposed to correspond to the second contact hole CNT2, the semiconductor layer 112 may be connected to the top conductive pattern UM through the second contact hole CNT2.

[0101] The semiconductor layer 112 may include polysilicon. In another example, the semiconductor layer 112 may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or a combination thereof. The semiconductor layer 112 may include a channel region 112c, a drain region 112a, and a source region 112b. The drain region 112a and the source region 112b may be disposed on two opposite sides of the channel region 112c. The gate electrode 114 may overlap with the channel region 112c.

[0102] The gate electrode 114 may include a low-resistance metal material. The gate electrode 114 may include a conductive material including Mo, Al, Cu, Ti, or a combination thereof, and the gate electrode 114 may include a single layer or multiple layers including the above materials.

[0103] The first gate insulating layer 113a between the semiconductor layer 112 and the gate electrode 114 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), or a combination thereof.

[0104] The second gate insulating layer 113b may cover the gate electrode 114. Similar to the first gate insulating layer 113a, the second gate insulating layer 113b may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), or a combination thereof.

[0105] The top electrode Cst2 of the storage capacitor Cst may be disposed on the second gate insulating layer 113b. The top electrode Cst2 may overlap with the gate electrode 114. The gate electrode 114 and the top electrode Cst2 may form the storage capacitor Cst. The gate electrode 114 may overlap with the top electrode Cst2, and the second gate insulating layer 113b is between the gate electrode 114 and the top electrode Cst2. For example, the gate electrode 114 may be used as the bottom electrode Cst1 of the storage capacitor Cst.

[0106] This means that the storage capacitor Cst may overlap with the thin film transistor TFT. In another embodiment, the bottom electrode Cst1 of the storage capacitor Cst may be disposed to be spaced apart from the gate electrode 114 such that the storage capacitor Cst does not overlap with the thin film transistor TFT.

[0107] The top electrode Cst2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers including the above materials.

[0108] The first interlayer insulating layer 115a may cover the top electrode Cst2. The first interlayer insulating layer 115a may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), or a combination thereof. The first interlayer insulating layer 115a may include a single layer or multiple layers including the inorganic insulating material.

[0109] In an embodiment, at least one of the drain electrode 116a and the source electrode 116b may be disposed on the first interlayer insulating layer 115a. For example, the drain electrode 116a may be disposed on the first interlayer insulating layer 115a, and the source electrode 116b may be disposed on the bottom surface 101D of the substrate 101. The source electrode 116b may be formed integrally with the bottom conductive pattern DM. As another example, the drain electrode 116a may be disposed on the bottom surface 101D of the substrate 101, and the source electrode 116b may be disposed on the first interlayer insulating layer 115a. Hereinafter, for convenience of description, a case where the drain electrode 116a may be disposed on the first interlayer insulating layer 115a and the source electrode 116b may be disposed on the bottom surface 101D of the substrate 101 will be described.

[0110] The drain electrode 116a and the source electrode 116b may include a material having excellent conductivity. The drain electrode 116a and the source electrode 116b may include a conductive material including Mo, Al, Cu, Ti, or a combination thereof, and the drain electrode 116a and the source electrode 116b may include a single layer or multiple layers including the above materials. In an embodiment, each of the drain electrode 116a and the source electrode 116b may include a multilayer structure of Ti / Al / Ti.

[0111] The second interlayer insulating layer 115b may cover the drain electrode 116a. Similar to the first interlayer insulating layer 115a, the second interlayer insulating layer 115b may include silicon oxide (SiO2), silicon nitride (SiN x )), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), or a combination thereof. The second interlayer insulating layer 115b may include a single layer or multiple layers including the above inorganic insulating materials.

[0112] In an embodiment, the connection electrode CM may be disposed on the second interlayer insulating layer 115b. The connection electrode CM may be connected to the drain electrode 116a through a contact hole. The connection electrode CM may connect the thin film transistor TFT to the organic light emitting diode OLED.

[0113] The planarization insulating layer 117 may include an organic insulating layer. The planarization insulating layer 117 may include an organic insulating material including a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, or a combination thereof.

[0114] The display element layer DEL can be disposed on the pixel circuit layer PCL having the above structure. The display element layer DEL can be disposed above the top surface 101U of the substrate 101. The display element layer DEL can include an organic light-emitting diode OLED. The pixel electrode 121 of the organic light-emitting diode OLED can be electrically connected to the thin-film transistor TFT through the contact hole of the planarization insulating layer 117.

[0115] The pixel electrode 121 can include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), aluminum zinc oxide (AZO), or a combination thereof. In another embodiment, the pixel electrode 121 can include a reflective layer, the reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a combination thereof. In another embodiment, the pixel electrode 121 can further include a layer on / under the reflective layer, the layer including ITO, IZO, ZnO, In2O3, or a combination thereof.

[0116] The pixel defining layer 119 can be disposed on the pixel electrode 121, and the pixel defining layer 119 can include an opening 119OP that exposes the central portion of the pixel electrode 121. The pixel defining layer 119 can include an organic insulating material and / or an inorganic insulating material. The opening 119OP can define an emission region (hereinafter, referred to as emission region EA) of light emitted from the organic light-emitting diode OLED. For example, the width of the opening 119OP can correspond to the width of the emission region EA.

[0117] The emission layer 122 can be disposed in the opening 119OP of the pixel defining layer 119. The emission layer 122 can include a polymeric organic material or a low-molecular-weight organic material that emits light having a color. Although not shown, a first functional layer and a second functional layer can be respectively disposed under and on the emission layer 122. The first functional layer can include, for example, a hole transport layer (HTL), or can include an HTL and a hole injection layer (HIL). The second functional layer can be an element disposed on the emission layer 122 and can be optionally provided. The second functional layer can include an electron transport layer (ETL) and / or an electron injection layer (EIL). Like the counter electrode 123 described below, the first functional layer and / or the second functional layer can be a common layer that completely covers the substrate 101.

[0118] The counter electrode 123 may include a conductive material having a low work function. For example, the counter electrode 123 may include a (semi)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or a combination thereof. In another example, the counter electrode 123 may further include a layer on the (semi)transparent layer including the above materials, and the layer includes ITO, IZO, ZnO, In2O3, or a combination thereof.

[0119] In an embodiment, the thin film encapsulation layer TFE may include at least one inorganic encapsulation layer or at least one organic encapsulation layer. In an embodiment, Figure 4 shows that the thin film encapsulation layer TFE may include a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133 that can be stacked (e.g., sequentially stacked).

[0120] The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 may include at least one inorganic material among the following: aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), silicon oxide (SiO2), silicon nitride (SiN x ) and silicon oxynitride (SiON). The organic encapsulation layer 132 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide, polyethylene, or a combination thereof. In an embodiment, the organic encapsulation layer 132 may include an acrylate.

[0121] The bottom conductive pattern DM may be disposed on the bottom surface 101D of the substrate 101 to reduce the parasitic capacitance Cp between the pixel electrode 121 and the source electrode 116b.

[0122] In the case where the source electrode 116b may be disposed on the first interlayer insulating layer 115a, the distance between the source electrode 116b and the pixel electrode 121 may be less than the distance in the case where the source electrode 116b may be disposed below the bottom surface 101D of the substrate 101. The value of the parasitic capacitance Cp may increase and the corresponding afterimage problem may increase.

[0123] Conversely, according to an embodiment, in the case where the source electrode 116b may be disposed on the bottom surface 101D of the substrate 101, the value of the parasitic capacitance Cp may decrease and the corresponding afterimage problem may decrease.

[0124] Figure 5 It is a schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 5 Since the same reference numerals as those in Figure 4 represent the same elements, their repeated description may be omitted.

[0125] Reference Figure 5 , the display device may include a substrate 101, thin film transistors TFTs on a top surface 101U, and organic light emitting diodes OLEDs. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 penetrates through the top surface 101U and the bottom surface 101D.

[0126] A top conductive pattern UM may be disposed between the substrate 101 and the thin film transistors TFTs. The top conductive pattern UM may overlap at least a part of the semiconductor layer 112. A bottom conductive pattern DM may be disposed on the bottom surface 101D of the substrate 101 and connected to the top conductive pattern UM through the first contact hole CNT1. A bottom planarization layer 103 may cover the bottom conductive pattern DM and be disposed on the bottom surface 101D of the substrate 101.

[0127] In an embodiment, the display device may further include a second thin film transistor TFT'. The thin film transistor TFT may be a switching thin film transistor, and the second thin film transistor TFT' may be a driving thin film transistor.

[0128] The second thin film transistor TFT' may include a second semiconductor layer 212, a second gate electrode 214, a second drain electrode 216a, and a second source electrode 216b.

[0129] The second semiconductor layer 212 may be disposed between the buffer layer 111 and the first gate insulating layer 113a. Similar to the semiconductor layer 112, the second semiconductor layer 212 may include one of the following: polysilicon, amorphous silicon, oxide semiconductor, organic semiconductor, and combinations thereof. The second semiconductor layer 212 may include a second channel region 212c, a second drain region 212a, and a second source region 212b, and the second drain region 212a and the second source region 212b are respectively disposed on two opposite sides of the second channel region 212c. The second gate electrode 214 may overlap the second channel region 212c.

[0130] The second gate electrode 214 may be disposed between the first gate insulating layer 113a and the second gate insulating layer 113b. Similar to the gate electrode 114, the second gate electrode 214 may include a low-resistance metal material.

[0131] In an embodiment, a top electrode Cst2 may be disposed between the second gate insulating layer 113b and the first interlayer insulating layer 115a and may overlap the second gate electrode 214. For example, the second gate electrode 214 may be used as a bottom electrode Cst1 of a storage capacitor Cst.

[0132] This means that the storage capacitor Cst can overlap with the second thin film transistor TFT'. In another embodiment, the bottom electrode Cst1 of the storage capacitor Cst can be set to be separated from the second gate electrode 214 such that the storage capacitor Cst does not overlap with the second thin film transistor TFT'.

[0133] In an embodiment, at least one of the second drain electrode 216a and the second source electrode 216b can be disposed on the first interlayer insulating layer 115a. For example, the second drain electrode 216a and the second source electrode 216b can be disposed on the first interlayer insulating layer 115a. In another embodiment, similar to the source electrode 116b, at least one of the second drain electrode 216a and the second source electrode 216b can be disposed on the bottom surface 101D of the substrate 101. Hereinafter, for convenience of description, the case where the second drain electrode 216a and the second source electrode 216b can be disposed on the first interlayer insulating layer 115a will be described.

[0134] Similar to the drain electrode 116a and the source electrode 116b, the second drain electrode 216a and the second source electrode 216b can include a material having excellent conductivity.

[0135] In an embodiment, the connection electrode CM can be connected to the second drain electrode 216a through a contact hole. The connection electrode CM can connect the second thin film transistor TFT' to the organic light emitting diode OLED.

[0136] In an embodiment, the bottom conductive pattern DM can be a part of the data line DLm (see Figure 2 ).

[0137] The bottom conductive pattern DM can be disposed on the bottom surface 101D of the substrate 101 (e.g., via the bottom buffer layer 102) to reduce the parasitic capacitance Cp between the pixel electrode 121 and the source electrode 116b. The bottom conductive pattern DM can be a part of the data line DLm (see Figure 2 ), and the parasitic capacitance Cp can store a voltage corresponding to the difference between the data voltage DLV (see Figure 2 ) and the voltage of the pixel electrode 121.

[0138] In the case where the source electrode 116b (which can be a part of the data line) can be disposed on the first interlayer insulating layer 115a, the distance between the source electrode 116b and the pixel electrode 121 can be smaller than the distance in the case where the source electrode 116b can be disposed below the bottom surface 101D of the substrate 101. The value of the parasitic capacitance Cp may increase and the corresponding afterimage problem may increase.

[0139] Conversely, in a case where the source electrode 116b according to an embodiment may be disposed on the bottom surface 101D of the substrate 101 (e.g., via the bottom buffer layer 102), the value of the parasitic capacitance Cp may be reduced and the corresponding afterimage problem may be reduced.

[0140] Figure 6 FIG. is a schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 6 Since the same reference numerals as those in Figure 4 represent the same elements, a repeated description thereof may be omitted.

[0141] Referring to Figure 6 , the display device may include a substrate 101, a thin film transistor TFT on the top surface 101U, and an organic light emitting diode OLED connected to the thin film transistor TFT. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 penetrates through the top surface 101U and the bottom surface 101D.

[0142] A top conductive pattern UM may be disposed between the substrate 101 and the thin film transistor TFT. The top conductive pattern UM may overlap at least a part of the semiconductor layer 112. A bottom conductive pattern DM may be disposed on the bottom surface 101D of the substrate 101 and connected to the top conductive pattern UM through the first contact hole CNT1. A bottom planarization layer 103 may cover the bottom conductive pattern DM and be disposed under the bottom surface 101D of the substrate 101.

[0143] In an embodiment, a drain electrode 116a' may be disposed on the second interlayer insulating layer 115b. The drain electrode 116a' may be connected to the semiconductor layer 112 through a contact hole. Specifically, the drain electrode 116a' may be connected to the semiconductor layer 112 through contact holes that overlap each other and are respectively disposed in the first gate insulating layer 113a, the second gate insulating layer 113b, the first interlayer insulating layer 115a, and the second interlayer insulating layer 115b.

[0144] Figure 7 FIG. is a schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 7 Since the same reference numerals as those in Figure 4 represent the same elements, a repeated description thereof may be omitted.

[0145] Referring to Figure 7 , the display device may include a substrate 101, a thin film transistor TFT on the top surface 101U, and an organic light emitting diode OLED connected to the thin film transistor TFT. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 penetrates through the top surface 101U and the bottom surface 101D.

[0146] The top conductive pattern UM can be disposed between the substrate 101 and the thin film transistor TFT. The top conductive pattern UM can overlap at least a portion of the semiconductor layer 112. The bottom conductive pattern DM can be disposed on the bottom surface 101D of the substrate 101 and connected to the top conductive pattern UM through the first contact hole CNT1. The bottom planarization layer 103 can cover the bottom conductive pattern DM and be disposed under the bottom surface 101D of the substrate 101.

[0147] In an embodiment, the semiconductor layer 112 can completely overlap with the top conductive pattern UM. The semiconductor layer 112 can be disposed on the top conductive pattern UM. The semiconductor layer 112 can not include a step difference and can include a flat bottom surface.

[0148] Figure 8 FIG. is a schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 8 which, since the same reference numerals as those of Figure 4 represent the same elements, the repeated description thereof can be omitted.

[0149] In Figure 8 which, in order to show a figure in which the first bottom electrode Cst3 described below can be connected to the gate electrode 114, one of the pixels can be shown from the other side. Accordingly, the source region 112b of the semiconductor layer 112 can be omitted, and the connection between the drain electrode 116a and the source region 112b of the semiconductor layer 112 can be omitted.

[0150] Referring to Figure 8 , the display device can include a substrate 101, a thin film transistor TFT on the top surface 101U, and an organic light emitting diode OLED connected to the thin film transistor TFT. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 penetrates through the top surface 101U and the bottom surface 101D.

[0151] The top conductive pattern UM can be disposed between the substrate 101 and the thin film transistor TFT. The top conductive pattern UM can overlap at least a portion of the semiconductor layer 112. The bottom conductive pattern DM can be disposed on the bottom surface 101D of the substrate 101 and connected to the top conductive pattern UM through the first contact hole CNT1. The bottom planarization layer 103 can cover the bottom conductive pattern DM and be disposed under the bottom surface 101D of the substrate 101.

[0152] In an embodiment, the display device may further include a first bottom electrode Cst3. The first bottom electrode Cst3 may be disposed between the substrate 101 and the bottom planarization layer 103. In other words, the first bottom electrode Cst3 may be disposed under the bottom surface 101D of the substrate 101. In an embodiment, the first bottom electrode Cst3 may be disposed on the same layer as the layer on which the bottom conductive pattern DM may be disposed. The first bottom electrode Cst3 may be disposed to be spaced apart from the bottom conductive pattern DM.

[0153] In an embodiment, the first bottom electrode Cst3 may be connected to the gate electrode 114 through a third contact hole CNT3 of the substrate 101. Specifically, the first bottom electrode Cst3 may be connected to the gate electrode 114 through a contact hole of the bottom buffer layer 102, the third contact hole CNT3, a contact hole of the buffer layer 111, and a contact hole of the first gate insulating layer 113a. The contact hole of the bottom buffer layer 102, the third contact hole CNT3, the contact hole of the buffer layer 111, and the contact hole of the first gate insulating layer 113a may overlap with each other and thus be provided as one contact hole.

[0154] The first bottom electrode Cst3 may include a conductive material including Al, Cu, Ti, or a combination thereof, and the first bottom electrode Cst3 may include a single layer or multiple layers including the above materials. In an embodiment, the first bottom electrode Cst3 may have a multi-layer structure of Ti / Al / Ti.

[0155] In an embodiment, the bottom insulating layer 104 may be disposed under the bottom planarization layer 103. Similar to the bottom planarization layer 103, the bottom insulating layer 104 may include an inorganic insulating material or an organic insulating material. In an embodiment, the bottom insulating layer 104 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x )), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). In another embodiment, the bottom insulating layer 104 may include an organic insulating material including a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a parylene polymer, a polyvinyl alcohol polymer, or a combination thereof. The bottom insulating layer 104 may planarize the bottom surface 101D of the substrate 101. Hereinafter, for convenience of description, the case where the bottom insulating layer 104 includes an organic insulating material may be described.

[0156] The second bottom electrode Cst4 may be disposed between the bottom planarization layer 103 and the bottom insulating layer 104. In an embodiment, the second bottom electrode Cst4 may be disposed corresponding to the first bottom electrode Cst3. Thus, the first bottom electrode Cst3 and the second bottom electrode Cst4 may constitute the bottom storage capacitor Cst'.

[0157] The second bottom electrode Cst4 may include a conductive material including Al, Cu, Ti, or a combination thereof, and the second bottom electrode Cst4 may include a single layer or multiple layers including the above materials. In an embodiment, the second bottom electrode Cst4 may have a multi-layer structure of Ti / Al / Ti.

[0158] The arrangement in which the first bottom electrode Cst3 may be connected to the gate electrode 114 can be used to reduce the resistance of the gate electrode 114. Thus, the afterimage problem that may occur due to the large resistance of the gate electrode 114 can be solved.

[0159] Since the bottom storage capacitor Cst' can be formed above the bottom surface 101D of the substrate 101, the capacitance capacity design range of the storage capacitor can be increased.

[0160] Figure 9 It is a schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 9 Since the same reference numerals as those in Figure 4 represent the same elements, their repeated description can be omitted.

[0161] Referring to Figure 9 , the display device may include a substrate 101, a thin film transistor TFT on the top surface 101U, and an organic light emitting diode OLED connected to the thin film transistor TFT. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 penetrates through the top surface 101U and the bottom surface 101D.

[0162] The top conductive pattern UM may be disposed between the substrate 101 and the thin film transistor TFT. The top conductive pattern UM may overlap at least a part of the semiconductor layer 112. The bottom conductive pattern DM may be disposed on the bottom surface 101D of the substrate 101 and connected to the top conductive pattern UM through the first contact hole CNT1. The bottom planarization layer 103 may cover the bottom conductive pattern DM and be disposed under the bottom surface 101D of the substrate 101.

[0163] In an embodiment, the top conductive pattern UM may include a multi-layer structure. For example, the top conductive pattern UM may include a first layer UM1 and a second layer UM2. The second layer UM2 may be disposed on the first layer UM1.

[0164] In an embodiment, the second layer UM2 may include a material different from that of the first layer UM1. For example, the first layer UM1 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), aluminum zinc oxide (AZO), or a combination thereof. The first layer UM1 may include the same metal as that of the pixel electrode 121. The second layer UM2 may include a metal. For example, the second layer UM2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu).

[0165] The top conductive pattern UM may include a multi-layer structure to protect the top conductive pattern UM while the first contact hole CNT1 can be formed. In the case where the first contact hole CNT1 can be formed, a dry etching process may be used and the dry etching process will be described below. In the case where the substrate 101 can be etched, a part of the top conductive pattern UM may be damaged by the etching process. In an embodiment, since the top conductive pattern UM may include a multi-layer structure and the first layer UM1 may include a conductive oxide resistant to dry etching, damage to the second layer UM2 can be prevented.

[0166] Figure 10 is a schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 10 since the same reference numerals as those of Figure 4 represent the same elements, their repeated description may be omitted.

[0167] Referring to Figure 10 , the display device may include a substrate 101, a thin film transistor TFT on the top surface 101U, and an organic light emitting diode OLED connected to the thin film transistor TFT. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 passes through the top surface 101U and the bottom surface 101D.

[0168] The top conductive pattern UM may be disposed between the substrate 101 and the thin film transistor TFT. The top conductive pattern UM may overlap at least a part of the semiconductor layer 112. The bottom conductive pattern DM may be disposed on the bottom surface 101D of the substrate 101 and connected to the top conductive pattern UM through the first contact hole CNT1. The bottom planarization layer 103 may cover the bottom conductive pattern DM and be disposed under the bottom surface 101D of the substrate 101.

[0169] In an embodiment, the drain electrode 116a and the source electrode 116b may be disposed on the first interlayer insulating layer 115a. The source electrode 116b may be disposed to be separated from the bottom conductive pattern DM. For example, the source electrode 116b and the bottom conductive pattern DM may not be formed integrally.

[0170] In an embodiment, at least one of the drain electrode 116a and the source electrode 116b may be connected to the top conductive pattern UM through the fourth contact hole CNT4. The fourth contact hole CNT4 may include a contact hole of the buffer layer 111, a contact hole of the first gate insulating layer 113a, a contact hole of the second gate insulating layer 113b, and a contact hole of the first interlayer insulating layer 115a that overlap each other.

[0171] The source electrode 116b may be connected to the source region 112b of the semiconductor layer 112 through the fifth contact hole CNT5. The fifth contact hole CNT5 may include a contact hole of the first gate insulating layer 113a, a contact hole of the second gate insulating layer 113b, and a contact hole of the first interlayer insulating layer 115a that overlap each other. The fifth contact hole CNT5 may be disposed to be separated from the fourth contact hole CNT4. Specifically, the fifth contact hole CNT5 may be disposed to be separated from the fourth contact hole CNT4 in the x direction.

[0172] As described above, since the bottom conductive pattern DM and the source electrode 116b may be connected to the top conductive pattern UM, the afterimage problem that may occur due to the large resistance of the source electrode 116b may be eliminated.

[0173] Figure 11 Schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 11 Since the same reference numerals as those in Figure 10 represent the same elements, the repeated description thereof may be omitted.

[0174] Refer to Figure 11 A display device may include a substrate 101, a thin film transistor TFT on the top surface 101U, and an organic light emitting diode OLED connected to the thin film transistor TFT. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 passes through the top surface 101U and the bottom surface 101D. The bottom conductive pattern DM may be disposed below the bottom surface 101D of the substrate 101, and the bottom planarization layer 103 may cover the bottom conductive pattern DM.

[0175] In an embodiment, the bottom conductive pattern DM may be connected to at least one of the source electrode 116b and the drain electrode 116a through the first contact hole CNT1. The bottom conductive pattern DM may be connected to at least one of the source electrode 116b and the drain electrode 116a through a contact hole including the first contact hole CNT1 overlapping with each other, a contact hole of the buffer layer 111, a contact hole of the first gate insulating layer 113a, a contact hole of the second gate insulating layer 113b, and a contact hole of the first interlayer insulating layer 115a. The top conductive pattern may be omitted.

[0176] Figure 12 FIG. is a schematic cross-sectional view of a pixel of a display device according to another embodiment. In Figure 12 Since the same reference numerals as those in Figure 11 represent the same elements, their repeated description may be omitted.

[0177] Referring to Figure 12 , the display device may include a substrate 101, a thin film transistor TFT on the top surface 101U, and an organic light emitting diode OLED. The substrate 101 includes a first contact hole CNT1, and the first contact hole CNT1 passes through the top surface 101U and the bottom surface 101D.

[0178] The bottom conductive pattern DM may be disposed under the bottom surface 101D of the substrate 101 and connected to at least one of the source electrode 116b and the drain electrode 116a through the first contact hole CNT1. The bottom planarization layer 103 may cover the bottom conductive pattern DM.

[0179] In an embodiment, the display device may further include a conductive pattern 116c. The conductive pattern 116c may contact at least a part of the drain electrode 116a and the source electrode 116b. For example, the conductive pattern 116c may contact the bottom surface of the source electrode 116b. In an embodiment, the conductive pattern 116c may be disposed to be spaced apart from the fifth contact hole CNT5. The conductive pattern 116c may be disposed to correspond to the first contact hole CNT1.

[0180] In an embodiment, the conductive pattern 116c may be connected to the bottom conductive pattern DM through the first contact hole CNT1. Specifically, the conductive pattern 116c may be disposed to correspond to the first contact hole CNT1 and connected to the bottom conductive pattern DM. Therefore, the bottom conductive pattern DM may be connected to the source region 112b of the semiconductor layer 112 through the conductive pattern 116c and the source electrode 116b.

[0181] The conductive pattern 116c may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The conductive pattern 116c may include the same metal as that of the pixel electrode 121.

[0182] The display device includes the conductive pattern 116c to protect the source electrode 116b while the first contact hole CNT1 can be formed. In the case where the first contact hole CNT1 can be formed, the dry etching process described below can be used. In the case where the substrate 101 can be etched, a part of the source electrode 116b may be damaged by the etching process. On the contrary, the embodiment includes a structure in which the conductive pattern 116c can be disposed under the source electrode 116b, and the conductive pattern 116c includes a conductive oxide resistant to dry etching. Therefore, the damage to the source electrode 116b can be prevented.

[0183] By using the manufacturing method described below, the bottom conductive pattern DM can be formed on the bottom surface 101D of the substrate 101.

[0184] Figures 13A to 13G is a schematic cross-sectional view of a method for manufacturing a display device according to an embodiment. In Figures 13A to 13G since the same reference numerals as those in Figure 4 represent the same elements, their repeated description can be omitted.

[0185] Referring to Figure 13A , the substrate 101 can be formed on the first carrier substrate G1. The bottom surface 101D of the substrate 101 may face the first carrier substrate G1. In the embodiment, the bottom surface 101D of the substrate 101 may contact the first carrier substrate G1.

[0186] In the embodiment, the display layer DL can be formed on the top surface 101U of the substrate 101. The display layer DL may include a pixel circuit layer and a display element layer, the pixel circuit layer includes a pixel circuit and an insulating layer, and the display element layer includes display elements.

[0187] In addition to forming the display layer DL, the top conductive pattern UM can be formed. The top conductive pattern UM can be formed to correspond to the portion where the first contact hole CNT1 can be formed.

[0188] The display layer DL may include a thin film transistor on the buffer layer 111 covering the top conductive pattern UM, and the thin film transistor includes a semiconductor layer 112, and the semiconductor layer 112 overlaps with a part of the top conductive pattern UM. The top conductive pattern UM can be connected to the semiconductor layer 112 through the second contact hole CNT2.

[0189] The thin film encapsulation layer TFE and the input sensing layer TSL can be sequentially disposed on the display layer DL. In an embodiment, an optical functional layer can be further formed.

[0190] Reference Figure 13B , the first carrier substrate G1 can be detached. Specifically, the first carrier substrate G1 can be detached from the bottom surface 101D of the substrate 101. The bottom surface 101D of the substrate 101 can be exposed.

[0191] Reference Figure 13C , the second carrier substrate G2 can be attached. The second carrier substrate G2 can be attached to face the top surface 101U of the substrate 101. In other words, the second carrier substrate G2 can be attached on the display layer DL.

[0192] Reference Figure 13D , the bottom buffer layer 102 can be formed on the bottom surface 101D of the substrate 101.

[0193] Reference Figure 13E , the first contact hole CNT1 can be formed, and the first contact hole CNT1 penetrates through the top surface 101U and the bottom surface 101D of the substrate 101.

[0194] The first contact hole CNT1 can be formed by the method described below.

[0195] A photoresist pattern can be formed on the bottom buffer layer 102.

[0196] The bottom contact hole CNTC can be formed in the top portion of the bottom buffer layer 102. The etching process can be a dry etching process.

[0197] By using the etching process, the first contact hole CNT1 can be formed in the top portion of the bottom surface 101D of the substrate 101. The first contact hole CNT1 can be connected to the bottom contact hole CNTC. The first contact hole CNT1 can expose the top conductive pattern UM. The etching process can be a dry etching process.

[0198] The photoresist pattern can be removed. For the method of removing the photoresist pattern, a known method can be used.

[0199] Reference Figure 13F , the bottom conductive pattern DM can be formed on the bottom buffer layer 102. The bottom conductive pattern DM can be formed by the following: forming a conductive layer through a deposition process and performing a patterning process. The bottom conductive pattern DM can be formed to correspond to the first contact hole CNT1. The bottom conductive pattern DM can be connected to the top conductive pattern UM through the first contact hole CNT1 and the bottom contact hole CNTC.

[0200] Reference Figure 13G, the bottom planarization layer 103 may cover the bottom conductive pattern DM. In an embodiment, when the bottom planarization layer 103 includes an organic material, the top surface of the bottom planarization layer 103 may be flat. In another embodiment, when the bottom planarization layer 103 includes an inorganic material, a chemical mechanical polishing (CMP) process may be additionally performed. The top surface of the bottom planarization layer 103 may be flat.

[0201] Figure 14A and Figure 14B is a schematic cross-sectional view of a method for manufacturing a display device according to another embodiment. In Figure 14A and Figure 14B , since the same reference numerals as those in Figure 13E and Figure 13F represent the same elements, their repeated description may be omitted.

[0202] Referring to Figure 14A and Figure 14B , during the operation of forming the display layer DL, the top conductive pattern UM may be formed on a portion where the first contact hole CNT1 may be formed.

[0203] In an embodiment, the top conductive pattern UM may include a first layer UM1 and a second layer UM2 including a metal different from the metal of the first layer UM1.

[0204] In an embodiment, the second layer UM2 may include a material different from the material of the first layer UM1. For example, the first layer UM1 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), aluminum zinc oxide (AZO).

[0205] In an embodiment, since the first layer UM1 includes a conductive oxide that resists dry etching, damage to the second layer UM2 can be prevented.

[0206] As described above, the embodiments may provide a display device including a conductive pattern on the bottom surface of a substrate, and a method for manufacturing the display device.

[0207] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of each feature or aspect in an embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art should understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims (including any equivalent means).

Claims

1. A display device, the display device comprising: a substrate, the substrate including a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface; a thin film transistor, the thin film transistor disposed above the top surface and including a semiconductor layer; a display element, the display element connected to the thin film transistor; a top conductive pattern, the top conductive pattern disposed between the substrate and the thin film transistor and overlapping the semiconductor layer of the thin film transistor; a bottom conductive pattern, the bottom conductive pattern disposed on the bottom surface and connected to the top conductive pattern through the first contact hole; a bottom planarization layer, the bottom planarization layer disposed on the bottom surface, the bottom planarization layer disposed on the bottom conductive pattern; and a bottom buffer layer, the bottom buffer layer disposed between the substrate and the bottom conductive pattern, the bottom buffer layer including an insulating material and a bottom contact hole connected to the first contact hole.

2. The display device according to claim 1, further comprising a buffer layer, the buffer layer disposed above the top conductive pattern and including a second contact hole, wherein the semiconductor layer is connected to the top conductive pattern through the second contact hole, wherein the first contact hole is disposed to be spaced apart from the second contact hole in a second direction intersecting a first direction perpendicular to the top surface.

3. The display device according to claim 1, wherein the substrate comprises: a base layer, the base layer including a polymer resin; and a barrier layer, the barrier layer including an inorganic material, wherein the base layer and the barrier layer are alternately stacked.

4. The display device according to claim 1, wherein: the thin film transistor includes a gate electrode, the gate electrode disposed above the semiconductor layer, and the gate electrode is connected to a first bottom electrode through a third contact hole in the substrate, the first bottom electrode disposed between the substrate and the bottom planarization layer.

5. The display device according to claim 4, further comprising: a bottom insulating layer, the bottom insulating layer below the bottom planarization layer; and a second bottom electrode, the second bottom electrode between the bottom planarization layer and the bottom insulating layer, the second bottom electrode corresponding to the first bottom electrode.

6. The display device according to claim 1, wherein the top conductive pattern comprises: a first layer, the first layer including a conductive oxide; and a second layer, the second layer including a metal.

7. The display device according to claim 1, wherein, the thin film transistor includes a source electrode and a drain electrode, the source electrode and the drain electrode each connected to the semiconductor layer disposed on the top surface, and at least one of the source electrode and the drain electrode is connected to the top conductive pattern through a fourth contact hole.

8. A display device, the display device comprising: a substrate, the substrate including a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface; A thin-film transistor, the thin-film transistor including a semiconductor layer, a source electrode, and a drain electrode each disposed above the top surface; A display element, the display element being connected to the thin-film transistor and disposed above the top surface; A bottom conductive pattern, the bottom conductive pattern being disposed on the bottom surface and connected to at least one of the source electrode and the drain electrode through the first contact hole; A bottom planarization layer, the bottom planarization layer being disposed on the bottom conductive pattern; And A bottom buffer layer, the bottom buffer layer being disposed between the substrate and the bottom conductive pattern, the bottom buffer layer including an insulating material and a bottom contact hole connected to the first contact hole.

9. A method of manufacturing a display device, the method comprising: Forming a display layer including a display element on a top surface of a substrate disposed on a first carrier substrate; Detaching the first carrier substrate from the bottom surface of the substrate; Attaching a second carrier substrate such that the second carrier substrate faces the top surface of the substrate; Forming a first contact hole in the substrate; Forming a bottom conductive pattern on the bottom surface, the bottom conductive pattern corresponding to the first contact hole; And Forming a bottom buffer layer, the bottom buffer layer being disposed between the substrate and the bottom conductive pattern, the bottom buffer layer including an insulating material and a bottom contact hole connected to the first contact hole.

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