Semiconductor memory device and method for manufacturing the same

Abstract

A semiconductor memory device and a manufacturing method thereof are provided. The semiconductor memory device comprises: a substrate including a cell array region and a boundary region; a first recessed region at an upper portion of the substrate located in the cell array region; a first bit line extending onto the boundary region and intersecting the first recessed region; a bit line contact in the first recessed region and contacting the first bit line; a second bit line spaced apart from the first recessed region and adjacent to the first bit line, the second bit line intersecting the cell array region and the boundary region; a cell buried insulating pattern between a side surface of the first bit line contact and an inner wall of the first recessed region; and a boundary buried insulating pattern covering the side walls of the first bit line and the second bit line in the boundary region and comprising the same material as that of the cell buried insulating pattern.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0133002, filed on October 24, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. Background Art

[0003] Semiconductor memory devices are widely used as key components in various electronic industries due to their characteristics such as miniaturization, multi-function and / or low manufacturing cost. However, as the electronic industry continues to develop, highly integrated semiconductor memory devices are being manufactured. In highly integrated semiconductor memory devices, the line width of each pattern thereof is miniaturized. However, forming a highly integrated semiconductor memory device with miniaturized patterns requires new exposure technology and / or expensive exposure technology. Therefore, new integration technologies are being studied. Summary of the invention

[0004] In an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a substrate including a cell array region and a boundary region; a first recessed region disposed at an upper portion of the substrate located in the cell array region; a first bit line extending onto the boundary region and intersecting the first recessed region; a bit line contact disposed in the first recessed region and contacting the first bit line; a second bit line spaced apart from the first recessed region and adjacent to the first bit line, the second bit line intersecting the cell array region and the boundary region; a cell buried insulating pattern disposed between a side surface of the bit line contact and an inner wall of the first recessed region; and a boundary buried insulating pattern covering side walls of the first and second bit lines in the boundary region and including the same material as that of the cell buried insulating pattern.

[0005] In an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a substrate, including a cell array region and a boundary region; a first recessed region, arranged at an upper portion of the substrate located in the cell array region; a first bit line, extending onto the boundary region and intersecting the first recessed region; a bit line contact, arranged in the first recessed region and contacting the first bit line; a second bit line, spaced apart from the first recessed region and adjacent to the first bit line, the second bit line intersecting the cell array region and the boundary region; a cell buried insulating pattern, placed between a side surface of the bit line contact and an inner wall of the first recessed region; a bit line spacer, covering a side wall of the first bit line in the cell array region; a boundary buried insulating pattern, covering a side wall of the first bit line and a second bit line in the boundary region, including a second recessed region, and including a material that is the same as that of the cell buried insulating pattern; and a residual spacer pattern, filling the second recessed region, wherein a top surface of the residual spacer pattern is coplanar with a top surface of the boundary buried insulating pattern.

[0006] In an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a substrate, including a cell array region and a boundary region; a first recessed region, arranged at an upper portion of the substrate located in the cell array region; a first bit line, extending onto the boundary region and intersecting the first recessed region; a second bit line, spaced apart from the first recessed region and adjacent to the first bit line, the second bit line intersecting the cell array region and the boundary region; a cell buried insulating pattern, disposed between a lower side surface of the first bit line and an inner wall of the first recessed region; a first spacer, a second spacer, and a third spacer, sequentially covering a side wall of the first bit line in the cell array region, the third spacer including a material different from that of the second spacer; a boundary buried insulating pattern, covering the side walls of the first and second bit lines in the boundary region, including the second recessed region and including a material identical to that of the cell buried insulating pattern; and a first residual spacer pattern, arranged in the second recessed region and including a material identical to that of the third spacer.

[0007] In an exemplary embodiment of the inventive concept, a method for manufacturing a semiconductor memory device includes the following steps: receiving a substrate including a cell array region and a boundary region; forming a first recessed region on the substrate in the cell array region; forming a bit line contact in the first recessed region, a first bit line contacts the bit line contact, and a second bit line is spaced apart from the first bit line and the first recessed region, wherein each of the first bit line and the second bit line extends onto the boundary region; filling the first recessed region with a cell buried insulating pattern; forming a boundary buried insulating pattern including a second recessed region, wherein the boundary buried insulating pattern contacts the side walls of the first bit line and the second bit line in the boundary region; covering the side walls of the first bit line in the cell array region with a bit line spacer; and filling the second recessed region with a residual spacer pattern, wherein the residual spacer pattern is formed by a portion of the bit line spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept together with the accompanying drawings. In the accompanying drawings:

[0009] Figure 1A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0010] Figure 1B According to an exemplary embodiment of the inventive concept Figure 1A A cross-sectional view taken along line AA' and line BB';

[0011] Figure 1C According to an exemplary embodiment of the inventive concept Figure 1A A cross-sectional view taken along line CC';

[0012] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A is a diagram sequentially showing the manufacturing process of an exemplary embodiment according to the inventive concept. Figure 1A A plan view of a process for producing a semiconductor memory device of a plan view;

[0013] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B According to an exemplary embodiment of the inventive concept FIG. 2A to FIG. 15A A cross-sectional view taken along line AA' and line BB';

[0014] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C and Fig. 15C According to an exemplary embodiment of the inventive concept FIG. 2A to FIG. 15A A cross-sectional view taken along line CC';

[0015] Fig.16A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0016] Fig. 16B According to an exemplary embodiment of the inventive concept Fig.16A A cross-sectional view taken along line AA' and line BB';

[0017] Fig. 16C According to an exemplary embodiment of the inventive concept Fig.16A A cross-sectional view taken along line CC';

[0018] Fig.17A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0019] Fig. 17B According to an exemplary embodiment of the inventive concept Fig.17A A cross-sectional view taken along line CC';

[0020] Fig.18A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0021] Fig.18B According to an exemplary embodiment of the inventive concept Fig.18A A cross-sectional view taken along line AA' and line BB'; and

[0022] Fig.19 According to an exemplary embodiment of the inventive concept Figure 1A A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings.

[0024] Figure 1A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept. Figure 1B According to an exemplary embodiment of the inventive concept Figure 1A A cross-sectional view taken along line AA' and line BB'. Figure 1C According to an exemplary embodiment of the inventive concept Figure 1A A cross-sectional view taken along line CC'.

[0025] Reference Figures 1A to 1C , a semiconductor substrate 100 (hereinafter, referred to as a substrate) is provided. The substrate 100 may include a cell array region CAR and a boundary region INT adjacent thereto. The boundary region INT may be disposed between the cell array region CAR and the peripheral circuit region. When the device separation pattern 102 is disposed on the substrate 100 in the cell array region CAR, an active portion ACT may be defined. Each active portion ACT may have an isolated shape. Each active portion ACT may have a strip shape elongated in a first direction D1 in a plan view. In a plan view, the active portion ACT may correspond to portions of the substrate 100 respectively surrounded by the device separation patterns 102. The device separation pattern 102 may be disposed in the boundary region INT.

[0026] The substrate 100 may include a semiconductor material. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Each device separation pattern 102 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and / or an oxynitride (e.g., silicon oxynitride). The active portions ACT may be arranged parallel to each other in the first direction D1, and an end portion of each active portion ACT may be arranged adjacent to the center of another active portion adjacent thereto.

[0027] In the cell array region CAR, the word line WL may intersect the active portion ACT. The word line WL may be disposed in a groove defined in the device separation pattern 102 and the active portion ACT. For example, the word line WL may be positioned close to the substrate 100. The word line WL may be parallel to the second direction D2 intersecting the first direction D1. The word line WL may be made of a conductive material. A gate dielectric layer 107 may be disposed between each word line WL and the inner surface of each groove. In other words, the gate dielectric layer 107 may be disposed between each word line WL and the device separation pattern 102. Each groove may have a bottom that is relatively deep in the device separation pattern 102 and relatively shallow in the active portion ACT. The gate dielectric layer 107 may include at least one of thermal oxide, silicon nitride, silicon oxynitride, and a high-K dielectric material. Each word line WL may have a curved bottom surface. The bottom surface of the word line WL on the device separation pattern 102 may be lower than the bottom surface of the word line WL on the active portion ACT.

[0028] The first doped region 112a may be disposed in each active portion ACT between a pair of word lines WL, and a pair of second doped regions 112b may be disposed in two edge regions of the active portion ACT, respectively. The first doped region 112a and the second doped region 112b may be doped with, for example, n-type impurities. The first doped region 112a may correspond to a common drain region, and the second doped region 112b may correspond to a source region. Each word line WL and the first doped region 112a and the second doped region 112b adjacent thereto may provide a transistor. Since the word line WL is disposed in a groove, the channel depth of the channel region below the word line WL may be increased in a restricted flat region. Therefore, for example, the short channel effect may be minimized.

[0029] Each word line WL may have a top surface lower than the top surface of each active portion ACT. A word line capping pattern 110 may be provided on each word line WL. Each word line capping pattern 110 may have a line shape extending in the longitudinal direction of the word line WL and may cover the entire top surface of each word line WL. The word line capping pattern 110 may fill a groove above the word line WL. The word line capping pattern 110 may be provided as, for example, a silicon nitride layer.

[0030] The lower interlayer insulating pattern 5c may be disposed on the substrate 100. The lower interlayer insulating pattern 5c may be disposed as at least one single layer or multiple layers selected from the group consisting of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0031] An upper portion of each of the substrate 100, the device separation pattern 102, and the word line capping pattern 110 may be partially recessed to provide a first recessed region R1. The first recessed region R1 may have a mesh shape in a plan view.

[0032] The bit line BL may be disposed on the lower interlayer insulating pattern 5c. The bit line BL may cross the word line capping pattern 110 and the word line WL. Figure 1A As shown in , the bit line BL may be parallel to a third direction D3 intersecting the first direction D1 and the second direction D2. For example, the bit line BL may extend along the third direction D3 and be spaced apart from each other in the second direction D2. The bit line BL may include a bit line polysilicon pattern 130, a bit line ohmic pattern 131, and a bit line metal-containing pattern 132 stacked sequentially. The bit line polysilicon pattern 130 may include polysilicon doped or undoped with impurities. The bit line ohmic pattern 131 may include a metal silicide layer. The bit line metal-containing pattern 132 may include at least one of a metal (e.g., tungsten, titanium, tantalum, etc.) and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and tungsten nitride). A bit line capping pattern 137 may be disposed on each bit line BL. The bit line capping pattern 137 may be made of an insulating material. For example, the bit line capping pattern 137 may include a nitride (e.g., silicon nitride) and / or a nitride oxide (e.g., silicon oxynitride).

[0033] The bit line contacts DC may be respectively disposed in the first recessed regions R1 crossing below the bit lines BL. The bit line contacts DC may include polysilicon doped with impurities. The bit line contacts DC may electrically connect the first doped regions 112a and the bit lines BL. For example, the bit line contacts DC may be extended bit line polysilicon patterns 130.

[0034] The cell buried insulating pattern 141 may be disposed in the first recessed region R1 in which the bit line contact DC is not disposed. The cell buried insulating pattern 141 may be disposed as at least one single layer or multiple layers selected from the group consisting of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The cell insulating liner 140 may be disposed between the cell buried insulating pattern 141 and the inner wall of the first recessed region R1 and between the cell buried insulating pattern 141 and the bit line contact DC. The cell insulating liner 140 may have an upper end positioned equal to or higher than the upper end of the cell buried insulating pattern 141. The cell insulating liner 140 may be made of an insulating material having an etching selectivity relative to the cell buried insulating pattern 141. For example, the cell buried insulating pattern 141 may be disposed as a silicon nitride layer, and the cell insulating liner 140 may be disposed as a silicon oxide layer.

[0035] The storage node contact BC may be disposed between a pair of bit lines BL adjacent to each other. The storage node contacts BC may be spaced apart from each other. The storage node contact BC may include polysilicon doped or undoped with impurities. The insulating fence 40 may be disposed between the storage node contacts BC located between the bit lines BL. The insulating fence 40 may be provided as an insulating layer, such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The storage node contacts BC and the insulating fence 40 may be arranged alternately and repeatedly along the bit line BL at one side of a bit line BL. The insulating fence 40 may have an upper end height greater than the upper end height of each storage node contact BC. In other words, the insulating fence 40 may protrude above the storage node contact BC.

[0036] The bonding pad LP is disposed on the storage node contact BC. The bonding pad LP may be made of a metal-containing material such as tungsten. The bonding pad LP may have an upper portion covering the top surface of the bit line cover pattern 137 and having a width greater than that of the storage node contact BC. The bonding pad LP may have a center offset from the center of the storage node contact BC in the second direction D2. The bit line BL may have a portion vertically overlapped with the bonding pad LP.

[0037] The storage node ohmic layer and the anti-diffusion pattern may be disposed between the storage node contact BC and the bonding pad LP. The storage node ohmic layer may include a metal silicide. The anti-diffusion pattern may include a metal nitride such as a titanium nitride layer and a tantalum nitride layer.

[0038] The first spacer 21, the second spacer 23, and the third spacer 25 may be disposed between the bit line BL and the storage node contact BC. The first spacer 21 may cover the sidewall of the bit line BL and the sidewall of the bit line cover pattern 137. The first spacer 21 may extend to be disposed between the cell insulating liner 140 and the bit line contact DC, between the cell insulating liner 140 and the inner wall of the first recessed region R1, and between the cell insulating liner 140 and the bottom surface of the first recessed region R1. The second spacer 23 may be disposed between the first spacer 21 and the third spacer 25. The second spacer 23 may have a lower end contacting the top surface of the lower interlayer insulating pattern 5c, the upper end of the cell insulating liner 140, and the upper end of the cell buried insulating pattern 141. The third spacer 25 may have a lower end covering the side surface of the lower interlayer insulating pattern 5c and contacting the top surface of the cell buried insulating pattern 141. The second spacer 23 may include an insulating material having an etching selectivity relative to the first spacer 21 and the third spacer 25. For example, the second spacer 23 may be provided as a silicon oxide layer, and each of the first spacer 21 and the third spacer 25 may be provided as a silicon nitride layer. Alternatively, the second spacer 23 may be an air gap region.

[0039] Each of the second spacer 23 and the third spacer 25 may have a top surface lower than that of the first spacer 21 to expose the sidewall of the first spacer 21. The fourth spacer 27b may be disposed between the upper sidewall of the first spacer 21 and the bonding pad LP. The fourth spacer 27b may contact the top surface of the second spacer 23. The storage node contact BC may have a top surface lower than that of the third spacer 25 to expose the upper sidewall of the third spacer 25. The fifth spacer 27c may be disposed between the upper sidewall of the third spacer 25 and the bonding pad LP. The fifth spacer 27c may have a Figure 1A The fourth spacer 27b and the fifth spacer 27c may include the same material. The first spacer 21, the second spacer 23, the third spacer 25, the fourth spacer 27b and the fifth spacer 27c may constitute a bit line spacer SP ( Fig. 15B ).

[0040] The bonding pads LP may be spaced apart from each other by the bonding pad separation pattern 148. The bonding pad separation pattern 148 may extend into the bit line capping pattern 137 and contact the top surface of the second spacer 23. The bonding pad separation pattern 148 may include, for example, at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The bonding pad separation pattern 148 may extend into the insulating fence 40 ( Figure 1C ). For example, when the bonding pad separation pattern 148 is disposed in the insulating fence 40, the bottom of the bonding pad separation pattern 148 may be disposed above the storage node contact BC.

[0041] The device separation pattern 102 in the boundary region INT may be covered by the boundary etch stop pattern 5b. The boundary etch stop pattern 5b may have the same material and structure as the material and structure of the lower interlayer insulating pattern 5c. The bit line BL may have an end extending onto the boundary region INT to contact the boundary etch stop pattern 5b. In the boundary region INT, the side surface of the bit line BL, the side surface of the bit line cover pattern 137, and the top surface of the boundary etch stop pattern 5b may be covered by the first residual spacer pattern 21r. The first residual spacer pattern 21r and the first spacer 21 may be connected to each other in a plan view and include the same material.

[0042] The first residual spacer pattern 21r may contact the boundary insulating liner 140r. The boundary insulating liner 140r may include the same material as that of the cell insulating liner 140. The boundary insulating liner 140r may contact the boundary buried insulating pattern 141r. The boundary buried insulating pattern 141r may include the same material as that of the cell buried insulating pattern 141. The boundary insulating liner 140r and the boundary buried insulating pattern 141r may be adjacent to the sidewalls of the adjacent bit line BL and the sidewalls of the adjacent bit line capping pattern 137 and may cover the boundary etch stop pattern 5b disposed therebetween. Figure 1C As shown in , the boundary etching stop pattern 5b, the first residual spacer pattern 21r, the boundary insulating liner 140r and the boundary buried insulating pattern 141r may be formed in sequence. The second recessed region R2 is disposed at the center of the boundary insulating liner 140r. The third residual spacer pattern 25r may be disposed in the second recessed region R2. The second residual spacer pattern 23r may be disposed between the third residual spacer pattern 25r and the boundary buried insulating pattern 141r. The second residual spacer pattern 23r may include the same material as the material of the second spacer 23. The third residual spacer pattern 25r may include the same material as the material of the third spacer 25.

[0043] Each of the first residual spacer pattern 21r, the boundary buried insulating pattern 141r, and the third residual spacer pattern 25r may have a top surface having the same height as that of the bit line capping pattern 137. Each of the boundary insulating liner 140r and the second residual spacer pattern 23r may have a top surface located lower than the top surface of the bit line capping pattern 137. The boundary insulating liner 140r may expose upper sidewalls of the first residual spacer pattern 21r and the boundary buried insulating pattern 141r adjacent thereto. Figure 1C As shown in FIG, the second residual spacer pattern 23r may directly contact edges of the boundary etch stop pattern 5b, the first residual spacer pattern 21r, the boundary insulating liner 140r, and the boundary buried insulating pattern 141r. The fourth residual spacer pattern 27r1 may be disposed between the third residual spacer pattern 25r and the boundary buried insulating pattern 141r.

[0044] The second residual spacer pattern 23r may expose the upper sidewalls of the third residual spacer pattern 25r and the boundary buried insulating pattern 141r adjacent to the second residual spacer pattern 23r. The fifth residual spacer pattern 27r2 may be disposed between the upper sidewall of the boundary buried insulating pattern 141r and the upper sidewall of the first residual spacer pattern 21r. The fourth residual spacer pattern 27r1 and the fifth residual spacer pattern 27r2 may include the same material as the fourth spacer 27b and the fifth spacer 27c. The fourth residual spacer pattern 27r1 and the fifth residual spacer pattern 27r2 may have an upper surface coplanar with the top surface of the bit line capping pattern 137.

[0045] exist Figure 1C In the cross-sectional view of , the second residual spacer pattern 23r may cover the sidewalls of the boundary etch stop pattern 5b, the first residual spacer pattern 21r, the boundary insulating liner 140r, and the boundary buried insulating pattern 141r. The third residual spacer pattern 25r may have a portion covering the sidewall of the second residual spacer pattern 23r. For example, the portion of the third residual spacer pattern 25r covering the sidewall of the second residual spacer pattern 23r may contact the cell buried insulating pattern 141 adjacent to the second residual spacer pattern 23r. The boundary insulating fence 40r may be disposed on the third residual spacer pattern 25r. The boundary insulating fence 40r may include the same material as the insulating fence 40. The boundary insulating fence 40r may be disposed in the third residual spacer pattern 25r and have a top surface coplanar with a top surface of the third residual spacer pattern 25r.

[0046] In a plan view, the first spacer 21 and the first residual spacer pattern 21r may be connected in an integrated (or one-piece) form. The second spacer 23 and the second residual spacer pattern 23r may be connected in an integrated manner. The third spacer 25 and the third residual spacer pattern 25r may be connected in an integrated manner. The fourth spacer 27b and the fifth spacer 27c may be connected to the fourth residual spacer pattern 27r1 in an integrated manner.

[0047] The upper interlayer insulating pattern 152 may be disposed on the bit line capping pattern 137 in the boundary region INT ( Figure 1B The upper interlayer insulating pattern 152 may also be disposed on the third residual spacer pattern 25r and the boundary insulating fence 40 in the boundary region INT ( Figure 1C ). The boundary line 150 may be disposed in the upper interlayer insulating pattern 152. The boundary line 150 may be connected to an end of the bit line BL or a circuit disposed at a peripheral circuit. The boundary line 150 may include the same material as that of the bonding pad LP.

[0048] In an exemplary embodiment of the inventive concept, the space between the bit lines BL is buried by the boundary buried insulating pattern 141r, the first to fifth residual spacer patterns 21r, 23r, 25r, 27r1, and 27r2, etc. The first to fifth residual spacer patterns 21r, 23r, 25r, 27r1, and 27r2 may constitute a portion of the bit line spacer SP. Therefore, bridging between the boundary line 150 and the storage node contact BC or the bit line contact DC adjacent thereto may be prevented. Therefore, malfunction of the semiconductor memory device may be prevented to enhance reliability.

[0049] FIG. 2A to FIG. 15A is a diagram sequentially showing the manufacturing process of an exemplary embodiment according to the inventive concept. Figure 1A A plan view of a process of a semiconductor memory device is shown in FIG. Figures 2B to 15B According to an exemplary embodiment of the inventive concept FIG. 2A to FIG. 15A A cross-sectional view taken along line AA' and line BB'. Figures 2C to 15C According to an exemplary embodiment of the inventive concept FIG. 2A to FIG. 15A A cross-sectional view taken along line CC'.

[0050] Reference FIG. 2A to FIG. 2C , a substrate 100 having a cell array region CAR and a boundary region INT is provided. A device separation pattern 102 may be formed on the substrate 100 to define an active portion ACT. The device separation pattern 102 may cover the entire boundary region INT. The active portion ACT may not be formed in the boundary region INT. A device separation trench may be formed in the substrate 100, and the device separation pattern 102 may fill the device separation trench. The device separation pattern 102 may include, for example, at least one material of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. In a plan view, the active portions ACT may be parallel to each other in a first direction D1. For example, the active portion ACT may have a shape such as Figure 2A . The grooves may be formed by patterning the active portion ACT and the device separation pattern 102. Here, by adjusting the etching conditions relative to the substrate 100 and the device separation pattern 102, the device separation pattern 102 may be etched further than the substrate 100. Therefore, each groove may have a curved bottom surface. In other words, the bottom surface of each groove may be deeper in the device separation pattern 102 than in the substrate 100.

[0051] Word lines WL may be formed in the grooves, respectively. A pair of word lines WL may intersect each active portion ACT. Before forming the word lines WL, a gate dielectric layer 107 may be formed on the inner surface of each groove. The gate dielectric layer 107 may be formed by a thermal oxidation process, a chemical vapor deposition process, and / or an atomic layer deposition process. The gate dielectric layer 107 may be formed, for example, by a silicon oxide layer, a silicon nitride layer, and / or a metal oxide layer. Thereafter, the word lines WL may be formed so that the grooves are filled by stacking gate conductive layers, and then the grooves are etched back. Each gate conductive layer may be formed, for example, of polysilicon doped with impurities, a metal nitride layer, and / or a metal. The top surface of the word line WL may be recessed to be lower than the top surface of the active portion ACT. The word line WL may extend in a second direction D2 intersecting the first direction D1. A word line capping pattern 110 may be formed on each word line WL so that the grooves are filled by stacking an insulating layer such as a silicon nitride layer on the substrate 100, and then the grooves are etched back. The first and second doped regions 112 a and 112 b may be formed by implanting dopants into the active portion ACT using the word line capping pattern 110 and the device separation pattern 102 as masks.

[0052] Reference FIG. 3A to FIG. 3C , an etch stop layer and a first polysilicon layer may be sequentially stacked on the front surface of the substrate 100. The polysilicon mask pattern 130a may be formed by patterning the first polysilicon layer. The etch stop layer, the device separation pattern 102, the substrate 100, and the word line capping pattern 110 may be etched by using the polysilicon mask pattern 130a as an etching mask to form a cell etch stop pattern 5a in the cell array region CAR, and simultaneously form a first recessed region R1 in the cell array region CAR. Here, the etch stop pattern 5b may be formed in the boundary region INT.

[0053] The unit etch stop pattern 5a and the boundary etch stop pattern 5b may be formed as at least one single layer or multiple layers of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The unit etch stop pattern 5a may be formed by a plurality of islands spaced apart from each other. The unit etch stop pattern 5a may cover the ends of two adjacent active portions ACT at the same time. For example, the ends of a single active portion ACT may be covered by the unit etch stop pattern 5a. The first recessed region R1 may have a mesh shape in a plan view. The first recessed region R1 may expose the first doped region 112a.

[0054] Reference FIG. 4A to FIG. 4C, the first recessed region R1 may be filled by stacking a second polysilicon layer 129 on the front surface of the substrate 100. In addition, the second polysilicon layer 129 located on the polysilicon mask pattern 130a may be removed by performing a planarization etching process on the second polysilicon layer 129 to expose the top surface of the polysilicon mask pattern 130a. A bit line ohmic layer 131a, a bit line metal-containing layer 132a, and a bit line capping layer 137a may be sequentially stacked on the polysilicon mask pattern 130a and the second polysilicon layer 129. The bit line ohmic layer 131a may be formed of a metal silicide such as cobalt silicide. The bit line ohmic layer 131a may be formed such that a metal layer is deposited on the polysilicon mask pattern 130a and the second polysilicon layer 129, and then a heat treatment process is performed, the polysilicon of the second polysilicon layer 129 and the polysilicon mask pattern 130a reacts with the metal layer to form a metal silicide, and then the unreacted metal layer is removed. The bit line metal-containing layer 132a may include, for example, tungsten. The bit line capping layer 137a may be formed of, for example, a silicon nitride layer.

[0055] A first mask pattern 139 defining a planar shape of the bit line BL may be formed on the bit line capping layer 137a. The first mask pattern 139 may be made of a material having an etching selectivity with respect to the bit line capping layer 137a, for example, an amorphous carbon layer (ACL), a silicon oxide layer, a spin-on hard mask (SOH), or a photoresist pattern. The first mask pattern 139 may extend in a third direction D3 that intersects both the first direction D1 and the second direction D2.

[0056] Reference FIG. 5A to FIG. 5C , a bit line BL including a bit line polysilicon pattern 130, a bit line ohmic pattern 131, and a bit line metal containing pattern 132, a bit line contact DC, and a bit line capping pattern 137 may be formed by sequentially etching the bit line capping layer 137a, the bit line metal containing layer 132a, the bit line ohmic layer 131a, the polysilicon mask pattern 130a, and the second polysilicon layer 129 using the first mask pattern 139 as an etching mask. In addition, the top surfaces of the etch stop patterns 5a and 5b and the inner wall and bottom surface of the first recessed region R1 may be partially exposed. The first mask pattern 139 may be removed.

[0057] Reference FIG. 6A to FIG. 6C, a first spacer layer 21a, an insulating liner layer 140a, and a buried insulating layer 141a may be conformally formed on the front surface of the substrate 100. The buried insulating layer 141a may have a thickness sufficient to fill the first recessed region R1. The first spacer layer 21a and the buried insulating layer 141a may include, for example, a silicon nitride layer. The insulating liner layer 140a may include, for example, a silicon oxide layer. In addition, a second mask pattern 142 that exposes the cell array region CAR while covering the boundary region INT may be formed on the buried insulating layer 141a. The second mask pattern 142 may include, for example, at least one single layer or multiple layers of an amorphous carbon layer (ACL), a silicon oxide layer, a spin-on hard mask (SOH), and a photoresist pattern.

[0058] Reference FIG. 7A to FIG. 7C , a cell insulating pad 140 and a cell buried insulating pattern 141 may be formed in the first recessed region R1 by performing an anisotropic etching process on the buried insulating layer 141a, the insulating liner layer 140a, and the first spacer layer 21a in the cell array region CAR using the second mask pattern 142 as an etching mask, and the top surface of the cell etching stop pattern 5a is exposed at the same time. In addition, a first spacer 21 may be formed. The first residual spacer pattern 21r, the boundary insulating pad 140r, and the boundary buried insulating pattern 141r may remain in the boundary region INT. In addition, the boundary buried insulating pattern 141r may be exposed by removing the second mask pattern 142. The cell buried insulating pattern 141 and the boundary buried insulating pattern 141r may be formed as part of the buried insulating layer 141a. The cell insulating pad 140 and the boundary insulating pad 140r may be formed as part of the insulating liner layer 140a. The first spacer 21 and the first residual spacer pattern 21 r may be formed as a portion of the first spacer layer 21 a .

[0059] Refer to 8A to Figure 8C , a second spacer 23 covering the sidewalls of the first spacer 21 in the cell array area CAR is formed by conformally stacking a second spacer layer on the front surface of the substrate 100 and anisotropically etching it. The second spacer layer may include, for example, a silicon oxide layer. In addition, an anisotropic etching process may be performed on the lower interlayer insulating pattern 5c to expose the top surface of the substrate 100 while maintaining the lower interlayer insulating pattern 5c under the second spacer 23 and the bit line BL. Here, an upper portion of the boundary buried insulating pattern 141r may be removed from the boundary area INT. In addition, a second residual spacer pattern 23r covering the sidewalls of the boundary buried insulating pattern 141r may be formed. The second spacer 23 and the second residual spacer pattern 23r may be formed as part of the second spacer layer. Here, when the central portion of the boundary buried insulating pattern 141r located between adjacent bit lines BL is etched, a second recessed area R2 may be formed. Figure 8CIn the cross-section of FIG. 5 , the second residual spacer pattern 23 r may cover sidewalls of the boundary etch stop pattern 5 b , the first residual spacer pattern 21 r , the boundary insulating liner 140 r , and the boundary buried insulating pattern 141 r .

[0060] Reference 9A to 9C , a third spacer layer 25a may be conformally formed on the front surface of the substrate 100. The third spacer layer 25a may fill a space between the second recessed region R2 in the boundary region INT and the second residual spacer pattern 23r adjacent thereto. Fig. 9C In the cross-section of FIG. 1 , the third spacer layer 25a may cover the top surface of the boundary buried insulating pattern 141r and the sidewall of the second residual spacer pattern 23r. In addition, the third spacer layer 25a may extend from the boundary region INT to the cell array region CAR. The third spacer layer 25a may include, for example, a silicon nitride layer.

[0061] Reference FIG. 10A to FIG. 10C , a first groove G1 exposing the second doping region 112b of the substrate 100 may be formed in the cell array region CAR by performing an anisotropic etching process on the third spacer layer 25a, and a third spacer 25 covering the sidewall of the second spacer 23 may be formed at the same time. Here, the third residual spacer pattern 25r may be retained between adjacent second residual spacer patterns 23r in the boundary region INT. The third spacer 25 and the third residual spacer pattern 25r may be formed as a part of the third spacer layer 25a. The third spacer 25 may reinforce the upper portion of the first spacer 21 and cover the upper portion of the second spacer 23 to prevent the cleaning solution used in the subsequent cleaning process from penetrating into the bit line BL. Therefore, the bit line BL may be prevented from being damaged. The exposed upper portion of the substrate 100 disposed near the bit line BL in the cell array region CAR may be partially etched by the anisotropic etching process.

[0062] Reference FIG. 11A to FIG. 11C , the first groove G1 is filled by stacking a polysilicon layer doped with impurities on the front surface of the substrate 100. A chemical mechanical polishing (CMP) process may be performed to expose the top surface of the bit line capping pattern 137, and simultaneously form a conductive pattern 50 in the first groove G1. Through the CMP process, the bit line capping pattern 137, the first to third spacers 21, 23, 25, the first to third residual spacer patterns 21r, 23r, 25r, the boundary buried insulating pattern 141r, and the boundary insulating liner 140r may have a flat top surface having the same height by partially removing the upper portions thereof. Therefore, the boundary buried insulating pattern 141r may have a 'U'-shaped cross-section. The conductive pattern 50 is not formed in the boundary region INT.

[0063] Reference FIG. 12A to FIG. 12C, initial storage node contacts 50a spaced apart from each other may be formed by etching the conductive pattern 50. In addition, an insulating fence 40 may be formed between the initial storage node contacts 50a by filling the space between the initial storage node contacts 50a with an insulating material and performing an etch-back process. Here, a boundary insulating fence 40r may be formed in the boundary region INT. The boundary insulating fence 40r may have a bottom surface higher than the bottom surface of the insulating fence 40. For example, the bottom surface of the boundary insulating fence 40r may contact an upper portion of the third residual spacer pattern 25r. Each of the insulating fence 40 and the boundary insulating fence 40r may have at least one single layer or multiple layers of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0064] Reference FIG. 13A to FIG. 13C , the upper portion of the initial storage node contact 50a may be partially removed in the cell array region CAR to expose the upper sidewall of the third spacer 25. The first hole H1 exposing the upper sidewall of the first spacer 21 may be formed by partially removing the upper portions of the second spacer 23 and the third spacer 25. Here, each top surface of the second spacer 23 and the third spacer 25 may have a height equal to or similar to that of the top surface of the initial storage node contact 50a. When the second spacer 23 is partially removed, the second residual spacer pattern 23r and the boundary insulating liner 140r may be partially removed in the boundary region INT to form the second hole H2 and the third hole H3, respectively.

[0065] Reference FIG. 14A to FIG. 14C , the initial storage node contact 50a may be partially removed to expose the upper sidewall of the third spacer 25 and form a storage node contact BC. A fourth spacer layer 27a may be conformally formed on the front surface of the substrate 100. The fourth spacer layer 27a may cover the upper sidewall of the first spacer 21, the upper sidewall of the third spacer 25, and the top surface of the storage node contact BC while filling the second hole H2 and the third hole H3. The fourth spacer layer 27a may be formed of, for example, a silicon nitride layer.

[0066] Reference FIG. 15A to FIG. 15C, a fourth spacer 27b covering the upper sidewall of the first spacer 21 and a fifth spacer 27c covering the upper sidewall of the third spacer 25 may be formed by performing an anisotropic etching process on the fourth spacer layer 27a. The fourth spacer 27b may be disposed above the fifth spacer 27c. Here, a fourth residual spacer pattern 27r1 may be formed in the second hole H2, and a fifth residual spacer pattern 27r2 may be formed in the third hole H3. In addition, the top surface of the storage node contact BC may be exposed. All of the fourth spacer 27b, the fifth spacer 27c, the fourth residual spacer pattern 27r1, and the fifth residual spacer pattern 27r2 may be formed as part of the fourth spacer layer 27a. Through the above process, the space between the bit lines BL in the boundary region INT may be buried by the boundary buried insulating pattern 141r, the boundary insulating liner 140r, and the first to fifth residual spacer patterns 21r, 23r, 25r, 27r1, and 27r2.

[0067] Refer again Figures 1A to 1C , a cleaning process may be performed to remove etching byproducts on the top surface of the storage node contact BC. In addition, an ohmic layer may be formed on the top surface of the storage node contact BC. For example, the ohmic layer may be formed of a metal silicide layer such as cobalt silicide. After the ohmic layer is formed, an anti-diffusion layer may be conformally formed on the front surface of the substrate 100. The anti-diffusion layer may be formed of, for example, a titanium nitride layer, a tantalum nitride layer, or a tungsten nitride layer. A bonding pad LP may be formed by forming a metal-containing layer on the front surface of the substrate 100 to fill the space between the bit line cover patterns 137 and then patterning it. The metal-containing layer may be, for example, tungsten. When the bonding pad LP is formed, a boundary line 150 may be formed in the boundary region INT. In addition, a bonding pad separation pattern 148 may be formed between the bonding pads LP. In addition, an upper interlayer insulating pattern 152 may be formed between the boundary lines 150.

[0068] In an exemplary embodiment of the inventive concept, the space between the bit lines BL can be buried by the boundary buried insulating pattern 141r, the first residual spacer pattern to the fifth residual spacer pattern 21r, 23r, 25r, 27r1 and 27r2, etc. If the space between the bit lines BL in the boundary area INT is not filled, when the conductive layer for forming the bonding pad LP and the boundary line 150 is formed, the conductive layer is inserted and retained between the bit lines BL to generate a bridge in which the boundary line 150 is electrically connected to the storage node contact BC or the bit line contact DC adjacent thereto. However, in an exemplary embodiment of the inventive concept, the space between the bit lines in the boundary area can be filled by forming a portion of a layer of an insulating pattern (e.g., a cell buried insulating pattern, a cell insulating liner, and a bit line spacer) adjacent to the bit line in the cell area to prevent the generation of a bridge between the bit line boundary line and the storage node contact or the bit line contact adjacent thereto. Therefore, it is possible to prevent the failure of the semiconductor memory device and improve reliability.

[0069] Fig.16A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept. Fig. 16B According to an exemplary embodiment of the inventive concept Fig.16A A cross-sectional view taken along line AA' and line BB'. Fig. 16C According to an exemplary embodiment of the inventive concept Fig.16A A cross-sectional view taken along line CC'.

[0070] Reference FIG. 16A to FIG. 16C , a semiconductor memory device according to an exemplary embodiment of the inventive concept does not include Figures 1A to 1C The fourth spacer 27b, the fifth spacer 27c, the fourth residual spacer pattern 27r1 and the fifth residual spacer pattern 27r2. The first to third spacers 21, 23 and 25 may constitute the bit line spacer SP in the cell array region CAR. The first to third spacers 21, 23 and 25 may have top surfaces having the same height as each other. In other words, the top surfaces of the first to third spacers 21, 23 and 25 may be coplanar. The top surfaces of the first to third residual spacer patterns 21r, 23r and 25r, the boundary buried insulating pattern 141r and the boundary insulating liner 140r may be located at the same height as the top surface of the bit line capping pattern 137 in the boundary region INT. The remaining structure may be the same as that of the reference Figures 1A to 1C The structure described is the same.

[0071] Fig.17A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept. Fig. 17B According to an exemplary embodiment of the inventive concept Fig.17AA cross-sectional view taken along the line C-C'. Fig.17A The cross-sections taken by the lines A-A' and B-B' can be compared with Figure 1B The same as those of . Fig.17A and Fig. 17B , a portion of the dummy word line DWL may be set in the boundary region INT adjacent to the cell array region CAR. The dummy word line DWL may not be operated. Fig. 17B In the cross section of FIG. 1 , the third residual spacer pattern 25r may overlap the dummy word line DWL. In addition, a word line capping pattern 110, a first recessed region R1, a first spacer 21, a cell insulating liner 140, and a cell buried insulating pattern 141 may be disposed on the dummy word line DWL. The remaining structure may be the same as that of FIG. Figures 1A to 1C The dummy word line DWL may be formed at the edge of the cell array region CAR in a pattern under the same process conditions in the etching process and the deposition process. Figure 6C The second mask pattern 142 is formed to cover the dummy word line DWL, and then subsequent processes are performed to manufacture Fig.17A and Fig. 17B A semiconductor memory device.

[0072] Fig.18A is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the inventive concept. Fig.18B According to an exemplary embodiment of the inventive concept Fig.18A A cross-sectional view taken along line AA' and line BB'.

[0073] Reference Fig.18A and Fig.18B, first to third bit lines BL1, BL2, and BL3 spaced apart from each other may be disposed on the substrate 100. Each of the first to third bit lines BL1, BL2, and BL3 may include a bit line polysilicon pattern 130, a bit line ohmic pattern 131, and a bit line metal-containing pattern 132 sequentially stacked. The second bit line BL2 may be disposed between the first bit line BL1 and the third bit line BL3. The second bit line BL2 may be spaced apart from the first bit line BL1 by a first distance DS1. The second bit line BL2 may be spaced apart from the bit line BL3 by a second distance DS2. The first distance DS1 may be greater than the second distance DS2. The third residual spacer pattern 25r and the sixth residual spacer pattern 27r3 may be disposed between the first bit line BL1 and the second bit line BL2 and between the fourth residual pattern 27r1. The sixth residual spacer pattern 27r3 may include the same material as that of the fourth residual spacer pattern 27r1. The third residual spacer pattern 25r is not disposed between the second bit line BL2 and the third bit line BL3. This may cause the second distance DS2 to be less than the first distance DS1. The second residual spacer pattern 23r disposed between the first bit line BL1 and the second bit line BL2 may have a width smaller than that of the second residual spacer pattern 23r disposed between the second bit line BL2 and the third bit line BL3. The remaining structure may be the same as that of the reference Figures 1A to 1C The structure described is the same.

[0074] Fig.19 According to an exemplary embodiment of the inventive concept Figure 1A A cross-sectional view taken along line BB'.

[0075] Reference Fig.19 In a semiconductor memory device according to an exemplary embodiment of the inventive concept, the second residual spacer pattern 23r and the boundary insulating liner 140r may not be disposed between the upper portions of the bit lines BL in the boundary region INT and between the bit line capping patterns 137. Only the fourth residual spacer pattern 27rl may be disposed between the third residual spacer pattern 25r and the boundary buried insulating pattern 141r. The boundary insulating liner 140r may remain between the first residual spacer pattern 21r and the boundary buried insulating pattern 141r while being adjacent to the lower end of the bit line BL. In addition, the fifth residual spacer pattern 27r2 may extend to be adjacent to the lower end of the bit line BL. For example, the fifth residual spacer pattern 27r2 may contact the boundary etch stop pattern 5b. The remaining structure may be the same as that of reference 1. Figures 1A to 1C The structure described is the same.

[0076] Can be formed Fig.19 The semiconductor memory device makes FIG. 14A to FIG. 14CThe second residual spacer pattern 23r is completely removed and the upper portion of the boundary insulating liner 140r is removed in the process of . Although the second residual spacer pattern 23r is completely removed and the upper portion of the boundary insulating liner 140r is removed as described above, the fourth residual spacer pattern 27r1 and the fifth fourth residual spacer pattern 27r2 are filled in the position where the second residual spacer pattern 23r and the upper portion of the boundary insulating liner 140r are not shown. Therefore, since the metal-containing layer is not inserted between the bit lines BL in the boundary area INT when the bonding pad LP and the boundary line 150 are formed, bridging between the boundary line 150 and the storage node contact BC or the bit line contact DC adjacent thereto can be prevented.

[0077] The semiconductor memory device according to the above exemplary embodiment of the inventive concept and the method for manufacturing the semiconductor memory device can prevent the bridging between the bit line boundary line and the storage node contact or the bit line contact adjacent thereto by filling a portion of a layer forming an insulating pattern (e.g., a cell buried insulating pattern, a cell insulating liner, and a bit line spacer) adjacent to the bit line in the cell array region in the space between the bit lines in the boundary region. Therefore, a semiconductor memory device with improved reliability can be provided.

[0078] Although the inventive concepts have been described with reference to exemplary embodiments of the inventive concepts, it is to be understood that the inventive concepts are not limited to the exemplary embodiments but various changes and modifications may be made thereto by those having ordinary skill in the art.

Claims

1. A semiconductor memory device, comprising: a substrate, including a cell array region and a boundary region; A first recessed region is disposed at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recessed region; a bit line contact disposed in the first recessed region and contacting the first bit line; a second bit line spaced apart from the first recessed region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a bit line spacer covering a side wall of a first bit line in a cell array region; a cell buried insulating pattern disposed between a side surface of the bit line contact and an inner wall of the first recessed region; a boundary buried insulating pattern covering sidewalls of the first and second bit lines in a boundary region and including the same material as that of the cell buried insulating pattern; a cell insulating liner disposed between the cell buried insulating pattern and an inner wall of the first recessed region and between the cell buried insulating pattern and a side wall of the bit line contact; a boundary insulating liner disposed between the boundary buried insulating pattern and the first bit line; and a first residual spacer pattern located between the first bit line and the second bit line in the boundary region and forming a portion of the bit line spacer, The boundary buried insulating pattern is disposed between the first bit line and the first residual spacer pattern in the boundary region and between the second bit line and the first residual spacer pattern in the boundary region.

2. The semiconductor memory device according to claim 1, further comprising: a bit line cover pattern disposed on each of the first bit line and the second bit line; as well as A storage node contact is located on the substrate in the cell array region, wherein the boundary buried insulating pattern covers the side surface of the bit line covering pattern, The cell buried insulating pattern is lower than a top surface of the first bit line, and The cell buried insulation pattern is lower than a top surface of the storage node contact.

3. The semiconductor memory device according to claim 2, wherein: A top surface of the boundary buried insulating pattern is coplanar with a top surface of the bit line capping pattern, and The cell insulating liner continuously extends from between the cell buried insulating pattern and the inner wall of the first recessed region to between the cell buried insulating pattern and the sidewall of the bit line contact.

4. The semiconductor memory device according to claim 1, wherein: The cell insulating spacer includes the same material as that of the boundary insulating spacer, and The cell insulating liner has an upper end positioned equal to or higher than an upper end of the cell buried insulating pattern.

5. The semiconductor memory device according to claim 4, wherein: The boundary insulation liner has an upper end lower than a top surface of the boundary buried insulation pattern.

6. The semiconductor memory device according to claim 2, wherein: The boundary buried insulating pattern includes a second recessed region, and The first residual spacer pattern is disposed in the second recessed region.

7. The semiconductor memory device according to claim 6, wherein: The boundary insulating liner exposes the upper sidewall of the boundary buried insulating pattern. The semiconductor memory device further includes: a second residual spacer pattern disposed between the bit line capping pattern and an upper sidewall of the boundary buried insulating pattern, The bit line spacer includes: a first spacer contacting a first bit line and a sidewall of the bit line cover pattern in the cell array region; and a second spacer covering an upper sidewall of the first spacer, and The second residual spacer pattern includes the same material as that of the second spacer.

8. The semiconductor memory device according to claim 6, wherein: The bit line spacer includes: a first spacer contacting a sidewall of a first bit line in a cell array region; a second spacer spaced apart from the first bit line and contacting a sidewall of the first spacer; and a third spacer, spaced apart from the first spacer and contacting a sidewall of the second spacer, The third spacer and the first residual spacer are connected to each other, and The first residual spacer pattern includes the same material as that of the third spacer.

9. The semiconductor memory device according to claim 8, further comprising: a second residual spacer pattern disposed between the first residual spacer pattern and the boundary buried insulating pattern, The second residual spacer pattern includes the same material as that of the second spacer.

10. The semiconductor memory device according to claim 9, wherein: The second residual spacer pattern has an upper end lower than a top surface of the boundary buried insulating pattern.

11. The semiconductor memory device according to claim 9, wherein: The first residual spacer pattern has a lower end closer to the substrate than a lower end of the second residual spacer pattern.

12. The semiconductor memory device according to claim 9, wherein: The second spacer and the third spacer expose the upper side wall of the first spacer, The second residual spacer pattern exposes an upper sidewall of the boundary buried insulating pattern, The bit line spacer further includes a fourth spacer covering an upper sidewall of the first spacer in the cell array region, The semiconductor memory device further includes a third residual spacer pattern disposed between an upper sidewall of the boundary buried insulating pattern and the first residual spacer pattern, and The third residual spacer pattern includes the same material as that of the fourth spacer.

13. The semiconductor memory device according to claim 6, further comprising a third bit line, the third bit line being spaced apart from the first bit line and the second bit line being located between the third bit line and the first bit line, in, The third bit line crosses the cell array region and the boundary region, and The second bit line is spaced apart from the first bit line by a first distance and from the third bit line by a second distance, The first distance is greater than the second distance.

14. The semiconductor memory device according to claim 13, wherein: The first residual spacer pattern is disposed between the first bit line and the second bit line and not between the second bit line and the third bit line.

15. The semiconductor memory device according to claim 13, wherein: The bit line spacer includes: a first spacer covering a sidewall of the first bit line in the cell array region and protruding upward from a top surface of the first bit line; and a second spacer covering an upper side wall of the first spacer, wherein the semiconductor memory device further comprises a second residual spacer pattern disposed in the second recessed region to contact the first residual spacer pattern in the boundary region, and The second residual spacer pattern includes the same material as that of the second spacer.

16. The semiconductor memory device according to claim 13, wherein: The bit line spacer includes: a first spacer covering a sidewall of the first bit line in the cell array region and protruding upward from a top surface of the first bit line; and a second spacer covering the sidewall of the first spacer and including a material different from that of the first spacer, The semiconductor memory device further comprises: a second residual spacer pattern disposed between the boundary buried insulating pattern and the first residual spacer pattern and between the first bit line and the second bit line in the boundary region; and a third residual spacer pattern disposed between the second bit line and the third bit line. wherein each of the second residual spacer pattern and the third residual spacer pattern includes a material that is the same as that of the second spacer, and Herein, the third residual spacer pattern has a width greater than that of the second residual spacer pattern.

17. A semiconductor memory device, comprising: a substrate, including a cell array region and a boundary region; A first recessed region is disposed at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recessed region; a bit line contact disposed in the first recessed region and contacting the first bit line; a second bit line spaced apart from the first recessed region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulating pattern disposed between a side surface of the bit line contact and an inner wall of the first recessed region; a bit line spacer covering a sidewall of a first bit line in a cell array region; a boundary buried insulating pattern covering sidewalls of the first bit line and the second bit line in a boundary region, including a second recessed region, and including the same material as that of the cell buried insulating pattern; a cell insulating liner disposed between the cell buried insulating pattern and the inner wall of the first recessed region and between the cell buried insulating pattern and the lower side wall of the first bit line; a boundary insulating liner disposed between the boundary buried insulating pattern and the first bit line; and a first residual spacer pattern filling the second recessed region and forming a portion of a bit line spacer, wherein the boundary buried insulating pattern is disposed between the first bit line and the first residual spacer pattern in the boundary region and between the second bit line and the first residual spacer pattern in the boundary region, and Wherein a top surface of the first residual spacer pattern is coplanar with a top surface of the boundary buried insulation pattern.

18. The semiconductor memory device according to claim 17, wherein: The cell insulating spacer includes the same material as that of the boundary insulating spacer, and The cell insulating liner has an upper end positioned equal to or higher than an upper end of the cell buried insulating pattern.

19. A semiconductor memory device, comprising: a substrate, including a cell array region and a boundary region; A first recessed region is disposed at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recessed region; a second bit line spaced apart from the first recessed region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; A cell buried insulating pattern is disposed between the lower surface of the first bit line and the inner wall of the first recessed region; a first spacer, a second spacer, and a third spacer sequentially covering a sidewall of a first bit line in a cell array region, the third spacer comprising a material different from that of the second spacer; a boundary buried insulating pattern covering sidewalls of the first bit line and the second bit line in a boundary region, including a second recessed region, and including the same material as that of the cell buried insulating pattern; a cell insulating liner disposed between the cell buried insulating pattern and the inner wall of the first recessed region and between the cell buried insulating pattern and the lower side wall of the first bit line; a boundary insulating liner disposed between the boundary buried insulating pattern and the first bit line; as well as a first residual spacer pattern disposed in the second recessed region, including a material identical to that of the third spacer and connected to the third spacer, The boundary buried insulating pattern is disposed between the first bit line and the first residual spacer pattern in the boundary region and between the second bit line and the first residual spacer pattern in the boundary region.

20. A method for manufacturing a semiconductor memory device, the method comprising the steps of: receiving a substrate including a cell array region and a boundary region; forming a first recessed region on the substrate in the cell array region; A bit line contact is formed in the first recessed region, the first bit line contacts the bit line contact, and the second bit line is spaced apart from the first bit line and the first recessed region, wherein Each of the first bit line and the second bit line extends onto the boundary region; filling the first recessed region with a first spacer, a cell insulating liner, and a cell buried insulating pattern, wherein the cell insulating liner is disposed between the cell buried insulating pattern and an inner wall of the first recessed region and between the cell buried insulating pattern and a lower sidewall of the first bit line; forming a boundary buried insulating pattern including a second recessed region, wherein the boundary buried insulating pattern contacts sidewalls of the first bit line and the second bit line in the boundary region, and a boundary insulating liner is disposed between the boundary buried insulating pattern and the first bit line; covering a side wall of a first bit line in a cell array region with a second spacer and a third spacer; and filling the second recessed region with a first residual spacer pattern, wherein the first residual spacer pattern is formed by a portion of the third spacer, and The boundary buried insulating pattern is disposed between the first bit line and the first residual spacer pattern in the boundary region and between the second bit line and the first residual spacer pattern in the boundary region.

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