A stable data transmission method and system based on LVDS

Abstract

The present invention provides a stable data transmission method and system based on LVDS. The method comprises: transmitting serial data to be transmitted in the form of low-voltage differential signal (LVDS) data, and simultaneously providing a corresponding clock for the serial data to synchronize the data; recovering the received corresponding clock and obtaining multiple phase clocks after PLL; sampling the received data using the multiple phase clocks; comparing the sampled values of the multiple phase clocks to obtain a critical point of at least one clock sampling value; using the critical point to find the most stable phase clock; and using the phase clock to synchronize the data and output it. The present invention reduces the design difficulty of PCB routing and chip interfaces, can stably sample data, and effectively improve the data transmission rate of LVDS.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data transmission, and in particular to a method and system for stable data transmission based on LVDS. Background Art

[0002] The existing LVDS (low voltage differential signaling) data transmission solution requires the transmission of a clock at the source end, and the equal length relationship between the data line and the clock line must be strictly controlled during PCB routing to maintain a certain phase relationship between the data and clock at the receiving end. This not only increases the difficulty of routing, but also poses challenges to the chip interface circuit design.

[0003] Existing LVDS (low voltage differential signal) data transmission technology solutions are as follows Figure 1 As shown in the figure, the following steps are involved: 1. The user's parallel data is first converted into serial data via a parallel-to-serial conversion circuit. This data is then transmitted as differential data to improve data transmission stability. 2. To ensure data synchronization, the parallel-to-serial conversion circuit on the transmitter side provides a real-time clock. 3. A clock recovery circuit is provided on the receiver side to recover the clock and convert the serial data into serial-to-parallel data using the recovered clock. This data transmission scheme requires strict control of the delay of the clock during PCB routing to ensure consistency between the delay of the data transmission and the delay of the data transmission.

[0004] The waveform diagram of its data and clock transmission is as follows Figure 2 As shown, we need to implement Figure 2 The phase relationship between data and clock is different. Due to different usage scenarios, it is necessary to analyze the existing environment, adjust the relationship between clock and data, and find a reasonable phase relationship between data and clock. This consumes a lot of time, and in order to ensure the stability of data transmission, the clock performance is greatly reduced. Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure provide a stable data transmission method and system based on LVDS, which can stably sample data while reducing PCB routing, effectively improving the data transmission rate of LVDS without reducing clock performance.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A stable data transmission method based on LVDS, the method comprising:

[0008] Convert the parallel data to be sent into serial data; send the serial data to the data receiving side in the form of low voltage differential signal (LVDS) data, and provide a clock to the serial data to synchronize the data;

[0009] At the data receiving side, the received accompanying clock is recovered and a multi-channel phase clock is obtained through a PLL (phase-locked loop). The received data is sampled using the multi-channel phase clock. The sampling values of the multi-channel phase clock are compared to obtain a critical point of at least one clock sampling value. The most stable phase clock is found using the critical point, and the data is synchronized with the phase clock before output.

[0010] Furthermore, when comparing the sampling values of the multiple phase clocks, if no critical point of the clock sampling value is found, resampling is performed and then comparison is performed to obtain at least one critical point of the clock sampling value.

[0011] Furthermore, after the local clock is recovered, 8 phase clocks are obtained after passing through the PLL phase-locked loop. The 8 phase clocks are used to sample the received data, and the sampling values of the 8 phase clocks are compared to obtain a critical point of at least one clock sampling value. The critical point is used to find the most stable phase clock, and the data is synchronized and output using the phase clock.

[0012] Furthermore, the phase difference between the 8 phase clocks is 45°.

[0013] The present invention also provides a data stable transmission system based on LVDS, comprising: a data transmitter and a data receiver;

[0014] The data transmitter is used to send data to the data receiver in the form of a low voltage differential signal (LVDS), and simultaneously provide a clock to synchronize the data;

[0015] The data receiver includes a clock recovery circuit and a differential data conversion circuit, which are used to recover the received clock signal and convert the received differential signal into serial data;

[0016] The data receiver also includes a synchronization circuit, which is used to obtain a multi-phase clock after the recovered accompanying clock passes through the PLL, and use the multi-phase clock to sample the converted serial data, compare the sampled values of the multi-phase clock to obtain a critical point of at least one clock sampling value, use the critical point to find the most stable phase clock, and use the phase clock to synchronize the data and output it.

[0017] Furthermore, the synchronization circuit includes a PLL phase-locked loop for integrating the recovered accompanying clocks to obtain multi-phase clocks;

[0018] It also includes a phase clock sampling circuit for sampling the converted serial data using the multi-channel phase clock and outputting the sampling result;

[0019] The system further includes a phase selection circuit for receiving the sampling result, comparing the sampling values of the multiple phase clocks using one clock, obtaining a critical point of at least one clock sampling value, finding the most stable phase clock using the critical point, and outputting the phase clock;

[0020] It also includes a unit synchronization circuit for receiving the most stable phase clock of the critical point and performing synchronization processing on data using the most stable phase clock of the critical point.

[0021] Furthermore, the output end of the phase selection circuit is also communicatively connected to the phase clock sampling circuit, for feeding back the selection result of not finding the critical point of the clock sampling value to the phase clock sampling circuit, so that the phase clock sampling circuit resamples.

[0022] Furthermore, the data receiver also includes a serial-to-parallel conversion circuit for receiving the clock and serial data processed by the synchronization circuit, and converting the serial data into parallel data using the clock and then outputting the parallel data.

[0023] Furthermore, the data transmitter includes a parallel-to-serial conversion circuit for converting the parallel data to be sent into serial data; the transmitting end of the parallel-to-serial conversion circuit is connected to a low-voltage differential data conversion circuit and a path clock generation circuit for sending the serial data in the form of a low-voltage differential signal LVDS to the data receiver, and synchronizing the data with the path clock.

[0024] Furthermore, the data transmitter is also used to first send parallel data and initialization characters, determine the phase relationship between the clock and the data, complete data initialization, and then send the data to the parallel-to-serial conversion circuit.

[0025] The present invention provides a stable data transmission method and system based on LVDS, which has the beneficial effect of overcoming the defects of traditional LVDS data transmission schemes that require the transmission of a clock at the transmission source end and the need to maintain a certain phase relationship between the data and the clock at the receiving end. The method and system of the present invention do not require the clock and data to have a phase relationship, only the same source is required, which reduces the design difficulty of PCB routing and chip interfaces. Since the phase correlation between data and clock can be ignored, the data data transmission rate of LVDS (low voltage differential signal) is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 This is a schematic diagram of the existing LVDS data transmission system:

[0028] Figure 2 for Figure 1 Waveform diagram of data and clock transmission in the existing LVDS data transmission system;

[0029] Figure 3 Schematic diagram of a stable data transmission system based on LVDS in an embodiment of the present invention;

[0030] Figure 4 A schematic diagram of the structure of a synchronization circuit in an embodiment of the present invention;

[0031] Figure 5 8-phase clock and data waveform diagram according to an embodiment of the present invention;

[0032] Figure 6 A schematic diagram of state transition of a synchronization circuit according to an embodiment of the present invention;

[0033] Figure 7 Schematic diagram of a stable data transmission system based on LVDS in another embodiment of the present invention;

[0034] Figure 8 2 is a waveform diagram showing the relationship between 8-phase clocks and data in another embodiment of the present invention;

[0035] Figure 9 FIG. 4 is a waveform diagram showing the relationship between 8-phase clocks and data in another embodiment of the present invention. DETAILED DESCRIPTION

[0036] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0037] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0038] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0039] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0040] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0041] refer to Figure 1 , Figure 1 Technical solution for existing LVDS (low voltage differential signal) data transmission:

[0042] 1. The user's parallel data is first converted into serial data through the parallel-to-serial conversion circuit, and then sent out in the form of differential data to improve data transmission stability;

[0043] 2. In order to synchronize the data, a real-time clock will be provided in the parallel-serial conversion circuit at the sending end.

[0044] 3. The receiving end provides a clock recovery circuit to recover the clock

[0045] 4. Use the recovered clock to convert the serial data into serial-to-parallel data.

[0046] The above is an existing LVDS (low voltage differential signal) data transmission solution. No synchronization circuit is provided at the data receiving end. This requires strict control of the delay of the accompanying clock and the delay of data transmission when routing the PCB.

[0047] The waveform diagram of data and clock transmission is as follows Figure 2 As shown. Ultimately, we need to achieve Figure 2The phase relationship between data and clock is different. Due to different usage scenarios, it is necessary to subdivide the existing environment and adjust the relationship between clock and data to find a reasonable phase relationship between data and clock. This is extremely time-consuming and ultimately sacrifices performance in exchange for data transmission stability.

[0048] Next, refer to Figure 3-9 , describing the LVDS-based stable data transmission system and method of the present invention.

[0049] like Figure 3 As shown, the LVDS-based data stable transmission system of the present invention includes: a data transmitter and a data receiver;

[0050] The data transmitter includes a parallel-to-serial conversion circuit for converting parallel data to be transmitted into serial data; a transmitting end of the parallel-to-serial conversion circuit is connected to a low voltage differential data conversion circuit and an accompanying clock generation circuit, for transmitting the serial data to the data receiver in the form of a low voltage differential signal LVDS and simultaneously providing an accompanying clock to synchronize the data;

[0051] The data transmitter is further configured to first send parallel data and initialization characters, determine the phase relationship between the clock and the data, complete data initialization, and then send the data to the parallel-to-serial conversion circuit.

[0052] The data receiver includes a clock recovery circuit and a differential data conversion circuit, which are used to recover the received clock signal and convert the received differential signal into serial data;

[0053] The data receiver also includes a synchronization circuit, which is used to obtain a multi-phase clock after the recovered accompanying clock passes through the PLL, and use the multi-phase clock to sample the converted serial data. The sampling values of the multi-phase clocks are compared to obtain a critical point of at least one clock sampling value. The critical point is used to determine the clock with the best phase relationship between the clock and data, that is, the most stable phase clock. The data is synchronized and output using the phase clock.

[0054] The data receiver also includes a serial-to-parallel conversion circuit for receiving the clock and serial data processed by the synchronization circuit, and converting the serial data into parallel data using the clock and then outputting the parallel data.

[0055] In the above-mentioned embodiment of the present invention, a synchronization circuit is added to the original LVDS transmission solution. The synchronization circuit synchronizes the data and outputs a clock with the best phase with the data.

[0056] In a preferred embodiment, the synchronization circuit includes a PLL phase-locked loop, which is used to integrate the recovered accompanying clocks to obtain multi-phase clocks;

[0057] It also includes a phase clock sampling circuit for sampling the converted serial data using the multi-channel phase clock and outputting the sampling result;

[0058] The system further includes a phase selection circuit for receiving the sampling result, comparing the sampling values of the multiple phase clocks using one clock, obtaining a critical point of at least one clock sampling value, finding the most stable phase clock using the critical point, and outputting the phase clock;

[0059] It also includes a unit synchronization circuit for receiving the most stable phase clock of the critical point and performing synchronization processing on data using the most stable phase clock of the critical point.

[0060] refer to Figure 4 , according to a specific embodiment, Figure 4 This is a block diagram of a synchronization circuit, which consists of a PLL, a phase clock sampling circuit, a phase selection circuit, and a unit synchronization circuit. The working process is as follows:

[0061] 1. The local clock generates eight phase clocks after passing through the PLL. Generally speaking, the more phase clocks there are, the better the phase between the final clock and data. However, increasing the number of phase clocks also increases the difficulty of PLL design. Therefore, as a compromise, eight phase clocks are ultimately selected in this embodiment. The phase difference between these eight phase clocks is 45°.

[0062] 2. The 8-phase clock sampling circuit uses 8-phase clocks to sample the received data and outputs the sampling results to the phase selection circuit.

[0063] 3. The phase selection circuit will use one clock to compare and judge the 8 clock sampling values, and find the zero boundary points of one or two clock samples. In this way, the one with the best clock and data relationship can be found from these 8 phase clocks, and the clock will be output to the next circuit. If this critical point is not found, the sampling result will be fed back to the previous level circuit for re-sampling, and finally an accurate phase clock will be found.

[0064] 4. The unit synchronization circuit will use the found phase clock to synchronize the data.

[0065] Figure 5 FIG. 1 is a waveform diagram showing the relationship between 8 phase clocks and data in this embodiment. As can be seen from the diagram, the clock with a phase of 180° can be selected as the most stable sampling clock by the phase selector circuit.

[0066] In another preferred embodiment, in the synchronization circuit, the output end of the phase selection circuit is also connected to the phase clock sampling circuit for feeding back the selection result of not finding the critical point of the clock sampling value to the phase clock sampling circuit so that the phase clock sampling circuit resamples. Figure 6 shown.

[0067] from Figure 6 It can be seen that during reset, the state machine is in an initial state. After reset, data is sampled using the eight phase clocks, and the state is in phase sampling. After sampling, the state jumps to phase selection. The phase selection state determines whether the sampling results meet the requirements. If they meet the requirements, it jumps to the unit synchronization state. If not, it jumps to phase sampling and re-sampling. The unit synchronization state uses the determined phase clock to synchronize data.

[0068] Figure 7 In another specific embodiment of the present invention, the working process is as follows:

[0069] 1. The data transmitter sends two types of data: an initialization character (a character that transitions between 0 and 1, used by the receiver to determine the phase relationship between the clock and data), and user data.

[0070] 2. The data selector has not been initialized at the receiving end and keeps sending initialization characters (such as 0xC) to determine the relationship between the clock and phase. After initialization is completed, user data is sent.

[0071] 3. The serial-to-parallel conversion circuit converts the user's parallel data into LVDS (low voltage differential signal) or other serial data and sends it out, and provides a clock along the way;

[0072] 4. PLL uses the accompanying clock to generate 8 phase clocks with a phase difference of 45°;

[0073] 5. The 8 phase sampling circuits use 8 phase clocks to sample the data respectively;

[0074] 6. The phase selection circuit will find the critical point of a jump through the initialization characters of 0 and 1, and based on this critical point, it can find the clock with the best data and clock phase;

[0075] 7. The unit synchronization circuit synchronizes the data for subsequent processing;

[0076] 8. The serial-to-parallel conversion circuit converts serial data into parallel data and compares the parallel data with the initialization character. If the character is correct, the sender is notified, the circuit initialization is completed, and user data transmission can be carried out.

[0077] Figure 8 This is a waveform diagram of the relationship between the 8-phase clock and data in this embodiment. This is a phase relationship between the clock and data. Figure 8 As can be seen from the figure, the phase and data of the accompanying clock are very poor, and the data is basically in a state of data jump. The data is prone to sampling errors. In this embodiment, 8 phase clocks are used to sample the data 8 times, and the data jump zero point will be found to be around 45°. In this way, the best phase relationship between the clock 225° and the data can be found.

[0078] Next, refer to Figure 8 , specifically explain the basic principle of using critical points to find the most stable phase clock. Assume that the phase relationship between the 8 phase clocks and data is as follows Figure 8 As shown, the data is sampled by the clock. It can be seen from the figure that the data sampled at 0° and 45° is 0, and the data sampled at 90°, 135°, 180°, 225°, 270°, and 315° is 1. At this time, it can be determined that the sampling clocks of 45° and 90° are the critical points of sampling. Push the 90° clock back by 3 clocks, that is, the 225° clock. It can be seen from the figure that the 225° clock is just in the center of the data and the data is in the most stable state.

[0079] Figure 9 This waveform diagram shows the relationship between eight phase clocks and data in another embodiment of the present invention. This illustrates another clock sampling relationship. At the sampling moment, the data does not transition, and the eight sampled data are identical, making it impossible to find a critical point. In this case, the results must be fed back to the eight-phase clock sampling circuit for resampling until a single phase clock is determined. Therefore, when selecting initialization characters, try to choose characters with frequent 0 and 1 transitions.

[0080] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A stable data transmission method based on LVDS, characterized in that: The method includes: The serial data to be sent is sent to the data receiving side in the form of low voltage differential signal LVDS data, and a clock is provided to the serial data to synchronize the data; The received accompanying clock is recovered and passed through PLL to obtain a multi-phase clock. The multi-phase clock is used to sample the received data. The sampling values of the multi-phase clocks are compared to obtain a critical point of at least one clock sampling value. The most stable phase clock is found using the critical point. The data is synchronized with the phase clock and then output.

2. The LVDS-based stable data transmission method according to claim 1, wherein: When comparing the sampling values of the multiple phase clocks, if no critical point of the clock sampling values is found, resampling is performed and then comparison is performed to obtain at least one critical point of the clock sampling value.

3. The stable data transmission method based on LVDS according to claim 1 or 2, characterized in that: After the local clock is recovered, 8 phase clocks are obtained after passing through the PLL. The 8 phase clocks are used to sample the received data, and the sampling values of the 8 phase clocks are compared to obtain the critical point of at least one clock sampling value. The critical point is used to find the most stable phase clock, and the data is synchronized with the phase clock before output.

4. The stable data transmission method based on LVDS according to claim 3, characterized in that: The phase difference between the 8 phase clocks is 45°.

5. A data stable transmission system based on LVDS, characterized in that: include: a data transmitter and a data receiver; The data transmitter is used to send data to the data receiver in the form of a low voltage differential signal (LVDS), and simultaneously provide a clock to synchronize the data; The data receiver includes a clock recovery circuit and a differential data conversion circuit, which are used to recover the received clock signal and convert the received differential signal into serial data; The data receiver also includes a synchronization circuit, which is used to obtain a multi-phase clock after the recovered accompanying clock passes through the PLL, and use the multi-phase clock to sample the converted serial data, compare the sampled values of the multi-phase clock to obtain a critical point of at least one clock sampling value, use the critical point to find the most stable phase clock, and use the phase clock to synchronize the data and output it.

6. The LVDS-based stable data transmission system according to claim 5, characterized in that: The synchronization circuit includes a PLL for integrating the recovered accompanying clocks to obtain multi-phase clocks; It also includes a phase clock sampling circuit for sampling the converted serial data using the multi-channel phase clock and outputting the sampling result; The system further includes a phase selection circuit for receiving the sampling result, comparing the sampling values of the multiple phase clocks using one clock, obtaining a critical point of at least one clock sampling value, finding the most stable phase clock using the critical point, and outputting the phase clock; It also includes a unit synchronization circuit for receiving the most stable phase clock of the critical point and performing synchronization processing on data using the most stable phase clock of the critical point.

7. The LVDS-based stable data transmission system according to claim 6, characterized in that: The output end of the phase selection circuit is also in communication connection with the phase clock sampling circuit, and is used to feed back the selection result of not finding the critical point of the clock sampling value to the phase clock sampling circuit, so that the phase clock sampling circuit resamples.

8. The LVDS-based stable data transmission system according to claim 6 or 7, characterized in that: The data receiver also includes a serial-to-parallel conversion circuit for receiving the clock and serial data processed by the synchronization circuit, and converting the serial data into parallel data using the clock and then outputting the parallel data.

9. The LVDS-based stable data transmission system according to claim 5, characterized in that: The data transmitter includes a parallel-to-serial conversion circuit for converting the parallel data to be sent into serial data; the transmitting end of the parallel-to-serial conversion circuit is connected to a low-voltage differential data conversion circuit and a clock generation circuit, for sending the serial data in the form of a low-voltage differential signal LVDS to the data receiver, and synchronizing the data with the clock.

10. The LVDS-based stable data transmission system according to claim 9, characterized in that: The data transmitter is further configured to first send parallel data and initialization characters, determine the phase relationship between the clock and the data, complete data initialization, and then send the data to the parallel-to-serial conversion circuit.

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