Solid-state imaging device and electronic apparatus

Abstract

A solid-state imaging device according to an embodiment of the present invention includes: a light-receiving surface; and a plurality of pixels arranged to face the light-receiving surface. Each pixel has: a photoelectric conversion unit that performs photoelectric conversion on light incident through the light-receiving surface; a first charge holding unit that holds the charge transferred from the photoelectric conversion unit; and a second charge holding unit that is arranged at a position where all or a part of the second charge holding unit overlaps with the first charge holding unit in a planar layout and is formed to be non-conductive with the first charge holding unit. Each pixel further has: a first transfer transistor that transfers the charge held by the first charge holding unit to a floating diffusion section; and a second transfer transistor that transfers the charge held by the second charge holding unit to the floating diffusion section.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device and an electronic device. Background Art

[0002] In electronic devices including imaging units such as digital cameras and digital video cameras, and mobile terminal units having an imaging function, solid-state imaging devices are applied. Examples of solid-state imaging devices include CMOS (Complementary MOS) image sensors, which read charges accumulated in photodiodes serving as photoelectric conversion elements via MOS (Metal Oxide Semiconductor) transistors (for example, refer to Patent Document 1).

[0003] In a CMOS image sensor having a global shutter function, a charge accumulation section is provided in each pixel. Since the signal of the previous frame is held in the charge accumulation section, it is necessary to provide a structure that shields the charge accumulation section from light in order to prevent the signal of the next frame from entering the charge accumulation section. However, it is difficult to sufficiently prevent light leakage into the charge accumulation section by simply providing such a structure. In view of this situation, for example, the methods described in Patent Documents 1 and 2 can be considered as countermeasures for this problem.

[0004] Citation List

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2013-150232

[0007] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2012-175259 Summary of the Invention

[0008] However, the method described in Patent Document 1 has a disadvantage that the resolution is significantly reduced. In addition, the method described in Patent Document 2 has a disadvantage that it is difficult to accurately eliminate the influence of obliquely incident light leaking into the charge accumulation section, and also has a disadvantage of low conversion efficiency. Therefore, there is a need to provide a solid-state imaging device that can accurately eliminate the influence of obliquely incident light leaking into the charge accumulation section while suppressing a decrease in resolution and a decrease in conversion efficiency, and an electronic device including the solid-state imaging device.

[0009] A solid-state imaging device according to an embodiment of the present invention includes: a light-receiving surface; and two or more pixels opposed to the light-receiving surface. Each pixel includes: a photoelectric conversion section that performs photoelectric conversion on light incident via the light-receiving surface, a first charge holding section that holds the charge transferred from the photoelectric conversion section, a second charge holding section, all or a part of the second charge holding section being arranged at a position overlapping with the first charge holding section in a planar layout and formed to be non-conductive with the first charge holding section. Each pixel further includes a first transfer transistor that transfers the charge held by the first charge holding section to a floating diffusion section; and a second transfer transistor that transfers the charge held by the second charge holding section to the floating diffusion section.

[0010] An electronic device according to an embodiment of the present invention includes: a solid-state imaging device that outputs image data corresponding to incident light; and a signal processing circuit that processes the image data. The solid-state imaging device provided in the electronic device has the same configuration as the aforementioned solid-state imaging device.

[0011] In the solid-state imaging device and the electronic device according to various embodiments of the present invention, there are provided: a first charge holding section that holds the charge transferred from the photoelectric conversion section, and a second charge holding section that is formed to be non-conductive with the first charge holding section. This makes it possible to reduce the PLS (Parastic Light Sensitibity) component included in the signal charge based on the signal charge read from the first charge holding section and the noise charge read from the second charge holding section. Further, in the solid-state imaging device and the electronic device according to various embodiments of the present invention, all or a part of the second charge holding section is arranged at a position overlapping with the first charge holding section in a planar layout. Compared with the case where the first charge holding section and the second charge holding section are arranged in parallel with each other in a planar layout, this can more accurately estimate the PLS component caused by oblique incidence. Further, in the solid-state imaging device and the electronic device according to various embodiments of the present invention, the first transfer transistor is used to read the charge from the first charge holding section, and the second transfer transistor is used to read the charge from the second charge holding section. As a result, a higher conversion efficiency is achieved compared with the case where the switching element is kept conductive during the charge reading from the first charge holding section. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing an example of a schematic configuration of a solid-state imaging device according to an embodiment of the present invention.

[0013] Figure 2 is a diagram showing Figure 1 an example of a circuit configuration of a sensor pixel and a read circuit of

[0014] Figure 3 is a diagram showing Figure 1A diagram of an example of the planar structure of a sensor pixel.

[0015] Figure 4 It is a diagram showing an example of a cross-sectional structure along line A-A of Figure 3

[0016] Figure 5 It is a diagram showing an example of a timing chart during imaging of a solid-state imaging device including a sensor pixel of Figure 4

[0017] Figure 6 It is a diagram showing an example of a modified timing chart during imaging of a solid-state imaging device including a sensor pixel of Figure 4

[0018] Figure 7 It is a diagram showing Figure 1 an example of a modified planar structure of a sensor pixel of

[0019] Figure 8 It is a diagram showing an example of a cross-sectional structure along line A-A of Figure 7

[0020] Figure 9 It is a diagram showing an example of a modified cross-sectional structure along line A-A of Figure 7

[0021] Figure 10 It is a diagram showing an example of a modified cross-sectional structure along line A-A of Figure 3

[0022] Figure 11 It is a diagram showing an example of a schematic structure of an electronic device including a solid-state imaging device according to any one of the foregoing embodiments and their modifications.

[0023] Figure 12 It is a diagram showing Figure 11 an example of an imaging step of the electronic device of

[0024] Figure 13 It is a diagram showing an example of correction coefficients for each pixel.

[0025] Figure 14 It is a diagram showing an example of correction coefficients for each pixel.

[0026] Figure 15 It is a block diagram showing an example of a schematic structure of a vehicle control system.

[0027] Figure 16 It is a diagram for assisting in explaining an example of the installation positions of an external information detection unit and an imaging unit. Detailed Description of the Invention

[0028] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the description will be made in the following order.

[0029] 1. Embodiment (Solid-state imaging device) Figures 1 to 6

[0030] 2. Modification example (Solid-state imaging device) Figures 7 to 10

[0031] 3. Application example (Electronic device) Figures 11 to 14

[0032] 4. Application example Figures 15 to 16

[0033] <1. Embodiment>

[0034] [Structure]

[0035] The solid-state imaging device 1 according to an embodiment of the present invention will be described. The solid-state imaging device 1 is, for example, a front-illuminated image sensor including a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like. The solid-state imaging device 1 receives light from a subject and performs photoelectric conversion on the light to generate an image signal, thereby capturing an image. The solid-state imaging device 1 outputs a pixel signal corresponding to the incident light.

[0036] The front-illuminated image sensor is an image sensor having a structure in which a photoelectric conversion unit such as a photodiode is provided between a light-receiving surface on which light from a subject is incident and the back surface of a semiconductor substrate. The photoelectric conversion unit receives light from a subject and converts the light into an electrical signal. It should be noted that the present invention is not limited to application to a CMOS image sensor.

[0037] Figure 1Shows an example of the schematic configuration of a solid-state imaging device 1 according to an embodiment of the present invention. The solid-state imaging device 1 includes a pixel array unit 10 and a logic circuit 20. The pixel array unit 10 includes two or more sensor pixels 11 and two or more read circuits 12 (described later). The sensor pixel 11 corresponds to a specific example of the "pixel" of the present invention. Each sensor pixel 11 performs photoelectric conversion and outputs a charge corresponding to the received light amount. The two or more sensor pixels 11 face the light-receiving surface 10A (described later) and are arranged in a rectangle in the pixel matrix unit 10. Each read circuit 12 outputs a pixel signal or a noise signal (described later) based on the charge output from the sensor pixel 11. For example, in the pixel array unit 10, one of the two or more read circuits 12 is provided for each sensor pixel 11. It should be noted that in the pixel array unit 10, one of the two or more read circuits 12 may also be provided for the two or more sensor pixels 11.

[0038] The pixel array unit 10 includes two or more pixel drive lines HSL and two or more data output lines VSL. The pixel drive line HSL is a wiring that receives a control signal for controlling the output of the charge accumulated in the sensor pixel 11. The pixel drive line HSL extends, for example, in the row direction. The data output line VSL is a wiring for outputting the pixel signal or the noise signal output from each read circuit 12 to the logic circuit 20. The data output line VSL extends, for example, in the column direction.

[0039] The logic circuit 20 includes, for example, a vertical drive circuit 21, a column signal processing circuit 22, a horizontal drive circuit 23, and a system control circuit 24. The logic circuit 20 (specifically, the horizontal drive circuit 23) outputs the output voltage of each sensor pixel 11 to an external device, thereby providing image data to the external device.

[0040] For example, the vertical drive circuit 21 sequentially selects two or more sensor pixels 11 based on a predetermined pixel row unit. The "predetermined pixel row unit" refers to a pixel row in which pixel selection is enabled by the same address. For example, in the case where a single sensor pixel 11 is assigned to a single read circuit 12, the "predetermined pixel row unit" refers to a single pixel row. Further, for example, in the case where two or more sensor pixels 11 share a single read circuit 12, if the layout of two or more sensor pixels 11 sharing the read circuit 12 is 2 pixel rows × n pixel columns (n is an integer of 1 or more), the "predetermined pixel row unit" refers to two pixel rows. Similarly, if the layout of two or more sensor pixels 11 sharing the read circuit 12 is 4 pixel rows × n pixel columns (n is an integer of 1 or more), the "predetermined pixel row unit" refers to four pixel rows. The vertical drive circuit 21 controls transistors (e.g., transfer transistors TRX, TRG, and DMG, and discharge transistor OFG) in each sensor pixel 11 via pixel drive lines HSL, and also controls transistors (e.g., reset transistor RST and selection transistor SEL) in each read circuit 12.

[0041] The column signal processing circuit 22 performs, for example, correlated double sampling (CDS) processing on pixel signals or noise signals output from each sensor pixel 11 in the row selected by the vertical drive circuit 21. For example, by performing CDS processing, the column signal processing circuit 22 extracts the signal level of the pixel signal or noise signal, and holds pixel data corresponding to the amount of light received by each pixel 11 or noise pixel data corresponding to the PLS. The column signal processing circuit 22 includes, for example, a column signal processing unit for each data output line VSL. The column signal processing unit includes, for example, a single slope A / D converter. The single slope A / D converter includes, for example, a comparator and a counter circuit. The horizontal drive circuit 23 outputs, for example, pixel data or noise pixel data held in the column signal processing circuit 22 to the outside sequentially. The system control circuit 24 controls the driving of each block (vertical drive circuit 21, column signal processing circuit 22, and horizontal drive circuit 23) in the logic circuit 20, for example.

[0042] Figure 2 An example of the circuit configuration of the sensor pixel 11 and the read circuit 12 is shown. In Figure 2Among them, the case where a single sensor pixel 11 is assigned to a single read circuit 12 is shown as an example. Each sensor pixel 11 includes components common to each other. Each sensor pixel 11 includes, for example, a photodiode PD, transfer transistors TRX, TRG, and DMG, a charge holding section MEM and DM, a floating diffusion section FD, a discharge transistor OFG, and a discharge floating diffusion section OFD. The transfer transistors TRX, TRG, and DMG and the discharge transistor OFG are, for example, NMOS (Metal Oxide Semiconductor) transistors.

[0043] The photodiode PD corresponds to a specific example of the "photoelectric conversion section" of the present invention. The charge holding section MEM corresponds to a specific example of the "first charge holding section" of the present invention. The charge holding section DM corresponds to a specific example of the "second charge holding section" of the present invention. The transfer transistor TRG corresponds to a specific example of the "first transistor" of the present invention. The transfer transistor DMG corresponds to a specific example of the "second transistor" of the present invention. The transfer transistor TRX corresponds to a specific example of the "third transistor" of the present invention.

[0044] The photodiode PD performs photoelectric conversion on light incident via the light receiving surface 10A (described later). The photodiode PD performs photoelectric conversion to generate charges corresponding to the amount of received light. The photodiode PD is, for example, a PN junction photoelectric conversion element. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TRX. The anode of the photodiode PD is electrically connected to a reference potential line (for example, ground GND).

[0045] The transfer transistor TRX is connected between the photodiode PD and the transfer transistor TRG. The transfer transistor TRX controls the potential of the charge holding section MEM in response to a control signal applied to the gate of the transfer transistor TRX. For example, when the transfer transistor TRX is turned on, the potential of the charge holding section MEM becomes deeper. In addition, for example, when the transfer transistor TRX is turned off, the potential of the charge holding section MEM becomes shallower. Once the transfer transistor TRX is turned on, the charges accumulated in the photodiode PD are transferred to the charge holding section MEM through the transfer transistor TRX. The drain of the transfer transistor TRX is electrically connected to the source of the transfer transistor TRG. The gate of the transfer transistor TRX is connected to the pixel drive line HSL.

[0046] The charge holding section MEM is an impurity semiconductor region that temporarily holds the charge accumulated in the photodiode PD. The charge holding section MEM holds the charge transferred from the photodiode PD. The charge holding section DM is an impurity semiconductor region that temporarily holds the charge for PLS (Parastic Light Sensitibity) correction. The charge holding section DM temporarily holds the charge generated by PLS. The charge holding section DM is formed as an impurity semiconductor region that is non-conductive with the charge holding section MEM. The charge holding section MEM, the charge holding section DM, and the floating diffusion section FD described later all include impurity semiconductor regions having a common conductivity type. In addition, the impurity concentration of each of the charge holding section MEM and the charge holding section DM is lower than the impurity concentration of the floating diffusion section FD described later.

[0047] PLS refers to stray light that appears according to the incident light amount when strong light is incident on the photodiode PD. If the charge generated by the stray light (hereinafter referred to as "noise charge") mixes into the charge holding section MEM, this noise charge will be superimposed as a noise component on the charge held in the charge holding section MEM (hereinafter referred to as "signal charge"). This causes noise to be included in the pixel signal, thus degrading the image quality of the obtained image. In order to remove the noise component from the pixel signal, the charge holding section DM holds the noise charge that has a correlation with the noise charge to be superimposed on the signal charge.

[0048] The transfer transistor TRG is connected between the transfer transistor TRX and the floating diffusion section FD. The transfer transistor TRG transfers the charge held in the charge holding section MEM to the floating diffusion section FD in response to a control signal applied to the gate of the transfer transistor TRG. For example, when the transfer transistor TRX is cut off and the transfer transistor TRG is turned on, the charge held in the charge holding section MEM is transferred to the floating diffusion section FD via the transfer transistor TRG. The drain of the transfer transistor TRG is electrically connected to the floating diffusion section FD. The gate of the transfer transistor TRG is connected to the pixel drive line HSL.

[0049] The transfer transistor DMG is connected between the charge holding section DM and the floating diffusion section FD. The transfer transistor DMG transfers the charge held in the charge holding section DM to the floating diffusion section FD in response to a control signal applied to the gate of the transfer transistor DMG. For example, when the transfer transistor DMG is turned on, the charge held in the charge holding section DM is transferred to the floating diffusion section FD via the transfer transistor DMG. The drain of the transfer transistor DMG is electrically connected to the floating diffusion section FD. The gate of the transfer transistor DGM is connected to the pixel drive line HSL.

[0050] The floating diffusion section FD is a floating diffusion region (impurity semiconductor region) that temporarily holds the charge output from the photodiode PD via the transfer transistor TRX and the transfer transistor TRG. For example, the reset transistor RST is connected to the floating diffusion section FD. The vertical signal line VSL is also connected to the floating diffusion section FD via the amplification transistor AMP and the selection transistor SEL. In addition, the floating diffusion section FD is a floating diffusion region that temporarily holds the charge output from the charge holding section DM via the transfer transistor DMG.

[0051] The discharge transistor OFG is connected between the photodiode PD and the power supply line VDD. The discharge transistor OFG initializes (resets) the photodiode PD in response to a control signal applied to the gate of the discharge transistor OFG. For example, when the discharge transistor OFG is turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. In other words, the photodiode PD is initialized. In addition, the discharge transistor OFG forms, for example, an overflow path between the transfer transistor TRX and the power supply line VDD, and discharges the charge overflowing from the photodiode PD to the power supply line VDD. The drain of the discharge transistor OFG is connected to the power supply line VDD, and the source of the discharge transistor OFG is connected between the photodiode PD and the transfer transistor TRX. The gate of the discharge transistor OFG is connected to the pixel drive line HSL.

[0052] The reset transistor RST is connected between the floating diffusion section FD and the power supply line VDD. The reset transistor RST initializes (resets) each region from the charge holding section MEM to the floating diffusion section FD in response to a control signal applied to the gate of the reset transistor RST. For example, when the transfer transistors TRG and DMG and the reset transistor RST are turned on, the potentials of the charge holding sections MEM and DM and the floating diffusion section FD are reset to the potential level of the power supply line VDD. In other words, the charge holding sections MEM and DM and the floating diffusion section FD are initialized. The drain of the reset transistor RST is connected to the power supply line VDD, and the source of the reset transistor RST is connected to the floating diffusion section FD. The gate of the reset transistor RST is connected to the pixel drive line HSL.

[0053] The amplifying transistor AMP has a gate connected to the floating diffusion FD, a drain connected to the power supply line VDD, and a source connected to the drain of the selection transistor SEL. The amplifying transistor AMP serves as an input section of a source follower circuit that reads the charge obtained by photoelectric conversion at the photodiode PD or the charge accumulated in the charge holding section DM. Since the source of the amplifying transistor AMP is connected to the vertical signal line VSL via the selection transistor SEL, the amplifying transistor AMP and a constant current source connected to one end of the vertical signal line VSL constitute a source follower circuit. The amplifying transistor AMP converts the charge obtained by photoelectric conversion at the photodiode PD into a pixel signal and outputs the pixel signal to the vertical signal line VSL via the selection transistor SEL. In addition, the amplifying transistor AMP converts the charge accumulated in the charge holding section DM into a noise signal and outputs the noise signal to the vertical signal line VSL via the selection transistor SEL.

[0054] The selection transistor SEL has a drain connected to the source of the amplifying transistor AMP, a source connected to the vertical signal line VSL, and a gate connected to the pixel drive line HSL. The selection transistor SEL controls the output of the pixel signal or the noise signal output from the amplifying transistor AMP to the vertical signal line VSL in response to a control signal applied to the gate of the selection transistor SEL. When the control signal is turned on, the selection transistor SEL enters the on state, and the sensor pixel 11 connected to the selection transistor SEL enters the selection state. When the sensor pixel 11 enters the selection state, the pixel signal or the noise signal output from the amplifying transistor AMP is read out to the column signal processing circuit 22 via the vertical signal line VSL.

[0055] Next, the structure of the sensor pixel 11 will be described in detail. Figure 3 An example of the planar structure of the sensor pixel 11 is shown. Figure 4 Shows along Figure 3 An example of the cross-sectional structure of the line A-A. Figure 3 And Figure 4 Are schematic diagrams and are not necessarily drawn to scale. In Figure 4 The density of the impurity concentration is represented by symbols including "P+", "N-", "N+", and "N++". In this article, for example, in the position represented as "P+", the value of the concentration of p-type impurities (acceptors) is higher than 1×10 16 cm －3 To 5×10 18 cm －3 The value within the range. "N+" indicates that the concentration of n-type impurities (donors) is higher than "N-". "N++" indicates that the concentration of n-type impurities (donors) is higher than "N+". In the position represented as "N-", for example, the concentration of n-type impurities (donors) has 1×1016 cm -3 to 5×10 18 cm -3 Values within the range.

[0056] The sensor pixel 11 is formed on the semiconductor substrate 30. For example, the semiconductor substrate 30 is a silicon substrate. The semiconductor substrate 30 includes a p-well layer 32 located on and near the upper surface of the semiconductor substrate 30, and includes an n-type semiconductor layer 31 located at a deeper position than the p-well layer 32. The p-well layer 32 is a p-type semiconductor region formed at and around the upper surface of the semiconductor substrate 30. In the p-well layer 32, an n-type semiconductor region 33 and a p-type semiconductor region 34 are formed. The p-type semiconductor region 34 is formed at the upper surface of the semiconductor substrate 30 and is in contact with the n-type semiconductor region 33. The n-type semiconductor region 33 and the p-type semiconductor region 34 are stacked in the thickness direction (normal direction) of the semiconductor substrate 30 and constitute the photodiode PD. The photodiode PD is arranged in a planar layout at a position adjacent to the charge holding section MEM and the charge holding section DM. The region of the upper surface of the semiconductor substrate 30 where the p-type semiconductor region 34 is formed is the light receiving surface 10A. In terms of the positional relationship with the photodiode PD, the light receiving surface 10A is formed at a position on the transfer transistor TRX side.

[0057] The charge holding section MEM is formed at a position in the p-well layer 32 opposite to the gate of the transfer transistor TRX. The charge holding section MEM is formed at a predetermined depth from the upper surface of the semiconductor substrate 30. The charge holding section MEM includes a semiconductor region of n-type impurities formed in the p-well layer 32. A p-type semiconductor region 35 is formed between the upper surface of the semiconductor substrate 30 and the charge holding section MEM.

[0058] The charge holding section DM is formed in a planar layout at a position where all or a part of the charge holding section DM in the p-well layer 32 overlaps with the charge holding section MEM. In other words, the sensor pixel 11 includes the charge holding section DM, which is located at a position in the p-well layer 32 where all or a part of the charge holding section DM overlaps with the charge holding section MEM. Starting from the upper surface (or the light receiving surface 10A) side of the semiconductor substrate 30, the p-type semiconductor region 35, the charge holding section MEM, and the charge holding section DM are arranged in sequence in the p-well layer 32. The charge holding section DM includes a semiconductor region of n-type impurities formed in the p-well layer 32. The charge holding section DM is formed to be non-conductive with the charge holding section MEM. The n-type impurity (donor) concentration of each of the charge holding section MEM and the charge holding section DM is lower than the n-type impurity (donor) concentration of the floating diffusion section FD.

[0059] The floating diffusion section FD and the discharge floating diffusion section OFD are formed to surround the region including the photodiode PD, the p-type semiconductor region 35, and the charge holding section DM. In other words, the sensor pixel 11 has the floating diffusion section FD and the discharge floating diffusion section OFD that surround the region including the photodiode PD, the p-type semiconductor region 35, and the charge holding section DM. Both the floating diffusion section FD and the discharge floating diffusion section OFD include semiconductor regions formed in the p-well layer 32 and having a high n-type impurity concentration.

[0060] The transfer transistor DMG is formed near the floating diffusion section FD. In other words, the sensor pixel 11 includes the transfer transistor DMG located near the floating diffusion section FD. The transfer transistor DMG includes the vertical gate VG that reaches the charge holding section DM. For example, the vertical gate VG contains a metal material. The discharge transistor OFG is formed near the discharge floating diffusion section OFD. In other words, the sensor pixel 11 includes the discharge transistor OFG located near the discharge floating diffusion section OFD.

[0061] The sensor pixel 11 includes the light shielding layer 36 located on the semiconductor substrate 30. The light shielding layer 36 has an opening 36A at a position facing the photodiode PD. The light receiving surface 10A is exposed within the opening 36A. The light shielding layer 36 is disposed around the light receiving surface 10A and at least at a position opposite to the charge holding section MEM. For example, the light shielding layer 36 contains a metal material.

[0062] [Operation]

[0063] Next, the imaging operation of the solid-state imaging device 1 according to the present embodiment will be described.

[0064] The solid-state imaging device 1 (specifically, the system control circuit 24) performs an imaging operation in a global shutter scheme according to an imaging instruction from the operation unit 250 described later. According to the global shutter scheme, the charge of the current frame is accumulated in the charge holding section MEM of each sensor pixel 11, and then the charge accumulated in the charge holding section MEM of each sensor pixel 11 is sequentially read. Figure 5 An example of a timing chart during the imaging operation of the solid-state imaging device 1 is shown.

[0065] First, before starting imaging, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the discharge transistor OFG and discharges the excess charge remaining in the photodiode PD to the outside. Then, the solid-state imaging device 1 (specifically, the system control circuit 24) starts imaging. Specifically, the solid-state imaging device 1 (specifically, the system control circuit 24) starts accumulating charge when the transfer transistors TRX, TRG, and DMG and the discharge transistor OFG are in the cut-off state. When light enters the photodiode PD through the light-receiving surface 10A, charge is generated by photoelectric conversion at the photodiode PD. The charge generated at the photodiode PD starts to accumulate in the photodiode PD.

[0066] Then, before transferring the charge accumulated in the photodiode PD to the charge holding section MEM, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistors TRG and DMG and the reset transistor RST to discharge the excess charge remaining in each of the charge holding section MEM and the floating diffusion section FD to the outside. Next, before the photoelectric conversion at the photodiode PD is completed, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistor TRX and deepens the potential of the charge holding section MEM, thereby transferring the charge accumulated in the photodiode PD to the charge holding section MEM. At this time, the solid-state imaging device 1 (specifically, the system control circuit 24) performs this transfer operation on all the sensor pixels 11 simultaneously.

[0067] After the photoelectric conversion at the photodiode PD is completed, the solid-state imaging device 1 (specifically, the system control circuit 24) turns off the transfer transistor TRX and confines the charge generated by the current frame imaging in the charge holding section MEM. Then, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the reset transistor RST and discharges the excess charge remaining in the floating diffusion section FD to the outside again.

[0068] Next, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistor DMG and discharges (transfers) the charge accumulated in the charge holding section DM to the floating diffusion section FD. At this time, the solid-state imaging device 1 (specifically, the system control circuit 24) keeps the selection transistor SEL turned on. By this step, a noise signal having a signal level corresponding to the potential of the floating diffusion section FD is generated at the amplification transistor AMP, and the generated noise signal is output to the vertical signal line VSL via the selection transistor SEL. The noise signal is generated based on the noise charge that is correlated with the noise charge to be superimposed on the signal charge accumulated in the charge holding section MEM. The solid-state imaging device 1 (specifically, the system control circuit 24) performs this reading operation for each predetermined pixel row unit.

[0069] Next, the solid-state imaging device 1 (specifically, the system control circuit 24) turns on the transfer transistor TRG and discharges (transfers) the charge accumulated in the charge holding unit MEM to the floating diffusion unit FD. At this time, the solid-state imaging device 1 (specifically, the system control circuit 24) keeps the selection transistor SEL turned on. Through this step, a pixel signal having a signal level corresponding to the potential of the floating diffusion unit FD is generated at the amplification transistor AMP, and the generated pixel signal is output to the vertical signal line VSL via the selection transistor SEL. The solid-state imaging device 1 (specifically, the system control circuit 24) performs this reading operation for each predetermined pixel row unit. In this way, the imaging operation of the solid-state imaging device 1 according to the present embodiment is performed.

[0070] Note that, for example, as Figure 6 shown, the solid-state imaging device 1 (specifically, the system control circuit 24) may perform an operation of reading charge from the charge holding unit MEM before an operation of reading charge from the charge holding unit DM.

[0071] [Effect]

[0072] Next, the effect of the solid-state imaging device 1 according to the present embodiment will be described.

[0073] In a CMOS image sensor having a global shutter function, a charge accumulation unit is provided in each pixel. Since the signal of the previous frame is held in the charge accumulation unit, it is necessary to provide a structure for shielding the charge accumulation unit to prevent the signal of the next frame from entering the charge accumulation unit. However, it is difficult to sufficiently prevent light leakage into the charge accumulation unit by simply providing such a structure. In view of this situation, for example, the methods described in the foregoing Patent Documents 1 and 2 can be considered as countermeasures for this problem.

[0074] In Patent Document 1, one of the pixels shared by two or more pixels is used as a PLS correction pixel. However, in this case, since the PLS correction pixel is buried in the pixel array, the resolution is greatly reduced.

[0075] In Patent Document 2, similar to this embodiment, a charge accumulation section for PLS correction is provided. However, in Patent Document 2, the charge accumulation section for PLS correction is arranged close to the floating diffusion section. This makes it difficult to accurately eliminate the PLS component caused by oblique incidence. For example, when the photodiode is formed adjacent to the charge accumulation section for PLS correction and the floating diffusion section, if light obliquely enters the photodiode from the side of the charge accumulation section for PLS correction, more noise charges will accumulate in the floating diffusion section than in the charge accumulation section for PLS correction. Conversely, when light obliquely enters the photodiode from the side of the floating diffusion section, more noise charges will accumulate in the charge accumulation section for PLS correction than in the floating diffusion section. Therefore, the ratio between the noise charges accumulated in the floating diffusion section and the noise charges accumulated in the charge accumulation section for PLS correction will vary according to the light incidence direction. Therefore, it is difficult to accurately remove the noise component from the pixel signal using the method described in Patent Document 2. Additionally, in Patent Document 2, a switching element is provided between the floating diffusion section and the amplification transistor, and furthermore, a switching element is also provided between the charge accumulation section for PLS correction and the amplification transistor. Therefore, when reading charges from the floating diffusion section, it is necessary to keep the switch between the floating diffusion section and the amplification transistor conducting. As a result, the reading operation is performed in a state of low conversion efficiency.

[0076] In contrast, in this embodiment, a charge holding section MEM for holding the charges transferred from the photodiode PD is provided, and a charge holding section DM formed to be non-conductive with the charge holding section MEM. This enables reduction of the PLS component included in the signal charges based on the signal charges read from the charge holding section MEM and the noise charges read from the charge holding section DM. Additionally, in this embodiment, all or a part of the charge holding section DM is arranged at a position overlapping with the charge holding section MEM in the planar layout. Compared with the case where the charge holding section MEM and the charge holding section DM are arranged in parallel with each other in the planar layout, this can more accurately estimate the PLS component caused by oblique incidence. Additionally, in this embodiment, a transfer transistor TRG is used to read charges from the charge holding section MEM, and a transfer transistor DMG is used to read charges from the charge holding section DM. As a result, compared with the case where the switching element is kept conducting when reading charges from the charge holding section MEM, a higher conversion efficiency is achieved. Therefore, while suppressing a reduction in resolution and a reduction in conversion efficiency, the influence of the obliquely incident light leaking into the charge accumulation section can be accurately eliminated.

[0077] In addition, in the present embodiment, the charge holding section MEM, the charge holding section DM, and the floating diffusion section FD each include an impurity semiconductor region of the same conductivity type. Further, the impurity concentration of the charge holding section MEM and the charge holding section DM is lower than that of the floating diffusion section FD. This creates a potential difference between the charge holding section MEM and the charge holding section DM and the floating diffusion section FD, enabling complete discharge of charges from the charge holding section MEM and the charge holding section DM respectively.

[0078] In addition, in the present embodiment, the transfer transistor DMG includes a vertical gate VG reaching the charge holding section DM. This enables reliable charge transfer from the charge holding section DM.

[0079] In addition, in the present embodiment, the photodiode PD is disposed adjacent to the charge holding section MEM and the charge holding section DM in a planar layout. Further, with respect to the positional relationship with the photodiode PD, the light receiving surface 10A is formed at a position on the side of the transfer transistor DMG. In other words, the solid-state imaging device 1 according to the present embodiment is a top-illuminated image sensor. Thus, the present invention is also applicable to a top-illuminated image sensor.

[0080] In addition, in the present embodiment, each sensor pixel 11 includes a light-shielding layer 36 disposed around the light receiving surface 10A and opposite to the charge holding section DM. This suppresses external light from directly entering the charge holding section DM without passing through the light receiving surface 10A. As a result, noise components can be reduced from mixing into the charges to be read from the charge holding section DM.

[0081] <2. Modification Example>

[0082] A modification example of the solid-state imaging device 1 according to the above embodiment will be described below.

[0083] [Modification Example A]

[0084] In the above embodiment, the light receiving surface 10A may be provided on the back surface of the semiconductor substrate 30. Figure 7 A modification example of the planar structure of the sensor pixel 11 is shown. Figure 8 Shows along Figure 7 an example of the cross-sectional structure along line A-A. Figure 7 And Figure 8 are schematic views and are not necessarily drawn to scale. In Figure 8 , the density of the impurity concentration is represented by symbols including "P+", "N-", "N+", and "N++". Here, in the positions represented as "P+", the value of the concentration of p-type impurities (acceptors) is higher than 1×10 16 cm －3 to 5×10 18 cm －3Values within the range. "N+" indicates that the concentration of n-type impurities (donors) is higher than "N-". "N++" indicates that the concentration of n-type impurities (donors) is higher than "N+". For example, at a position denoted as "N-", the concentration of n-type impurities (donors) has a value in the range of 1×10 16 cm -3 to 5×10 18 cm -3 within the range.

[0085] The sensor pixel 11 is formed on the semiconductor substrate 30. For example, the semiconductor substrate 30 is a silicon substrate. The semiconductor substrate 30 includes a p-well layer 32 located on and near the upper surface of the semiconductor substrate 30, and includes an n-type semiconductor layer 31 located at a deeper position than the p-well layer 32. The p-well layer 32 is a p-type semiconductor region formed at and around the upper surface of the semiconductor substrate 30. In the p-well layer 32, a photodiode PD is formed. The photodiode PD includes, for example, an n-type semiconductor region formed in the p-well layer 32. The photodiode PD is arranged in a planar layout at a position where a part of the photodiode PD overlaps with the charge holding section MEM and the charge holding section DM. The light receiving surface 10A is located in the region on the back surface of the semiconductor substrate 30 opposite to the photodiode PD. In terms of the positional relationship with the photodiode PD, the light receiving surface 10A is formed at a position on the opposite side of the transfer transistor TRX.

[0086] The charge holding section MEM is formed at a position in the p-well layer 32 opposite to the gate of the transfer transistor TRX. The charge holding section MEM is formed at a predetermined depth from the upper surface of the semiconductor substrate 30. The charge holding section MEM includes a semiconductor region of n-type impurities formed in the p-well layer 32. A p-type semiconductor region 35 is formed between the upper surface of the semiconductor substrate 30 and the charge holding section MEM.

[0087] The charge holding section DM is formed in the p-well layer 32 in a planar layout at a position where all or a part of the charge holding section DM overlaps with the charge holding section MEM. In other words, the sensor pixel 11 includes the charge holding section DM, which is at a position in the p-well layer 32 where all or a part of the charge holding section DM overlaps with the charge holding section MEM in a planar layout. Further, the photodiode PD is arranged in a planar layout at a position where a part of the photodiode PD overlaps with the charge holding section MEM and the charge holding section DM. Therefore, the photodiode PD, the charge holding section DM, the charge holding section MEM, and the p-type semiconductor region 35 are arranged in this order in the p-well layer 32 starting from the back side (light-receiving surface 10A) of the semiconductor substrate. The charge holding section DM includes a semiconductor region of n-type impurities formed in the p-well layer 32. The charge holding section DM is formed so as not to be electrically conductive with the charge holding section MEM. The n-type impurity (donor) concentration in each of the charge holding section MEM and the charge holding section DM is lower than the n-type impurity (donor) concentration in the floating diffusion section FD.

[0088] The floating diffusion section FD and the discharging floating diffusion section OFD are formed to surround the region including the photodiode PD, the charge holding section DM, the charge holding section MEM, and the p-type semiconductor region 35. In other words, the sensor pixel 11 has the floating diffusion section FD and the discharging floating diffusion section OFD that surround the region including the photodiode PD, the charge holding section DM, the charge holding section MEM, and the p-type semiconductor region 35. Both the floating diffusion section FD and the discharging floating diffusion section OFD include semiconductor regions formed in the p-well layer 32 and having a high n-type impurity concentration.

[0089] The transfer transistor DMG is formed near the floating diffusion section FD. In other words, the sensor pixel 11 includes the transfer transistor DMG located near the floating diffusion section FD. The transfer transistor DMG includes the vertical gate VG1 that reaches the charge holding section DM. For example, the vertical gate VG1 contains a metal material.

[0090] The discharging transistor OFG is formed near the discharging floating diffusion section OFD. In other words, the sensor pixel 11 includes the discharging transistor OFG located near the discharging floating diffusion section OFD. The discharging transistor OFG includes the vertical gate VG2 that reaches the photodiode PD. For example, the vertical gate VG2 contains a metal material.

[0091] The sensor pixel 11 includes the transfer transistor TRX located at a position opposite to the charge holding section MEM. The transfer transistor TRX includes the vertical gate VG3 that reaches the photodiode PD. For example, the vertical gate VG3 contains a metal material.

[0092] The sensor pixel 11 includes a light-shielding layer 37 located on the semiconductor substrate 30. The light-shielding layer 37 is disposed at least at a position opposite to the charge holding portion MEM. For example, the light-shielding layer 37 contains a metal material. The sensor pixel 11 further includes a light-shielding layer 38 located between the photodiode PD and the charge holding portion DM. For example, the light-shielding layer 38 is disposed at positions opposite to the charge holding portion MEM and the charge holding portion DM. For example, the light-shielding layers 37 and 38 contain a metal material. It should be noted that, for example, as Figure 9 shown, the light-shielding layer 38 can be omitted as needed.

[0093] In this modification, similar to the foregoing embodiment, there is provided a charge holding portion MEM that holds the charge transferred from the photodiode PD, and a charge holding portion DM that is formed to be non-conductive with the charge holding portion MEM. This makes it possible to reduce the PLS component included in the signal charge based on the signal charge read from the charge holding portion MEM and the noise charge read from the charge holding portion DM. Further, in this modification, all or a part of the charge holding portion DM is disposed at a position overlapping with the charge holding portion MEM in the planar layout. Compared with the case where the charge holding portion MEM and the charge holding portion DM are disposed in parallel with each other in the planar layout, this can more accurately estimate the PLS component caused by the oblique incidence. Further, in this embodiment, a transfer transistor TRG is used to read the charge from the charge holding portion MEM, and a transfer transistor DMG is used to read the charge from the charge holding portion DM. As a result, a higher conversion efficiency is achieved compared with the case where the switching element is kept on during the charge reading from the charge holding portion MEM. Therefore, while suppressing the reduction in resolution and the reduction in conversion efficiency, it is possible to accurately eliminate the influence of the obliquely incident light leaking into the charge accumulation portion.

[0094] Further, in this modification, the transfer transistor DMG includes a vertical gate VG1 that reaches the charge holding portion DM. This makes it possible to reliably perform charge transfer from the charge holding portion DM.

[0095] Further, in this modification, the photodiode PD is disposed in the planar layout at a position where a part of the photodiode PD overlaps with the charge holding portion MEM and the charge holding portion DM. Further, in terms of the positional relationship with the photodiode PD, the light-receiving surface 10A is formed at a position opposite to the transfer transistor DMG. In other words, the solid-state imaging device 1 according to this modification is a back-illuminated image sensor. Therefore, the present invention is also applicable to a back-illuminated image sensor.

[0096] In addition, in this modification example, each sensor pixel 11 includes a light-shielding layer 38 located between the photodiode PD and the charge holding section DM. This makes it possible to suppress external light from directly entering the charge holding section DM without passing through the light-receiving surface 10A. As a result, it is possible to reduce the mixing of noise components into the charge to be read from the charge holding section DM.

[0097] [Modification Example B]

[0098] In the foregoing embodiment, for example, as Figure 10 shown, the vertical gate VG can be omitted. In this case, instead of the vertical gate VG, in the p-well layer 32, an n-type semiconductor region 39 that reaches the charge holding section DM and has an impurity concentration higher than that of the charge holding section DM is formed. In other words, in this modification example, each sensor pixel 11 includes an n-type semiconductor region 39 that reaches the charge holding section DM and has an impurity concentration higher than that of the charge holding section DM. Even in this case, charge transfer can be reliably performed from the charge holding section DM.

[0099] <3. Application Examples>

[0100] The present invention is not limited to applications to solid-state imaging devices. More specifically, this technology is applicable not only to solid-state imaging devices, but also to any electronic device including a solid-state imaging device, such as: a camera module including an optical lens system, etc., an imaging unit such as a digital camera or a video camera, a mobile terminal unit having an imaging function (e.g., a smartphone or a tablet terminal), or a copying machine using a solid-state imaging device in an image reading section.

[0101] Figure 11 is a block diagram showing a configuration example of an electronic device 2 including the solid-state imaging device 1 according to any one of the foregoing embodiments and their modification examples.

[0102] The electronic device 2 is, for example, any electronic device including an imaging unit such as a digital camera or a video camera and a mobile terminal unit such as a smartphone or a tablet terminal. The electronic device 2 includes, for example, the solid-state imaging device 1 according to any one of the foregoing embodiments and their modification examples, a DSP circuit 210, a frame memory 220, a display section 230, a storage section 240, an operation section 250, and a power supply section 260. The DSP circuit 210 corresponds to a specific example of the "signal processing circuit" of the present invention. In the electronic device 2, the DSP circuit 210, the frame memory 220, the display section 230, the storage section 240, the operation section 250, and the power supply section 260 are connected to each other via a bus 270.

[0103] The solid-state imaging device 1 according to any one of the foregoing embodiments and their modifications outputs image data corresponding to incident light. The DSP circuit 210 is a signal processing circuit that processes signals (image data) output from the solid-state imaging device 1 according to any one of the foregoing embodiments and their modifications. The frame memory 220 temporarily holds the image data processed by the DSP circuit 210 in units of frames. The display unit 230 includes, for example, a panel-type display such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state imaging device 1 according to any one of the foregoing embodiments and their modifications. The storage unit 240 stores the image data of the moving image or the still image captured by the solid-state imaging device 1 according to any one of the foregoing embodiments and their modifications in a storage medium such as a semiconductor memory or a hard disk. The storage unit 240 also stores a correction coefficient α, which will be described later, in a storage medium such as a semiconductor memory or a hard disk. The operation unit 250 outputs operation instructions for various functions of the electronic device 2 according to the user's operations. The power supply unit 260 appropriately supplies various types of power serving as the operation power for the DSP circuit 210, the frame memory 220, the display unit 230, the storage unit 240, and the operation unit 250 to these power supply targets.

[0104] Next, the imaging steps of the electronic device 2 will be described.

[0105] Figure 12 An example of a flowchart showing the imaging operation of the electronic device 2 is shown. The user operates the operation unit 250 to instruct the start of imaging (step S101). The operation unit 250 then sends an imaging instruction to the solid-state imaging device 1 (step S102). After receiving the imaging instruction, the solid-state imaging device 1 (specifically, the system control circuit 24) performs imaging under the global shutter operation (step S103).

[0106] The solid-state imaging device 1 outputs the image data I l and the noise image data I 2 to the DSP circuit 210. Here, the image data I l is data of pixel signals for all pixels, and the pixel signals are generated based on the charges accumulated in the charge holding unit MEM. The noise image data I 2 is data of noise signals for all pixels, and the noise signals are generated based on the charges accumulated in the charge holding unit DM.

[0107] The DSP circuit 210 is based on the image data I 1 input from the solid-state imaging device 1 2Perform a predetermined noise reduction process (step S104). The DSP circuit 210 performs the above-described noise reduction process using the correction coefficient α stored in the storage unit 240. The DSP circuit 210 causes the frame memory 220 to hold the image data I obtained through the noise reduction process c , and the frame memory 220 causes the storage unit 240 to store the image data I c (step S105). In this way, imaging is performed by the electronic device 2

[0108] Figure 13 and Figure 14 respectively show examples of the correction coefficients for each pixel used in the above-described noise reduction process

[0109] For example, as Figure 13 shown, in the case where two or more sensor pixels 11 include two or more sensor pixels 11R for red light, two or more sensor pixels 11G for green light, and two or more sensor pixels 11B for blue light, a correction coefficient α for red light can be set for each color of the sensor pixel 11. It should be noted that Figure 13 as an example, the following case is shown: a correction coefficient α is set for the sensor pixel 11R for red light R , a correction coefficient α is set for the sensor pixel 11G for green light G , and a correction coefficient α is set for the sensor pixel 11B for blue light B . In addition Figure 13 schematically shows a state in which one sensor pixel 11R, two sensor pixels 11G, and one sensor pixel 11B constitute one color sensor pixel. The correction coefficient α R , the correction coefficient α G and the correction coefficient α B are, for example, values corresponding to wavelengths and are different from each other

[0110] In addition, for example, as Figure 14 shown, the correction coefficient α can be set corresponding to the position in the pixel array unit 10. It should be noted that Figure 14 as an example, the following case is shown: a correction coefficient α is set for the central part of the pixel array unit 10 a , a correction coefficient α is set for the upper central part of the pixel array unit 10 b , a correction coefficient α is set for the lower central part of the pixel array unit 10 c , a correction coefficient α is set for the central left part of the pixel array unit 10 d , a correction coefficient α is set for the upper left part of the pixel array unit 10 e , and a coefficient α is set for the lower left part of the pixel array unit 10 f, a correction coefficient α is set for the central right part of the pixel array unit 10 g , a correction coefficient α is set for the upper right part of the pixel array unit 10 h , and a correction coefficient α is set for the lower right part of the pixel array unit 10 i . The correction coefficient α a , the correction coefficient α b , the correction coefficient α c , the correction coefficient α d , the correction coefficient α e , the correction coefficient α f , the correction coefficient α g , the correction coefficient α h and the correction coefficient α i are, for example, values corresponding to positions in the pixel array unit 10 and are different from each other.

[0111] The DSP circuit 210 performs a predetermined noise reduction process based on the image data I 1 input from the solid-state imaging device 1 and the noise image data I 2 to obtain image data I with reduced PLS noise c . The DSP circuit 210, for example, subtracts the image data (αI 1 ) obtained by multiplying the noise image data I 2 by a predetermined correction coefficient α from the image data I 2 ), thereby reducing the noise contained in the image data I 1 . For example, the DSP circuit 210 obtains the image data I c according to the following formula (1).

[0112] I c = I 1 - αI 2 (1)

[0113] In the electronic device 2, the solid-state imaging device 1 according to any one of the foregoing embodiments and their modifications is used, and the above-described noise reduction process is performed at the DSP circuit 210. This makes it possible to accurately eliminate the influence of obliquely incident light leaking into the charge accumulation unit while suppressing a reduction in resolution and a reduction in conversion efficiency.

[0114] <4. Application Example>

[0115] The technology according to the present invention (the present invention) can be applied to various products. For example, the technology according to the embodiments of the present invention can be implemented as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

[0116] Figure 15It is a block diagram showing an example of the schematic configuration of a vehicle control system which is an example of a mobile body control system to which the technology according to an embodiment of the present invention can be applied.

[0117] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In Figure 15 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and a vehicle-mounted network interface (I / F: interface) 12053 are shown.

[0118] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 functions as a control device for devices such as a driving force generation device for generating a vehicle driving force, such as an internal combustion engine, a drive motor, etc., a driving force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the vehicle steering angle, and a braking device for generating a vehicle braking force.

[0119] The body system control unit 12020 controls the operation of various types of devices provided on the vehicle according to various types of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from a mobile device serving as an alternative key can be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the vehicle door lock device, electric window device, and vehicle lights, etc.

[0120] The outside vehicle information detection unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, a camera unit 12031 is connected to the outside vehicle information detection unit 12030. The outside vehicle information detection unit 12030 causes the camera unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside vehicle information detection unit 12030 can perform object detection processing such as for a person, a vehicle, an obstacle, a sign, characters on the road surface, etc. or distance measurement processing for these objects.

[0121] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light. The imaging unit 12031 can output the electrical signal as an image or can output the electrical signal as information regarding distance measurement. In addition, the light received by the imaging unit 12031 can be visible light or can be invisible light such as infrared light.

[0122] The in-vehicle information detection unit 12040 detects information regarding the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 for detecting the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the degree of fatigue or the degree of concentration of the driver, or can determine whether the driver is dozing off.

[0123] The microcomputer 12051 calculates control target values for the driving force generation device, the steering mechanism, or the braking device based on the information regarding the inside and outside of the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, and outputs a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS: advanced driver assistance system), and the functions of the advanced driver assistance system include collision avoidance or impact mitigation of the vehicle, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0124] In addition, based on the information regarding the inside and outside of the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can perform cooperative control such as autonomous driving aimed at enabling the vehicle to drive autonomously without relying on the operation of the driver by controlling the driving force generation device, the steering mechanism, or the braking device, etc.

[0125] In addition, based on the information regarding the outside of the vehicle obtained by the out-vehicle information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlamp to switch from high beam to low beam according to the positions of the preceding vehicle or the oncoming vehicle detected by the out-vehicle information detection unit 12030, thereby performing cooperative control aimed at preventing glare.

[0126] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of notifying information to vehicle passengers or outside the vehicle visually or auditorily. Figure 15In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display or a head-up display.

[0127] Figure 16 FIG. is an example showing the installation position of the imaging unit 12031.

[0128] In Figure 16 the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0129] The imaging unit 12031 including the imaging units 12101, 12102, 12103, 12104, and 12105 is provided, for example, at the front nose, side mirrors, rear bumper, and rear door positions of the vehicle 12100 and at the upper position of the in-vehicle windshield. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the in-vehicle windshield mainly acquire the front images of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire the side images of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or rear door mainly acquires the rear images of the vehicle 12100. The imaging unit 12105 provided at the upper part of the in-vehicle windshield is mainly used to detect oncoming vehicles, pedestrians, obstacles, signal lights, traffic signs, or lanes.

[0130] Incidentally, Figure 16 FIG. shows an example of the imaging ranges of the imaging units 12101 to 12104. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided at the rear bumper or rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0131] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements or may be an imaging element having pixels for phase difference detection.

[0132] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100), and thereby particularly extract the following three-dimensional object as the preceding vehicle: the closest three-dimensional object located on the traveling path of the vehicle 12100 and traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). Additionally, the microcomputer 12051 can preset the following distance to be maintained from the preceding vehicle and execute automatic braking control (including following stop control) or automatic acceleration control (including following start control), etc. Therefore, cooperative control of autonomous driving can be executed that aims to automatically drive the vehicle without relying on the driver's operation.

[0133] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12501 can classify the three-dimensional object data regarding the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 has difficulty visually recognizing. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and executes forced deceleration or avoidance steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0134] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed through the following steps: a step of extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras; and a step of determining whether the object is a pedestrian by performing pattern matching processing on a series of feature points representing the object contour. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 such that an emphasized rectangular contour line is superimposed and displayed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 such that an icon representing a pedestrian or the like is displayed at a required position.

[0135] Examples of the mobile body control system to which the technology of the present invention can be applied have been described above. The technology of the present invention can be applied to the imaging unit 12031 in the above configuration. Specifically, the solid-state imaging device 1 according to any one of the foregoing embodiments and their modifications can be applied to the imaging unit 12031. Applying the technology of the present invention to the imaging unit 12031 enables obtaining a high-definition captured image with less noise. Therefore, high-precision control using the captured image can be performed in the mobile body control system.

[0136] The present invention has been described with reference to the embodiments, modifications, application examples, and usage examples of the present invention. However, the present invention is not limited to the above-described embodiments and the like, and various modifications can be made. It should be noted that the effects described herein are merely examples. The effects of the present invention are not limited to the effects described herein. The present invention may have any effects other than the effects described herein.

[0137] In addition, the present invention may also have the following configuration.

[0138] (1) A solid-state imaging device, comprising:

[0139] A light-receiving surface;

[0140] Two or more pixels opposed to the light-receiving surface, wherein,

[0141] Each of the pixels includes:

[0142] A photoelectric conversion unit that performs photoelectric conversion on light incident via the light-receiving surface,

[0143] A first charge holding unit that holds the charge transferred from the photoelectric conversion unit,

[0144] A second charge holding section, which is disposed in a planar layout at a position where all or a part of the second charge holding section overlaps with the first charge holding section, and is formed to be non-conductive with the first charge holding section,

[0145] A first transfer transistor, which transfers the charge held by the first charge holding section to a floating diffusion section, and

[0146] A second transfer transistor, which transfers the charge held by the second charge holding section to the floating diffusion section.

[0147] (2) The solid-state imaging device according to (1), wherein,

[0148] The first charge holding section, the second charge holding section, and the floating diffusion section each include an impurity semiconductor region of a common conductivity type, and

[0149] The impurity concentration of each of the first charge holding section and the second charge holding section is lower than the impurity concentration of the floating diffusion section.

[0150] (3) The solid-state imaging device according to (2), wherein the second transfer transistor includes a vertical gate reaching the second charge holding section.

[0151] (4) The solid-state imaging device according to (2), wherein the second transfer transistor is electrically connected to the second charge holding section through an impurity semiconductor region that reaches the second charge holding section and has an impurity concentration higher than the impurity concentration of the second charge holding section.

[0152] (5) The solid-state imaging device according to any one of (1) to (4), wherein,

[0153] Each of the pixels further includes a third transfer transistor, which transfers the charge accumulated in the photoelectric conversion section to the first charge holding section,

[0154] The photoelectric conversion section is disposed in the planar layout at a position adjacent to the first charge holding section and the second charge holding section, and

[0155] In terms of the positional relationship with the photoelectric conversion section, the light-receiving surface is formed at a position on the side of the third transfer transistor.

[0156] (6) The solid-state imaging device according to (5), wherein each of the pixels includes a light-shielding layer, which is disposed around the light-receiving surface and at least at a position opposite to the first charge holding section.

[0157] (7) The solid-state imaging device according to any one of (1) to (4), wherein,

[0158] Each of the pixels further includes a third transfer transistor that transfers the charge accumulated in the photoelectric conversion section to the first charge holding section.

[0159] In the planar layout, the photoelectric conversion section is disposed at a position where a part of the photoelectric conversion section overlaps with the first charge holding section and the second charge holding section, and

[0160] In terms of the positional relationship with the photoelectric conversion section, the light-receiving surface is formed at a position on the opposite side of the third transfer transistor.

[0161] (8) The solid-state imaging device according to (7), wherein each of the pixels includes a light-shielding layer located between the photoelectric conversion section and the second charge holding section.

[0162] (9) An electronic device includes:

[0163] A solid-state imaging device that outputs image data corresponding to incident light; and

[0164] A signal processing circuit that processes the image data,

[0165] The solid-state imaging device includes:

[0166] A light-receiving surface;

[0167] Two or more pixels that face the light-receiving surface, wherein

[0168] Each of the pixels includes:

[0169] A photoelectric conversion section that performs photoelectric conversion on the light incident through the light-receiving surface,

[0170] A first charge holding section that holds the charge transferred from the photoelectric conversion section,

[0171] A second charge holding section that is disposed in the planar layout at a position where all or a part of the second charge holding section overlaps with the first charge holding section, and is formed to be non-conductive with the first charge holding section,

[0172] A first transfer transistor that transfers the charge held by the first charge holding section to the floating diffusion section, and

[0173] A second transfer transistor that transfers the charge held by the second charge holding section to the floating diffusion section, and

[0174] The signal processing circuit reduces the noise included in the first image data based on the first image data and the second image data. The first image data is generated based on the charges held by the first charge holding unit, and the second image data is generated based on the charges held by the second charge holding unit.

[0175] (10) The electronic device according to (9), wherein the signal processing circuit reduces the noise included in the first image data by subtracting third image data from the first image data. The third image data is obtained by multiplying the second image data by a predetermined correction coefficient.

[0176] The solid-state imaging device and the electronic device according to respective embodiments of the present invention are provided with: a first charge holding unit that holds charges transferred from a photoelectric conversion unit, and a second charge holding unit that is formed to be non-conductive with the first charge holding unit. All or part of the second charge holding unit is arranged at a position overlapping the first charge holding unit in a planar layout. A first transfer transistor is used to read charges from the first charge holding unit, and a second transfer transistor is used to read charges from the second charge holding unit. Therefore, it is possible to accurately eliminate the influence of obliquely incident light leaking into the charge accumulation unit while suppressing a reduction in resolution and a reduction in conversion efficiency.

[0177] This application claims priority based on Japanese Patent Application No. 2018-175983 filed with the Japan Patent Office on September 20, 2018, the entire contents of which are incorporated herein by reference.

[0178] It should be understood that those skilled in the art can make various deformations, combinations, sub-combinations, and substitutions according to design requirements and other factors, and they are within the scope of the appended claims or their equivalents.

Claims

1. A solid-state imaging device, which comprises: a light-receiving surface; two or more pixels opposed to the light-receiving surface, wherein each of the pixels comprises: a photoelectric conversion section that performs photoelectric conversion on light incident via the light-receiving surface, a first charge holding section that holds the charge transferred from the photoelectric conversion section, a second charge holding section that temporarily holds the charge for parasitic light sensitivity correction, the second charge holding section being arranged in a planar layout at a position where all or a part of the second charge holding section overlaps with the first charge holding section and being formed so as not to be electrically conductive with the first charge holding section, a first transfer transistor that transfers the charge held by the first charge holding section to a floating diffusion section, and a second transfer transistor that transfers the charge held by the second charge holding section to the floating diffusion section.

2. The solid-state imaging device according to claim 1, wherein the first charge holding section, the second charge holding section, and the floating diffusion section each include an impurity semiconductor region of a common conductivity type, and the impurity concentration of each of the first charge holding section and the second charge holding section is lower than the impurity concentration of the floating diffusion section.

3. The solid-state imaging device according to claim 2, wherein the second transfer transistor includes a vertical gate reaching the second charge holding section.

4. The solid-state imaging device according to claim 2, wherein the second transfer transistor is electrically connected to the second charge holding section through an impurity semiconductor region that reaches the second charge holding section and has an impurity concentration higher than the impurity concentration of the second charge holding section.

5. The solid-state imaging device according to any one of claims 1-4, wherein each of the pixels further includes a third transfer transistor that transfers the charge accumulated in the photoelectric conversion section to the first charge holding section, the photoelectric conversion section is arranged in the planar layout at a position adjacent to the first charge holding section and the second charge holding section, and in terms of the positional relationship with the photoelectric conversion section, the light-receiving surface is formed at a position on the third transfer transistor side.

6. The solid-state imaging device according to claim 5, wherein each of the pixels includes a light-shielding layer arranged around the light-receiving surface and at least opposed to the first charge holding section.

7. The solid-state imaging device according to any one of claims 1-4, wherein each of the pixels further includes a third transfer transistor that transfers the charge accumulated in the photoelectric conversion section to the first charge holding section, the photoelectric conversion section is arranged in the planar layout at a position where a part of the photoelectric conversion section overlaps with the first charge holding section and the second charge holding section, and in terms of the positional relationship with the photoelectric conversion section, the light-receiving surface is formed at a position on the opposite side of the third transfer transistor.

8. The solid-state imaging device according to claim 7, wherein each of the pixels includes a light-shielding layer located between the photoelectric conversion section and the second charge holding section.

9. An electronic device comprises: The solid-state imaging device according to any one of claims 1 to 8, which outputs image data corresponding to incident light; and a signal processing circuit that processes the image data, and the signal processing circuit reduces noise included in the first image data based on first image data and second image data, the first image data being generated based on charges held in the first charge holding unit, and the second image data being generated based on charges held in the second charge holding unit.

10. The electronic device according to claim 9, wherein the signal processing circuit reduces noise included in the first image data by subtracting third image data from the first image data, the third image data being obtained by multiplying the second image data by a predetermined correction coefficient.

Images