Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a ground pad on a substrate, a lower electrode on the ground pad, the lower electrode electrically connected to the ground pad, a dielectric layer on the lower electrode, the dielectric layer extending along a contour of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including a first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2019-0135044, filed on October 29, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the same that uses a capacitor as a data storage element. Background Technology

[0003] Recently, as semiconductor devices with larger storage capacities have become highly integrated, design rules have continued to decrease. This trend can also be seen in Dynamic Random Access Memory (DRAM), a type of semiconductor memory device. For DRAM to function, a certain level of capacitance is required in each cell.

[0004] Increasing the capacitance increases the amount of charge stored in the capacitor, thereby improving the refresh characteristics of the semiconductor device. Improved refresh characteristics in semiconductor devices can increase their yield.

[0005] To increase capacitance, methods have been studied, such as using a dielectric layer with a high dielectric constant in the capacitor or increasing the contact area between the lower electrode of the capacitor and the dielectric layer. Summary of the Invention

[0006] Various aspects of this disclosure provide a semiconductor device with improved performance and reliability through interface engineering between the plate electrode and the top electrode.

[0007] Various aspects of this disclosure also provide a method for manufacturing a semiconductor device with improved performance and reliability through interface engineering between the plate electrode and the top electrode.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: a ground pad located on a substrate; a lower electrode located on the ground pad and electrically connected to the ground pad; a dielectric layer located on the lower electrode and extending along the contour of the lower electrode; an upper electrode located on the dielectric layer; and an upper plate electrode located on the upper electrode and including a first fluorine (F), wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the concentration of the first fluorine in the upper plate electrode decreases with increasing distance from the interface of the upper plate electrode.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: a ground pad located on a substrate; a lower electrode located on the ground pad and electrically connected to the ground pad; a dielectric layer located on the lower electrode and extending along the contour of the lower electrode; an upper electrode located on the dielectric layer; and an upper plate electrode including a lower plate region and an upper plate region located on the upper electrode, wherein the lower plate region is located between the upper electrode and the upper plate region, and wherein the lower plate region includes fluorine, and the upper plate region does not include fluorine.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device includes: a trench located in a substrate; a gate electrode filling a portion of the trench; a buried contact located on at least one side of the gate electrode and electrically connected to the substrate; a ground pad located on the buried contact; and a capacitor electrically connected to the ground pad, wherein the capacitor includes a lower electrode electrically connected to the ground pad, a dielectric layer located on the lower electrode, an upper electrode located on the dielectric layer, and an upper plate electrode located on the upper electrode, wherein the upper plate electrode includes fluorine, and wherein the concentration of fluorine in the upper plate electrode decreases with increasing distance from the upper electrode.

[0011] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a lower electrode on a ground pad; forming a dielectric layer on the lower electrode along the contour of the lower electrode; forming an upper electrode on the dielectric layer; and forming a fluorine-doped upper plate electrode on the upper electrode.

[0012] However, the aspects of this disclosure are not limited to those set forth herein, and will become more apparent to those skilled in the art from the following detailed description of the disclosure. Attached Figure Description

[0013] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0014] Figure 1 This is a diagram illustrating a semiconductor device according to some embodiments;

[0015] Figure 2 yes Figure 1 A magnified view of part P;

[0016] Figures 3 to 6 It shows along Figure 2 A schematic diagram illustrating different examples of fluorine (F) concentrations in line A;

[0017] Figure 7 This is a diagram illustrating a semiconductor device according to some embodiments;

[0018] Figure 8 It shows along Figure 7 A schematic diagram showing the concentration of fluorine (F) in line A;

[0019] Figure 9 This is a diagram illustrating a semiconductor device according to some embodiments;

[0020] Figure 10 It shows along Figure 9 A schematic diagram showing the concentration of fluorine (F) in line A;

[0021] Figure 11 This is a diagram illustrating a semiconductor device according to some embodiments;

[0022] Figure 12 This is a diagram illustrating a semiconductor device according to some embodiments;

[0023] Figure 13 This is a diagram illustrating a semiconductor device according to some embodiments;

[0024] Figure 14 This is a diagram illustrating a semiconductor device according to some embodiments;

[0025] Figure 15 This is a schematic layout diagram illustrating a semiconductor device according to some embodiments;

[0026] Figure 16 It is along Figure 15 A sectional view taken from line II; and

[0027] Figures 17 to 21 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0028] Figure 1 This is a diagram illustrating a semiconductor device according to some embodiments. Figure 2 yes Figure 1 A magnified view of part P. Figure 3 It shows along Figure 2 A schematic diagram of the concentration of fluorine (F) in line A.

[0029] Reference Figures 1 to 3 According to some embodiments, a semiconductor device may include: a first ground pad 120, a lower electrode 200, a capacitor dielectric layer 250, an upper electrode 260, and an upper plate electrode 270.

[0030] The first grounding pad 120 may be disposed on the substrate 100. The first grounding pad 120 may be connected to the substrate 100. The first grounding pad 120 may be electrically connected to a conductive area formed on or in the substrate 100.

[0031] The first grounding pad 120 can be connected to the substrate 100 via the first storage contact 115. The first grounding pad 120 can be disposed on the first storage contact 115.

[0032] The first interlayer insulation layer 110 may be disposed on the substrate 100. The first storage contact 115 and the first grounding pad 120 may be disposed in the first interlayer insulation layer 110 on the substrate 100.

[0033] Substrate 100 may be bulk silicon or silicon-on-insulator (SOI) substrate. Optionally, substrate 100 may be a silicon substrate or may include other materials such as silicon germanide, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto. In the following description, it is assumed that substrate 100 is a silicon substrate.

[0034] The first interlayer insulating layer 110 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof.

[0035] The first storage contact 115 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

[0036] The first grounding pad 120 may include, for example, at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, and a metal.

[0037] In a semiconductor device according to some embodiments, the first ground pad 120 may include tungsten (W).

[0038] An etch stop layer 130 may be disposed on the first interlayer insulating layer 110. The etch stop layer 130 may expose at least a portion of the first ground pad 120.

[0039] For example, an etch stop layer 130 may be disposed on the first ground pad 120. The etch stop layer 130 may include a lower electrode hole that exposes at least a portion of the first ground pad 120.

[0040] The etch stop layer 130 may include at least one of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbon oxynitride (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon carbonitride oxynitride (SiOCN). For example, the term "silicon carbon oxynitride (SiCO)" refers to the presence of silicon (Si), carbon (C), and oxygen (O), but does not refer to the ratio between silicon (Si), carbon (C), and oxygen (O).

[0041] The lower electrode 200 can be disposed on the first grounding pad 120. The lower electrode 200 is electrically connected to the first grounding pad 120.

[0042] The lower electrode 200 can extend in a second direction DR2, which is the thickness direction of the substrate 100. The length of the lower electrode 200 extending in the second direction DR2 is greater than the length of the lower electrode 200 extending in the first direction DR1.

[0043] Optionally, the lower electrode 200 extends a greater length in the second direction DR2 than it has a greater width in the first direction DR1. The lower electrode 200 may have, for example, a cylindrical (e.g., rectangular) shape.

[0044] Here, the second direction DR2 can refer to a direction parallel to the thickness direction of the substrate 100. The first direction DR1, which intersects the second direction DR2, refers to a direction parallel to the top surface of the substrate 100 or the top surface of the first interlayer insulating layer 110.

[0045] A portion of the lower electrode 200 may be disposed within the etch stop layer 130. The lower electrode 200 may extend through the etch stop layer 130 to be electrically connected to the first ground pad 120. For example, a portion of the sidewall of the lower electrode 200 may contact the etch stop layer 130.

[0046] The lower electrode 200 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), a conductive metal oxide (e.g., iridium oxide or niobium oxide), etc., but this disclosure is not limited thereto. In a semiconductor device according to some embodiments, the lower electrode 200 may include titanium nitride (TiN). Additionally, in a semiconductor device according to some embodiments, the lower electrode 200 may include niobium nitride (NbN).

[0047] The lower support pattern 140 can be disposed on the etch stop layer 130. The lower support pattern 140 is spaced apart from the etch stop layer 130 in the second direction DR2.

[0048] The lower support pattern 140 can contact the lower electrode 200. The lower support pattern 140 can contact a portion of the sidewall of the lower electrode 200.

[0049] The lower support pattern 140 can connect to the lower electrode 200 adjacent to it in the first direction DR1. Although Figure 1 Two lower electrodes 200 are shown connected by a lower support pattern 140, but this is merely for ease of description and the present disclosure is not limited thereto.

[0050] The upper support pattern 150 can be disposed on the lower support pattern 140. The upper support pattern 150 is spaced apart from the lower support pattern 140 in the second direction DR2.

[0051] The upper support pattern 150 can contact the lower electrode 200. The upper support pattern 150 can contact a portion of the sidewall of the lower electrode 200. Although... Figure 1 Two lower electrodes 200 are shown connected by an upper support pattern 150, but this is merely for ease of description and the present disclosure is not limited thereto.

[0052] For example, as shown, the top surface of the upper support pattern 150 may be flush with (i.e., coplanar) with the top surface of the lower electrode 200. As another example, the top surface of the lower electrode 200 may protrude beyond the top surface of the upper support pattern 150 in a second direction DR2 away from the substrate 100. In the following description, it is assumed that the top surface of the upper support pattern 150 is flush with the top surface of the lower electrode 200.

[0053] Each of the lower support pattern 140 and the upper support pattern 150 may include at least one of, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbon oxynitride (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon carbonitride oxynitride (SiOCN). In a semiconductor device according to some embodiments, each of the lower support pattern 140 and the upper support pattern 150 may include silicon carbonitride (SiCN) or silicon nitride.

[0054] although Figure 1 It is shown that the thickness of the lower support pattern 140 in the second direction DR2 is smaller than the thickness of the upper support pattern 150 in the second direction DR2, but this disclosure is not limited thereto. The thickness of the lower support pattern 140 in the second direction DR2 may be the same as the thickness of the upper support pattern 150 in the second direction DR2.

[0055] Unlike the illustrated example, a semiconductor device according to some embodiments may include only one of the lower support pattern 140 and the upper support pattern 150. Alternatively, in a semiconductor device according to some embodiments, an additional support pattern may be disposed between the etch stop layer 130 and the lower support pattern 140, or between the lower support pattern 140 and the upper support pattern 150.

[0056] A capacitor dielectric layer 250 may be disposed on the lower electrode 200. The capacitor dielectric layer 250 may be formed on the interface 200is of the lower electrode 200. The interface 200is of the lower electrode 200 may be a surface of the lower electrode 200 facing the capacitor dielectric layer 250. The interface 200is of the lower electrode 200 may be a portion of the surface defining the external shape of the lower electrode 200 facing the capacitor dielectric layer 250.

[0057] The capacitor dielectric layer 250 may be formed along the surface of the lower electrode 200, the surface of the lower support pattern 140, the surface of the upper support pattern 150, and the top surface of the etch stop layer 130. The capacitor dielectric layer 250 may extend along the contours of the lower electrode 200, the upper support pattern 150, the lower support pattern 140, and the etch stop layer 130 (e.g., conformally extending over the lower electrode 200, the upper support pattern 150, the lower support pattern 140, and the etch stop layer 130).

[0058] Since the lower support pattern 140 and the upper support pattern 150 are in contact with the lower electrode 200, the capacitor dielectric layer 250 does not extend between the lower support pattern 140 and the lower electrode 200, nor does it extend between the upper support pattern 150 and the lower electrode 200. Furthermore, the capacitor dielectric layer 250 does not extend between the etch stop layer 130 and the lower electrode 200.

[0059] The capacitor dielectric layer 250 may include, for example, one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but is not limited thereto. Although the capacitor dielectric layer 250 is shown as a single layer, this is merely for the purpose of description, and this disclosure is not limited thereto.

[0060] In a semiconductor device according to some embodiments, the capacitor dielectric layer 250 may include a stacked structure in which zirconium oxide, aluminum oxide and zirconium oxide are stacked in sequence.

[0061] In a semiconductor device according to some embodiments, capacitor dielectric layer 250 may include a dielectric layer containing hafnium (Hf).

[0062] In a semiconductor device according to some embodiments, the capacitor dielectric layer 250 may have a stacked structure including a ferroelectric material layer and a paraelectric material layer.

[0063] A ferroelectric material layer can possess ferroelectric properties. A ferroelectric material layer can have sufficient thickness to possess ferroelectric properties. The thickness range of a ferroelectric material layer with ferroelectric properties can vary depending on the ferroelectric material.

[0064] For example, the ferroelectric material layer may include a single metal oxide. The ferroelectric material layer may include a single metal oxide layer. Here, the single metal oxide may be a binary compound composed of a metal and oxygen. The ferroelectric material layer including the single metal oxide may have an orthorhombic crystal system.

[0065] As an example, the metal included in the single metal oxide layer can be hafnium (Hf). The single metal oxide layer can be a hafnium oxide (HfO) layer. Here, the hafnium oxide layer can have a stoichiometric chemical formula or it can have a non-stoichiometric chemical formula.

[0066] As another example, the metal included in the single metal oxide layer can be one of various rare earth metals belonging to the lanthanides. The single metal oxide layer can be a rare earth metal oxide layer formed from a rare earth metal belonging to the lanthanides. Here, the rare earth metal (belonging to the lanthanides) oxide layer can have a stoichiometric chemical formula or it can have a non-stoichiometric chemical formula.

[0067] The ferroelectric material layer may also include dopants incorporated into the single metal oxide layer. The doping concentration can vary depending on the type of dopant, but the doping concentration of the dopant included in the ferroelectric material layer can be 10% or lower.

[0068] As an example, when the single metal oxide layer is a hafnium oxide layer, the dopant may include at least one of gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum (Ta), strontium (Sr), and niobium (Nb). As another example, when the single metal oxide layer is a rare earth metal (belonging to the lanthanides) oxide layer, the dopant may include at least one of silicon (Si), aluminum (Al), hafnium (Hf), zirconium (Zr), and niobium (Nb).

[0069] As another example, the ferroelectric material layer may not include dopants incorporated into the single metal oxide layer.

[0070] When the ferroelectric material layer comprises a single metal oxide layer, the ferroelectric material layer may have a thickness of, for example, 1 nanometer (nm) or larger and 10 nm or smaller.

[0071] For example, the ferroelectric material layer may include a bimetallic oxide. The ferroelectric material layer may include a bimetallic oxide layer. Here, the bimetallic oxide may be a ternary compound composed of two metals and oxygen. The ferroelectric material layer including the bimetallic oxide may have an orthorhombic crystal system.

[0072] The metal included in the bimetallic oxide layer can be, for example, hafnium (Hf) and zirconium (Zr). The bimetallic oxide layer can be a hafnium-zirconium oxide layer (Hf...x Zr (1-x) In the bimetallic oxide layer, x can be 0.2 or greater and 0.8 or less. Here, the hafnium zirconium oxide layer (Hf x Zr (1-x) O) can have a chemical formula that conforms to stoichiometry, or it can have a chemical formula that does not conform to stoichiometry.

[0073] As an example, the ferroelectric material layer may also include dopants doped into the bimetallic oxide layer. The dopants may include at least one of gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum (Ta), and strontium (Sr). As another example, the ferroelectric material layer may not include dopants doped into the bimetallic oxide layer.

[0074] When the ferroelectric material layer includes a bimetallic oxide layer, the ferroelectric material layer can have a thickness of, for example, 1 nm or larger and 20 nm or smaller.

[0075] For example, the paraelectric material layer can be a dielectric layer including zirconium (Zr) or a stacked layer including zirconium (Zr), but is not limited thereto. Although the paraelectric material layer has the same chemical formula, it can exhibit ferroelectric or paraelectric properties depending on the crystal structure of the dielectric material.

[0076] Paraelectric materials can have a positive permittivity, while ferroelectric materials can have a negative permittivity within a predetermined range. In other words, paraelectric materials can have a positive capacitance, and ferroelectric materials can have a negative capacitance.

[0077] Generally, when two or more capacitors with positive capacitance are connected in series, the sum of their capacitances decreases. However, when a negative capacitor with negative capacitance and a positive capacitor with positive capacitance are connected in series, the sum of their capacitances increases.

[0078] The upper electrode 260 may be disposed on the capacitor dielectric layer 250. The upper electrode 260 may extend along the contour of the capacitor dielectric layer 250.

[0079] The upper electrode 260 may include a first surface 260sa and a second surface 260sb that are back-to-back with each other. The second surface 260sb of the upper electrode 260 may face the capacitor dielectric layer 250.

[0080] The upper electrode 260 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), a conductive metal oxide (e.g., iridium oxide or niobium oxide), etc., but this disclosure is not limited thereto. In a semiconductor device according to some embodiments, the upper electrode 260 may include titanium nitride (TiN). Additionally, in a semiconductor device according to some embodiments, the upper electrode 260 may include niobium nitride (NbN).

[0081] The upper electrode 260 may include fluorine (F) doping. A detailed description of the upper electrode 260 will be given in the description of the upper plate electrode 270.

[0082] The upper plate electrode 270 can be disposed on the upper electrode 260. The upper plate electrode 270 can be disposed on the first surface 260sa of the upper electrode 260.

[0083] The upper plate electrode 270 includes an interface 270is facing a first surface 260sa of the upper electrode 260. The interface 270is of the upper plate electrode 270 may be defined along the contour of the upper electrode 260.

[0084] The upper electrode 270 may include at least one of an elemental semiconductor material layer and a compound semiconductor material layer. The upper electrode 270 may include doped n-type or p-type impurities.

[0085] Elemental semiconductor material layers may include, for example, silicon or germanium layers. Compound semiconductor material layers may include, for example, silicon-germanium layers. In a semiconductor device according to some embodiments, the upper plate electrode 270 may include a silicon-germanium layer.

[0086] The upper electrode 270 may include fluorine (F) dopant (i.e., F dopant). The upper electrode 270 may include a lower electrode region 270LR containing fluorine (F) dopant and an upper electrode region 270UR not containing fluorine dopant. The lower electrode region 270LR may be defined between the upper electrode 260 and the upper electrode region 270UR.

[0087] The region of the upper electrode 270 that includes fluorine (F) doping is defined as the lower plate region 270LR. The region of the upper electrode 270 that does not include fluorine (F) doping is defined as the upper plate region 270UR. The lower plate region 270LR and the upper plate region 270UR can be distinguished based on whether or not they include fluorine (F) doping.

[0088] The upper electrode 270 may include a portion in which the concentration of fluorine (F) doping decreases with increasing distance from the interface 270is of the upper electrode 270 (i.e., with increasing distance from the interface 270is of the upper electrode 270). The concentration of fluorine (F) doping in the lower electrode region 270LR with increasing distance from the interface 270is of the upper electrode 270 ( / cm³)3 It can be reduced.

[0089] The concentration of fluorine (F) doping can be highest at the boundary portion of the interface 270is of the upper plate electrode 270, which includes the upper plate electrode 270. The concentration of fluorine (F) doping decreases as one moves away from the boundary portion of the upper plate electrode 270.

[0090] As the interface 270is moves away from the upper electrode 270, the concentration of fluorine (F) doping in the upper electrode 260 can decrease. As the distance moves from the first surface 260sa of the upper electrode 260 towards the second surface 260sb of the upper electrode 260, the concentration of fluorine (F) doping in the upper electrode 260 can also decrease.

[0091] although Figure 3 The distribution of fluorine (F) doping in the upper electrode 260 up to the second surface 260sb of the upper electrode is shown, but this is merely for illustrative purposes and the present disclosure is not limited thereto. The upper electrode 260 may include a first portion containing fluorine (F) doping and a second portion not containing fluorine (F).

[0092] although Figure 3 The diagram shows that the concentration of fluorine (F) doping is highest at interface 270is of the upper plate electrode 270, but this is merely for ease of description and the present disclosure is not limited thereto. The portion of the upper plate electrode 270 with the highest concentration of fluorine (F) doping can be a region of arbitrary thickness.

[0093] exist Figure 3 In this context, the concentration of fluorine (F) indicates only how large or small the concentration is for each region (e.g., within different parts of each region). Figure 3 In this context, the concentration of fluorine (F) is not expressed as a quantified concentration value.

[0094] The portion of the upper electrode 270 disposed between the upper support pattern 150 and the lower support pattern 140 and / or between the lower support pattern 140 and the etch stop layer 130 may include the upper plate region 270UR or may not include the upper plate region 270UR. This may depend on the extent to which the doped fluorine (F) diffuses in the upper electrode 270.

[0095] Unlike the example shown, the upper plate electrode 270 may not be formed between the upper support pattern 150 and the lower support pattern 140 and / or between the lower support pattern 140 and the etch stop layer 130.

[0096] The dielectric material included in the capacitor dielectric layer 250 may include a metal oxide. If oxygen is released from the dielectric material and the number of oxygen vacancies in the dielectric material increases, the breakdown voltage of the capacitor decreases. That is, when oxygen vacancies appear in the metal oxide forming the capacitor dielectric layer 250, the breakdown voltage of the capacitor including the capacitor dielectric layer 250 decreases.

[0097] However, by doping fluorine (F) into the portion of the upper plate electrode 270 that forms the boundary with the upper electrode 260, the breakdown voltage of the capacitor including the capacitor dielectric layer 250 can be increased.

[0098] The second interlayer insulating layer 160 may be disposed on the upper plate electrode 270. The second interlayer insulating layer 160 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), and combinations thereof.

[0099] Figures 4 to 6 It is shown along some embodiments Figure 2 A schematic diagram illustrating different examples of fluorine (F) concentrations for line A. For simplicity, the following description will focus on the reference... Figures 1 to 3 The differences in the descriptions.

[0100] Reference Figure 4 In a semiconductor device according to some embodiments, a portion of the capacitor dielectric layer 250 may include fluorine (F) doping.

[0101] The fluorine (F) doping in the capacitor dielectric layer 250 is not distributed throughout the entire capacitor dielectric layer 250.

[0102] The capacitor dielectric layer 250 may include a first region containing fluorine (F) doping and a second region not containing fluorine (F) doping. The first region of the capacitor dielectric layer 250 may be adjacent to the upper electrode 260. On the interface 200is of the lower electrode 200, the second region of the capacitor dielectric layer 250 and the first region of the capacitor dielectric layer 250 may be sequentially defined.

[0103] although Figure 4 The fluorine (F) doping in the capacitor dielectric layer 250 is shown to gradually decrease as it moves away from the second surface 260sb of the upper electrode 260, but this is merely for the sake of illustration and the present disclosure is not limited thereto.

[0104] Reference Figure 5 and Figure 6 In a semiconductor device according to some embodiments, the lower electrode 200 may include doped fluorine (F). For example, the lower electrode 200 may include a second region of fluorine (F) spaced apart from a first region of fluorine (F) in the upper electrode 260 and the upper plate electrode 270.

[0105] As the distance from the interface 200is of the lower electrode 200 increases, the concentration of fluorine (F) doping in the lower electrode 200 can decrease. The concentration of fluorine (F) doping can be highest at the boundary portion of the lower electrode 200 that includes the interface 200is. For example, the concentration of fluorine (F) doping in the lower electrode 200 can be highest at the interface 200is of the lower electrode 200.

[0106] exist Figure 5 In the capacitor dielectric layer 250, the boundary portion adjacent to the interface 200is of the lower electrode 200 does not include fluorine (F) doping.

[0107] exist Figure 6 In this capacitor dielectric layer 250, a third region containing fluorine (F) doping and a second region not containing fluorine (F) doping may be included. The third region of the capacitor dielectric layer 250 may be adjacent to the lower electrode 200. On the interface 200is of the lower electrode 200, the third region and the second region of the capacitor dielectric layer 250 may be sequentially defined.

[0108] Although it has been shown that the fluorine (F) doping in the capacitor dielectric layer 250 gradually decreases with respect to the interface 200is away from the lower electrode 200, this is merely for the sake of illustration and the present disclosure is not limited thereto.

[0109] Figure 7 This is a diagram illustrating a semiconductor device according to some embodiments. For simplicity, the following description will focus on the references... Figures 1 to 3 The differences in the descriptions.

[0110] Figure 8 It shows along Figure 7 A schematic diagram of the concentration of fluorine (F) in line A.

[0111] Reference Figure 7 and Figure 8 In a semiconductor device according to some embodiments, the upper plate electrode 270 may include a first plate electrode layer 271 and a second plate electrode layer 272.

[0112] The first plate electrode layer 271 can be disposed on the first surface 260sa of the upper electrode 260. The first plate electrode layer 271 includes the interface 270is of the upper plate electrode 270.

[0113] The second electrode layer 272 can be disposed on the first electrode layer 271. The first electrode layer 271 can be disposed between the upper electrode 260 and the second electrode layer 272.

[0114] The lower plate region 270LR may include a portion of the second plate electrode layer 272 and the first plate electrode layer 271. The upper plate region 270UR includes a portion of the second plate electrode layer 272, but does not include the first plate electrode layer 271.

[0115] Each of the first electrode layer 271 and the second electrode layer 272 may include a semiconductor material layer containing p-type or n-type impurities. In a semiconductor device according to some embodiments, the first electrode layer 271 may include an elemental semiconductor material layer. The second electrode layer 272 may include a compound semiconductor material layer. For example, the first electrode layer 271 may include a silicon layer, and the second electrode layer 272 may include a silicon-germanium layer.

[0116] The concentration of fluorine (F) doping in the upper electrode 270 can be highest in the first electrode layer 271. As the distance from the first electrode layer 271 increases, the concentration of fluorine (F) doping in the second electrode layer 272 can decrease.

[0117] Figure 9 This is a diagram illustrating a semiconductor device according to some embodiments. For simplicity, the following description will focus on the references... Figures 1 to 3 The differences in the descriptions.

[0118] Figure 10 It shows along Figure 9 A schematic diagram of the concentration of fluorine (F) in line A.

[0119] Reference Figure 9 and Figure 10 According to some embodiments, the semiconductor device may also include an upper passivation layer 265 disposed between the capacitor dielectric layer 250 and the upper electrode 260.

[0120] The upper passivation layer 265 can hinder / prevent oxygen atoms included in the capacitor dielectric layer 250 from moving to the upper electrode 260. The upper passivation layer 265 can be formed along the second surface 260sb of the upper electrode 260.

[0121] The upper passivation layer 265 may include a metal oxide. The upper passivation layer 265 may include at least one of, for example, titanium oxide, tantalum oxide, molybdenum oxide, tin oxide, and niobium oxide.

[0122] The upper passivation layer 265 may include doped fluorine (F). Although it has been shown that the doped fluorine (F) in the upper passivation layer 265 is distributed to the portion that forms the boundary with the capacitor dielectric layer 250, this is merely for the purpose of description and the present disclosure is not limited thereto. The upper passivation layer 265 may include a first portion containing doped fluorine (F) and a second portion not containing doped fluorine (F).

[0123] Figure 11This is a diagram illustrating a semiconductor device according to some embodiments. Figure 12 This is a diagram illustrating a semiconductor device according to some embodiments. For simplicity, the following description will focus on the references... Figures 1 to 3 The differences in the descriptions.

[0124] Reference Figure 11 According to some embodiments, the semiconductor device may also include a lower passivation layer 266 disposed between the capacitor dielectric layer 250 and the lower electrode 200.

[0125] The lower passivation layer 266 can hinder / prevent oxygen atoms included in the capacitor dielectric layer 250 from moving to the lower electrode 200. The lower passivation layer 266 can be formed along the interface 200is of the lower electrode 200.

[0126] The lower passivation layer 266 may include a metal oxide. The lower passivation layer 266 may include at least one of, for example, titanium oxide, tantalum oxide, molybdenum oxide, tin oxide, and niobium oxide.

[0127] Reference Figure 12 According to some embodiments, the semiconductor device may further include an insertion layer 255 disposed between the lower electrode 200 and the upper electrode 260. The insertion layer 255 may be disposed in the capacitor dielectric layer 250.

[0128] The insertion layer 255 can promote the crystallization of the capacitor dielectric layer 250. Through the insertion layer 255, the capacitor dielectric layer 250 can be divided into a first portion 250a and a second portion 250b of the capacitor dielectric layer 250. The insertion layer 255 can contact the first portion 250a and the second portion 250b of the capacitor dielectric layer 250.

[0129] The insertion layer 255 may include at least one of titanium (Ti), niobium (Nb), molybdenum (Mo), or tin (Sn) nitrides and oxides. Optionally, the insertion layer 255 may include at least one of ruthenium (Ru) and ruthenium oxide.

[0130] Figure 13 This is a diagram illustrating a semiconductor device according to some embodiments. Figure 14 This is a diagram illustrating a semiconductor device according to some embodiments. For simplicity, the following description will focus on the references... Figures 1 to 3 The differences in the descriptions.

[0131] Reference Figure 13 In a semiconductor device according to some embodiments, the lower electrode 200 may include a bottom 202 extending along the top surface of the first ground pad 120 and a sidewall portion 201 protruding from the bottom 202.

[0132] The bottom 202 of the lower electrode 200 may be parallel to the substrate 100. The sidewall portion 201 of the lower electrode 200 may extend along the second direction DR2.

[0133] The sidewall portion 201 of the lower electrode 200 may have a three-dimensional shape, such as a barrel shape. The lower electrode 200 may have, for example, a cylindrical shape.

[0134] Reference Figure 14 According to some embodiments, the semiconductor device may also include an insulating pattern 170 that contacts the lower electrode 200 and extends along the second direction DR2.

[0135] An insulating pattern 170 may be disposed on the etch stop layer 130. The insulating pattern 170 may include sidewalls 170s and a top surface 170us.

[0136] The first grounding pad 120 can be disposed in the etch stop layer 130. The lower electrode 200 can be disposed on the etch stop layer 130.

[0137] The lower electrode 200 may include a bottom 202 extending along the top surface of the first grounding pad 120 and a sidewall portion 201 protruding from the bottom 202. The sidewall portion 201 of the lower electrode 200 may extend along a second direction DR2. The sidewall portion 201 of the lower electrode 200 may extend along the sidewall 170s of the insulating pattern 170.

[0138] The lower electrode 200 may include a first sidewall 200ss1 and a second sidewall 200ss2. The second sidewall 200ss2 of the lower electrode 200 may face the sidewall 170s of the insulating pattern 170. For example, the lower electrode 200 may have an L-shape.

[0139] The capacitor dielectric layer 250 may extend along the first sidewall 200ss1 of the lower electrode 200. However, the capacitor dielectric layer 250 does not extend along the second sidewall 200ss2 of the lower electrode 200. The capacitor dielectric layer 250 is not disposed between the second sidewall 200ss2 of the lower electrode 200 and the sidewall 170s of the insulating pattern 170. The capacitor dielectric layer 250 extends along the upper surface 170us of the insulating pattern 170.

[0140] Figure 15 This is a schematic layout diagram illustrating a semiconductor device according to some embodiments. Figure 16 It is along Figure 15 The sectional view taken from line II.

[0141] although Figure 15 An example layout diagram of a dynamic random access memory (DRAM) including a capacitor CAP is shown, but this disclosure is not limited thereto. Additionally, Figure 15The fourth direction DR4 can correspond to Figure 1 The first direction DR1.

[0142] Reference Figure 15 A semiconductor device according to some embodiments may include a plurality of active regions ACT. The active regions ACT may be formed on a substrate 100 (see...). Figure 16 Device isolation layer 305 in ) (see Figure 16 )limited.

[0143] As the design specifications of semiconductor devices decrease, as shown, the active region ACT can be configured as a diagonal or slanted strip shape. The active region ACT can have a strip shape extending along the fifth direction DR5.

[0144] On the active region ACT, multiple gate electrodes can be positioned across the active region ACT along a third direction DR3. The multiple gate electrodes can extend parallel to each other. The multiple gate electrodes can be, for example, multiple word lines WL.

[0145] Word lines (WL) can be arranged at equal intervals. The width of the word lines (WL) or the interval between them can be determined according to design rules.

[0146] On the word line WL, multiple bit lines BL can be set, extending along a fourth direction DR4 perpendicular to the word line WL. These multiple bit lines BL can extend parallel to each other.

[0147] Bit lines BL can be arranged at equal intervals. The width of bit lines BL or the interval between bit lines BL can be determined according to design rules.

[0148] A semiconductor device according to some embodiments may include various contact arrangements formed on an active region ACT. These various contact arrangements may include, for example, direct contacts DC, buried contacts BC, a second ground pad LP, etc.

[0149] Here, direct contact DC can refer to the contact that electrically connects the active region ACT to the bit line BL. Buried contact BC can refer to the contact that electrically connects the active region ACT to the capacitor CAP (see...). Figure 16 The lower electrode 200 (see) Figure 16 ) contact components.

[0150] In the arrangement structure, the contact area between the buried contact BC and the active region ACT can be small. Therefore, in order to increase the contact area with the active region ACT and increase the contact area with the lower electrode 200 (see... Figure 16 The contact area of ​​the grounding pad LP can be introduced to conduct electricity.

[0151] The second grounding pad LP can be disposed between the active region ACT and the buried contact BC, or between the buried contact BC and the lower electrode 200 of the capacitor CAP. In a semiconductor device according to some embodiments, the second grounding pad LP can be disposed between the buried contact BC and the lower electrode 200 of the capacitor CAP. By introducing the second grounding pad LP to increase the contact area, the contact resistance between the active region ACT and the lower electrode 200 of the capacitor CAP can be reduced.

[0152] In a semiconductor device according to some embodiments, a direct contact DC may be disposed in the central portion of the active region ACT. Buried contacts BC may be disposed at both (i.e., opposite) ends of the active region ACT.

[0153] Since the buried contact BC is located at both ends of the active area ACT, the second grounding pad LP can be set to be adjacent to both ends of the active area ACT, so as to partially overlap with the buried contact BC.

[0154] In other words, the buried contact BC can be formed as an isolation layer 305 from the device (see Figure 16 ) and the active region ACT overlay between adjacent word lines WL and between adjacent bit lines BL.

[0155] The word line WL can be formed to be embedded in the substrate 100. The word line WL can be set across the active region ACT between the direct contact DC or the embedded contact BC.

[0156] As shown, two word lines WL can be configured to intersect an active region ACT. Because the active region ACT is configured with a slanted shape, the word lines WL can have an angle of less than 90 degrees relative to the active region ACT.

[0157] The direct contact element DC and the buried contact element BC can be arranged symmetrically. Therefore, the direct contact element DC and the buried contact element BC can be arranged in a straight line along the third direction DR3 and the fourth direction DR4.

[0158] On the other hand, unlike the direct contact DC and the buried contact BC, the second grounding pad LP can be arranged in a zigzag pattern on the fourth direction DR4 where the bit line BL extends. Furthermore, the second grounding pad LP can be configured to overlap the same side surface of each bit line BL on the third direction DR3 where the word line WL extends.

[0159] For example, each of the second ground pads LP in the first line can be stacked with the left surface of the corresponding bit line BL, and each of the second ground pads LP in the second line can be stacked with the right surface of the corresponding bit line BL.

[0160] Reference Figure 15and Figure 16 According to some embodiments, a semiconductor device may include gate structures 315_1 and 315_2, a second storage contact 350, and a capacitor CAP.

[0161] Device isolation layer 305 can be formed in substrate 100. Device isolation layer 305 can have a shallow trench isolation (STI) structure with excellent device isolation characteristics. Device isolation layer 305 can define an active region ACT on substrate 100.

[0162] like Figure 15 As shown, the active region ACT defined by the device isolation layer 305 can have an island shape with a short axis and a long axis. The active region ACT can have an inclined shape with an angle of less than 90 degrees relative to the word line WL formed in the device isolation layer 305.

[0163] Furthermore, the active region ACT can have an inclined shape, with an angle of less than 90 degrees relative to the bit line BL formed on the device isolation layer 305. That is, the active region ACT can extend in a fifth direction DR5 with a predetermined angle relative to the third direction DR3 and the fourth direction DR4.

[0164] Gate structures 315_1 and 315_2 may be formed in the substrate 100 and the device isolation layer 305. Gate structures 315_1 and 315_2 may be formed across the device isolation layer 305 and the active region ACT defined by the device isolation layer 305.

[0165] Gate structures 315_1 and 315_2 include gate structure 315_1 in the active region ACT of substrate 100 and gate structure 315_2 in device isolation layer 305.

[0166] Gate structures 315_1 and 315_2 may include a buried gate trench 320t, a gate insulating layer 330, a gate electrode 320, and a gate block pattern 340 formed in the substrate 100 and the device isolation layer 305. The gate electrode 320 may correspond to a word line WL.

[0167] For example, the depth of the buried gate trench 320t formed in the substrate 100 may be different from the depth of the buried gate trench 320t formed in the device isolation layer 305.

[0168] The gate insulating layer 330 may extend along the sidewalls and bottom surface of the buried gate trench 320t. The gate insulating layer 330 may extend along the contour of at least a portion of the buried gate trench 320t.

[0169] The gate insulating layer 330 may include at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide.

[0170] High dielectric constant materials may include, for example, at least one selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0171] The gate electrode 320 may be formed on the gate insulating layer 330. The gate electrode 320 may fill a portion of the buried gate trench 320t.

[0172] The gate electrode 320 may include, for example, materials made from titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum aluminum aluminum aluminum carbonitride (TiAlCN), titanium aluminum aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper ( The gate electrode 320 may be selected from the group consisting of at least one of the following: Cu, cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinumide (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), doped polycrystalline silicon, doped polycrystalline silicon germanium, and combinations thereof. The gate electrode 320 may include conductive metal oxides, conductive metal nitrides, etc., and may include oxide forms of the aforementioned materials.

[0173] A gate block pattern 340 may be formed on the gate electrode 320. The gate block pattern 340 may fill the remaining portion of the buried gate trench 320t in which the gate electrode 320 is formed. The gate block pattern 340 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof.

[0174] The third lower interlayer insulating layer 370 can be disposed on the substrate 100 and the device isolation layer 305. The third lower interlayer insulating layer 370 can cover the gate structures 315_1 and 315_2.

[0175] The second storage contact 350 may be formed in the third lower interlayer insulating layer 370. The second storage contact 350 may be connected to the substrate 100. More specifically, the second storage contact 350 may be electrically connected to a source / drain region formed in the active region ACT of the substrate 100.

[0176] The second storage contact 350 may be disposed on at least one side of the gate structures 315_1 and 315_2. For example, the second storage contact 350 may be disposed on both (i.e., opposite) sides of the gate structures 315_1 and 315_2. The second storage contact 350 may correspond to the buried contact BC.

[0177] Additionally, the second storage contact 350 can correspond to Figures 1 to 14 The first storage contact 115.

[0178] Storage pad 360 may be formed on second storage contact 350. Storage pad 360 may be electrically connected to second storage contact 350. Here, storage pad 360 may correspond to second ground pad LP.

[0179] In addition, the storage pad 360 can correspond to Figures 1 to 14 The first grounding pad is 120.

[0180] A third upper interlayer insulating layer 375 may be formed on a third lower interlayer insulating layer 370. The third upper interlayer insulating layer 375 may surround the storage pad 360. The third upper interlayer insulating layer 375 and the third lower interlayer insulating layer 370 may correspond to... Figures 1 to 13 The first interlayer insulation layer 110.

[0181] The lower electrode etch stop layer 380 can be formed on the third upper interlayer insulating layer 375 and the storage pad 360. The lower electrode etch stop layer 380 can correspond to Figures 1 to 14 Etching stop layer 130.

[0182] Capacitor CAP can be disposed on storage pad 360. Capacitor CAP can be connected to storage pad 360. That is, capacitor CAP can be electrically connected to second storage contact 350.

[0183] The capacitor CAP may include a lower electrode 200, a capacitor dielectric layer 250, an upper electrode 260, and an upper plate electrode 270. The lower support pattern 140 and the upper support pattern 150 may be formed on the lower electrode etch stop layer 380.

[0184] Including the lower electrode 200, capacitor dielectric layer 250, upper electrode 260 and upper plate electrode 270 in capacitor CAP and reference Figures 1 to 14 The descriptions are basically the same.

[0185] Figures 17 to 21 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments.

[0186] Reference Figure 17 The first storage contact 115 and the first grounding pad 120 can be formed in the first interlayer insulation layer 110 on the substrate 100.

[0187] An etch stop layer 130, a lower molding layer 111, a lower support layer 140p, an upper molding layer 112, and an upper support layer 150p can be sequentially formed on the first interlayer insulating layer 110.

[0188] On the first grounding pad 120, the lower electrode 200 can be formed to pass through the etch stop layer 130, the lower molding layer 111, the lower support layer 140p, the upper molding layer 112 and the upper support layer 150p.

[0189] Reference Figure 18 An upper support pattern 150 and a lower support pattern 140 can be formed to connect adjacent lower electrodes 200. Each of the upper support pattern 150 and the lower support pattern 140 can contact a portion of the sidewall of the lower electrode 200.

[0190] The upper support pattern 150 can be formed by removing a portion of the upper support layer 150p. The upper molding layer 112 can be removed from the area where the upper support pattern 150 is not formed.

[0191] Subsequently, the lower support pattern 140 can be formed by removing a portion of the lower support layer 140p. The lower molding layer 111 can be removed from the areas where the lower support pattern 140 is not formed.

[0192] Therefore, spaces can be formed between the upper support pattern 150 and the lower support pattern 140, and between the lower support pattern 140 and the etch stop layer 130.

[0193] Reference Figure 19 A capacitor dielectric layer 250 can be formed on the lower electrode 200.

[0194] The capacitor dielectric layer 250 can be formed along the top and side surfaces of the lower electrode 200, the bottom and top surfaces of the lower support pattern 140, the bottom and top surfaces of the upper support pattern 150, and the top surface of the etch stop layer 130. The capacitor dielectric layer 250 can be formed along the contours of the lower electrode 200, the upper support pattern 150, the lower support pattern 140, and the etch stop layer 130.

[0195] An upper electrode 260 can be formed on the capacitor dielectric layer 250. The upper electrode 260 can be formed along the contour of the capacitor dielectric layer 250.

[0196] Reference Figure 20 An interface layer 220 can be formed on the upper electrode 260 by a surface treatment process 50. The interface layer 220 can be formed along the contour of the upper electrode 260.

[0197] Interface layer 220 may include fluorine (F). For example, surface treatment process 50 may be performed using a first precursor containing a semiconductor element (e.g., silicon or germanium) and a second precursor containing fluorine (F). The second precursor may include, but is not limited to, nitrogen trifluoride (NF3).

[0198] As an example, interface layer 220 may be a semiconductor material layer doped with fluorine (F). As another example, interface layer 220 may be the fluorine (F) treated interface portion of the upper electrode 260.

[0199] Reference Figure 21 After the interface layer 220 is formed, the upper plate electrode 270 can be formed on the upper electrode 260.

[0200] The interface layer 220 can be included in the upper plate electrode 270. As a result, a fluorine (F) doped upper plate electrode 270 can be formed.

[0201] Unlike the above description, an interface layer including fluorine (F) may be further formed on the exposed lower electrode 200 before the capacitor dielectric layer 250 is formed.

[0202] Unlike the above description, interface layer 220 can be Figure 7 The first plate electrode layer 271.

[0203] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various modifications in form and detail may be made therein without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Grounding pad, located on the base; The lower electrode is located on the grounding pad and is electrically connected to the grounding pad. A dielectric layer is located on the lower electrode and extends along the contour of the lower electrode. The upper electrode is located on the dielectric layer; and Upper plate electrode, located on the upper electrode. The upper plate electrode includes the interface facing the upper electrode. The upper electrode, specifically the portion near the interface, contains the first fluorine ion. The concentration of the first fluorine in the portion of the upper electrode decreases as the distance from the interface of the upper electrode increases.

2. The semiconductor device according to claim 1, wherein, The upper electrode includes the first fluorine.

3. The semiconductor device according to claim 2, in, The upper electrode includes a first surface facing the dielectric layer and a second surface facing the upper plate electrode, and The concentration of the first fluorine in the upper electrode decreases from the second surface of the upper electrode to the first surface of the upper electrode.

4. The semiconductor device according to claim 1, wherein, The upper electrode includes a compound semiconductor material layer.

5. The semiconductor device according to claim 1, in, The upper electrode includes a first plate electrode layer located on the upper electrode and a second plate electrode layer located on the first plate electrode layer, and The first electrode layer includes an elemental semiconductor material layer, and the second electrode layer includes a compound semiconductor material layer.

6. The semiconductor device according to claim 1, wherein, A portion of the dielectric layer includes the first fluorine.

7. The semiconductor device according to claim 1, in, The lower electrode includes a second fluorine, and The concentration of the second fluorine in the lower electrode is highest at the interface between the lower electrode and the dielectric layer.

8. The semiconductor device according to claim 1, wherein, The lower electrode has a rectangular or cylindrical shape that extends along the thickness direction of the substrate.

9. The semiconductor device according to claim 1, wherein, The lower electrode includes a bottom extending along the top surface of the grounding pad and a sidewall portion protruding from the end of the bottom.

10. A semiconductor device, the semiconductor device comprising: Grounding pad, located on the base; The lower electrode is located on the grounding pad and is electrically connected to the grounding pad. A dielectric layer is located on the lower electrode and extends along the contour of the lower electrode. The upper electrode is located on the dielectric layer; and The upper electrode includes an upper plate region and a lower plate region located on the upper electrode. The lower plate region is located between the upper electrode and the upper plate region, and The lower plate area includes fluorine, while the upper plate area does not.

11. The semiconductor device according to claim 10, in, The upper plate electrode includes the interface facing the upper electrode, and The concentration of fluorine in the lower plate region decreases as the distance from the interface of the upper plate electrode increases.

12. The semiconductor device according to claim 10, in, The upper electrode contains fluorine, and The upper electrode, lower electrode, dielectric layer, and upper plate electrode are included in the capacitor of the semiconductor device.

13. The semiconductor device according to claim 10, wherein, The upper electrode includes a compound semiconductor material layer.

14. The semiconductor device according to claim 10, in, The upper electrode includes a first plate electrode layer located on the upper electrode and a second plate electrode layer located on the first plate electrode layer. The first electrode layer comprises an elemental semiconductor material layer, and the second electrode layer comprises a compound semiconductor material layer. The first plate electrode layer is included in the lower plate region.

15. The semiconductor device of claim 10, further comprising: The passivation layer is located between the dielectric layer and the top electrode.

16. A semiconductor device, the semiconductor device comprising: Trench, located in the substrate; The gate electrode is located in the trench; An embedded contact is located on at least one side of the gate electrode and electrically connected to the substrate; Grounding pad, located on the buried contact component; as well as The capacitor is electrically connected to the grounding pad. The capacitor includes a lower electrode electrically connected to a grounding pad, a dielectric layer on the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode. Among them, only the portion of the upper plate electrode closest to the upper electrode contains fluorine, and The concentration of fluorine in the portion of the upper electrode decreases as the distance from the upper electrode increases.

17. The semiconductor device according to claim 16, wherein, The upper electrode contains fluorine.

18. The semiconductor device according to claim 16, wherein, The upper electrode includes a silicon-germanium layer.

19. The semiconductor device according to claim 18, wherein, The upper electrode also includes a silicon layer placed between the silicon-germanium layer and the upper electrode.

20. The semiconductor device of claim 16, wherein, The upper plate electrode includes a lower plate region containing fluorine and an upper plate region not containing fluorine.

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