Memory device

Abstract

The present invention discloses a memory device, including a channel element, a storage element, and an electrode element. The channel element includes a first channel portion, a second channel portion, and an intermediate channel portion. The intermediate channel portion is between the first channel portion and the second channel portion. The first channel portion has opposite first sidewall channel surfaces and second sidewall channel surfaces. The intermediate channel portion has opposite third sidewall channel surfaces and fourth sidewall channel surfaces. The first sidewall channel surface and the second sidewall channel surface of the first channel portion are respectively outside the third sidewall channel surface and the fourth sidewall channel surface of the intermediate channel portion. A memory cell is defined in the storage element between the channel element and the electrode element.

Description

Technical Field

[0001] The present invention relates to a memory device. Background Art

[0002] As the critical dimensions of components in integrated circuits are gradually reduced to the limit perceivable by the process technology, designers have begun to search for technologies that can achieve greater memory density, thereby achieving a lower cost per bit. Summary of the Invention

[0003] The present invention relates to a memory device.

[0004] According to one aspect of the present invention, a memory device is provided. The memory device includes a channel element, a storage element, and an electrode element. The channel element includes a first channel portion, a second channel portion, and an intermediate channel portion. The intermediate channel portion is between the first channel portion and the second channel portion. The first channel portion has opposite first and second sidewall channel surfaces. The intermediate channel portion has opposite third and fourth sidewall channel surfaces. The first and second sidewall channel surfaces of the first channel portion are respectively outside the third and fourth sidewall channel surfaces of the intermediate channel portion. A memory cell is defined in the storage element between the channel element and the electrode element.

[0005] According to another aspect of the present invention, a memory device is provided. The memory device includes a channel element, a storage element, and an electrode element. The storage element includes a first storage portion, a second storage portion, and an intermediate storage portion. The intermediate storage portion is between the first storage portion and the second storage portion. The first storage portion has opposite first and second outer sidewall storage surfaces. The intermediate storage portion has opposite third and fourth outer sidewall storage surfaces. The first and second outer sidewall storage surfaces of the first storage portion are respectively outside the third and fourth outer sidewall storage surfaces of the intermediate storage portion. A memory cell is defined in the storage element between the channel element and the electrode element.

[0006] According to still another aspect of the present invention, a memory device is provided. The memory device includes an insulating element, a channel element, a storage element, and an electrode element. The insulating element has a straight stripe shape. The channel element surrounds the sidewall surface of the insulating element. A memory cell is defined in the storage element between the channel element and the electrode element.

[0007] In order to have a better understanding of the above and other aspects of the present invention, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows: Brief Description of the Drawings

[0008] Figure 1 A cross-sectional view of a memory device according to an embodiment.

[0009] Figure 2 Cross-sectional view of a memory device according to another embodiment.

[0010] Figure 3 Cross-sectional view of a memory device according to another embodiment.

[0011] Figure 4 Cross-sectional view of a memory device according to another embodiment.

[0012] Figures 5A to 17B Illustrates a method of manufacturing a memory device according to an embodiment.

[0013] Figure 18 Cross-sectional view of a memory device according to an embodiment.

[0014] Figure 19A Cross-sectional view of a memory device according to an embodiment.

[0015] Figure 19B Cross-sectional view of a memory device according to an embodiment.

[0016]

Reference Signs

[0017] 100: Channel element

[0018] 110: First channel portion

[0019] 112: First sidewall channel surface

[0020] 114: Second sidewall channel surface

[0021] 120: Second channel portion

[0022] 122: Fifth sidewall channel surface

[0023] 124: Sixth sidewall channel surface

[0024] 130: Intermediate channel portion

[0025] 132: Third sidewall channel surface

[0026] 134: Fourth sidewall channel surface

[0027] 200: Memory element

[0028] 210: First memory portion

[0029] 212: First outer sidewall memory surface

[0030] 214: Second outer sidewall memory surface

[0031] 220: Second memory portion

[0032] 222: Fifth outer wall storage surface

[0033] 224: Sixth outer wall storage surface

[0034] 230: Intermediate storage section

[0035] 232: Third outer wall storage surface

[0036] 234: Fourth outer wall storage surface

[0037] 300: Electrode element

[0038] 400: Insulating element

[0039] 500: Columnar element

[0040] 650: Substrate

[0041] 651: Stacked structure

[0042] 652: Material layer

[0043] 654: Insulating layer

[0044] 656: Hole

[0045] 658: Material column

[0046] 660: Mask layer

[0047] 661: Opening

[0048] 663, 671: Channel

[0049] 665, 665A: Opening

[0050] 669, 675, 681: Hole

[0051] 673: Slit

[0052] 674: Insulating film

[0053] 676: Material element

[0054] 678: First conductive via

[0055] 680: Second conductive via

[0056] D1: First direction

[0057] D2: Second direction

[0058] D3: Third direction

[0059] K1, K1A, K2, K2A: Dimension

[0060] M1: First metal layer

[0061] M2: The second metal layer Detailed implementation manners

[0062] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0063] The following uses some embodiments for illustration. It should be noted that the present invention does not show all possible embodiments, and other embodiments not presented in the present invention may also be applicable. In addition, the dimensional ratios in the drawings are not drawn in proportion to the actual products. Therefore, the description in the specification and the drawings is only for describing the embodiments and not for limiting the protection scope of the present invention. In addition, the descriptions in the embodiments, such as partial structures, process steps, and material applications, etc., are only for illustrative purposes and not for limiting the scope of protection of the present invention. The details of the steps and structures in the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present invention. The following uses the same / similar symbols to represent the same / similar elements for illustration.

[0064] Please refer to Figure 1 , which is a cross-sectional view of a memory device of an embodiment. The memory device includes a channel element 100, a storage element 200, and an electrode element 300.

[0065] The channel element 100 may have a shape configuration that extends in a first direction D1 and has opposite end portions that each extend in a second direction D2 beyond opposite side surfaces of the intermediate portion. The first direction D1 is different from the second direction D2. In one embodiment, the first direction D1 is substantially perpendicular to the second direction D2. For example, the first direction D1 is the Y direction, and the second direction D2 is the X direction.

[0066] Specifically, the channel element 100 may include a first channel portion 110, a second channel portion 120, and an intermediate channel portion 130. The intermediate channel portion 130 may be located between the first channel portion 110 and the second channel portion 120. The sidewall surface of the first channel portion 110 includes opposite first sidewall channel surfaces 112 and second sidewall channel surfaces 114. The intermediate channel portion 130 has opposite third sidewall channel surfaces 132 and fourth sidewall channel surfaces 134. The sidewall surface of the second channel portion 120 includes opposite fifth sidewall channel surfaces 122 and sixth sidewall channel surfaces 124. The first sidewall channel surface 112, the third sidewall channel surface 132, and the fifth sidewall channel surface 122 are on the same side of the channel element 100. The second sidewall channel surface 114, the fourth sidewall channel surface 134, and the sixth sidewall channel surface 124 are on the same opposite side of the channel element 100. The third sidewall channel surface 132 may be located between the first sidewall channel surface 112 and the fifth sidewall channel surface 122. The fourth sidewall channel surface 134 may be located between the second sidewall channel surface 114 and the sixth sidewall channel surface 124. The first sidewall channel surface 112 and the second sidewall channel surface 114 of the first channel portion 110 are respectively on the outer sides of the third sidewall channel surface 132 and the fourth sidewall channel surface 134 of the intermediate channel portion 130 in the second direction D2. The fifth sidewall channel surface 122 and the sixth sidewall channel surface 124 of the second channel portion 120 are respectively on the outer sides of the third sidewall channel surface 132 and the fourth sidewall channel surface 134 of the intermediate channel portion 130 in the second direction D2.

[0067] The intermediate channel portion 130 may have a straight stripe shape extending in the first direction D1. The third sidewall channel surface 132 and the fourth sidewall channel surface 134 of the intermediate channel portion 130 may have a flat shape extending in the first direction D1. The first channel portion 110 may have a bow shape, and its sidewall surface has an open-loop shape, wherein the first sidewall channel surface 112 and the second sidewall channel surface 114 of the sidewall surface have opposite open-loop shapes. The second channel portion 120 may have a bow shape, and its sidewall surface has an open-loop shape, wherein the fifth sidewall channel surface 122 and the sixth sidewall channel surface 124 of the sidewall surface have opposite open-loop shapes.

[0068] In one embodiment, the channel element 100 may have, for example, Figure 1The solid dumbbell-shaped configuration shown. Specifically, the first channel portion 110 may have a superior bow shape, and its sidewall surface has a superior arc shape greater than 180 degrees, wherein the first sidewall channel surface 112 and the second sidewall channel surface 114 of the sidewall surface have an inferior arc shape less than 180 degrees, and the bending directions are opposite to each other. The second channel portion 120 may have a superior bow shape, and its sidewall surface has a superior arc shape greater than 180 degrees, wherein the fifth sidewall channel surface 122 and the sixth sidewall channel surface 124 of the sidewall surface have an inferior arc shape less than 180 degrees, and the bending directions are opposite to each other. The flat third sidewall channel surface 132 of the intermediate channel portion 130 may be adjacent between the first sidewall channel surface 112 and the fifth sidewall channel surface 122. The flat fourth sidewall channel surface 134 of the intermediate channel portion 130 may be adjacent between the second sidewall channel surface 114 and the sixth sidewall channel surface 124. The first channel portion 110 and the second channel portion 120 may be symmetrically arranged with the intermediate channel portion 130 as the center.

[0069] The storage element 200 can be wound around the sidewall surface of the channel element 100 and can have a closed-loop shape. The inner sidewall surface of the storage element 200 can be adjacent to the channel element 100. The storage element 200 includes a first storage portion 210, a second storage portion 220, and an intermediate storage portion 230. The intermediate storage portion 230 is located between the first storage portion 210 and the second storage portion 220. The outer sidewall surface of the first storage portion 210 includes opposite first outer sidewall storage surfaces 212 and second outer sidewall storage surfaces 214. The outer sidewall surface of the intermediate storage portion 230 includes opposite third outer sidewall storage surfaces 232 and fourth outer sidewall storage surfaces 234. The outer sidewall surface of the second storage portion 220 includes opposite fifth outer sidewall storage surfaces 222 and sixth outer sidewall storage surfaces 224. The first outer sidewall storage surface 212, the third outer sidewall storage surface 232, and the fifth outer sidewall storage surface 222 of the outer sidewall surface of the storage element 200 are on the same side of the storage element 200. The second outer sidewall storage surface 214, the fourth outer sidewall storage surface 234, and the sixth outer sidewall storage surface 224 of the outer sidewall surface of the storage element 200 are on the same other side of the storage element 200. The third outer sidewall storage surface 232 can be located between the first outer sidewall storage surface 212 and the fifth outer sidewall storage surface 222. The fourth outer sidewall storage surface 234 can be located between the second outer sidewall storage surface 214 and the sixth outer sidewall storage surface 224. The first outer sidewall storage surface 212 and the second outer sidewall storage surface 214 of the first storage portion 210 are respectively on the outer sides of the third outer sidewall storage surface 232 and the fourth outer sidewall storage surface 234 of the intermediate storage portion 230 in the second direction D2. The fifth outer sidewall storage surface 222 and the sixth outer sidewall storage surface 224 of the second storage portion 220 are respectively on the outer sides of the third outer sidewall storage surface 232 and the fourth outer sidewall storage surface 234 of the intermediate storage portion 230 in the second direction D2.

[0070] The intermediate storage portion 230 can have a straight stripe shape extending in the first direction D1. The intermediate storage portion 230, the third outer sidewall storage surface 232, the fourth outer sidewall storage surface 234, and the inner sidewall storage surface can have a flat shape extending in the first direction D1. The first storage portion 210 can have an open-loop shape, and its sidewall surface (including the first outer sidewall storage surface 212, the second outer sidewall storage surface 214, and the inner sidewall storage surface) also has an open-loop shape. The second storage portion 220 can have an open-loop shape, and its sidewall surface (including the fifth outer sidewall storage surface 222, the sixth outer sidewall storage surface 224, and the inner sidewall storage surface) also has an open-loop shape.

[0071] In one embodiment, the storage element 200 can have as Figure 1The closed-loop shape of the dumbbell contour shown, or the hollow dumbbell shape configuration. Specifically, the first storage portion 210 and the second storage portion 220 may have a major arc shape, and the bending directions are opposite to each other. The two parallel straight stripes of the middle storage portion 230 may be adjacent between the first storage portion 210 and the second storage portion 220. The first storage portion 210 and the second storage portion 220 may be symmetrically arranged with the middle storage portion 230 as the center. The storage element 200 may have a uniform thickness. The electrode element 300 may surround the outer wall surface of the storage element 200.

[0072] In an embodiment, the storage unit is defined in the storage element 200 between the channel element 100 and the electrode element 300. The first channel portion 110 may be electrically connected to one of a source electrode and a drain electrode, and the second channel portion 120 may be electrically connected to the other of the source electrode and the drain electrode. Alternatively, the first channel portion 110 may serve as one of a channel source and a channel drain, and the second channel portion 120 may serve as the other of the channel source and the channel drain. The electrode element 300 may be used as a word line.

[0073] As Figure 1 shown, the channel element 100 and the storage element 200 may integrally have a solid dumbbell shape. This memory component according to the embodiment can have a smaller cell size, and thus can improve the storage cell array density of the memory device. The first channel portion 110 and the second channel portion 120 have a larger area / size than the middle channel portion 130, and thus can improve the process alignment with the upper conductive element (such as Figure 17A and Figure 17B the first conductive via 678 shown) and have a good electrical connection relationship, with a large process window and an improved product qualification rate.

[0074] Please refer to Figure 2 , which is a cross-sectional view of a memory device of another embodiment. Figure 2 And Figure 1 the difference is that the memory device further includes an insulating element 400. The middle channel portion 130 of the channel element 100 is separated into two middle channel portions 130 by the insulating element 400. The insulating element 400 may have a straight stripe shape extending in the first direction D1. The channel element 100 surrounds the side wall surface of the insulating element 400. In this embodiment, the third side wall channel surface 132 and the fourth side wall channel surface 134 of the middle channel portion 130 may be outer side wall channel surfaces. The middle channel portion 130 may have an inner side wall channel surface adjacent to the insulating element 400.

[0075] As Figure 2As shown, the insulating element 400 and the channel element 100 may integrally have a solid dumbbell shape. The insulating element 400, the channel element 100, and the storage element 200 may integrally have a solid dumbbell shape. This memory component according to an embodiment can have a smaller cell size, and thus can improve the storage cell array density of the memory device. The first channel portion 110 and the second channel portion 120 have a larger area / size than the intermediate channel portion 130, and thus can improve the process alignment of the upper conductive element (such as Figure 17A and Figure 17B the first conductive via 678 shown) and have a good electrical connection relationship, with a large process operation window and an improved product qualification rate.

[0076] Please refer to Figure 3 , which is a cross-sectional view of a memory device according to yet another embodiment. Figure 3 and Figure 2 The difference is that the memory device further includes a columnar element 500. The first channel portion 110 and the second channel portion 120 of the channel element 100 may have an annular shape, and the inner wall channel surface thereof has a closed annular shape and surrounds the side wall surface of the columnar element 500. In an embodiment, the conductivity of the columnar element 500 is greater than or substantially equal to the conductivity of the channel element 100. In an embodiment, the columnar element 500 may include the same or different channel materials as the channel element 100 (such as undoped or doped N-type / P-type polysilicon and other semiconductor materials), and the columnar element 500 can be regarded as a part of the channel element 100. In another embodiment, the columnar element 500 may include electrode materials (such as metals or heavily doped N-type / P-type polysilicon and other semiconductor materials), wherein the columnar element 500 on the side of the first channel portion 110 can be used as one of the source or the drain, and the columnar element 500 on the side of the second channel portion 120 can be used as the other of the source or the drain.

[0077] As Figure 3 shown, the insulating element 400, the channel element 100, and the columnar element 500 may integrally have a solid dumbbell shape. The insulating element 400, the channel element 100, the storage element 200, and the columnar element 500 may integrally have a solid dumbbell shape. This memory component according to an embodiment can have a smaller cell size, and thus can improve the storage cell array density of the memory device. The first channel portion 110 and the columnar element 500 as a whole, and the second channel portion 120 and the columnar element 500 as a whole, have a larger area / size than the intermediate channel portion 130, and thus can improve the process alignment of the upper conductive element (such as Figure 17A and Figure 17B the first conductive via 678 shown) and have a good electrical connection relationship, with a large process operation window and an improved product qualification rate.

[0078] Please refer to Figure 4, which is a cross-sectional view of a memory device of yet another embodiment. Figure 4 and Figure 1 The difference is that the memory device further includes a columnar element 500.

[0079] As Figure 4 shown, the channel element 100 and the columnar element 500 may integrally have a solid dumbbell shape. The channel element 100, the storage element 200, and the columnar element 500 may integrally have a solid dumbbell shape. This memory component according to the embodiment can have a smaller cell size, and thus can improve the storage cell array density of the memory device. The first channel portion 110 and the columnar element 500 are integral, and the second channel portion 120 and the columnar element 500 are integral, and have a larger area / size than the middle channel portion 130, so that the process alignment of the upper conductive element (such as Figure 17A and Figure 17B the first conductive via 678 shown) can be improved and a good electrical connection relationship can be achieved. The process operation window is large, and the product qualification rate is increased.

[0080] Figures 5A to 17B Illustrates a manufacturing method of a memory device according to an embodiment.

[0081] Please refer to Figure 5A and Figure 5B . Figure 5A is a longitudinal cross-sectional view of the memory device, which may be drawn along the Figure 5B IJ cross-sectional line shown. Figure 5B is a top view of the memory device. A stacked structure 651 is formed on the substrate 650. The stacked structure 651 includes alternately stacked material layers 652 and insulating layers 654. The material of the material layer 652 is different from the material of the insulating layer 654. In one embodiment, the material layer 652 includes a nitride such as silicon nitride. The insulating layer 654 includes an oxide such as silicon oxide. However, the present invention is not limited thereto, and other suitable insulating materials may be used for the insulating layer 654, and other suitable materials such as dielectric materials or conductive materials may be used for the material layer 652. Holes 656 may be formed in the stacked structure 651 by using yellow light lithography etching technology, and then material columns 658 are formed to fill the holes 656. In one embodiment, the material column 658 may include an oxide. For example, the material column 658 may include silicon oxide formed by a low-temperature oxidation process. However, the present invention is not limited thereto, and other suitable materials may also be used for the material column 658, such as organic dielectric materials, etc.

[0082] Please refer to Figure 6A and Figure 6B . Figure 6A is a longitudinal cross-sectional view of the memory device, which may be drawn along the Figure 6B IJ cross-sectional line shown. Figure 6BIt is a top view of a memory device. A mask layer 660 can be formed on the stacked structure 651. The mask layer 660 can have an opening 661 exposing a part of the material pillar 658 and the part of the stacked structure 651 located between the material pillars 658. The mask layer 660 can include a photoresist formed by a yellow light lithography process. Then, the part of the material pillar 658 and the stacked structure 651 exposed by the opening 661 of the mask layer 660 can be removed by an etching process to form a channel 663 as shown in Figure 7A and Figure 7B . Figure 7A It is a longitudinal cross-sectional view of a memory device, which can be drawn along the Figure 7B IJ section line shown in Figure 7B It is a top view of a memory device. Then, the mask layer 660 ( Figure 6A and Figure 6B ) can be removed. The material pillar 658 is removed to form an opening 665 as shown in Figure 8A and Figure 8B . The opening 665 in the stacked structure 651 can have a dumbbell shape. Figure 8A It is a longitudinal cross-sectional view of a memory device, which can be drawn along the Figure 8B IJ section line shown in Figure 8B It is a top view of a memory device.

[0083] Please refer to Figure 9A and Figure 9B . Figure 9A It is a longitudinal cross-sectional view of a memory device, which can be drawn along the Figure 9B IJ section line shown in Figure 9B It is a transverse cross-sectional view of a memory device, which can be drawn along the Figure 9A PQ section line shown in 2 O 3 ), hafnium oxide (HfO 2 ), etc. The channel element 100 can be formed on the sidewall surface of the memory element 200 exposed by the opening 665. In one embodiment, as shown in Figure 9A and Figure 9BThe method for forming the channel element 100 shown may include forming channel material on all surfaces exposed by the storage element 200, and then the portion of the channel material located at the bottom of the opening 665 and the portion on the upper surface of the stacked structure 651 may be removed by anisotropic etching or back etching. The portion of the channel material remaining on the sidewall surfaces of the storage element 200 after etching forms the channel element 100. In one embodiment, the channel material includes polysilicon formed by deposition methods such as chemical vapor deposition or physical vapor deposition, but the present invention is not limited thereto.

[0084] Please refer to Figure 10A and Figure 10B . Figure 10A is a longitudinal cross-sectional view of the memory device, which may be drawn along the Figure 10B IJ cross-sectional line shown. Figure 10B is a transverse cross-sectional view of the memory device, which may be drawn along the Figure 10A PQ cross-sectional line shown. The insulating element 400 is formed on the sidewall surfaces of the channel element 100 exposed by the opening 665 and the upper surface of the storage element 200, and on the storage element 200 on the upper surface of the stacked structure 651. The insulating element 400 may include an oxide such as silicon oxide formed by a suitable deposition method such as chemical vapor deposition or physical vapor deposition, but the present invention is not limited thereto. In one embodiment, the deposition thickness of the insulating element 400 is at least carried out until the middle part of the opening 665 is completely filled with the insulating element 400, and the two opposite end portions of the opening 665 may be partially filled with the insulating element 400 leaving holes 669. An isotropic etching method, for example, may be used to etch the surface of the insulating element 400 exposed from the holes 669 until the inner wall channel surfaces of the first channel portion 110 and the second channel portion 120 of the channel element 100 are exposed, and holes 675 as shown in Figure 11A and Figure 11B are formed. This etching step may leave the insulating element 400 in the middle part of the opening 665. Figure 11A is a longitudinal cross-sectional view of the memory device, which may be drawn along the Figure 11B IJ cross-sectional line shown. Figure 11B is a transverse cross-sectional view of the memory device, which may be drawn along the Figure 11A PQ cross-sectional line shown.

[0085] Please refer to Figure 12A and Figure 12B . Figure 12A is a longitudinal cross-sectional view of the memory device, which may be drawn along the Figure 12B IJ cross-sectional line shown. Figure 12B is a transverse cross-sectional view of the memory device, which may be drawn along the Figure 12AThe PQ cross-section line shown is drawn. The columnar element 500 can be filled in the hole 675. In one embodiment, the columnar element 500 can include a conductor material or a semiconductor material such as polysilicon and the like. Then, an etch-back step can be performed to remove the material on the upper surface of the stacked structure 651.

[0086] Please refer to Figure 13A and Figure 13B . Figure 13A is a longitudinal cross-sectional view of the memory device, which can be drawn along the Figure 13B IJ cross-section line shown. Figure 13B is a transverse cross-sectional view of the memory device, which can be drawn along the Figure 13A PQ cross-section line shown. The channel 671 can be formed in the stacked structure 651 by using a yellow light lithography etching process. The channel 671 can expose the side surfaces of the insulating layer 654 and the material layer 652 of the stacked structure 651 and the upper surface of the substrate 650. The material layer 652 (which can be used as a sacrificial layer) exposed by the channel 671 can be removed by using an etching step to form the slits 673 as shown in Figure 14A and Figure 14B .

[0087] Please refer to Figure 14A and Figure 14B . Figure 14A is a longitudinal cross-sectional view of the memory device, which can be drawn along the Figure 14B IJ cross-section line shown. Figure 14B is a transverse cross-sectional view of the memory device, which can be drawn along the Figure 14A PQ cross-section line shown. The slit 673 can expose the outer sidewall surface of the storage element 200, the upper surface / lower surface of the insulating layer 654, and the upper surface of the substrate 650.

[0088] Please refer to Figure 15A and Figure 15B . Figure 15A is a longitudinal cross-sectional view of the memory device, which can be drawn along the Figure 15B IJ cross-section line shown. Figure 15B is a transverse cross-sectional view of the memory device, which can be drawn along the Figure 15A PQ cross-section line shown. The electrode element 300 can be formed in the slit 673. The electrode element 300 can include a metal layer such as tungsten (W) and so on. The electrode element 300 can also include a barrier layer having conductive properties formed on the metal layer. The barrier layer can include, for example, tantalum nitride (TaN), titanium nitride (TiN) and so on. In one embodiment, the electrode element 300 can be formed on the dielectric film after the dielectric film is formed. The dielectric film can include a high dielectric constant (high K) material such as aluminum oxide (Al 2 O 3 ), hafnium dioxide (HfO2 ) and other suitable dielectric materials. The electrode elements 300 are arranged separately from each other in the third direction D3 through the insulating layer 654 on the sidewall surfaces of the storage elements 200. The third direction D3 is different from the first direction D1 and the second direction D2. In one embodiment, the third direction D3 may be substantially perpendicular to the first direction D1 and the second direction D2. The third direction D3 may be the Z direction, for example, the direction perpendicular to the upper surface of the substrate 650.

[0089] In one embodiment, the material of the columnar element 500 may be the same as that of the channel element 100, and the structure constituting the memory cell may be similar Figure 2 to the structure shown, that is, the columnar element 500 may act as a component constituting the channel element 100. In another embodiment, the material of the columnar element 500 may be different from that of the channel element 100, and the structure constituting the memory cell may be similar Figure 3 to the structure shown.

[0090] In the embodiment, the electrode element 300 is a gate electrode element and serves as a word line. The memory cell is defined in the storage element 200 between the channel element 100 and the electrode element 300. The memory cells in different layers in the third direction D3 are electrically connected in parallel between the first channel portion 110 and the second channel portion 120 of the channel element 100. The memory device may include an AND type memory device. The manufacturing method according to the embodiment can form the memory device in a self-aligned manner, with a simple method and reduced cost.

[0091] Please refer to Figure 16A and Figure 16B . Figure 16A is a longitudinal sectional view of the memory device, which may be drawn along the Figure 16B IJ sectional line shown. Figure 16B is a transverse sectional view of the memory device, which may be drawn along the Figure 16A PQ sectional line shown. An insulating film 674 can be formed in the channel 671. The insulating film 674 may include an oxide such as silicon oxide, or a nitride such as silicon nitride, or other suitable insulating materials. The insulating film 674 can be formed by a suitable method such as physical vapor deposition or chemical vapor deposition. A material element 676 can be formed on the insulating film 674 and fill the channel 671. In one embodiment, the material element 676 is a conductive element, which can be electrically insulated from the electrode element 300 in the stacked structure through the insulating film 674. In this example, a bias voltage can be applied to the material element 676 to inject current for joule heating of the memory cell, which can thereby improve the performance of the memory cell such as endurance and data retention. In another embodiment, the material element 676 is an insulating material, for example, including an oxide such as silicon oxide, etc., and can be used as a bypass element together with the insulating film 674.

[0092] Please refer to Figure 17A and Figure 17B . Figure 17A is a longitudinal cross-sectional view of a memory device, which may be drawn along the Figure 17B IJ cross-sectional line shown. Figure 17B is a top view of a memory device. A first conductive via 678 may be formed on a columnar element 500. A first metal layer M1 may be formed on the first conductive via 678. A second conductive via 680 may be formed on the first metal layer M1. A second metal layer M2 may be formed on the second conductive via 680. In one embodiment, the first channel portion 110 is electrically connected to the source, and the second channel portion 120 is electrically connected to the drain.

[0093] In another embodiment, a structure as shown in Figures 5A to 8B may be formed using a similar Figure 18 step flow concept. Figure 18 The difference between the structure and Figure 8B the structure is that in this embodiment, the middle portion of the opening 665A formed in the stacked structure 651 has a smaller dimension K1A (e.g., width) in the second direction D2. For example, Figure 18 the ratio of dimension K1A to dimension K2A (i.e., K1A / K2A) in Figure 8B is less than the ratio of dimension K1 to dimension K2 (i.e., K1 / K2) of the opening 665 in

[0094] In one embodiment, after forming the memory element 200 and the channel element 100 in the opening 665A as shown in Figure 18 , a structure as shown in Figure 19A and Figure 19B may be formed. Figure 19A is a longitudinal cross-sectional view of a memory device, which may be drawn along the Figure 19B IJ cross-sectional line shown. Figure 19B is a transverse cross-sectional view of a memory device, which may be drawn along the Figure 19A PQ cross-sectional line shown. Figure 19A and Figure 19B The embodiment of Figure 9A and Figure 9B differs from the embodiment shown in Figures 10A to 12B in that the middle portion of the opening 665A is completely filled with the memory element 200 and the channel element 100, so the steps related to forming the insulating element 400 may be omitted. In one embodiment, Figure 19A and Figure 19B the structure of Figures 13A to 17BThe manufacturing steps described above, in this example, the structure of the memory cell can be as shown in Figure 1 as follows.

[0095] In another embodiment, the channel element 100 can be formed by a suitable deposition method such as chemical vapor deposition or physical vapor deposition, completely filling the middle part of the opening 665A and partially filling the two opposite end parts of the opening 665A leaving holes (such as Figure 4 the hole 681 in), then, the holes can be filled with the columnar element 500. Then, the manufacturing steps as described in Figures 13A to 17B can be continued. In this example, the structure of the memory cell can be as shown in Figure 4 as follows.

[0096] According to the above disclosure, the memory device of the embodiment can have an improved memory cell array density.

[0097] The specific embodiments described above further elaborate on the object, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.

Claims

1. A memory device, comprising: a channel element including a first channel portion, a second channel portion, and an intermediate channel portion, the intermediate channel portion being between the first channel portion and the second channel portion, the first channel portion having a first sidewall channel surface and a second sidewall channel surface opposite to each other, the intermediate channel portion having a third sidewall channel surface and a fourth sidewall channel surface opposite to each other, the first sidewall channel surface and the second sidewall channel surface of the first channel portion being respectively outside the third sidewall channel surface and the fourth sidewall channel surface of the intermediate channel portion, the first channel portion being electrically connected to one of a source electrode and a drain electrode, and the second channel portion being electrically connected to the other of the source electrode and the drain electrode; a memory element; and an electrode element, wherein a memory cell is defined in the memory element between the channel element and the electrode element.

2. The memory device according to claim 1, further comprising a columnar element, the first channel portion of the channel element surrounding a sidewall surface of the columnar element, the columnar element including channel material or electrode material.

3. The memory device according to claim 1, wherein the second channel portion has a fifth sidewall channel surface and a sixth sidewall channel surface opposite to each other, the fifth sidewall channel surface and the sixth sidewall channel surface of the second channel portion being respectively outside the third sidewall channel surface and the fourth sidewall channel surface of the intermediate channel portion.

4. The memory device according to claim 1, wherein the channel element has a dumbbell-shaped configuration.

5. A memory device, comprising: a channel element including a first channel portion, a second channel portion, and an intermediate channel portion, the intermediate channel portion being between the first channel portion and the second channel portion, the first channel portion having a first sidewall channel surface and a second sidewall channel surface opposite to each other, the intermediate channel portion having a third sidewall channel surface and a fourth sidewall channel surface opposite to each other, the first sidewall channel surface and the second sidewall channel surface of the first channel portion being respectively outside the third sidewall channel surface and the fourth sidewall channel surface of the intermediate channel portion, the first channel portion being electrically connected to one of a source electrode and a drain electrode, and the second channel portion being electrically connected to the other of the source electrode and the drain electrode; a memory element including a first memory portion, a second memory portion, and an intermediate memory portion, the intermediate memory portion being between the first memory portion and the second memory portion, the first memory portion having a first outer sidewall memory surface and a second outer sidewall memory surface opposite to each other, the intermediate memory portion having a third outer sidewall memory surface and a fourth outer sidewall memory surface opposite to each other, the first outer sidewall memory surface and the second outer sidewall memory surface of the first memory portion being respectively outside the third outer sidewall memory surface and the fourth outer sidewall memory surface of the intermediate memory portion; and an electrode element, wherein a memory cell is defined in the memory element between the channel element and the electrode element.

6. The memory device according to claim 5, wherein the second storage portion has a fifth outer sidewall storage surface and a sixth outer sidewall storage surface that are opposite to each other, and the fifth outer sidewall storage surface and the sixth outer sidewall storage surface of the second storage portion are respectively outside the third outer sidewall storage surface and the fourth outer sidewall storage surface of the intermediate storage portion.

7. A memory device, comprising: an insulating element having a straight stripe shape; a channel element surrounding a sidewall surface of the insulating element; a storage element; and an electrode element, wherein a storage cell is defined in the storage element between the channel element and the electrode element; wherein the channel element includes a first channel portion, a second channel portion, and an intermediate channel portion, the intermediate channel portion is between the first channel portion and the second channel portion, the first channel portion has a first sidewall channel surface and a second sidewall channel surface that are opposite to each other, the intermediate channel portion has a third sidewall channel surface and a fourth sidewall channel surface that are opposite to each other, the first sidewall channel surface and the second sidewall channel surface of the first channel portion are respectively outside the third sidewall channel surface and the fourth sidewall channel surface of the intermediate channel portion, the first channel portion is electrically connected to one of a source electrode and a drain electrode, and the second channel portion is electrically connected to the other of the source electrode and the drain electrode.

8. The memory device according to any one of claims 1 to 7, comprising a plurality of the electrode elements, which are arranged separately from each other in a vertical direction on a sidewall surface of the storage element, wherein a plurality of the storage cells are defined in the storage element between the channel element and these electrode elements.

9. The memory device according to claim 8, wherein these storage cells are electrically connected in parallel.

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