Active pattern structure and semiconductor device comprising the same

Abstract

An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to the upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of the buffer structure can include aluminum silicon oxide, and an upper active pattern on the buffer structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0142901, filed on November 8, 2019, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The example embodiments relate to active patterned structures and semiconductor devices including active patterned structures. More specifically, the example embodiments relate to finFETs including buffer structures. Background Technology

[0004] When active fins are formed during the fabrication of a FinFET, the active fins can have an increasing width from top to bottom due to the characteristics of the patterning process. Therefore, current may concentrate in the upper portion of the active fin, or leakage current may occur in the lower portion. Specifically, because the active fins are scaled down, the leakage current increases in the lower portion of the active fin. Summary of the Invention

[0005] The example embodiment provides an active patterned structure with improved properties.

[0006] An example embodiment provides a semiconductor device with improved characteristics.

[0007] According to some embodiments of the present invention, an active patterning structure is provided. The active patterning structure may include: a lower active pattern that protrudes from the upper surface of the substrate in a vertical direction substantially perpendicular to the upper surface of the substrate; a buffer structure located on the lower active pattern, at least a portion of the buffer structure may include alumina silicon; and an upper active pattern located on the buffer structure.

[0008] According to some embodiments of the present invention, an active patterning structure is provided. The active patterning structure may include: a lower active pattern protruding from the upper surface of the substrate in a vertical direction substantially perpendicular to the upper surface of the substrate; a buffer located on the lower active pattern and comprising aluminum-doped silicon; and an upper active pattern whose width increases from the upper portion of the upper active pattern toward the lower portion of the upper active pattern. The minimum width of the buffer may be equal to or less than the width of the upper surface of the upper active pattern.

[0009] According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device may include: an active pattern structure located on a substrate; an isolation pattern located on the substrate; a gate electrode structure located on the active pattern structure; and a source / drain layer. The active pattern structure may include: a lower active pattern protruding from the upper surface of the substrate in a vertical direction substantially perpendicular to the upper surface of the substrate; a buffer structure located on the lower active pattern, at least a portion of the buffer structure comprising alumina silicon; and an upper active pattern located on the buffer structure. The isolation pattern may be stacked with at least a portion of the sidewalls of the active pattern structure. The source / drain layer may be located on the portion of the active pattern structure adjacent to the gate electrode structure.

[0010] The semiconductor device according to the example embodiment may include: a lower active pattern protruding from the upper surface of a substrate, at least a portion of a buffer structure comprising silicon alumina and located on the lower active pattern; and an upper active pattern located on the buffer structure. Therefore, the width of the area where the lower and upper active patterns contact can be reduced, thereby also reducing leakage current between them. Attached Figure Description

[0011] Figures 1 to 4 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0012] Figures 5 to 7 This is a cross-sectional view of an active patterned structure according to an example embodiment.

[0013] Figure 8 and Figure 9 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0014] Figure 10 and Figure 11 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0015] Figures 12 to 18 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0016] Figures 19 to 29 These are plan views and / or cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0017] Figures 30 to 32 This is a cross-sectional view of a semiconductor device according to an example embodiment. Detailed Implementation

[0018] The active patterning structure and the semiconductor device including the active patterning structure according to the exemplary embodiments will be described more fully below with reference to the accompanying drawings.

[0019] Figures 1 to 4 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0020] Reference Figure 1 A first buffer layer 110, a semiconductor layer 120, and a first mask 130 can be sequentially formed on a substrate 100.

[0021] The substrate 100 may include silicon, germanium, silicon-germanium, or III-V compounds (e.g., GaP, GaAs, GaSb). In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0022] The first buffer layer 110 may include impurity-doped silicon whose oxidation reaction is greater than that of the substrate 100 and the semiconductor layer 120 (e.g., aluminum-doped silicon).

[0023] The semiconductor layer 120 may include silicon, germanium, silicon-germanium, or III-V compounds (e.g., GaP, GaAs, GaSb). In some embodiments, the semiconductor layer 120 may include a material substantially the same as that of the substrate 100.

[0024] In an example embodiment, the first mask 130 may extend in a first direction substantially parallel to the upper surface of the substrate 100, and a plurality of first masks 130 may be formed in a second direction substantially parallel to the upper surface of the substrate 100 and intersecting the second direction. In an example embodiment, the first direction and the second direction may be orthogonal to each other or perpendicular to each other.

[0025] Reference Figure 2 The first mask 130 can be used as a mask to etch the semiconductor layer 120, the first buffer layer 110 and the substrate 100.

[0026] Therefore, a fin structure comprising a first lower active pattern 105, a first buffer 112, and a first upper active pattern 125 stacked sequentially can be formed. The fin structure can extend in a first direction and multiple fin structures can be formed in a second direction.

[0027] A first recess 135 may be formed between adjacent fins of the fin structure in the second direction. That is, the fins of the fin structure may be spaced apart from each other in the second direction by means of the first recess 135.

[0028] Etching processes can include quadruple patterning (QPT) and extreme ultraviolet (EUV) lithography.

[0029] In an example embodiment, the first lower active pattern 105 and the first upper active pattern 125 may comprise substantially the same material.

[0030] In example embodiments, the width of each of the first lower active pattern 105 and the first upper active pattern 125 may increase from its upper portion to a lower portion closer to the substrate 100. In some example embodiments, the width of the upper surface of the first buffer 112 may be greater than the width of the first upper active pattern 125.

[0031] After the etching process, the first mask 130 can be removed.

[0032] Reference Figure 3 This can partially oxidize the sidewalls of the first buffer 112 exposed by the first recess 135.

[0033] Therefore, a second buffer 114 can be formed at each of the opposite sidewalls of the first buffer 112 in the second direction. The first buffer 112 and the second buffer 114 can form a buffer structure 116, and the first lower active pattern 105, the buffer structure 116, and the first upper active pattern 125 can form an active pattern structure. The first lower active pattern 105 and the first upper active pattern 125 can be referred to as the first active pattern 150.

[0034] In the example embodiment, the first lower active pattern 105 and the first upper active pattern 125 can be spaced apart from each other in the vertical direction by the buffer structure 116.

[0035] In an example embodiment, the second buffer 114 may protrude from the first active pattern 150 in a second direction.

[0036] The first buffer 112 may include materials whose oxidation reaction is greater than that of the substrate 100, the first lower active pattern 105, and / or the first upper active pattern 125. Therefore, when an oxidation reaction is performed at the first buffer 112, the substrate 100, the first lower active pattern 105, and the first upper active pattern 125 may not be oxidized, or may be oxidized less.

[0037] In an example embodiment, the first buffer 112 may have a concave sidewall in the second direction, and the second buffer 114 may have a convex shape in the second direction.

[0038] In an example embodiment, the width of the second buffer 114 may gradually decrease in the vertical direction from its center portion toward its upper or lower portion.

[0039] In an example embodiment, the sidewall of the second buffer 114 may have a slope that can gradually change in the vertical direction relative to the upper surface of the substrate 100.

[0040] The second buffer 114 may include oxides, such as silicon alumina.

[0041] Reference Figure 4 This can form an isolation pattern 140 to partially fill the first recess 135 between the fin structures.

[0042] Specifically, the isolation pattern 140 can be formed by forming an isolation layer on the substrate 100 and the active pattern structure, planarizing the isolation layer until the upper surface of the first active pattern 125 can be exposed, and removing the upper portion of the isolation layer.

[0043] In the example embodiment, the isolation pattern 140 may cover the sidewall of the first lower active pattern 105 or overlap with the sidewall of the first lower active pattern 105, but may not cover the sidewall of the buffer structure 116 and the first upper active pattern 125 or overlap with the sidewall of the buffer structure 116 and the first upper active pattern 125.

[0044] The isolation pattern 140 may include oxides, such as silicon oxide.

[0045] As described above, a first buffer layer 110 and a semiconductor layer 120 can be sequentially stacked on a substrate 100. The semiconductor layer 120, the first buffer layer 110, and the upper portion of the substrate 100 can be etched to form a first upper active pattern 125, a first buffer 112, and a first lower active pattern 105, respectively. An oxidation process can be performed on the first buffer 112 to form a second buffer 114 on the sidewalls of the first buffer 112. The first buffer 112 may include a material with a high oxidation reactivity; therefore, the first active pattern 150 may not be oxidized or may be oxidized less, allowing only the first buffer 112 to be selectively oxidized.

[0046] Therefore, a second buffer 114, comprising an oxide having a bandgap larger than that of the first lower active pattern 105 and the first upper active pattern 125, can be inserted between the first lower active pattern 105 and the first upper active pattern 125. The width of the first buffer 112, excluding the oxide, can be smaller than the width of the first upper active pattern 125, thereby reducing leakage current from the first upper active pattern 125 to the first lower active pattern 105.

[0047] Figures 5 to 7 This is a cross-sectional view of an active patterned structure according to an example embodiment.

[0048] In addition to the height of the isolation pattern, these active pattern structures can be combined with... Figure 4 The active pattern structures are basically the same or similar. Therefore, the same reference numerals refer to the same elements, and detailed descriptions of them are omitted here.

[0049] Reference Figure 5The isolation pattern 140 may cover the sidewall of the first lower active pattern 105 and the lower sidewall of the buffer structure 116 or overlap with the sidewall of the first lower active pattern 105 and the lower sidewall of the buffer structure 116, but may not cover the upper sidewall of the buffer structure 116 and the sidewall of the first upper active pattern 125 or overlap with the upper sidewall of the buffer structure 116 and the sidewall of the first upper active pattern 125.

[0050] Reference Figure 6 The isolation pattern 140 may cover the sidewall of the first lower active pattern 105 and the sidewall of the buffer structure 116 or overlap with the sidewall of the first lower active pattern 105 and the sidewall of the buffer structure 116, but may not cover the sidewall of the first upper active pattern 125 or overlap with the sidewall of the first upper active pattern 125.

[0051] Reference Figure 7 The isolation pattern 140 may cover the sidewall of the first lower active pattern 105, the sidewall of the buffer structure 116, and the lower sidewall of the first upper active pattern 125, or may overlap with the sidewall of the first lower active pattern 105, the sidewall of the buffer structure 116, and the lower sidewall of the first upper active pattern 125, but may not cover the upper sidewall of the first upper active pattern 125 or may not overlap with the upper sidewall of the first upper active pattern 125.

[0052] That is, the isolation pattern 140 can completely cover the sidewall of the first lower active pattern 105 or completely overlap with the sidewall of the first lower active pattern 105. However, it can completely cover the sidewall of the buffer structure 116 or completely overlap with the sidewall of the buffer structure 116, or partially cover the sidewall of the buffer structure 116 or partially overlap with the sidewall of the buffer structure 116. In addition, the isolation pattern 140 can partially cover the sidewall of the first upper active pattern 125 or partially overlap with the sidewall of the first upper active pattern 125.

[0053] Figure 8 and Figure 9 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0054] This method may include references Figures 1 to 3 The processes shown are basically the same or similar, so repeated explanations are omitted here.

[0055] Reference Figure 8 It can execute with Figures 1 to 3 The process is essentially the same or similar, and the second buffer 114 can be removed. Therefore, the sidewall of the first buffer 112 can be removed through the first recess 135.

[0056] In an example embodiment, the width of the first buffer 112 may gradually increase from its center portion toward its upper or lower portion in a vertical direction perpendicular to the substrate 100.

[0057] In an example embodiment, the sidewall of the first buffer 112 may have a slope that can gradually change in the vertical direction relative to the upper surface of the substrate 100.

[0058] In an example embodiment, the minimum width of the first buffer 112 may be equal to or less than the width of the upper surface of the first active pattern 125.

[0059] Reference Figure 9 It can execute with Figure 4 The process is essentially the same or similar, so that the isolation pattern 140 can be formed to cover the sidewall of the first lower active pattern 105 or superimpose with the sidewall of the first lower active pattern 105.

[0060] In an example embodiment, the upper surface of the isolation pattern 140 may be lower than the upper surface of the first buffer 112. In some embodiments, the upper surface of the isolation pattern 140 may be substantially coplanar with the lower surface of the first buffer 112.

[0061] As shown above, the first buffer 112 can be formed between the first lower active pattern 105 and the first upper active pattern 125 to include a portion whose width is smaller than the width of the lower surface of the first upper active pattern 125, thereby reducing the leakage current from the first upper active pattern 125 to the first lower active pattern 105.

[0062] Figure 10 and Figure 11 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0063] This method may include basic and reference Figures 1 to 4 The processes shown are the same or similar, so repeated explanations are omitted here.

[0064] Reference Figure 10 It can be executed and referenced. Figures 1 to 3 The processes shown are basically the same or similar.

[0065] However, the first buffer 112 can be completely oxidized to form the second buffer 114, through which the first lower active pattern 105 and the first upper active pattern 125 can be spaced apart from each other by the second buffer 114.

[0066] In particular, the first buffer 112 may include a material with a high oxidation reactivity so that it can be easily oxidized, and thus not only the sidewalls of the first buffer 112 but also the central portion between the sidewalls can be completely oxidized.

[0067] In an example embodiment, the width of the second buffer 114 may gradually decrease in the vertical direction from its center portion toward its upper or lower portion.

[0068] Reference Figure 11 It can be executed and referenced. Figure 4 The processes shown are substantially the same or similar to those used to form an isolation pattern 140 that covers the sidewall of the first lower active pattern 105 or overlaps with the sidewall of the first lower active pattern 105.

[0069] As shown above, the first lower active pattern 105 and the first upper active pattern 125 can be spaced apart from each other by a second buffer 114 including oxide, thereby reducing the leakage current from the first upper active pattern 125 to the first lower active pattern 105.

[0070] Figures 12 to 18 This is a cross-sectional view illustrating a method for forming an active patterned structure according to an example embodiment.

[0071] Reference Figure 12 and Figure 13 A second mask 510 can be formed on the substrate 500, and the second mask 510 can be used as an etching mask to partially etch the upper portion of the substrate 500 to form a second active pattern 502 protruding from the upper surface of the substrate 500 in a vertical direction perpendicular to the substrate.

[0072] The substrate 500 may include silicon, germanium, silicon-germanium, or III-V compounds (e.g., GaP, GaAs, GaSb). In some embodiments, the substrate 500 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0073] In the example embodiment, the second active pattern 502 may extend in a first direction, and a plurality of second active patterns 502 may be formed in a second direction. Second recesses 515 may be formed between adjacent second active patterns 502 in the second direction. That is, the second active patterns 502 may be spaced apart from each other in the second direction by the second recesses 515.

[0074] Reference Figure 14 and Figure 15 A third mask layer 520 can be formed on the substrate 500, the second active pattern 502, and the second mask 510, and the third mask layer 520 can be partially etched to expose the upper surface of the substrate 100 and the lower portion of the second active pattern 502. Therefore, the third mask 525 can be formed to cover the upper portion of the second mask 510 and the second active pattern 502 or to be superimposed on the upper portion of the second mask 510 and the second active pattern 502.

[0075] In an example embodiment, the second mask 510 and the third mask 525 may comprise substantially the same material and therefore may be merged with each other.

[0076] Reference Figure 16 The second buffer layer 530 can be formed on the exposed upper surface of the substrate 500, the exposed lower portion of the second active pattern 502, and the second mask 510 and the third mask 525.

[0077] The second buffer layer 530 may include a material whose oxidation reaction is greater than that of the substrate 500, such as aluminum-doped silicon.

[0078] Reference Figure 17 The second buffer layer 530 can be completely oxidized, and the oxidized second buffer layer 530 can be removed.

[0079] The second buffer layer 530 comprises aluminum-doped silicon, and the substrate 500 and the second active pattern 502 comprise undoped silicon or undoped silicon-germanium. Therefore, the aluminum included in the second buffer layer 530 can diffuse into the portions of the substrate 500 and the second active pattern 502 that contact the second buffer layer 530. Additionally, the portions of the substrate 500 and the second active pattern 502 that contact the second buffer layer 530 can be oxidized.

[0080] Therefore, a third buffer layer 540 can be formed on the lower portion of the second active pattern 502 that is not covered by or superimposed with the second mask 510 and the third mask 525 and on the upper surface of the substrate 500, and the second active pattern 502 can be transformed into a third active pattern 504.

[0081] The third buffer layer 540 may include, for example, an oxide of silicon alumina.

[0082] Reference Figure 18 The third buffer layer 540 and the upper portion of the substrate 500 can be partially etched using the second mask 510 and the third mask 525, which are sequentially stacked on the third active pattern 504, so that the second recess 515 between the third active patterns 504 can be expanded downward.

[0083] Therefore, the third active pattern 504 can be transformed into the fourth active pattern 505, and the portion of the third buffer layer 540 located on the lower part of the third active pattern 504 can be transformed into the third buffer 545.

[0084] The isolation pattern 550 may be formed as a basic fill or at least a partial fill of the enlarged second recess 515, and cover or overlap the lower sidewall of the fourth active pattern 505.

[0085] The fourth active pattern 505 may include a second lower active pattern 505b and a second upper active pattern 505a. The sidewalls of the second lower active pattern 505b may be covered by or superimposed on the isolation pattern 550. The second upper active pattern 505a protrudes upward from the upper surface of the isolation pattern 550 in a vertical direction perpendicular to the substrate.

[0086] exist Figure 18 In this invention, the isolation pattern 550 partially covers or overlaps with the sidewall of the third buffer 545; however, the inventive concept is not limited thereto. That is, the isolation pattern 550 may not cover or overlap with the sidewall of the third buffer 545, or it may completely cover or overlap with the sidewall of the third buffer 545.

[0087] In an example embodiment, the lower surface of the second upper active pattern 505a and the upper surface of the second lower active pattern 505b can contact each other between the third buffer 545.

[0088] In an example embodiment, the sidewalls of the second lower active pattern 505b, the third buffer 545, and the second upper active pattern 505a may have a constant slope relative to the upper surface of the substrate 500. In some embodiments, the inner sidewall of the third buffer 545 may have a slope relative to the upper surface of the substrate 500 that can vary in a vertical direction perpendicular to the substrate.

[0089] like Figure 18 As shown, a third buffer 545 comprising an oxide with a bandgap greater than that of the second lower active pattern 505b and the second upper active pattern 505a can be at least partially inserted between the second lower active pattern 505b and the second upper active pattern 505a. Therefore, the width of the lower portion of the second upper active pattern 505a that contacts the upper portion of the second lower active pattern 505b is reduced, thereby reducing the leakage current from the second upper active pattern 505a to the second lower active pattern 505b.

[0090] Figures 19 to 29 These are plan views and / or cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 19 , Figure 22 , Figure 24 and Figure 27 It's a floor plan. Figure 20 , Figure 21 , Figure 23 , Figure 25 , Figure 26 , Figure 28 and Figure 29 It is a cross-sectional view.

[0091] Figure 20and Figure 28 These are cross-sectional views taken along line A-A' of the corresponding plan view. Figure 21 , Figure 25 and Figure 29 These are cross-sectional views taken along line B-B' of the corresponding plan view. Figure 23 and Figure 26 These are cross-sectional views taken along line C-C' of the corresponding plan view.

[0092] Semiconductor devices may include basic and Figure 6 The active pattern structures are the same or similar to the active pattern structures, therefore the same reference numerals denote the same elements, and repeated descriptions are omitted here.

[0093] Reference Figures 19 to 21 A dummy gate structure 190 can be formed on the buffer structure 116, the first active pattern 125, and the isolation pattern 140.

[0094] The dummy gate structure 190 can be formed by sequentially forming a dummy gate insulating layer, a dummy gate electrode layer, and a dummy gate mask layer, patterning the dummy gate mask layer to form a dummy gate mask 180, and sequentially etching the dummy gate electrode layer and the dummy gate insulating layer using the dummy gate mask 180 as an etching mask.

[0095] Therefore, a dummy gate structure 190, comprising a dummy gate insulating pattern 160, a dummy gate electrode 170, and a dummy gate mask 180 stacked sequentially, can be formed on the substrate 100.

[0096] The dummy gate insulating layer may include, for example, an oxide of silicon oxide; the dummy gate electrode layer may include, for example, polysilicon; and the dummy gate mask layer may include, for example, a nitride of silicon nitride.

[0097] The dummy gate insulating layer, dummy gate electrode layer, and dummy gate mask layer can be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. In some embodiments, the dummy gate insulating layer can be formed on the first active pattern 125 using a thermal oxidation process. In this case, the dummy gate insulating layer can be formed only on the upper surface of the first active pattern 125.

[0098] In an example embodiment, the dummy gate structure 190 may extend in a second direction and may form a plurality of gate structures 190 in a first direction.

[0099] After a spacer layer is formed on the first active pattern 125 and isolation pattern 140 to cover or stack with the dummy gate structure 190, the spacer layer can be anisotropically etched to form a gate spacer 200 on each of the opposite sidewalls of the dummy gate structure 190 in the first direction.

[0100] Fin spacers 210 may be formed on each of the opposing sidewalls of the second buffer 114 in the second direction. However, the inventive concept is not limited thereto. That is, fin spacers 210 may also be formed on each of the opposing sidewalls of the first active pattern 125 in the second direction, as will be described later. Figures 30 to 32 As shown.

[0101] The spacer layer may include, for example, a silicon nitride. In some embodiments, the spacer layer may have a stacked structure comprising sequentially stacked nitride layers and oxide layers.

[0102] Reference Figure 22 and Figure 23 The portion of the first active pattern 125 adjacent to the gate spacer 200 and the portion of the buffer structure 116 below it can be etched to form the third recess 220.

[0103] exist Figure 23 In this process, portions of the first active pattern 125 and the buffer structure 116 are partially etched to form the third recess 220, such that the bottom of the third recess is higher than the bottom surface of the buffer structure 116. However, the inventive concept is not limited to this. That is, the third recess 220 can be formed by etching only the upper portion of the first active pattern 125 so that the bottom of the third recess 220 is higher than the upper surface of the buffer structure 116, as will be discussed later. Figures 30 to 32 As shown.

[0104] When the third recess 220 is formed, the fin spacers 210 on each of the opposite sidewalls of the second buffer 114 can be removed, either partially or completely.

[0105] In the example embodiment, the etching process for forming the third recess 220 and the etching process for forming the gate spacer 200 and the fin spacer 210 can be performed in situ.

[0106] Reference Figures 24 to 26 A source / drain layer 230 can be formed to fill or at least partially fill the third recess 220.

[0107] In an example embodiment, the source / drain layer 230 can be formed by a selective epitaxial growth (SEG) process that uses the upper surface of the first buffer 112 exposed by the third recess 220 as a seed.

[0108] In the example embodiment, the SEG process can be performed using a silicon source gas, a germanium source gas, an etching gas, and a carrier gas, thus forming a monocrystalline silicon-germanium layer for use as the source / drain layer 230. Alternatively, the SEG process can be performed using a p-type impurity source gas, and a monocrystalline silicon-germanium layer doped with p-type impurities can be formed for use as the source / drain layer 230.

[0109] According to some embodiments, the SEG process can be performed using a silicon source gas, a carbon source gas, an etching gas, and a carrier gas. Therefore, a single-crystal silicon carbide layer can be formed as the source / drain layer 230. Alternatively, an n-type impurity source gas can be used to perform the SEG process, thus forming a single-crystal silicon carbide layer doped with n-type impurities for use as the source / drain layer 230. In addition, the SEG process can be performed using a silicon source gas, an etching gas, and a carrier gas, thus forming a single-crystal silicon layer as the source / drain layer 230. In this case, an n-type impurity source gas and the gases mentioned above can be used to form a single-crystal silicon layer doped with n-type impurities.

[0110] The source / drain layer 230 can be grown not only in a vertical direction perpendicular to the substrate 100, but also in a horizontal direction parallel to the top surface of the substrate 100, to fill or at least partially fill the third recess 220. The source / drain layer 230 can contact the sidewalls of the gate spacer 200. In an example embodiment, the source / drain layer 230 may have a cross-section with a pentagonal shape cut along the second direction.

[0111] In an example embodiment, when adjacent buffer structures 116 in the second direction are close to each other, the source / drain layers 230 grown on adjacent first buffers 112 in the first buffers 112 can merge with each other. Figure 26 The illustration shows three source / drain layers 230 grown on three adjacent first buffers 112, each merged with the others. However, the inventive concept is not limited to this. Thus, for example, two or more source / drain layers 230 can be grown to merge with each other.

[0112] An insulating interlayer 240, covering or superimposed on the dummy gate structure 190, gate spacer 200, fin spacer 210, and source / drain layer 230, can be formed on the first active pattern 125 and isolation pattern 140 to achieve sufficient height, and the insulating interlayer 240 can be planarized until the upper surface of the dummy gate electrode 170 of the dummy gate structure 190 can be exposed. In the planarization process, the dummy gate mask 180 and the upper portion of the gate spacer 200 can be removed.

[0113] The space between the merged source / drain layer 230 and the isolation pattern 140 may not be completely filled by the insulating interlayer 240, thus forming an air gap 250 therein.

[0114] The insulating interlayer 240 may include silicon oxide, such as Tonen silazane (TOSZ). Planarization can be performed by chemical mechanical polishing (CMP) and / or etching back processes.

[0115] Reference Figures 27 to 29 The exposed dummy gate electrode 170 and dummy gate insulating pattern 160 can be removed to form an opening that exposes the inner sidewall of the gate spacer 200 and the upper surface of the first active pattern 125. The gate electrode structure 300 can be formed to fill or at least partially fill the opening.

[0116] In the example embodiment, the exposed dummy gate electrode 170 and dummy gate insulating pattern 160 can be removed by both dry etching and wet etching processes. For example, hydrofluoric acid can be used to perform the wet etching process.

[0117] Specifically, the gate electrode structure 300 can be formed by the following process: performing a thermal oxidation process on the exposed upper surface of the first active pattern 125 to form an interface pattern 260; sequentially forming a gate insulating layer and a work function control layer on the interface pattern 260, the isolation pattern 140, the gate spacer 200, and the insulating interlayer 240; forming a gate electrode layer on the work function control layer to fill or at least partially fill the remainder of the opening; and planarizing the gate electrode layer, the work function control layer, and the gate insulating layer until the upper surface of the insulating interlayer 240 can be exposed. The gate electrode structure 300 may include the interface pattern 260, the gate insulating pattern 270, the work function control pattern 280, and the gate electrode 290.

[0118] Function control layers and gate electrode layers can be formed using CVD, ALD, PVD, and other processes. Heat treatments such as rapid thermal annealing (RTA), spike-type RTA, flash RTA, or laser annealing can also be performed.

[0119] In some embodiments, the interface pattern 260 can be formed as a gate insulating layer or gate electrode layer by a CVD process or an ALD process. In this case, the interface pattern 260 can be formed not only on the upper surface of the first active pattern 125, but also on the upper surface of the isolation pattern 140 and the inner sidewall of the gate spacer 200. In some embodiments, the interface pattern 260 may not be formed.

[0120] Gate insulating pattern 270 and work function control pattern 280 can be sequentially stacked on the surface of interface pattern 260, the upper surface of isolation pattern 140 and the inner sidewall of gate spacer 200, and gate electrode 290 can be formed on work function control pattern 280 to fill or at least partially fill the rest of the opening.

[0121] The gate electrode structure 300 and the source / drain layer 230 can form a transistor. Depending on the conductivity type of the source / drain layer 230, the transistor can be a PMOS transistor or an NMOS transistor.

[0122] The upper portion of the gate electrode structure 300 and the gate spacer 200 can be removed to form a fourth recess (not shown), a cover pattern (not shown) can be formed to fill the fourth recess, and contact plugs (not shown), vias (not shown) and wiring (not shown) can be formed to electrically connect them to the source / drain layer 230 and / or the gate electrode structure 300 to complete the fabrication of the semiconductor device.

[0123] As shown above, a second buffer 114, which includes an oxide with a band gap greater than that of the first lower active pattern 105 and the first upper active pattern 125, can be inserted between the first lower active pattern 105 and the first upper active pattern 125. The width of the first buffer 112, which does not include the oxide, can be smaller than the width of the first upper active pattern 125, so that the leakage current from the first upper active pattern 125 to the first lower active pattern 105 can be reduced.

[0124] Figures 30 to 32 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0125] Figure 30 It is a cross-sectional view taken along line A-A' of the corresponding plan view. Figure 31 It is a cross-sectional view taken along line B-B' of the corresponding plan view. Figure 32 It is a cross-sectional view taken along line C-C' of the corresponding plan view.

[0126] In addition to the shape of the active pattern structure beneath the source / drain layer 230 and the gate electrode structure 300, this semiconductor device can be coupled with... Figures 27 to 29 The semiconductor devices are essentially the same or similar. Therefore, the same reference numerals denote the same elements, and detailed descriptions of them are omitted here.

[0127] Reference Figures 30 to 32 Semiconductor devices may include Figure 7 The image shown is not the one depicted. Figure 6 The active pattern structure shown.

[0128] Therefore, the fin spacer 210 can be formed on each of the opposite sidewalls of the first active pattern 125 in the second direction, and the source / drain layer 230 can be formed on the first active pattern 125.

[0129] Specifically, the third recess 220 used to form the source / drain layer 230 ( Figure 23 As shown, the third recess 220 can be formed by etching only the upper portion of the first active pattern 125, and the buffer structure 116 below the first active pattern 125 can be left unetched during the etching process. Therefore, the bottom of the third recess 220 can be higher than the upper surface of the buffer structure 116, and the source / drain layer 230 can be formed on the first active pattern 125.

[0130] As described above, although the invention has been described with reference to exemplary embodiments, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept.

Claims

1. An active pattern structure, comprising: a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to the upper surface of the substrate; a buffer structure on the lower active pattern, wherein at least a portion of the buffer structure comprises aluminum silicon oxide; an upper active pattern on the buffer structure; a first buffer comprising silicon doped with aluminum; and a second buffer on a sidewall of the first buffer, the second buffer comprising aluminum silicon oxide.

2. The active pattern structure of claim 1, wherein, The second buffer protrudes from the lower active pattern and the upper active pattern in a horizontal direction substantially parallel to the upper surface of the substrate.

3. The active pattern structure of claim 1, further comprising: an isolation pattern on the substrate, wherein the isolation pattern is on a sidewall of the lower active pattern, and wherein an upper surface of the isolation pattern is lower than an upper surface of the buffer structure relative to the upper surface of the substrate.

4. The active pattern structure of claim 3, wherein, The upper surface of the isolation pattern is substantially coplanar with a lower surface of the buffer structure.

5. The active pattern structure of claim 1, wherein, A width of the upper active pattern increases from an upper portion of the upper active pattern toward a lower portion of the upper active pattern adjacent to the buffer structure.

6. The active pattern structure of claim 5, wherein, A width of an upper surface of the buffer structure is greater than a width of an upper surface of the upper active pattern.

7. The active pattern structure of claim 1, wherein, The lower active pattern and the upper active pattern comprise substantially the same material.

8. An active pattern structure, comprising: a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to the upper surface of the substrate; a buffer structure on the lower active pattern, wherein at least a portion of the buffer structure comprises aluminum silicon oxide; and an upper active pattern on the buffer structure, wherein the buffer structure is on an edge upper portion of a surface of the lower active pattern, wherein the upper active pattern is on a central portion of an upper surface of the lower active pattern and on an upper surface of the buffer structure, and wherein the lower active pattern and the upper active pattern are in direct contact with each other.

9. The active pattern structure of claim 8, wherein, The lower active pattern and the upper active pattern comprise substantially the same semiconductor material.

10. The active pattern structure of claim 8, further comprising: an isolation pattern on the substrate, wherein the isolation pattern is on a sidewall of the lower active pattern and a sidewall of the buffer structure, and wherein an upper surface of the isolation pattern is substantially coplanar with or higher than an upper surface of the buffer structure.

11. The active pattern structure of claim 8, wherein, A width of the buffer structure increases in the vertical direction from a central portion of the buffer structure toward an upper portion or a lower portion of the buffer structure.

12. The active pattern structure of claim 11, wherein, A sidewall of the buffer structure has a slope relative to the upper surface of the substrate that varies in the vertical direction.

13. The active pattern structure of claim 8, further comprising: an isolation pattern on the substrate, wherein the isolation pattern is on a sidewall of the lower active pattern, and wherein an upper surface of the isolation pattern is substantially coplanar with or lower than an upper surface of the buffer structure relative to the upper surface of the substrate.

14. The active pattern structure of claim 8, wherein, The lower active pattern and the upper active pattern comprise substantially the same semiconductor material.

15. A semiconductor device, comprising: an active pattern structure on a substrate, the active pattern structure comprising: a lower active pattern protruding from an upper surface of the substrate in a vertical direction substantially perpendicular to the upper surface of the substrate; a buffer structure on the lower active pattern, wherein at least a portion of the buffer structure comprises aluminum silicon oxide; and an upper active pattern on the buffer structure; an isolation pattern on the substrate, wherein the isolation pattern is on at least a portion of a sidewall of the active pattern structure; a gate electrode structure on the active pattern structure; and a source / drain layer on a portion of the active pattern structure adjacent to the gate electrode structure, wherein the isolation pattern is on a sidewall of the lower active pattern, and wherein an upper surface of the isolation pattern is lower than an upper surface of the buffer structure relative to the upper surface of the substrate.

16. The semiconductor device according to claim 15, wherein The gate electrode structure contacts at least a portion of a sidewall of the buffer structure.

17. The semiconductor device according to claim 15, wherein The buffer structure comprises: a first buffer comprising silicon doped with aluminum; and a second buffer on a sidewall of the first buffer, the second buffer comprising aluminum silicon oxide.

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