Display device and method for manufacturing the same

Abstract

The present disclosure relates to a display device and a method of manufacturing the same. The display device may include: a substrate including a display area and a non-display area; and a plurality of pixels disposed on the display area and each including a plurality of sub-pixels, each of the plurality of sub-pixels including an emission area and a non-emission area. Each of the sub-pixels may include a display element layer including at least one light-emitting element that emits light. The display element layer includes: a first electrode and a second electrode spaced apart from each other, the light-emitting element being disposed between the first electrode and the second electrode; and connection lines including a first connection line extending in a row direction of the substrate and connected to the first electrode, and a second connection line extending parallel to the first connection line and connected to the second electrode. Two connection lines having a symmetric structure may be disposed in an area between corresponding emission areas of two adjacent sub-pixels in a column direction of the substrate among the plurality of sub-pixels.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0002] A light-emitting diode (hereinafter, referred to as "LED") can have relatively satisfactory durability even under adverse environmental conditions, and the LED can have excellent performance in terms of lifespan and brightness.

[0003] In order to apply an LED to a lighting device, a display device, etc., it is necessary to connect the LED to an electrode so that the voltage of a power source can be applied to the LED. Various studies related to the arrangement relationship between the LED and the electrode have been conducted. Summary of the Invention

[0004] Technical Problem

[0005] Various embodiments of the present disclosure relate to a display device capable of minimizing misalignment of ultra-small light-emitting diodes and thus enhancing the light output efficiency of the light-emitting diodes, and a method of manufacturing the display device.

[0006] Technical Solution

[0007] A display device according to an embodiment of the present disclosure may include: a substrate including a display area and a non-display area; and a plurality of pixels disposed on the display area, each including a plurality of sub-pixels, each of the plurality of sub-pixels including an emission area and a non-emission area. Each of the sub-pixels may include a display element layer including at least one light-emitting element that emits light. The display element layer includes: a first electrode and a second electrode spaced apart from each other, the light-emitting element being disposed between the first electrode and the second electrode; and connection lines including a first connection line extending in the row direction of the substrate and connected to the first electrode, and a second connection line extending parallel to the first connection line and connected to the second electrode. Two connection lines having a symmetric structure among the connection lines may be disposed in an area located between corresponding emission areas of two adjacent sub-pixels among the plurality of sub-pixels in the column direction of the substrate.

[0008] In an embodiment of the present disclosure, an area between corresponding emission areas of two sub-pixels may be a non-emission area. The two connection lines may form a mirror-symmetric structure with respect to an imaginary line extending in the row direction in an area between corresponding emission areas of the two sub-pixels.

[0009] In an embodiment of the present disclosure, the two connection lines may include: a first connection line disposed in one of the two sub-pixels and connected to a first electrode of one of the two sub-pixels; and a first connection line disposed in the other of the two sub-pixels and connected to a first electrode of the other of the two sub-pixels.

[0010] In an embodiment of the present disclosure, the second electrode of each of the two sub-pixels may include a 2-1 electrode and a 2-2 electrode branched from a second connection line of the corresponding one of the two sub-pixels to an emission region of the corresponding one of the two sub-pixels. The 2-1 electrode and the 2-2 electrode may be spaced apart from each other. The first electrode of the corresponding one of the two sub-pixels may be disposed between the 2-1 electrode and the 2-2 electrode.

[0011] In an embodiment of the present disclosure, the first electrode of each of the two sub-pixels may include a 1-1 electrode and a 1-2 electrode branched from a first connection line of the corresponding one of the two sub-pixels to an emission region of the corresponding one of the two sub-pixels. The 1-1 electrode and the 1-2 electrode may be spaced apart from each other. The second electrode of the corresponding one of the two sub-pixels may be disposed between the 1-1 electrode and the 1-2 electrode.

[0012] In an embodiment of the present disclosure, the second connection line of one of the two sub-pixels may be disposed above the first connection line in the column direction in one of the two sub-pixels. The second connection line of the other of the two sub-pixels may be disposed below the first connection line in the column direction in the other sub-pixel.

[0013] In an embodiment of the present disclosure, the second connection lines of each of the two sub-pixels may be spaced apart from each other. The emission region of each of the two sub-pixels may be disposed between the second connection lines of each of the two sub-pixels in the column direction.

[0014] In an embodiment of the present disclosure, the second electrode of each of the two sub-pixels may include a 2-1 electrode, a 2-2 electrode, and a 2-3 electrode branched from a second connection line of one of the two sub-pixels to an emission region of one of the two sub-pixels. The 2-1 electrode and the 2-2 electrode may be spaced apart from each other. The 1-1 electrode may be disposed between the 2-1 electrode and the 2-2 electrode. The 2-2 electrode and the 2-3 electrode may be spaced apart from each other. The 1-2 electrode may be disposed between the 2-2 electrode and the 2-3 electrode.

[0015] In an embodiment of the present disclosure, the two connection lines may include: a second connection line disposed in one of the two sub-pixels and connected to the second electrode of one of the two sub-pixels; and a second connection line disposed in the other of the two sub-pixels and connected to the second electrode of the other of the two sub-pixels.

[0016] In an embodiment of the present disclosure, the first electrode of each of the two sub-pixels may include a 1-1 electrode and a 1-2 electrode branched from the first connection line of one of the two sub-pixels to the emission region of one of the two sub-pixels. The 1-1 electrode and the 1-2 electrode may be spaced apart from each other. The second electrode of one of the two sub-pixels may be disposed between the 1-1 electrode and the 1-2 electrode.

[0017] In an embodiment of the present disclosure, the second electrode of each of the two sub-pixels may include a 2-1 electrode and a 2-2 electrode branched from the second connection line of one of the two sub-pixels to the emission region of one of the two sub-pixels. The 2-1 electrode and the 2-2 electrode may be spaced apart from each other. The first electrode of one of the two sub-pixels may be disposed between the 2-1 electrode and the 2-2 electrode.

[0018] In an embodiment of the present disclosure, the first connection line of one of the two sub-pixels may be disposed above the second connection line in the column direction in one of the two sub-pixels. The first connection line of the other of the two sub-pixels may be disposed below the second connection line in the column direction in the other of the two sub-pixels.

[0019] In an embodiment of the present disclosure, the first connection lines of each of the two sub-pixels may be spaced apart from each other. Each emission region of the two sub-pixels may be disposed between the corresponding first connection lines of each of the two sub-pixels in the column direction.

[0020] In an embodiment of the present disclosure, the first electrode of each of the two sub-pixels may include a 1-1 electrode, a 1-2 electrode, and a 1-3 electrode branched from the first connection line of one of the two sub-pixels to the emission region of one of the two sub-pixels. The 1-1 electrode and the 1-2 electrode may be spaced apart from each other. The 2-1 electrode may be disposed between the 1-1 electrode and the 1-2 electrode. The 1-2 electrode and the 1-3 electrode may be spaced apart from each other. The 2-2 electrode may be disposed between the 1-2 electrode and the 1-3 electrode.

[0021] In an embodiment of the present disclosure, the display element layer may include: a first contact electrode connecting the first electrode to one end of the opposite ends of the light-emitting element; and a second contact electrode connecting the second electrode to the other end of the opposite ends of the light-emitting element.

[0022] In an embodiment of the present disclosure, each of the sub-pixels may further include a pixel circuit layer including at least one transistor electrically connected to the light-emitting element.

[0023] The display device described above may be manufactured by a method including: providing a substrate, disposing a plurality of sub-pixels on the substrate, each of the plurality of sub-pixels including an emission region and a non-emission region; and forming a display element layer on the substrate, the display element layer emitting light from the emission region of each of the sub-pixels.

[0024] In an embodiment of the present disclosure, forming the display element layer may include: forming a first electrode and a second electrode spaced apart from each other in the emission region, and at the same time, forming a first metal layer and a second metal layer in the non-emission region, wherein the first metal layer is connected to the first electrode and extends in one direction, and the second metal layer is connected to the second electrode and extends parallel to the first direction; forming an electric field between the first electrode and the second electrode by applying different alignment voltages to the first metal layer and the second metal layer, and then aligning a plurality of light-emitting elements between the first electrode and the second electrode; forming connection lines on the substrate including the light-emitting elements by removing a part of one of the first metal layer and the second metal layer, the connection lines including a first connection line connected to the first electrode and a second connection line connected to the second electrode; forming a first contact electrode electrically connecting the first electrode to one end of the opposite ends of each of the light-emitting elements; and forming a second contact electrode electrically connecting the second electrode to the other end of the opposite ends of each of the light-emitting elements.

[0025] In an embodiment of the present disclosure, aligning the plurality of light-emitting elements may include disposing two metal layers formed on the same layer and to which the same alignment voltage is applied in the first metal layer or the second metal layer in a region between the corresponding emission regions of two sub-pixels disposed adjacent to each other in the column direction of the substrate in the sub-pixels.

[0026] Advantageous Effects

[0027] Various embodiments of the present disclosure may provide a display device and a method of manufacturing the display device, in which the light-emitting elements are only disposed in a target region, thereby enhancing the optical efficiency of the light-emitting elements. Description of the Drawings

[0028] Figure 1a and Figure 1bEach is a schematic perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0029] Figure 2 Shows a display device according to an embodiment of the present disclosure, and specifically, is a schematic plan view showing a display device using Figure 1a the light-emitting element shown as a light source.

[0030] Figures 3a to 3c Is a schematic circuit diagram showing an example of a first sub-pixel among the first sub-pixel to the third sub-pixel of Figure 2 a display device according to various embodiments.

[0031] Figure 4 Is Figure 2 a schematic enlarged plan view of the region EA1 of

[0032] Figure 5 Is a schematic cross-sectional view taken along the line I-I' of Figure 4

[0033] Figures 6a to 6f Is a schematic plan view sequentially showing a method of manufacturing Figure 4 a display device of

[0034] Figure 7 Shows a display device according to an embodiment of the present disclosure, and is a schematic enlarged plan view corresponding to Figure 2 the region EA1 of

[0035] Figure 8 And Figure 9 Shows a display device according to an embodiment of the present disclosure, and is a schematic enlarged plan view corresponding to Figure 2 the region EA1 of

[0036] Figure 10 Shows a display device according to an embodiment of the present disclosure, and is a schematic enlarged plan view corresponding to Figure 2 the region EA1 of

[0037] Figure 11 Shows a display device according to an embodiment of the present disclosure, and is a schematic enlarged plan view corresponding to Figure 2 the region EA1 of

[0038] Figure 12 Shows a display device according to an embodiment of the present disclosure, and is a schematic enlarged plan view corresponding to Figure 2 the region EA1 of Detailed Description

[0039] ​Since the present disclosure allows for various variations and multiple embodiments, some embodiments will be shown in the accompanying drawings and described in detail in the present disclosure. However, this is not intended to limit the present disclosure to a specific practice mode, and it will be understood that all variations, equivalents, and alternatives that do not depart from the spirit and technical scope of the present disclosure are encompassed in the present disclosure.

[0040] Throughout the disclosure, the same reference numerals always denote the same parts in the various drawings and embodiments of the present disclosure. For clarity of illustration, the dimensions of the elements in the drawings may be exaggerated. It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In the present disclosure, the singular form is intended to also include the plural form unless the context clearly indicates otherwise.

[0041] It will also be understood that when used in this specification, the terms "comprising", "including", "having", etc. denote the presence of the stated features, wholes, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. Further, when a first portion of, for example, a layer, film, region, or plate is disposed on a second portion, the first portion may be directly on the second portion, or a third portion may be interposed between the first portion and the second portion. When it is stated that a first portion of, for example, a layer, film, region, or plate is formed on a second portion, the surface of the second portion on which the first portion is formed is not limited to the upper surface of the second portion, but may include other surfaces such as the side surface or the lower surface of the second portion. Conversely, when a first portion of, for example, a layer, film, region, or plate is below a second portion, the first portion may be directly below the second portion, or a third portion may be interposed between the first portion and the second portion.

[0042] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] Figure 1a and Figure 1b are perspective views showing various types of light-emitting elements according to an embodiment of the present disclosure. Although Figure 1a and Figure 1b show cylindrical light-emitting elements, the present disclosure is not limited thereto.

[0044] Referring to Figure 1a and Figure 1b, a light-emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer (or a first conductive semiconductor layer) 11, a second semiconductor layer (or a second conductive semiconductor layer) 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. For example, the light-emitting element LD may include a stack formed by sequentially stacking the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0045] In an embodiment of the present disclosure, the light-emitting element LD may have a rod-shaped form extending in one direction. If the direction along which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have a first end and a second end in the extending direction. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be provided at the first end, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 may be provided at the second end.

[0046] Although the light-emitting element LD may have the form of a cylinder, the present disclosure is not limited thereto. The light-emitting element LD may have a rod-shaped form or a strip-shaped form extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). For example, the length L of the light-emitting element LD in the longitudinal direction may be greater than its diameter. The light-emitting element LD may include a light-emitting diode manufactured in an ultra-small size, having a diameter and / or a length L corresponding to, for example, micron-scale or nano-scale dimensions.

[0047] However, the size of the light-emitting element LD is not limited thereto, and the size of the light-emitting element LD may be changed to meet the requirements of an illumination device or a self-emitting display device to which the light-emitting element LD is applied.

[0048] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include a semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. The material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of a variety of other materials.

[0049] The active layer 12 may be formed on the first conductive semiconductor layer 11 and have a single or multiple quantum well structures. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or under the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. Materials such as AlGaN or AlInGaN may be used to form the active layer 12.

[0050] If an electric field having a predetermined voltage or a greater voltage is applied to opposite ends of the light-emitting element LD, the light-emitting element LD emits light through recombination of electron-hole pairs in the active layer 12.

[0051] The second conductive semiconductor layer 13 may be provided on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive semiconductor layer 11. For example, the second conductive semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive semiconductor layer 13 may include a semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant such as Mg. The material forming the second conductive semiconductor layer 13 is not limited thereto, and the second conductive semiconductor layer 13 may be formed of various other materials.

[0052] In an embodiment of the present disclosure, in addition to including the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13, the light-emitting element LD may Figure 1a further include an electrode layer 15 provided on the second conductive semiconductor layer 13 as shown in. In addition, in an embodiment, as Figure 1b shown in, in addition to including the electrode layer 15, the light-emitting element LD may further include another electrode layer 16 provided on one end of the first conductive semiconductor layer 11.

[0053] Although each of the electrode layers 15 and 16 may be formed of an ohmic contact electrode, the present disclosure is not limited thereto. The electrode layers 15 and 16 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO, and their oxides or alloys may be used alone or in combination with each other. However, the present disclosure is not limited thereto.

[0054] The materials included in the respective electrode layers 15 and 16 may be the same as or different from each other. The electrode layers 15 and 16 may be substantially transparent or translucent. Therefore, the light generated from the light-emitting element LD can pass through the electrode layers 15 and 16 and then be emitted to the outside of the light-emitting element LD.

[0055] In an embodiment of the present disclosure, the light-emitting element LD may further include an insulating film 14. However, in some embodiments of the present disclosure, the insulating film 14 may be omitted or may cover at least one of the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13.

[0056] As Figure 1aAs shown, the insulating film 14 can be disposed on a part of the light-emitting element LD instead of on one of the opposite ends of the light-emitting element LD. In this case, the insulating film 14 can expose only the electrode layer 15 disposed on one end of the second conductive semiconductor layer 13 of the light-emitting element LD and surround the entire side surface of the components other than the electrode layer 15. Here, the insulating film 14 can allow at least the opposite ends of the light-emitting element LD to be exposed to the outside. For example, the insulating film 14 not only allows the electrode layer 15 disposed on one end of the second conductive semiconductor layer 13 to be exposed to the outside, but also allows one end of the first conductive semiconductor layer 11 to be exposed to the outside.

[0057] In an embodiment, as Figure 1b shown, when the electrode layers 15 and 16 are disposed on the respective opposite ends of the light-emitting element LD, the insulating film 14 can allow at least one region of each of the electrode layers 15 and 16 to be exposed to the outside. As another example, in an embodiment, the insulating film 14 may not be provided.

[0058] In an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include at least one insulating material selected from SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto. In other words, various materials having insulating properties can be used.

[0059] If the insulating film 14 is disposed on the light-emitting element LD, a short circuit between the active layer 12 and the first electrode and / or the second electrode (this region is not shown) can be prevented. Due to the insulating film 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting element LD. When the light-emitting elements LD are disposed close to each other, the insulating film 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD.

[0060] The light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be formed by a surface treatment process.

[0061] Figure 2 A display device according to an embodiment of the present disclosure is shown, and specifically, a schematic plan view of a display device using the Figure 1a light-emitting element shown as a light source is shown.

[0062] For illustration, Figure 2 the structure of the display device is schematically shown, focusing on the display area on which an image is displayed. In some embodiments, although not shown, at least one driving circuit (e.g., a scan driver and a data driver) and / or signal lines may be further provided in the display device.

[0063] Referring to Figure 1aand Figure 2 According to an embodiment of the present disclosure, a display device may include: a substrate SUB; pixels PXL disposed on the substrate SUB and each including at least one light-emitting element LD; a driver (not shown) disposed on the substrate SUB and configured to drive the pixels PXL; and a line component (not shown) disposed to connect the pixels PXL to the driver.

[0064] The display device may be classified into a passive matrix type display device and an active matrix type display device according to a driving method. For example, in the case where the display device according to an embodiment is implemented as an active matrix type, each of the pixels PXL may include: a driving transistor configured to control the amount of current to be supplied to the light-emitting element LD; and a switching transistor configured to transmit a data signal to the driving transistor.

[0065] Recently, an active matrix type display device capable of selectively turning on each pixel PXL in consideration of resolution, contrast, and operating speed has become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix type display device in which the pixels PXL are turned on in groups may also use components (e.g., a first electrode and a second electrode) for driving the light-emitting element LD.

[0066] The substrate SUB may include a display area DA and a non-display area NDA.

[0067] In an embodiment, the display area DA may be disposed in a central area of the display device, and the non-display area NDA may be disposed in a peripheral area of the display device so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0068] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which some of a driver for driving the pixels PXL and a line component for connecting the pixels PXL to the driver are disposed.

[0069] The display area DA may have various shapes. For example, the display area DA may have various forms, such as a closed polygon including a straight line, a circle including a curve, an ellipse, etc., and a semi-circle, a semi-ellipse, etc. including a straight line and a curve.

[0070] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the display area DA.

[0071] Pixels PXL can be disposed in a display area DA on a substrate SUB. Each of the pixels PXL represents a minimum unit for displaying an image, and a plurality of pixels PXL can be provided.

[0072] Each of the pixels PXL can include a light-emitting element LD, which is configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light-emitting element LD can have a small size in the range from nanometers to micrometers, and can be connected in parallel with the light-emitting elements disposed adjacent thereto. The light-emitting element LD can form a light source of the corresponding pixel PXL.

[0073] The pixels PXL can be arranged in a matrix form along rows extending in a first direction DR1 and columns extending in a second direction DR2 intersecting the first direction DR1. However, the arrangement of the pixels PXL is not limited to a specific arrangement. In other words, the pixels PXL can be arranged in various forms.

[0074] A driver can provide signals to each pixel PXL through line components, and thus control the operation of the pixel PXL. In Figure 2 order to facilitate the description, the line components are omitted.

[0075] The driver can include: a scan driver configured to provide a scan signal to the pixel PXL through a scan line; an emission driver configured to provide an emission control signal to the pixel PXL through an emission control line; a data driver configured to provide a data signal to the pixel PXL through a data line; and a timing controller. The timing controller can control the scan driver, the emission driver, and the data driver.

[0076] Figures 3a to 3c is a schematic circuit diagram showing an example of a first sub-pixel among first to third sub-pixels of a Figure 2 display device according to various embodiments.

[0077] Referring to Figures 3a to 3c each of the first to third sub-pixels can be configured to have an effective pixel. However, there is no particular limitation on the type, configuration, and / or driving method of each of the first to third sub-pixels. For example, each of the first to third sub-pixels can be configured to have a pixel of a passive or active display device that can have various known structures.

[0078] In addition, referring to Figures 3a to 3c each of the first to third sub-pixels can have substantially the same or similar structure. Hereinafter, for convenience, the first sub-pixel among the first to third sub-pixels will be described as a representative example.

[0079] Referring to Figure 1a and Figure 2And Figure 3a , the first sub-pixel SP1 may include a light-emitting circuit 100 and a pixel driving circuit 144. The light-emitting circuit 100 is configured to generate light having a luminance corresponding to a data signal, and the pixel driving circuit 144 is configured to drive the light-emitting circuit 100.

[0080] In an embodiment, the light-emitting circuit 100 may include a light-emitting element LD connected in parallel between a first driving power supply VDD and a second driving power supply VSS. The first driving power supply VDD and the second driving power supply VSS may have different electric potentials. For example, the first driving power supply VDD may be set as a high-potential power supply, and the second driving power supply VSS may be set as a low-potential power supply. Here, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to a threshold voltage or a voltage greater than the threshold voltage of the light-emitting element LD during the emission period of the first sub-pixel SP1. The first electrode (e.g., an anode electrode) of each of the light-emitting elements LD may be connected to the first driving power supply VDD via the pixel driving circuit 144. The second electrode (e.g., a cathode electrode) of each of the light-emitting elements LD may be connected to the second driving power supply VSS.

[0081] Each of the light-emitting elements LD may emit light with a luminance corresponding to a driving current controlled by the pixel driving circuit 144.

[0082] Although Figures 3a to 3c an embodiment in which the light-emitting elements LD are connected in parallel to each other in the same direction (e.g., forward) between the first driving power supply VDD and the second driving power supply VSS is shown, the present disclosure is not limited thereto. For example, in an embodiment, some of the light-emitting elements LD may be connected forward between the first driving power supply VDD and the second driving power supply VSS, while other light-emitting elements of the light-emitting elements LD may be connected reversely. One of the first driving power supply VDD and the second driving power supply VSS may be provided in the form of an alternating voltage. In this case, the light-emitting elements LD in the forward direction and the light-emitting elements LD in the reverse direction may emit light alternately. As another example, in an embodiment, the first sub-pixel SP1 may include only a single light-emitting element LD.

[0083] In an embodiment of the present disclosure, the pixel driving circuit 144 may include a first transistor T1 and a second transistor T2, and a storage capacitor Cst. The structure of the pixel driving circuit 144 is not limited to Figure 3a the structure of the embodiment shown in

[0084] The first electrode of the first transistor T1 (switching transistor) is connected to the data line Dj, and the second electrode of the first transistor T1 is connected to the first node N1. Here, the first and second electrodes of the first transistor T1 may be different electrodes. For example, if the first electrode is the source electrode, the second electrode is the drain electrode. The gate electrode of the first transistor T1 is connected to the scan line Si.

[0085] When a scan signal having a voltage (e.g., a low-level voltage) capable of turning on the first transistor T1 is provided from the scan line Si, the first transistor T1 turns on to electrically connect the data line Dj and the first node N1. Here, the data signal of the corresponding frame is provided to the data line Dj, whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be stored in the storage capacitor Cst.

[0086] The first electrode of the second transistor (T2; driving transistor) is connected to the first driving power supply VDD, and the second electrode of the second transistor T2 is electrically connected to the first electrode of each of the light-emitting elements LD. The gate electrode of the second transistor T2 is connected to the first node N1. Thus, the second transistor T2 can control the amount of driving current to be provided to the light-emitting element LD in response to the voltage of the first node N1.

[0087] One electrode of the storage capacitor Cst is connected to the first driving power supply VDD, and the other electrode of the storage capacitor Cst is connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal provided to the first node N1 and holds the charged voltage until the data signal of a subsequent frame is provided.

[0088] For illustration purposes, Figure 3a A pixel driving circuit 144 having a relatively simple structure is shown, which includes a first transistor T1 configured to transmit a data signal to the first sub-pixel SP1, a storage capacitor Cst configured to store the data signal, and a second transistor T2 configured to provide a driving current corresponding to the data signal to the light-emitting element LD.

[0089] However, the present disclosure is not limited thereto, and the structure of the pixel driving circuit 144 can be changed in various ways. For example, the pixel driving circuit 144 may further include at least one transistor (such as a transistor configured to compensate for the threshold voltage of the second transistor T2, a transistor configured to initialize the first node N1, and / or a transistor configured to control the emission time of the light-emitting element LD) or other circuit elements (such as a boosting capacitor for raising the voltage of the first node N1).

[0090] In addition, although in Figure 3aIn [the figure], the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel driving circuit 144 are shown as P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel driving circuit 144 may be changed to an N-type transistor.

[0091] Referring to Figure 1a , Figure 2 and Figure 3b , the first transistor T1 and the second transistor T2 according to an embodiment of the present disclosure may be formed of N-type transistors. Except for the change in the connection positions of some components due to the change in the transistor type, Figure 3b the configuration and operation of the pixel driving circuit 144 shown in Figure 3a are similar to the configuration and operation of the pixel driving circuit 144 of

[0092] Therefore, a detailed description will be omitted.

[0092] In an embodiment of the present disclosure, the configuration of the pixel driving circuit 144 is not limited to the embodiment shown in Figure 3a and Figure 3b . For example, the pixel driving circuit 144 may be configured in the same manner as the embodiment shown in Figure 3c .

[0093] Referring to Figure 1a , Figure 2 and Figure 3c , the pixel driving circuit 144 may be connected to the scan line Si and the data line Dj of the first sub-pixel SP1. For example, if the first sub-pixel SP1 is disposed in the i-th row and the j-th column of the display area DA, the pixel driving circuit 144 of the first sub-pixel SP1 may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0094] In an embodiment, the pixel driving circuit 144 may also be connected to at least one scan line. For example, the first sub-pixel SP1 disposed in the i-th row of the display area DA may be further connected to the (i - 1)-th scan line Si-1 and / or the (i + 1)-th scan line Si+1.

[0095] In an embodiment, the pixel driving circuit 144 may be connected not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, the pixel driving circuit 144 may also be connected to the initialization power supply Vint.

[0096] The pixel driving circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0097] The first electrode (e.g., the source electrode) of the first transistor T1 (driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and the second electrode (e.g., the drain electrode) of the first transistor T1 can be connected to one end of each of the light-emitting elements LD via the sixth transistor T6. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the driving current flowing through the light-emitting element LD between the first driving power supply VDD and the second driving power supply VSS in response to the voltage of the first node N1.

[0098] The second transistor T2 (switching transistor) can be connected between the j-th data line Dj connected to the first sub-pixel SP1 and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the i-th scan line Si connected to the first sub-pixel SP1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is provided from the i-th scan line Si, the second transistor T2 is turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the j-th data line Dj can be transmitted to the first transistor T1.

[0099] The third transistor T3 is connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the i-th scan line Si. When a scan signal having a gate-on voltage is provided from the i-th scan line Si, the third transistor T3 is turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 can be connected in the form of a diode.

[0100] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, e.g., the (i - 1)-th scan line Si - 1. When a scan signal having a gate-on voltage is provided to the (i - 1)-th scan line Si - 1, the fourth transistor T4 is turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. Here, the initialization power supply Vint can have a voltage equal to or less than the minimum voltage of the data signal.

[0101] The fifth transistor T5 is connected between the first driving power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, e.g., the i-th emission control line Ei. The fifth transistor T5 can be turned off when an emission control signal having a gate cut-off voltage is provided to the i-th emission control line Ei, and can be turned on in other cases.

[0102] The sixth transistor T6 is connected between the first transistor T1 and the first end of the light-emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be cut off when an emission control signal having a gate cut-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0103] The seventh transistor T7 is connected between the first end of the light-emitting element LD and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to one of the scan lines of the subsequent stage, for example, connected to the (i + 1)-th scan line Si+1. When a scan signal having a gate conduction voltage is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint can be supplied to the first end of the light-emitting element LD.

[0104] The storage capacitor Cst is connected between the first driving power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to both the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0105] For convenience, Figure 3c it is shown that the first transistor T1 to the seventh transistor T7 are all formed as P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 included in the pixel driving circuit 144 may be formed as an N-type transistor, or all of the first transistor T1 to the seventh transistor T7 may be formed as N-type transistors.

[0106] Figure 4 is Figure 2 a schematic enlarged plan view of the region EA1 of. Figure 5 is a schematic cross-sectional view taken along Figure 4 the line I-I' of.

[0107] For illustration, Figure 4 the first pixel to the third pixel are schematically shown, the first pixel to the third pixel are arranged adjacent to each other in the column direction, and each of the first pixel to the third pixel includes three sub-pixels arranged adjacent to each other in the row direction. Specifically, for the first pixel to the third pixel adjacent to each other in the column direction (e.g., in the vertical direction) in the display area, Figure 4 the three sub-pixels included in each of the first pixel to the third pixel are shown.

[0108] In Figure 4In [the figure], for illustrative purposes, the light-emitting elements provided in each sub-pixel are shown as being horizontally aligned. However, the alignment of the light-emitting elements is not limited thereto. For example, at least some of the light-emitting elements may be aligned in a direction intersecting the horizontal direction.

[0109] In addition, for illustrative purposes, Figure 4 the illustration of the transistors connected to the light-emitting elements and the signal lines connected to the transistors has been omitted in [the figure].

[0110] In addition, although Figure 4 and Figure 5 show the simplified structures of each of the first pixel to the third pixel, for example, each electrode is shown as having only a single electrode layer, but the present disclosure is not limited thereto.

[0111] Referring to Figure 1a 、 Figure 2 、 Figure 4 and Figure 5 According to an embodiment of the present disclosure, a display device may include a substrate SUB, on which pixels PXL are provided. For illustrative purposes, the following description of the embodiment will focus on three pixels, for example, a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3, which are arranged adjacent to each other in the column direction of the substrate SUB among the pixels PXL.

[0112] The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be arranged adjacent to each other on the substrate SUB in a second direction DR2. In an embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include at least one sub-pixel.

[0113] In an embodiment of the present disclosure, the first pixel PXL1 may include three sub-pixels arranged adjacent to each other on the substrate SUB in a first direction DR1, for example, a first sub-pixel SP1_1, a second sub-pixel SP2_1, and a third sub-pixel SP3_1. The first sub-pixel SP1_1 may be provided on the first column C1 and the first row R1 of the substrate SUB. The second sub-pixel SP2_1 may be provided on the second column C2 and the first row R1 of the substrate SUB. The third sub-pixel SP3_1 may be provided on the third column C3 and the first row R1 of the substrate SUB.

[0114] Each of the first first sub-pixel SP1_1, the second first sub-pixel SP2_1, and the third first sub-pixel SP3_1 may include an emission circuit 100 configured to emit light (hereinafter referred to as an "emission region"), and a non-emission region 200 disposed around the periphery of the emission region 100 and not emitting light therethrough. In an embodiment of the present disclosure, the pixel region of each of the first first sub-pixel SP1_1, the second first sub-pixel SP2_1, and the third first sub-pixel SP3_1 may include the emission region 100 and the non-emission region 200 of the corresponding sub-pixel. The substrate SUB, the pixel circuit layer PCL, and the display element layer DPL may be disposed in the pixel region of each of the first first sub-pixel SP1_1, the second first sub-pixel SP2_1, and the third first sub-pixel SP3_1.

[0115] In an embodiment of the present disclosure, the second pixel PXL2 may include three sub-pixels disposed adjacent to each other in a first direction DR1 on the substrate SUB, for example, the first second sub-pixel SP1_2, the second second sub-pixel SP2_2, and the third second sub-pixel SP3_2. The first second sub-pixel SP1_2 may be disposed on the first column C1 and the second row R2 of the substrate SUB. The second second sub-pixel SP2_2 may be disposed on the second column C2 and the second row R2 of the substrate SUB. The third second sub-pixel SP3_2 may be disposed on the third column C3 and the second row R2 of the substrate SUB.

[0116] Each of the first second sub-pixel SP1_2, the second second sub-pixel SP2_2, and the third second sub-pixel SP3_2 may include an emission region 100 configured to emit light, and a non-emission region 200 disposed around the periphery of the emission region 100. In an embodiment of the present disclosure, the pixel region of each of the first second sub-pixel SP1_2, the second second sub-pixel SP2_2, and the third second sub-pixel SP3_2 may include the emission region 100 and the non-emission region 200 of the corresponding sub-pixel. The substrate SUB, the pixel circuit layer PCL, and the display element layer DPL may be disposed in the pixel region of each of the first second sub-pixel SP1_2, the second second sub-pixel SP2_2, and the third second sub-pixel SP3_2.

[0117] In an embodiment of the present disclosure, the third pixel PXL3 may include three sub-pixels disposed adjacent to each other in a first direction DR1 on a substrate SUB. For example, the first-third sub-pixel SP1_3, the second-third sub-pixel SP2_3, and the third-third sub-pixel SP3_3. The first-third sub-pixel SP1_3 may be disposed on the first column C1 and the third row R3 of the substrate SUB. The second-third sub-pixel SP2_3 may be a sub-pixel disposed on the second column C2 and the third row R3 of the substrate SUB. The third-third sub-pixel SP3_3 may be disposed on the third column C3 and the third row R3 of the substrate SUB.

[0118] Each of the first-third sub-pixel SP1_3, the second-third sub-pixel SP2_3, and the third-third sub-pixel SP3_3 may include an emission region 100 configured to emit light, and a non-emission region 200 disposed to surround the periphery of the emission region 100. In an embodiment of the present disclosure, the pixel region of each of the first-third sub-pixel SP1_3, the second-third sub-pixel SP2_3, and the third-third sub-pixel SP3_3 may include the emission region 100 and the non-emission region 200 of the corresponding sub-pixel. The substrate SUB, the pixel circuit layer PCL, and the display element layer DPL may be disposed in the pixel region of each of the first-third sub-pixel SP1_3, the second-third sub-pixel SP2_3, and the third-third sub-pixel SP3_3.

[0119] The pixel circuit layer PCL of each of the nine sub-pixels SP1_1, SP2_1, SP3_1, SP1_2, SP2_2, SP3_2, SP1_3, SP2_3, and SP3_3 may include a buffer layer BFL disposed on the substrate SUB, a first transistor T1 and a second transistor T2 disposed on the buffer layer BFL, and a driving voltage line DVL. In addition, the pixel circuit layer PCL may further include a passivation layer PSV disposed on the first transistor T1, the second transistor T2, and the driving voltage line DVL.

[0120] The substrate SUB may include an insulating material such as glass, an organic polymer, or a crystal. In addition, the substrate SUB may be made of a flexible material so as to be bendable or foldable, and have a single-layer or multi-layer structure.

[0121] The buffer layer BFL may be disposed on the substrate SUB and prevent impurities from diffusing into the first transistor T1 and the second transistor T2. Depending on, for example, the material or processing conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0122] The first transistor T1 may be a driving transistor, which is electrically connected to some of the light-emitting elements LD provided in the display element layer DPL of the corresponding sub-pixel to drive the light-emitting element LD. The second transistor T2 may correspond to a switching transistor configured to switch the first transistor T1.

[0123] Each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, and a source electrode SE and a drain electrode DE.

[0124] The semiconductor layer SCL may be provided on the buffer layer BFL. The semiconductor layer SCL may include a source region in contact with the source electrode SE and a drain region in contact with the drain electrode DE. The region between the source region and the drain region may be a channel region.

[0125] The semiconductor layer SCL may include a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the source region and the drain region may include a semiconductor pattern doped with impurities.

[0126] The gate electrode GE may be provided on the semiconductor layer SCL, and a gate insulating layer GI is interposed between the gate electrode GE and the semiconductor layer SCL.

[0127] The source electrode SE and the drain electrode DE may be in contact with the source region and the drain region of the semiconductor layer SCL through corresponding contact holes penetrating the interlayer insulating layer ILD and the gate insulating layer GI, respectively.

[0128] The driving voltage line DVL may be provided on the interlayer insulating layer ILD, but the present disclosure is not limited thereto. In some embodiments, the driving voltage line DVL may be provided on one of the insulating layers included in the pixel circuit layer PCL. The second driving power supply VSS (see Figure 3a ) may be applied to the driving voltage line DVL.

[0129] The passivation layer PSV may include a first contact hole CH1 exposing at least a part of the drain electrode DE of the first transistor T1, and a second contact hole CH2 exposing at least a part of the driving voltage line DVL.

[0130] The display element layer DPL of each of the nine sub-pixels SP1_1, SP2_1, SP3_1, SP1_2, SP2_2, SP3_2, SP1_3, SP2_3, and SP3_3 may include a partition wall (or wall) PW provided on the passivation layer PSV, a first electrode EL1 and a second electrode EL2, a first connection line CNL1, a second connection line CNL2, a light-emitting element LD, and a first contact electrode CNE1 and a second contact electrode CNE2.

[0131] The partition wall PW can be disposed in the emission region 100 of each of the nine sub-pixels SP1_1, SP2_1, SP3_1, SP1_2, SP2_2, SP3_2, SP1_3, SP2_3, and SP3_3 on the passivation layer PSV. Although not shown, a pixel defining layer (or dam layer) can be formed and / or disposed in the non-emission region 200 between adjacent sub-pixels to define the emission region 100 of each sub-pixel, wherein the pixel defining layer (or dam layer) is formed of the same material as that of the partition wall PW.

[0132] The partition wall PW can be spaced apart from an adjacent partition wall PW disposed there-nearby by a predetermined distance on the passivation layer PSV. Two adjacent partition walls PW can be disposed on the passivation layer PSV and spaced apart from each other by a length L of a light-emitting element LD. As Figure 5 shown, the partition wall PW can include a curved surface having a cross-sectional shape (such as a semi-circular or semi-elliptical shape) with a width decreasing from one surface of the passivation layer PSV toward its upper end, but the present disclosure is not limited thereto.

[0133] In an embodiment, the partition wall PW can have a trapezoidal cross-section with a width decreasing from one surface of the passivation layer PSV toward its upper end. In a cross-sectional view, the shape of each of the partition walls PW is not limited to the above examples and can be changed in various ways as long as the efficiency of light emitted from each of the light-emitting elements LD can be enhanced. Two adjacent partition walls PW can be disposed on the passivation layer PSV in the same plane and have the same height.

[0134] In an embodiment of the present disclosure, each of the light-emitting elements LD can be formed of a light-emitting diode including a material having an inorganic crystal structure and having an ultra-small size, for example, in a range from the nanometer scale to the micrometer scale. The light-emitting element LD can be disposed in the emission region 100 of each sub-pixel and emit light.

[0135] Each of the light-emitting elements LD can include a first conductive semiconductor layer 11, a second conductive semiconductor layer 13, and an active layer 12 interposed between the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. In some embodiments, each of the light-emitting elements LD can further include an electrode layer 15 disposed on one side of the second conductive semiconductor layer 13.

[0136] Each of the light-emitting elements LD can include a first end EP1 and a second end EP2. One of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 can be disposed on the first end EP1, and the other of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 can be disposed on the second end EP2. In an embodiment of the present disclosure, each of the light-emitting elements LD can emit any one of colored light and / or white light.

[0137] A second insulating layer INS2 covering a part of the upper surface of each of the light-emitting elements LD may be provided on the light-emitting elements LD. Accordingly, opposite ends EP1 and EP2 of each of the light-emitting elements LD may be exposed to the outside.

[0138] A first insulating layer INS1 may be provided under each of the light-emitting elements LD. The first insulating layer INS1 may fill a space between the passivation layer PSV and each of the light-emitting elements LD to stably support the light-emitting elements LD and prevent the light-emitting elements LD from being removed from the passivation layer PSV. The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0139] A first connection line CNL1 and a second connection line CNL2 may be provided in a non-emitting region 200 of each sub-pixel.

[0140] The second connection line CNL2 may extend from the non-emitting region 200 of each sub-pixel to the non-emitting region 200 of an adjacent sub-pixel. For example, the second connection line CNL2 provided in the non-emitting region 200 of the 1-1 sub-pixel SP1_1 may extend in a first direction DR1 to sub-pixels adjacent to the 1-1 sub-pixel SP1_1 (i.e., the 2-1 sub-pixel SP2_1 and the 3-1 sub-pixel SP3_1). The second connection line CNL2 may be provided to be shared among the 1-1 sub-pixel SP1_1, the 2-1 sub-pixel SP2_1, and the 3-1 sub-pixel SP3_1.

[0141] The first connection line CNL1 may be provided only in the non-emitting region 200 of a corresponding sub-pixel to independently drive each sub-pixel. For example, the first connection line CNL1 provided in the non-emitting region 200 of the 1-1 sub-pixel SP1_1 may be electrically separated and / or physically separated from the first connection line CNL1 provided in the non-emitting region 200 of the 2-1 sub-pixel SP2_1 adjacent to the 1-1 sub-pixel SP1_1. The first connection line CNL1 provided in the non-emitting region 200 of the 2-1 sub-pixel SP2_1 may be electrically separated and / or physically separated from the first connection line CNL1 provided in the non-emitting region 200 of the 3-1 sub-pixel SP3_1 adjacent to the 2-1 sub-pixel SP2_1.

[0142] The first connection line CNL1 and the second connection line CNL2 may be provided on the same layer and include the same material.

[0143] The first electrode EL1 and the second electrode EL2 may be disposed in the emission region 100 of each sub-pixel, and each of the first electrode EL1 and the second electrode EL2 may have a strip shape extending in a second direction DR2 intersecting the first direction DR1. The first electrode EL1 and the second electrode EL2 may be disposed on the same plane and spaced apart from each other by a predetermined distance.

[0144] The first electrode EL1 may include a first-1 electrode EL1_1 and a first-2 electrode EL1_2, wherein the first-1 electrode EL1_1 and the first-2 electrode EL1_2 branch from a first connection line CNL1 extending in the first direction DR1 into the emission region 100 of each sub-pixel in the second direction DR2. The first-1 electrode EL1_1, the first-2 electrode EL1_2, and the first connection line CNL1 may be integral with each other and electrically connected and / or physically connected to each other.

[0145] The second electrode EL2 may extend in the second direction DR2 and may be electrically connected to a second connection line CNL2. In an embodiment of the present disclosure, the second electrode EL2 may branch from the second connection line CNL2 into the emission region 100 of each sub-pixel in the second direction DR2. The second electrode EL2 and the second connection line CNL2 may be integral with each other and electrically connected and / or physically connected to each other.

[0146] Each of the first electrode EL1 and the second electrode EL2 may be used as an alignment electrode to align the light-emitting element LD in the emission region 100 of each sub-pixel.

[0147] Before aligning the light-emitting element LD in the emission region 100 of each sub-pixel, a first alignment voltage may be applied to the first electrode EL1 through the first connection line CNL1, and a second alignment voltage may be applied to the second electrode EL2 through the second connection line CNL2. The first alignment voltage and the second alignment voltage may have different voltage levels. When predetermined alignment voltages having different voltage levels are respectively applied to the first electrode EL1 and the second electrode EL2, an electric field may be formed between the first electrode EL1 and the second electrode EL2. Accordingly, the light-emitting element LD may be aligned between the first electrode EL1 and the second electrode EL2 on the passivation layer PSV.

[0148] In a plan view, the second electrode EL2 may be disposed between the first-1 electrode EL1_1 and the first-2 electrode EL1_2 and spaced apart from each of the first-1 electrode EL1_1 and the first-2 electrode EL1_2 by a predetermined distance. The first-1 electrode EL1_1, the first-2 electrode EL1_2, and the second electrode EL2 may be alternately disposed on the passivation layer PSV.

[0149] After the light-emitting element LD is aligned in the emission region 100 of each sub-pixel, each of the first electrode EL1 and the second electrode EL2 can serve as a driving electrode for driving the light-emitting element LD.

[0150] The first electrode EL1 and the second electrode EL2 can be made of a material having a predetermined reflectivity to allow the light emitted from the opposite ends EP1 and EP2 of each of the light-emitting elements LD to travel in the direction in which the image of the display device is displayed (e.g., in the forward direction).

[0151] In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2, the first connection line CNL1, and the second connection line CNL2 can be provided on the same layer and formed of the same material.

[0152] The first electrode EL1 and the second electrode EL2, the first connection line CNL1, and the second connection line CNL2 can be formed of a conductive material having a predetermined reflectivity. The conductive material can include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or their alloys, conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), and conductive polymers such as PEDOT. The materials of the first electrode EL1 and the second electrode EL2, the first connection line CNL1, and the second connection line CNL2 are not limited to the above materials.

[0153] Each of the first electrode EL1 and the second electrode EL2, the first connection line CNL1, and the second connection line CNL2 can have a single-layer structure, but the present disclosure is not limited thereto. For example, it can have a multilayer structure formed by stacking two or more materials of metals, alloys, conductive oxides, and conductive polymers. In an embodiment, each of the first electrode EL1 and the second electrode EL2, the first connection line CNL1, and the second connection line CNL2 can have a multilayer structure so as to minimize the voltage drop due to signal delay in the case of transmitting signals to the opposite ends EP1 and EP2 of each of the light-emitting elements LD.

[0154] Since the first electrode EL1 and the second electrode EL2 have a shape corresponding to the shape of the partition wall PW, the light emitted from the opposite ends EP1 and EP2 of each of the light-emitting elements LD can be reflected by the first electrode EL1 and the second electrode EL2 and travel more effectively in the forward direction of the display device. Therefore, the efficiency of the light emitted from the light-emitting element LD can be enhanced.

[0155] In an embodiment of the present disclosure, the partition wall PW and the first electrode EL1 and the second electrode EL2 can be used as reflection components that enable the light emitted from each of the light-emitting elements LD to travel in the forward direction of the display device, thereby enhancing the light output efficiency of the light-emitting elements LD.

[0156] Any one of the first electrode EL1 and the second electrode EL2 can correspond to the anode electrode, and the other can correspond to the cathode electrode. In an embodiment of the present disclosure, the first electrode EL1 can be the anode electrode, and the second electrode EL2 can be the cathode electrode.

[0157] In an embodiment of the present disclosure, the light-emitting element LD can include a first light-emitting element LD1 aligned between the 1-1 electrode EL1_1 and the second electrode EL2, and a second light-emitting element LD2 aligned between the second electrode EL2 and the 1-2 electrode EL1_2.

[0158] In an embodiment of the present disclosure, the first connection line CNL1 can be electrically connected to the drain electrode DE of the first transistor T1 through the first contact hole CH1 of the passivation layer PSV. Since the first connection line CNL1 and the first electrode EL1 are integrated, the signal of the first transistor T1 applied to the first connection line CNL1 can be transmitted to the first electrode EL1.

[0159] The first electrode EL1 can be arranged adjacent to one end of the opposite ends EP1 and EP2 of each of the light-emitting elements LD, and can be electrically connected to each of the light-emitting elements LD through the first contact electrode CNE1. Therefore, the signal of the first transistor T1 applied to the first electrode EL1 can be transmitted to each of the light-emitting elements LD through the first contact electrode CNE1.

[0160] In an embodiment of the present disclosure, the second connection line CNL2 can be electrically connected to the driving voltage line DVL through the second contact hole CH2 of the passivation layer PSV. Since the second connection line CNL2 and the second electrode EL2 are integrated, the voltage of the second driving power supply VSS of the driving voltage line DVL applied to the second connection line CNL2 can be transmitted to the second electrode EL2.

[0161] The second electrode EL2 can be arranged adjacent to the other end of the opposite ends EP1 and EP2 of each of the light-emitting elements LD, and can be electrically connected to each of the light-emitting elements LD through the second contact electrode CNE2. Therefore, the voltage of the second driving power supply VSS applied to the second electrode EL2 can be transmitted to each of the light-emitting elements LD.

[0162] The first contact electrode CNE1 may be disposed on the first electrode EL1 to electrically connect and / or physically and reliably connect one end of each of the opposite ends EP1 and EP2 of the first electrode EL1 to the light-emitting element LD. The first contact electrode CNE1 may be formed of a transparent conductive material to allow light emitted from each of the light-emitting elements LD and reflected by the first electrode EL1 to travel in the forward direction of the display device without loss in the forward direction.

[0163] In a plan view, the first contact electrode CNE1 may cover and overlap the first electrode EL1. In addition, the first contact electrode CNE1 may partially overlap one of the opposite ends EP1 and EP2 of each of the light-emitting elements LD.

[0164] In an embodiment of the present disclosure, the first contact electrode CNE1 may include a first - 1 contact electrode CNE1_1 disposed on the first - 1 electrode EL1_1 and a first - 2 contact electrode CNE1_2 disposed on the first - 2 electrode EL1_2. In a plan view, the first - 1 contact electrode CNE1_1 may overlap the first ends EP1 of each of the first light - emitting elements LD1 and the first - 1 electrode EL1_1. In a plan view, the first - 2 contact electrode CNE1_2 may overlap the second ends EP2 of each of the second light - emitting elements LD2 and the first - 2 electrode EL1_2.

[0165] A third insulating layer INS3 covering the first contact electrode CNE1 may be disposed on the first contact electrode CNE1. The third insulating layer INS3 may prevent the first contact electrode CNE1 from being exposed to the outside, thereby preventing corrosion of the first contact electrode CNE1.

[0166] The third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although the third insulating layer INS3 may have a single - layer structure as shown in the figure, the present disclosure is not limited thereto. For example, the third insulating layer INS3 may have a multi - layer structure. In the case where the third insulating layer INS3 has a multi - layer structure, the third insulating layer INS3 may have a structure formed by alternately stacking an inorganic insulating layer and an organic insulating layer. For example, the third insulating layer INS3 may have a structure formed by sequentially stacking a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer.

[0167] The second contact electrode CNE2 can be disposed on the second electrode EL2. In a plan view, the second contact electrode CNE2 can cover and overlap with the second electrode EL2. In addition, the second contact electrode CNE2 can overlap with the second ends EP2 of each of the first light-emitting elements LD1 and the first ends EP1 of each of the second light-emitting elements LD2. The second contact electrode CNE2 and the first contact electrode CNE1 can be made of the same material, but the present disclosure is not limited thereto.

[0168] A fourth insulating layer INS4 covering the second contact electrode CNE2 can be disposed on the second contact electrode CNE2. The fourth insulating layer INS4 can prevent the second contact electrode CNE2 from being exposed to the outside, thereby preventing the second contact electrode CNE2 from being corroded. The fourth insulating layer INS4 can be formed of an inorganic insulating layer or an organic insulating layer.

[0169] An outer coating OC can be provided on the fourth insulating layer INS4. The outer coating OC can be a planarization layer that reduces the step difference formed by the partition wall PW, the first electrode EL1 and the second electrode EL2, the first contact electrode CNE1 and the second contact electrode CNE2, etc. disposed below the outer coating OC. The outer coating OC can be a packaging layer that prevents oxygen, water, etc. from infiltrating into the light-emitting element LD. In some embodiments, the outer coating OC can be omitted.

[0170] As described above, a predetermined voltage can be applied to the opposite ends EP1 and EP2 of each of the light-emitting elements LD through the first electrode EL1 and the second electrode EL2, respectively. Therefore, each of the light-emitting elements LD can emit light through the recombination of electron-hole pairs in the active layer 12 of each of the light-emitting elements LD. Here, the active layer 12 can emit light having a wavelength range from 400 nm to 900 nm.

[0171] A first capping layer CPL1_1 and CPL1_2 and a second capping layer CPL2 can be further provided in the emission region 100 of each sub-pixel.

[0172] The first capping layers CPL1_1 and CPL1_2 can include a first capping layer CPL1_1 disposed on the 1-1 electrode EL1_1 and a first capping layer CPL1_2 disposed on the 1-2 electrode EL1_2. The second capping layer CPL2 can be disposed on the second electrode EL2. The first capping layer CPL1_1, the first capping layer CPL1_2, and the second capping layer CPL2 can prevent the corresponding electrodes from being damaged by defects that may occur during the manufacturing process of the display device, and can further enhance the adhesion between the corresponding electrodes and the passivation layer PSV.

[0173] The first capping layer CPL1_1, the first capping layer CPL1_2, and the second capping layer CPL2 may be formed of a transparent conductive material such as IZO so as to minimize the loss of light emitted from each of the light emitting elements LD and reflected by the corresponding electrode in the forward direction of the display device. The first capping layer CPL1_1, the first capping layer CPL1_2, and the second capping layer CPL2 may be disposed on the same layer and include the same material.

[0174] In an embodiment of the present disclosure, the non-emitting region 200 may be disposed between the corresponding emitting regions 100 of two sub-pixels adjacent to each other in the second direction DR2 (e.g., in the column direction). For example, the non-emitting region 200 may be disposed between the emitting region 100 of the first sub-pixel SP1_1 disposed on the first column C1 and the emitting region 100 of the first sub-pixel SP1_2. Hereinafter, for the sake of explanation, the region formed between the corresponding emitting regions 100 of two adjacent sub-pixels disposed on the same column in the second direction DR2, the non-emitting region 200, may be designated as a pixel boundary region, and the reference numeral "300" will be used to designate the pixel boundary region and prevent confusion with the term "non-emitting region 200".

[0175] Two connection lines may be disposed in the sub-pixel boundary region 300 (hereinafter, referred to as the "first sub-pixel boundary region") disposed between the emitting region 100 of the first sub-pixel SP1_1 and the emitting region 100 of the first sub-pixel SP1_2. The two connection lines may include a first connection line CNL1 disposed in the first sub-pixel SP1_1 and a first connection line CNL1 disposed in the first sub-pixel SP1_2.

[0176] Hereinafter, for the sake of explanation, the first connection line CNL1 of the first sub-pixel SP1_1 disposed in the first sub-pixel boundary region 300 will be referred to as the first connection line 1-1, and the first connection line CNL1 of the first sub-pixel SP1_2 will be referred to as the first connection line 1-2.

[0177] The first connection line CNL1 and the first connection line CNL1 may be disposed in the first sub-pixel boundary region 300 and spaced apart from each other by a predetermined distance, and thus electrically separated and / or physically separated from each other. An imaginary line IL extending in the first direction DR1 may be disposed between the first connection line CNL1 and the first connection line CNL1. The first connection line CNL1 and the first connection line CNL1 may form a mirror-symmetrical structure based on the imaginary line IL. The first connection line CNL1 may be disposed on the upper side in the second direction DR2 based on the imaginary line IL, and the first connection line CNL1 may be disposed on the lower side in the second direction DR2 based on the imaginary line IL.

[0178] The first connection line CNL1_1 can be electrically connected and / or physically connected to the first electrode EL1 of the first sub-pixel SP1_1. The first electrode EL1 of the first sub-pixel SP1_1 can branch upward from the first connection line CNL1_1 in the second direction DR2, and is thus disposed in the emission region 100 of the first sub-pixel SP1_1. In a plan view, the first connection line CNL1_1 and the first electrode EL1 disposed in the first sub-pixel SP1_1 can have an "╨" shape, but the present disclosure is not limited thereto. In the "╨" shaped portion, the "─" shaped portion (which extends in the first direction DR1) can be the first connection line CNL1_1, and the "ll" shaped portion that branches upward from the "─" shaped portion in the second direction DR2 can be the first electrode EL1 of the first sub-pixel SP1_1.

[0179] The first connection line CNL1_2 can be electrically connected and / or physically connected to the first electrode EL1 of the first sub-pixel SP1_2. The first electrode EL1 of the first sub-pixel SP1_2 can branch downward from the first connection line CNL1_2 in the second direction DR2, and is thereby disposed in the emission region 100 of the first sub-pixel SP1_2. In a plan view, the first connection line CNL1_2 and the first electrode EL1 disposed in the first sub-pixel SP1_2 can have a "╥" shape, but the present disclosure is not limited thereto. In the "╥" shaped portion, the "─" shaped portion (which extends in the first direction DR1) can be the first connection line CNL1_2, and the "ll" shaped portion that branches downward from the "─" shaped portion in the second direction DR2 can be the first electrode EL1 of the first sub-pixel SP1_2.

[0180] In a plan view, the second connection line CNL2 connected to the second electrode EL2 of the first sub-pixel SP1_1 can be disposed on the upper side of the first connection line CNL1_1 in the second direction DR2. In a plan view, the second connection line CNL2 connected to the second electrode EL2 of the first sub-pixel SP1_2 can be disposed on the lower side of the first connection line CNL1_2 in the second direction DR2. The second connection line CNL2 connected to the second electrode EL2 of the first sub-pixel SP1_1 and the second connection line CNL2 connected to the second electrode EL2 of the first sub-pixel SP1_2 can be spaced apart from each other, and the corresponding emission regions 100 of the first sub-pixel SP1_1 and the first sub-pixel SP1_2 are interposed therebetween.

[0181] As described above, the first connection line CNL1 and the second connection line CNL1 forming a mirror-symmetric structure based on the imaginary line IL can be disposed in the first sub-pixel boundary region 300 between the corresponding emission regions 100 of the first sub-pixel SP1_1 and the second sub-pixel SP1_2, where the first sub-pixel SP1_1 and the second sub-pixel SP1_2 are arranged adjacent to each other in the second direction DR2. When the light-emitting elements LD are aligned in the corresponding sub-pixels, the first connection line CNL1 and the second connection line CNL1 disposed in the first sub-pixel boundary region 300 can transmit the same alignment voltage to the first electrodes EL1 of the corresponding sub-pixels.

[0182] For example, the first connection line CNL1 can provide a first alignment voltage to the first electrode EL1 of the first sub-pixel SP1_1, and the second connection line CNL1 can provide a first alignment voltage to the first electrode EL1 of the second sub-pixel SP1_2. In an embodiment of the present disclosure, a ground voltage can be applied as the first alignment voltage to the first connection line CNL1 and the second connection line CNL1, but the present disclosure is not limited thereto. In an embodiment, an AC voltage or a DC voltage maintained at a constant voltage level can be applied as the first alignment voltage to the first connection line CNL1 and the second connection line CNL1.

[0183] In an embodiment of the present disclosure, since the first alignment voltages having the same electric potential are respectively applied to the first connection line CNL1 and the second connection line CNL1, an electric field for aligning the light-emitting elements LD is not formed between the first connection line CNL1 and the second connection line CNL1 disposed in the first sub-pixel boundary region 300.

[0184] Therefore, the light-emitting elements LD are not aligned in the first sub-pixel boundary region 300 (which is a non-emission region 200), and the light-emitting elements LD can be only concentratedly aligned in the target region (for example, concentratedly aligned in the emission region 100 of each sub-pixel). As a result, in an embodiment of the present disclosure, the light-emitting elements LD are only concentratedly aligned in the target region of each sub-pixel (that is, only concentratedly aligned in the emission region 100), thereby abnormal alignment defects in which the light-emitting elements LD are aligned in an undesired region (for example, the sub-pixel boundary region 300) can be prevented.

[0185] In addition, since the light-emitting elements LD are concentrated and aligned in the emission regions 100 of each sub-pixel, contact failures between the light-emitting elements LD and the electrodes electrically connected to the light-emitting elements LD can be minimized. In an embodiment of the present disclosure, the electrodes may include a first electrode EL1 and a second electrode EL2, but the present disclosure is not limited thereto. In an embodiment, the electrodes may include a first contact electrode CNE1 and a second contact electrode CNE2.

[0186] The sub-pixel boundary region 300 may also be provided between the respective emission regions 100 of the 2-1 sub-pixel SP2_1 and the 2-2 sub-pixel SP2_2 arranged adjacent to each other in the second direction DR2. Two first connection lines CNL1 having a mirror-symmetrical structure may also be provided in the sub-pixel boundary region 300. Similarly, the sub-pixel boundary region 300 may also be provided between the respective emission regions 100 of the 3-1 sub-pixel SP3_1 and the 3-2 sub-pixel SP3_2 arranged adjacent to each other in the second direction DR2. Two first connection lines CNL1 having a mirror-symmetrical structure may also be provided in the sub-pixel boundary region 300.

[0187] In an embodiment of the present disclosure, the sub-pixel boundary region 300 (hereinafter referred to as the "second sub-pixel boundary region") may also be provided between the respective emission regions 100 of the 2-2 sub-pixel SP2_2 and the 2-3 sub-pixel SP2_3 arranged adjacent to each other in the second direction DR2. Two connection lines may be provided in the second sub-pixel boundary region 300. The two connection lines may include a second connection line CNL2 provided in the 2-2 sub-pixel SP2_2 and a second connection line CNL2 provided in the 2-3 sub-pixel SP2_3.

[0188] Hereinafter, for the sake of explanation, the second connection line CNL2 of the 2-2 sub-pixel SP2_2 provided in the second sub-pixel boundary region 300 will be referred to as the 2-1 connection line, and the second connection line CNL2 provided in the 2-3 sub-pixel SP2_3 will be referred to as the 2-2 connection line.

[0189] The 2-1 connection line CNL2 and the 2-2 connection line CNL2 may be disposed in the second sub-pixel boundary region 300, and spaced apart from each other by a predetermined distance, and thus electrically separated and / or physically separated from each other. An imaginary line IL extending in the first direction DR1 may be disposed between the 2-1 connection line CNL2 and the 2-2 connection line CNL2. The 2-1 connection line CNL2 and the 2-2 connection line CNL2 may form a mirror-symmetric structure based on the imaginary line IL. The 2-1 connection line CNL2 may be disposed on the upper side in the second direction DR2 with respect to the imaginary line IL, and the 2-2 connection line CNL2 may be disposed on the lower side in the second direction DR2 with respect to the imaginary line IL.

[0190] The 2-1 connection line CNL2 may be electrically connected and / or physically connected to the second electrode EL2 of the 2-2 sub-pixel SP2_2. The second electrode EL2 of the 2-2 sub-pixel SP2_2 may branch upward from the 2-1 connection line CNL2 in the second direction DR2, and thus be disposed in the emission region 100 of the 2-2 sub-pixel SP2_2. In a plan view, the 2-1 connection line CNL2 and the second electrode EL2 disposed in the 2-2 sub-pixel SP2_2 may have an "┴" shape, but the present disclosure is not limited thereto. In the "┴" shaped portion, the "─" shaped portion (which extends in the first direction DR1) may be the 2-1 connection line CNL2, and the "l" shaped portion that branches upward from the "─" shaped portion in the second direction DR2 may be the second electrode EL2 of the 2-2 sub-pixel SP2_2.

[0191] The 2-2 connection line CNL2 may be electrically connected and / or physically connected to the second electrode EL2 of the 2-3 sub-pixel SP2_3. The second electrode EL2 of the 2-3 sub-pixel SP2_3 may branch downward from the 2-2 connection line CNL2 in the second direction DR2, and thus be disposed in the emission region 100 of the 2-3 sub-pixel SP2_3. In a plan view, the 2-2 connection line CNL2 and the second electrode EL2 disposed in the 2-3 sub-pixel SP2_3 may have a "┬" shape, but the present disclosure is not limited thereto. In the "┬" shaped portion, the "─" shaped portion (which extends in the first direction DR1) may be the 2-2 connection line CNL2, and the "l" shaped portion that branches downward from the "─" shaped portion in the second direction DR2 may be the second electrode EL2 of the 2-3 sub-pixel SP2_3.

[0192] In a plan view, a first connection line CNL1 connected to a first electrode EL1 of a 2-2 sub-pixel SP2_2 may be disposed above a 2-1 connection line CNL2 in a second direction DR2. In the plan view, a first connection line CNL1 connected to a first electrode EL1 of a 2-3 sub-pixel SP2_3 may be disposed below the 2-2 connection line CNL2 in the second direction DR2. The first connection line CNL1 connected to the first electrode EL1 of the 2-2 sub-pixel SP2_2 and the first connection line CNL1 connected to the first electrode EL1 of the 2-3 sub-pixel SP2_3 may be spaced apart from each other, and corresponding emission regions 100 of the 2-2 sub-pixel SP2_2 and the 2-3 sub-pixel SP2_3 may be interposed therebetween.

[0193] As described above, the 2-1 connection line CNL2 and the 2-2 connection line CNL2 that form a mirror-symmetric structure with respect to an imaginary line IL may be disposed in a second sub-pixel boundary region 300 located between the corresponding emission regions 100 of the 2-2 sub-pixel SP2_2 and the 2-3 sub-pixel SP2_3, where the 2-2 sub-pixel SP2_2 and the 2-3 sub-pixel SP2_3 are arranged adjacent to each other in the second direction DR2. When the light-emitting elements LD are aligned in the corresponding sub-pixels, the 2-1 connection line CNL2 and the 2-2 connection line CNL2 may transmit the same alignment voltage to the second electrodes EL2 of the corresponding sub-pixels.

[0194] For example, the 2-1 connection line CNL2 may supply a second alignment voltage to the second electrode EL2 of the 2-2 sub-pixel SP2_2, and the 2-2 connection line CNL2 may supply a second alignment voltage to the second electrode EL2 of the 2-3 sub-pixel SP2_3. In an embodiment of the present disclosure, an AC voltage or a DC voltage maintained at a constant voltage level may be applied as the second alignment voltage to the 2-1 connection line CNL2 and the 2-2 connection line CNL2, but the present disclosure is not limited thereto. In an embodiment, a ground voltage may be applied to the 2-1 connection line CNL2 and the 2-2 connection line CNL2.

[0195] In an embodiment of the present disclosure, since the second alignment voltages having the same electric potential are respectively applied to the 2-1 connection line CNL2 and the 2-2 connection line CNL2, an electric field for aligning the light-emitting element LD is not formed between the 2-1 connection line CNL2 and the 2-2 connection line CNL2 provided in the second sub-pixel boundary region 300. Therefore, the light-emitting element LD is not aligned in the second sub-pixel boundary region 300 (which is the non-emission region 200), and the light-emitting element LD can be only concentratedly aligned in the target region (for example, concentratedly aligned in the emission region 100 of each sub-pixel). As a result, in the embodiment of the present disclosure, the light-emitting element LD is only in the target region of each sub-pixel (that is, only concentratedly aligned in the emission region 100), so that abnormal alignment defects in which the light-emitting element LD is aligned in an undesired region (for example, the sub-pixel boundary region 300) can be prevented.

[0196] The sub-pixel boundary region 300 may also be provided between the corresponding emission regions 100 of the 1-2 sub-pixel SP1_2 and the 1-3 sub-pixel SP1_3 which are arranged adjacent to each other in the second direction DR2. Two second connection lines CNL2 having a mirror-symmetrical structure may also be provided in the sub-pixel boundary region 300. Similarly, the sub-pixel boundary region 300 may also be provided between the corresponding emission regions 100 of the 3-2 sub-pixel SP3_2 and the 3-3 sub-pixel SP3_3 which are arranged adjacent to each other in the second direction DR2. Two second connection lines CNL2 having a mirror-symmetrical structure may also be provided in the sub-pixel boundary region 300.

[0197] Figures 6a to 6f sequentially shows the manufacturing Figure 4 of a display device.

[0198] Referring to Figure 1a , Figure 2 , Figure 4 , Figure 5 and Figure 6a , a pixel circuit layer PCL of each sub-pixel is formed on a substrate SUB. Each sub-pixel may include an emission region 100 and a non-emission region 200. The sub-pixel boundary region 300 (which is the non-emission region 200) is provided between the corresponding emission regions 100 of two sub-pixels arranged adjacent to each other in the second direction DR2.

[0199] The pixel circuit layer PCL may further include a first transistor T1 and a second transistor T2, a drive voltage line DVL, and a passivation layer PSV. The passivation layer PSV may include a first contact hole CH1 exposing a part of the drain electrode DE of the first transistor T1, and a second contact hole CH2 exposing a part of the drive voltage line DVL.

[0200] Referring toFigure 1a , Figure 2 , Figure 4 , Figure 5 , Figure 6a and Figure 6b , a partition wall PW is formed on the passivation layer PSV in the emission region 100 of each sub-pixel.

[0201] The partition wall PW may be spaced apart from an adjacent partition wall PW by a predetermined distance on the passivation layer PSV. The partition wall PW may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0202] A metal layer MTL, a first electrode EL1, and a second electrode EL2 are formed on the passivation layer PSV including the partition wall PW.

[0203] The metal layer MTL, the first electrode EL1, and the second electrode EL2 may include the same material and each may be formed of a single layer or multiple layers. In the case where the metal layer MTL, the first electrode EL1, and the second electrode EL2 are each formed of multiple layers, each of the metal layer MTL, the first electrode EL1, and the second electrode EL2 may have a structure formed by sequentially stacking a first conductive layer formed of ITO, a second conductive layer formed of Ag, and a third conductive layer formed of ITO.

[0204] The first electrode EL1 and the second electrode EL2 and the metal layer MTL may be integral with each other. The first electrode EL1 and the second electrode EL2 may be provided in portions of the emission region 100 and the non-emission region 200 of each sub-pixel. The metal layer MTL may be provided in the non-emission region 200 of each sub-pixel.

[0205] The metal layer MTL may include a first metal layer MTL1 extending in a first direction DR1 and electrically connected and / or physically connected to the first electrode EL1, and a second metal layer MTL2 parallel to the extension direction of the first metal layer MTL1 and electrically connected and / or physically connected to the second electrode EL2.

[0206] The first electrode EL1 may branch from the first metal layer MTL1 into the emission region 100 of each sub-pixel in a second direction DR2. The first electrode EL1 may include a 1-1 electrode EL1_1 and a 1-2 electrode EL1_2 that branch from the first metal layer MTL1 into the emission region 100 of each sub-pixel. The second electrode EL2 may branch from the second metal layer MTL2 into the emission region 100 of each sub-pixel in the second direction DR2. The 1-1 electrode EL1_1, the second electrode EL2, and the 1-2 electrode EL1_2 may be spaced apart from each other at regular intervals. Specifically, the first electrode EL1 and the second electrode EL2 may be electrically separated and / or physically separated from each other.

[0207] After the alignment of the light-emitting element LD in each sub-pixel has been completed, a part of the first metal layer MTL1 can be removed. This process will be described in detail below with reference to Figure 6d this process.

[0208] The sub-pixel boundary region 300 is provided between the respective emission regions 100 of two sub-pixels arranged adjacent to each other in the second direction DR2. Two metal layers MTL can be provided in the sub-pixel boundary region 300. The two metal layers MTL can form a mirror-symmetrical structure based on an imaginary line IL extending in the first direction DR1.

[0209] The two metal layers MTL provided in the sub-pixel boundary region 300 can include a first metal layer MTL1 connected to the first electrode EL1 of one of the two sub-pixels adjacent to each other in the second direction DR2, and a first metal layer MTL1 connected to the first electrode EL1 of the other sub-pixel. In an embodiment, the two metal layers MTL provided in the sub-pixel boundary region 300 can include a second metal layer MTL2 connected to the second electrode EL2 of one of the two sub-pixels adjacent to each other in the second direction DR2, and a second metal layer MTL2 connected to the second electrode EL2 of the other sub-pixel.

[0210] Referring to Figure 1a 、 Figure 2 、 Figure 4 、 Figure 5 and Figures 6a to 6c , a first insulating material layer (not shown) is formed on the first electrode EL1 and the second electrode EL2. The first insulating material layer can be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0211] Thereafter, by applying respective alignment voltages to the first electrode EL1 and the second electrode EL2 of each sub-pixel via the first metal layer MTL1 and the second metal layer MTL2, an electric field is formed between the first electrode EL1 and the second electrode EL2. In the case where DC power or AC power having a predetermined voltage and period is repeatedly applied to each of the first electrode EL1 and the second electrode EL2 via the first metal layer MTL1 and the second metal layer MTL2 a plurality of times, an electric field can be formed between the first electrode EL1 and the second electrode EL2 due to the potential difference between the first electrode EL1 and the second electrode EL2.

[0212] Here, alignment voltages having the same electric potential can be respectively applied to two metal layers provided in the sub-pixel boundary region 300. For example, in a case where two first metal layers MTL1 (which are connected to first electrodes EL1 of each of two sub-pixels adjacent to each other in the second direction DR2) are provided in the sub-pixel boundary region 300, the same alignment voltage can be applied to each of the two first metal layers MTL1. In an embodiment, in a case where two second metal layers MTL2 (which are connected to second electrodes EL2 of each of two sub-pixels adjacent to each other in the second direction DR2) are provided in the sub-pixel boundary region 300, the same alignment voltage can be applied to each of the two second metal layers MTL2.

[0213] Since the same alignment voltage is applied to two metal layers MTL provided in the sub-pixel boundary region 300, there is no potential difference between the two metal layers MTL. Therefore, an electric field can be not formed between the two metal layers MTL.

[0214] After an electric field is formed between a first electrode EL1 and a second electrode EL2 provided in an emission region 100 of each sub-pixel, a light-emitting element LD is provided by an inkjet printing method or the like. For example, the light-emitting element LD can be provided onto a passivation layer PSV of an emission region 100 of each sub-pixel by disposing a nozzle above the passivation layer PSV and dropping a solvent including the light-emitting element LD onto the passivation layer PSV via the nozzle. The solvent can be one of acetone, water, ethanol, and toluene, but the present disclosure is not limited thereto. For example, the solvent can include a material that can be evaporated at room temperature or by heating. In addition, the solvent can have a form of an ink or a paste. The method of providing the light-emitting element LD is not limited to the foregoing method. The method of providing the light-emitting element LD can be changed. Subsequently, the solvent can be removed.

[0215] If the light-emitting element LD is provided onto the passivation layer PSV, the light-emitting element LD can be induced to perform self-alignment by the electric field formed between the first electrode EL1 and the second electrode EL2. Therefore, the light-emitting element LD can be aligned between the first electrode EL1 and the second electrode EL2. In other words, the light-emitting element LD can be centrally aligned in a target region (for example, an emission region 100 of each sub-pixel).

[0216] In an embodiment of the present disclosure, each of the light-emitting elements LD can be aligned between a first electrode EL1 and a second electrode EL2 on a first insulating material layer.

[0217] Refer to Figure 1a 、 Figure 2 、 Figure 4 、 Figure 5 and Figures 6a to 6d, after the alignment of the light-emitting element LD is completed, the first connection line CNL1 and the second connection line CNL2 are respectively formed by removing corresponding portions of the first metal layer MTL1 and the second metal layer MTL2 from each sub-pixel.

[0218] Specifically, the first connection line CNL1 can be formed by removing the portion of the first metal layer MTL1 that is located between the sub-pixels arranged adjacent to each other in the first direction DR1, so that each sub-pixel can operate independently of the adjacent sub-pixels. In an example of removing a part of the first metal layer MTL1, an etching method can be used, but the present disclosure is not limited thereto. The first connection line CNL1 can extend in the first direction DR1 and can be disposed in the non-emitting region 200 of each sub-pixel. The first connection line CNL1 can be electrically connected and / or physically connected to the first electrode EL1 of each sub-pixel.

[0219] Meanwhile, the second connection line CNL2 that is electrically disconnected from the alignment line (not shown) disposed on the non-display region NDA of the substrate SUB can be formed by partially removing at least a part of the second metal layer MTL2. The alignment line disposed on the non-display region NDA can be a line configured to transmit the alignment voltage corresponding to each of the first metal layer MTL1 and the second metal layer MTL2 from an external power source. The second connection line CNL2 can extend in the first direction DR1 and can be disposed in the non-emitting region 200 of each sub-pixel. The second connection line CNL2 can be electrically connected and / or physically connected to the second electrode EL2 of each sub-pixel. In addition, the second connection line CNL2 can be provided to be shared by adjacent sub-pixels.

[0220] Through the above manufacturing process, two connection lines can be provided in the sub-pixel boundary region 300 corresponding to the non-emitting region 200 (which is located between the corresponding emitting regions 100 of two sub-pixels adjacent to each other in the second direction DR2). The two connection lines can form a mirror-symmetric structure in the sub-pixel boundary region 300 with respect to the imaginary line IL extending in the first direction DR1.

[0221] For example, the two connection lines provided in the sub-pixel boundary region 300 can include the first connection line CNL1 connected to the first electrode EL1 of one of the two sub-pixels adjacent to each other in the second direction DR2, and the first connection line CNL1 connected to the first electrode EL1 of the other of the two sub-pixels. In an embodiment, the two connection lines provided in the sub-pixel boundary region 300 can include the second connection line CNL2 connected to the second electrode EL2 of one of the two sub-pixels adjacent to each other in the second direction DR2, and the second connection line CNL2 connected to the second electrode EL2 of the other of the two sub-pixels.

[0222] After forming a second insulating material layer (not shown) on a passivation layer PSV provided with a first connection line CNL1, a second connection line CNL2, etc., the second insulating material layer is patterned using a mask to form a second insulating layer INS2 in the emission region 100 of each sub-pixel. The second insulating layer INS2 can allow opposite ends EP1 and EP2 of each of the light-emitting elements LD aligned in each sub-pixel to be exposed.

[0223] The first insulating material layer can also be patterned by the aforementioned mask process such that the first insulating layer INS1 can be formed in the emission region 100 of each sub-pixel. In an embodiment, the first insulating layer INS1 and the second insulating layer INS2 can be patterned by a mask process for forming a third insulating layer INS3 described below and formed together.

[0224] Referring to Figure 1a 、 Figure 2 、 Figure 4 、 Figure 5 and Figures 6a to 6e , a first contact electrode CNE1 is formed in the emission region 100 of each sub-pixel.

[0225] The first contact electrode CNE1 can be formed on the first electrode EL1 and electrically connected to the first electrode EL1. In addition, the first contact electrode CNE1 can be formed on one end of opposite ends EP1 and EP2 of each of the light-emitting elements LD and electrically connected to one end of each of the light-emitting elements LD. Therefore, the first electrode EL1 and one end of each of the light-emitting elements LD can be electrically connected to each other through the first contact electrode CNE1.

[0226] The first contact electrode CNE1 can include a first - 1 contact electrode CNE1_1 provided on the first - 1 electrode EL1_1 and a first - 2 contact electrode CNE1_2 provided on the first - 2 electrode EL1_2.

[0227] Subsequently, after depositing a third insulating material layer (not shown) on the passivation layer PSV provided with the first contact electrode CNE1, a third insulating layer INS3 overlapping the first contact electrode CNE1 is formed using a mask. The first contact electrode CNE1 can not be exposed to the outside by the third insulating layer INS3. The second electrode EL2 and the other ends of opposite ends EP1 and EP2 of each of the light-emitting elements LD can be exposed to the outside.

[0228] Referring to Figure 1a 、 Figure 2 、 Figure 4 、 Figure 5 and Figures 6a to 6f , a second contact electrode CNE2 is formed in the emission region 100 of each sub-pixel.

[0229] The second contact electrode CNE2 may be disposed on the second electrode EL2 exposed to the outside, and may be electrically connected and / or physically connected to the second electrode EL2. In addition, the second contact electrode CNE2 may be formed on the other end of each of the light-emitting elements LD exposed to the outside, and may be electrically connected to the other end of each of the light-emitting elements LD. Accordingly, the second electrode EL2 and the other end of each of the light-emitting elements LD may be electrically connected to each other through the second contact electrode CNE2.

[0230] Subsequently, a fourth insulating layer INS4 is formed on the second contact electrode CNE2. The fourth insulating layer INS4 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. Subsequently, an outer coating OC is formed on the fourth insulating layer INS4.

[0231] Figure 7 A display device according to an embodiment of the present disclosure is shown, and is a schematic enlarged plan view corresponding to Figure 2 the region EA1.

[0232] Except that the second electrode branched from the second connection line includes a 2-1 electrode and a 2-2 electrode, and the first electrode branched from the first connection line includes one first electrode, Figure 7 the configuration of the display device shown in Figure 4 may be substantially equivalent to or similar to

[0233] the configuration of the display device of Figure 7 Therefore, for

[0234] the display device of Figure 1a , Figure 2 and Figure 7 According to an embodiment of the present disclosure, the display device may include a substrate SUB, on which a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 are disposed. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be disposed adjacent to each other in the second direction DR2 on the substrate SUB. In an embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include at least one sub-pixel.

[0235] The first pixel PXL1 may include a 1-1 sub-pixel SP1_1, a 2-1 sub-pixel SP2_1, and a 3-1 sub-pixel SP3_1. The second pixel PXL2 may include a 1-2 sub-pixel SP1_2, a 2-2 sub-pixel SP2_2, and a 3-2 sub-pixel SP3_2. The third pixel PXL3 may include a 1-3 sub-pixel SP1_3, a 2-3 sub-pixel SP2_3, and a 3-3 sub-pixel SP3_3.

[0236] Each sub-pixel may include a substrate SUB, a pixel circuit layer (refer to Figure 5 PCL) disposed on the substrate SUB, and a display element layer (refer to Figure 5 DPL) disposed on the pixel circuit layer PCL.

[0237] In an embodiment of the present disclosure, a sub-pixel boundary region 300 is disposed between emission regions 100 of two sub-pixels disposed adjacent to each other in a second direction DR2. Two connection lines may be disposed in the sub-pixel boundary region 300. For example, two connection lines may be disposed in the sub-pixel boundary region 300 (hereinafter referred to as the "first sub-pixel boundary region") disposed between the emission region 100 of the 1-1 sub-pixel SP1_1 and the emission region 100 of the 1-2 sub-pixel SP1_2. The two connection lines may include a second connection line CNL2 (hereinafter referred to as the "2-1 connection line") disposed in the 1-1 sub-pixel SP1_1 and a second connection line CNL2 (hereinafter referred to as the "2-2 connection line") disposed in the 1-2 sub-pixel SP1_2.

[0238] The 2-1 connection line CNL2 and the 2-2 connection line CNL2 may be disposed in the first sub-pixel boundary region 300, spaced apart from each other by a predetermined distance, and thus electrically separated and / or physically separated from each other. An imaginary line IL extending in a first direction DR1 may be disposed between the 2-1 connection line CNL2 and the 2-2 connection line CNL2. The 2-1 connection line CNL2 and the 2-2 connection line CNL2 may form a mirror-symmetrical structure based on the imaginary line IL. The 2-1 connection line CNL2 may be disposed on the upper side in the second direction DR2 with respect to the imaginary line IL, and the 2-2 connection line CNL2 may be disposed on the lower side in the second direction DR2 with respect to the imaginary line IL.

[0239] The second - 1 connection line CNL2 can be electrically and / or physically connected to the second electrode EL2 of the first - 1 sub - pixel SP1_1. The second electrode EL2 of the first - 1 sub - pixel SP1_1 can include a second - 1 electrode EL2_1 and a second - 2 electrode EL2_2, which branch upward from the second - 1 connection line CNL2 disposed in the first sub - pixel boundary region 300 in the second direction DR2. The second - 1 electrode EL2_1 and the second - 2 electrode EL2_2 can be disposed in the emission region 100 of the first - 1 sub - pixel SP1_1. In this case, the second contact electrode CNE2 can include a second - 1 contact electrode CNE2_1 disposed on the second - 1 electrode EL2_1 and a second - 2 contact electrode CNE2_2 disposed on the second - 2 electrode EL2_2.

[0240] The second - 1 connection line CNL2 and the second electrode EL2 disposed in the first - 1 sub - pixel SP1_1 can have an "╨" shape in a plan view, but the present disclosure is not limited thereto. In the "╨" - shaped portion, the "─" - shaped portion (which extends in the first direction DR1) can be the second - 1 connection line CNL2, and the "ll" - shaped portion that branches upward from the "─" - shaped portion in the second direction DR2 can be the second - 1 electrode EL2_1 and the second - 2 electrode EL2_2.

[0241] The second - 2 connection line CNL2 can be electrically and / or physically connected to the second electrode EL2 of the first - 2 sub - pixel SP1_2. The second electrode EL2 of the first - 2 sub - pixel SP1_2 can include a second - 1 electrode EL2_1 and a second - 2 electrode EL2_2, which branch downward from the second - 2 connection line CNL2 disposed in the first sub - pixel boundary region 300 in the second direction DR2. The second - 1 electrode EL2_1 and the second - 2 electrode EL2_2 can be disposed in the emission region 100 of the first - 2 sub - pixel SP1_2.

[0242] The second - 2 connection line CNL2 and the second electrode EL2 disposed in the first - 2 sub - pixel SP1_2 can have an "╥" shape in a plan view, but the present disclosure is not limited thereto. In the "╥" - shaped portion, the "─" - shaped portion (which extends in the first direction DR1) can be the second - 2 connection line CNL2, and the "ll" - shaped portion that branches downward from the "─" - shaped portion in the second direction DR2 can be the second - 1 electrode EL2_1 and the second - 2 electrode EL2_2.

[0243] In a plan view, a first connection line CNL1 connected to a first electrode EL1 of a first sub-pixel SP1_1 may be disposed above a second connection line CNL2 in a second direction DR2. In the plan view, a first connection line CNL1 connected to a first electrode EL1 of a first sub-pixel SP1_2 may be disposed below a second connection line CNL2 in the second direction DR2. The first connection line CNL1 connected to the first electrode EL1 of the first sub-pixel SP1_1 and the first connection line CNL1 connected to the first electrode EL1 of the first sub-pixel SP1_2 may be spaced apart from each other, and corresponding emission regions 100 of the first sub-pixel SP1_1 and the first sub-pixel SP1_2 are interposed therebetween.

[0244] When a light-emitting element LD is aligned in a corresponding sub-pixel, the second connection line CNL2 and the second connection line CNL2 may transmit the same alignment voltage to a second electrode EL2 of the corresponding sub-pixel. The second connection line CNL2 may extend in a first direction DR1 to sub-pixels SP2_1 and SP3_1 adjacent to the first sub-pixel SP1_1. The second connection line CNL2 may extend in the first direction DR1 to sub-pixels SP2_2 and SP3_2 adjacent to the first sub-pixel SP1_2.

[0245] A sub-pixel boundary region 300 may also be disposed between corresponding emission regions 100 of a second sub-pixel SP2_1 and a second sub-pixel SP2_2 that are arranged adjacent to each other in the second direction DR2. Two second connection lines CNL2 having a mirror-symmetric structure may also be disposed in the sub-pixel boundary region 300. Similarly, the sub-pixel boundary region 300 may also be disposed between corresponding emission regions 100 of a third sub-pixel SP3_1 and a third sub-pixel SP3_2 that are arranged adjacent to each other in the second direction DR2. Two second connection lines CNL2 having a mirror-symmetric structure may also be disposed in the sub-pixel boundary region 300.

[0246] In an embodiment of the present disclosure, a sub-pixel boundary region 300 (hereinafter, referred to as a "second sub-pixel boundary region") may also be disposed between corresponding emission regions 100 of a second sub-pixel SP2_2 and a second sub-pixel SP2_3 that are arranged adjacent to each other in the second direction DR2. Two connection lines may be disposed in the second sub-pixel boundary region 300. The two connection lines may include a first connection line CNL1 (hereinafter, referred to as a "first connection line 1-1") disposed in the second sub-pixel SP2_2 and a first connection line CNL1 (hereinafter, referred to as a "first connection line 1-2") disposed in the second sub-pixel SP2_3.

[0247] An imaginary line IL extending in a first direction DR1 may be provided between a first-to-first connection line CNL1 and a first-to-second connection line CNL1. The first-to-first connection line CNL1 and the first-to-second connection line CNL1 may form a mirror-symmetric structure based on the imaginary line IL. The first-to-first connection line CNL1 may be provided on an upper side in a second direction DR2 with respect to the imaginary line IL, and the first-to-second connection line CNL1 may be provided on a lower side in the second direction DR2 with respect to the imaginary line IL.

[0248] The first-to-first connection line CNL1 may be electrically and / or physically connected to a first electrode EL1 of a second-to-second sub-pixel SP2_2. The first electrode EL1 of the second-to-second sub-pixel SP2_2 may branch upward from the first-to-first connection line CNL1 provided in a second sub-pixel boundary region 300 in the second direction DR2, and is thus provided in an emission region 100 of the second-to-second sub-pixel SP2_2. The first-to-first connection line CNL1 and the first electrode EL1 provided in the second-to-second sub-pixel SP2_2 may have an "┴" shape in a plan view, but the present disclosure is not limited thereto. In the "┴" shaped portion, the "─" shaped portion (which extends in the first direction DR1) may be the first-to-first connection line CNL1, and the "l" shaped portion branching upward from the "─" shaped portion in the second direction DR2 may be the first electrode EL1 of the second-to-second sub-pixel SP2_2.

[0249] The first-to-second connection line CNL1 may be electrically and / or physically connected to a first electrode EL1 of a second-to-third sub-pixel SP2_3. The first electrode EL1 of the second-to-third sub-pixel SP2_3 may branch downward from the first-to-second connection line CNL1 provided in the second sub-pixel boundary region 300 in the second direction DR2, and is thus provided in an emission region 100 of the second-to-third sub-pixel SP2_3. The first-to-second connection line CNL1 and the first electrode EL1 provided in the second-to-third sub-pixel SP2_3 may have a "┬" shape in a plan view, but the present disclosure is not limited thereto. In the "┬" shaped portion, the "─" shaped portion (which extends in the first direction DR1) may be the first-to-second connection line CNL1, and the "l" shaped portion branching downward from the "─" shaped portion in the second direction DR2 may be the first electrode EL1 of the second-to-third sub-pixel SP2_3.

[0250] In a plan view, a second connection line CNL2 connected to a second electrode EL2 of a 2-2 sub-pixel SP2_2 may be disposed above a 1-1 connection line CNL1 in a second direction DR2. In the plan view, a second connection line CNL2 connected to a second electrode EL2 of a 2-3 sub-pixel SP2_3 may be disposed below a 1-2 connection line CNL1 in the second direction DR2. The second connection line CNL2 connected to the second electrode EL2 of the 2-2 sub-pixel SP2_2 and the second connection line CNL2 connected to the second electrode EL2 of the 2-3 sub-pixel SP2_3 may be spaced apart from each other, and corresponding emission regions 100 of the 2-2 sub-pixel SP2_2 and the 2-3 sub-pixel SP2_3 may be interposed therebetween.

[0251] When the light-emitting element LD is aligned in the corresponding sub-pixel, the 1-1 connection line CNL1 and the 1-2 connection line CNL1 may transmit the same alignment voltage to a first electrode EL1 of the corresponding sub-pixel.

[0252] A sub-pixel boundary region 300 may also be disposed between corresponding emission regions 100 of a 1-2 sub-pixel SP1_2 and a 1-3 sub-pixel SP1_3 that are arranged adjacent to each other in the second direction DR2. Two first connection lines CNL1 having a mirror-symmetric structure may also be disposed in the sub-pixel boundary region 300. Similarly, the sub-pixel boundary region 300 may also be disposed between corresponding emission regions 100 of a 3-2 sub-pixel SP3_2 and a 3-3 sub-pixel SP3_3 that are arranged adjacent to each other in the second direction DR2. Two first connection lines CNL1 having a mirror-symmetric structure may also be disposed in the sub-pixel boundary region 300.

[0253] Figure 8 and Figure 9 A display device according to an embodiment of the present disclosure is schematically illustrated, and is a schematic enlarged plan view corresponding to Figure 2 an area EA1.

[0254] Except that two connection lines in a sub-pixel boundary region disposed between corresponding emission regions of two sub-pixels arranged adjacent to each other in a second direction do not form a symmetric structure, Figure 8 and Figure 9 the structure of the display device shown in Figure 4 may be substantially equivalent to or similar to the structure of the display device of

[0255] For Figure 8 and Figure 9For the display device, the following description will focus on the differences from those of the foregoing embodiments to avoid repetitive explanations. Components not separately described in the following description of the present embodiment may be consistent with the components of the foregoing embodiments. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0256] Referring to Figure 1a , Figure 2 , Figure 8 and Figure 9 , a display device according to an embodiment of the present disclosure may include a substrate SUB, on which a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 are disposed. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be disposed adjacent to each other in a second direction DR2 on the substrate SUB. In an embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include at least one sub-pixel.

[0257] The first pixel PXL1 may include a first-1 sub-pixel SP1_1, a second-1 sub-pixel SP2_1, and a third-1 sub-pixel SP3_1. The second pixel PXL2 may include a first-2 sub-pixel SP1_2, a second-2 sub-pixel SP2_2, and a third-2 sub-pixel SP3_2. The third pixel PXL3 may include a first-3 sub-pixel SP1_3, a second-3 sub-pixel SP2_3, and a third-3 sub-pixel SP3_3.

[0258] Each sub-pixel may include a substrate SUB, a pixel circuit layer disposed on the substrate SUB (refer to Figure 5 PCL), and a display element layer disposed on the pixel circuit layer PCL (refer to Figure 5 DPL).

[0259] In an embodiment of the present disclosure, a sub-pixel boundary region 300 is disposed between emission regions 100 of two sub-pixels disposed adjacent to each other in a second direction DR2. Two connection lines may be disposed in the sub-pixel boundary region 300.

[0260] For example, the two connection lines may be disposed in a sub-pixel boundary region 300 (hereinafter referred to as "first sub-pixel boundary region") disposed between the emission region 100 of the first-1 sub-pixel SP1_1 and the emission region 100 of the first-2 sub-pixel SP1_2.

[0261] As Figure 8As shown, the two connection lines may include a first connection line CNL1 disposed in the 1-1 sub-pixel SP1_1 and a first connection line CNL1 disposed in the 1-2 sub-pixel SP1_2. The first connection line CNL1 disposed in the 1-1 sub-pixel SP1_1 and the first connection line CNL1 disposed in the 1-2 sub-pixel SP1_2 may be spaced apart from each other by a predetermined distance, and may be electrically separated and / or physically separated from each other, and an imaginary line IL is interposed therebetween and the imaginary line IL extends in the first direction DR1. When the light-emitting element LD is aligned in the corresponding sub-pixel, the first connection line CNL1 disposed in the 1-1 sub-pixel SP1_1 and the first connection line CNL1 disposed in the 1-2 sub-pixel SP1_2 may transmit the same alignment voltage to the first electrode EL1 of the corresponding sub-pixel.

[0262] The first connection line CNL1 disposed in the 1-1 sub-pixel SP1_1 may be disposed on the upper side in the second direction DR2 with respect to the imaginary line IL. The first connection line CNL1 disposed in the 1-2 sub-pixel SP1_2 may be disposed on the lower side with respect to the imaginary line IL.

[0263] The first connection line CNL1 disposed in the 1-1 sub-pixel SP1_1 may be electrically connected and / or physically connected to the first electrode EL1 of the 1-1 sub-pixel SP1_1. The first electrode EL1 of the 1-1 sub-pixel SP1_1 may branch upward from the first connection line CNL1 disposed in the corresponding sub-pixel in the second direction DR2, and is thus disposed in the emission region 100 of the 1-1 sub-pixel SP1_1.

[0264] The first connection line CNL1 disposed in the 1-2 sub-pixel SP1_2 may be electrically connected and / or physically connected to the first electrode EL1 of the corresponding sub-pixel. The first electrode EL1 of the 1-2 sub-pixel SP1_2 may include a 1-1 electrode EL1_1 and a 1-2 electrode EL1_2, which branch downward from the first connection line CNL1 disposed in the corresponding sub-pixel in the second direction DR2. The 1-1 electrode EL1_1 and the 1-2 electrode EL1_2 may be disposed in the emission region 100 of the 1-2 sub-pixel SP1_2.

[0265] As Figure 8As shown, two first connection lines CNL1 may be provided in a sub-pixel boundary region 300 between corresponding emission regions 100 of two sub-pixels adjacent to each other in a second direction DR2 (i.e., between the corresponding emission regions 100 of the 1-1 sub-pixel SP1_1 and the 1-2 sub-pixel SP1_2), and the two first connection lines CNL1 may be electrically and / or physically connected to a first electrode EL1 of a corresponding sub-pixel. In this case, two second connection lines CNL2 may be provided in a sub-pixel boundary region 300 between corresponding emission regions 100 of the 2-2 sub-pixel SP2_2 and the 2-3 sub-pixel SP2_3 (which are adjacent to each other in the second direction DR2), and the two second connection lines CNL2 may be electrically and / or physically connected to a second electrode EL2 of a corresponding sub-pixel.

[0266] In an embodiment, as Figure 9 shown, two second connection lines CNL2 may be provided in a sub-pixel boundary region 300 between corresponding emission regions 100 of the 1-1 sub-pixel SP1_1 and the 1-2 sub-pixel SP1_2 (which are adjacent to each other in the second direction DR2). The two second connection lines CNL2 may include a second connection line CNL2 provided in the 1-1 sub-pixel SP1_1 and a second connection line CNL2 provided in the 1-2 sub-pixel SP1_2. The second connection line CNL2 provided in the 1-1 sub-pixel SP1_1 and the second connection line CNL2 provided in the 1-2 sub-pixel SP1_2 may be spaced apart from each other and may be electrically and / or physically separated from each other, and a virtual line IL is interposed therebetween and the virtual line IL extends in a first direction DR1. When a light-emitting element LD is aligned in a corresponding sub-pixel, the second connection line CNL2 provided in the 1-1 sub-pixel SP1_1 and the second connection line CNL2 provided in the 1-2 sub-pixel SP1_2 may transmit the same alignment voltage to the second electrode EL2 of a corresponding sub-pixel.

[0267] The second connection line CNL2 provided in the 1-1 sub-pixel SP1_1 may be disposed on an upper side in the second direction DR2 with respect to the virtual line IL. The second connection line CNL2 provided in the 1-2 sub-pixel SP1_2 may be disposed on a lower side with respect to the virtual line IL.

[0268] The second connection line CNL2 provided in the 1-1 sub-pixel SP1_1 may be electrically and / or physically connected to the second electrode EL2 of the 1-1 sub-pixel SP1_1. The second electrode EL2 of the 1-1 sub-pixel SP1_1 may branch upward from the second connection line CNL2 provided in a corresponding sub-pixel in the second direction DR2 and is thus disposed in the emission region 100 of the 1-1 sub-pixel SP1_1.

[0269] The second connection line CNL2 provided in the 1-2nd sub-pixel SP1_2 can be electrically connected and / or physically connected to the second electrode EL2 of the corresponding sub-pixel. The second electrode EL2 of the 1-2nd sub-pixel SP1_2 can include a 2-1st electrode EL2_1 and a 2-2nd electrode EL2_2, which branch downward from the second connection line CNL2 provided in the corresponding sub-pixel in the second direction DR2. The 2-1st electrode EL2_1 and the 2-2nd electrode EL2_2 can be provided in the emission region 100 of the 1-2nd sub-pixel SP1_2.

[0270] As Figure 9 shown, two second connection lines CNL2 can be provided in the sub-pixel boundary region 300 between the corresponding emission regions 100 of two adjacent sub-pixels in the second direction DR2 (i.e., between the corresponding emission regions 100 of the 1-1st sub-pixel SP1_1 and the 1-2nd sub-pixel SP1_2), and the two second connection lines CNL2 can be electrically connected and / or physically connected to the second electrode EL2 of the corresponding sub-pixel. In this case, two first connection lines CNL1 can be provided in the sub-pixel boundary region 300 between the corresponding emission regions 100 of the 2-2nd sub-pixel SP2_2 and the 2-3rd sub-pixel SP2_3 (which are adjacent to each other in the second direction DR2), and the two first connection lines CNL1 can be electrically connected and / or physically connected to the first electrode EL1 of the corresponding sub-pixel.

[0271] Figure 10 shows a display device according to an embodiment of the present disclosure, and is a schematic enlarged plan view corresponding to Figure 2 the region EA1 in

[0272] Except that each of the two first connection lines provided in the sub-pixel boundary region is electrically connected and / or physically connected to the first electrode of the corresponding sub-pixel through a bridging pattern, Figure 10 the configuration of the display device shown in Figure 4 can be substantially equivalent to or similar to

[0273] the configuration of the display device in Figure 10 . Therefore, for

[0274] the display device in Figure 1a 、 Figure 2 and Figure 10, a display device according to an embodiment of the present disclosure may include a substrate SUB, on which a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 are provided. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be provided on the substrate SUB to be adjacent to each other in a second direction DR2. In an embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include at least one sub-pixel.

[0275] The first pixel PXL1 may include a first sub-pixel SP1_1, a second sub-pixel SP2_1, and a third sub-pixel SP3_1. The second pixel PXL2 may include a first sub-pixel SP1_2, a second sub-pixel SP2_2, and a third sub-pixel SP3_2. The third pixel PXL3 may include a first sub-pixel SP1_3, a second sub-pixel SP2_3, and a third sub-pixel SP3_3.

[0276] In an embodiment of the present disclosure, a sub-pixel boundary region 300 is provided in a non-emission region 200 between corresponding emission regions 100 of two sub-pixels that are provided to be adjacent to each other in the second direction DR2. For example, two connection lines may be provided in a sub-pixel boundary region 300 (hereinafter, referred to as "first sub-pixel boundary region") between the corresponding emission regions 100 of the first sub-pixel SP1_1 and the first sub-pixel SP1_2. The two connection lines may include a first connection line CNL1 provided in the first sub-pixel SP1_1 (hereinafter, referred to as "1-1 connection line") and a first connection line CNL1 provided in the first sub-pixel SP1_2 (hereinafter, referred to as "1-2 connection line").

[0277] The 1-1 connection line CNL1 and the 1-2 connection line CNL1 may be provided in the first sub-pixel boundary region 300 and spaced apart from each other by a predetermined distance, and thus electrically separated and / or physically separated from each other. An imaginary line IL extending in a first direction DR1 may be provided between the 1-1 connection line CNL1 and the 1-2 connection line CNL1. The 1-1 connection line CNL1 and the 1-2 connection line CNL1 may form a mirror-symmetric structure with respect to the imaginary line IL. The 1-1 connection line CNL1 provided in the first sub-pixel boundary region 300 may be provided on the upper side in the second direction DR2 with respect to the imaginary line IL, and the 1-2 connection line CNL1 may be provided on the lower side in the second direction DR2 with respect to the imaginary line IL.

[0278] The first - first connection line CNL1 can be electrically and / or physically connected to the first electrode EL1 disposed in the emission region 100 of the first - first sub - pixel SP1_1 through the bridging pattern BRP. The first - first connection line CNL1, the first electrode EL1, and the bridging pattern BRP can be integral with each other. The first electrode EL1 can be disposed in at least a part of the emission region 100 of the first - first sub - pixel SP1_1 and at least a part of the first sub - pixel boundary region 300. The first - first connection line CNL1 and the bridging pattern BRP can be disposed in the first sub - pixel boundary region 300.

[0279] The first electrode EL1 of the first - first sub - pixel SP1_1 can include a first - first electrode EL1_1 and a first - second electrode EL1_2, which branch upward from the bridging pattern BRP of the bridging pattern BRP disposed in the first sub - pixel boundary region 300 in the second direction DR2.

[0280] The first - second connection line CNL1 can be electrically and / or physically connected to the first electrode EL1 disposed in the emission region 100 of the first - second sub - pixel SP1_2 through the bridging pattern BRP. The first - second connection line CNL1, the first electrode EL1, and the bridging pattern BRP can be integral with each other. The first electrode EL1 can be disposed in at least a part of the emission region 100 of the first - second sub - pixel SP1_2 and at least a part of the first sub - pixel boundary region 300. The first - second connection line CNL1 and the bridging pattern BRP can be disposed in the first sub - pixel boundary region 300.

[0281] The first electrode EL1 of the first - second sub - pixel SP1_2 can branch downward from the bridging pattern BRP disposed in the first sub - pixel boundary region 300 in the second direction DR2 and can be disposed in a part of the emission region 100 of the first - second sub - pixel SP1_2 and a part of the first sub - pixel boundary region 300.

[0282] As described above, the first - first connection line CNL1 and the first - second connection line CNL1, which form a mirror - symmetric structure with respect to the imaginary line IL, can be disposed in the first sub - pixel boundary region 300 located between the corresponding emission regions 100 of the first - first sub - pixel SP1_1 and the first - second sub - pixel SP1_2 (which are arranged adjacent to each other in the second direction DR2). In the case where the light - emitting elements LD are aligned in the corresponding sub - pixels, each of the first - first connection line CNL1 and the first - second connection line CNL1 disposed in the first sub - pixel boundary region 300 can transmit the same alignment voltage to the first electrode EL1 of the corresponding sub - pixel.

[0283] In an embodiment of the present disclosure, a sub-pixel boundary region 300 (hereinafter referred to as the "second sub-pixel boundary region") may also be provided between the corresponding emission regions 100 of the 2-2 sub-pixels SP2_2 and the 2-3 sub-pixels SP2_3 that are arranged adjacent to each other in the second direction DR2. Two connection lines may be provided in the second sub-pixel boundary region 300. The two connection lines may include a second connection line CNL2 (hereinafter referred to as the "2-1 connection line") provided in the 2-2 sub-pixel SP2_2, and a second connection line CNL2 (hereinafter referred to as the "2-2 connection line") provided in the 2-3 sub-pixel SP2_3.

[0284] The 2-1 connection line CNL2 and the 2-2 connection line CNL2 may be provided in the second sub-pixel boundary region 300 and spaced apart from each other by a predetermined distance, and thus electrically separated and / or physically separated from each other. An imaginary line IL extending in the first direction DR1 may be provided between the 2-1 connection line CNL2 and the 2-2 connection line CNL2. The 2-1 connection line CNL2 and the 2-2 connection line CNL2 may form a mirror-symmetrical structure with respect to the imaginary line IL. The 2-1 connection line CNL2 may be provided on the upper side in the second direction DR2 with respect to the imaginary line IL, and the 2-2 connection line CNL2 may be provided on the lower side in the second direction DR2 with respect to the imaginary line IL.

[0285] The 2-1 connection line CNL2 may be electrically connected and / or physically connected to a second electrode EL2 provided in the emission region 100 of the 2-2 sub-pixel SP2_2. The second electrode EL2 of the 2-2 sub-pixel SP2_2 may branch upward from the 2-1 connection line CNL2 in the second direction DR2, and thus be provided in at least a part of the emission region 100 of the corresponding sub-pixel and at least a part of the second sub-pixel boundary region 300.

[0286] The 2-2 connection line CNL2 may be electrically connected and / or physically connected to a second electrode EL2 provided in the emission region 100 of the 2-3 sub-pixel SP2_3. The second electrode EL2 of the 2-3 sub-pixel SP2_3 may branch downward from the 2-2 connection line CNL2 in the second direction DR2, and thus be provided in at least a part of the emission region 100 of the corresponding sub-pixel and at least a part of the second sub-pixel boundary region 300.

[0287] Figure 11 A display device according to an embodiment of the present disclosure is shown and is a schematic enlarged plan view corresponding to Figure 2 the region EA1.

[0288] Except that the second electrode includes a 2-1 electrode, a 2-2 electrode, and a 2-3 electrode, and each of the first connection line and the second connection line is integral with the bridging pattern, Figure 11 the configuration of the display device shown in Figure 10 may be substantially equivalent to or similar to

[0289] Therefore, for Figure 11 the display device in

[0290] the following description will focus on the differences from those of the foregoing embodiments to avoid repetitive description. Components not separately described in the following description of the present embodiment may be consistent with the components of the foregoing embodiments. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0290] Referring to Figure 1a 、 Figure 2 and Figure 11 a display device according to an embodiment of the present disclosure may include a substrate SUB, on which a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 are provided. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be provided on the substrate SUB to be adjacent to each other in a second direction DR2. In an embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include at least one sub-pixel.

[0291] The first pixel PXL1 may include a 1-1 sub-pixel SP1_1, a 2-1 sub-pixel SP2_1, and a 3-1 sub-pixel SP3_1. The second pixel PXL2 may include a 1-2 sub-pixel SP1_2, a 2-2 sub-pixel SP2_2, and a 3-2 sub-pixel SP3_2. The third pixel PXL3 may include a 1-3 sub-pixel SP1_3, a 2-3 sub-pixel SP2_3, and a 3-3 sub-pixel SP3_3.

[0292] In an embodiment of the present disclosure, a sub-pixel boundary region 300 is provided in a non-emission region 200 between corresponding emission regions 100 of two sub-pixels arranged to be adjacent to each other in the second direction DR2. For example, two connection lines may be provided in a sub-pixel boundary region 300 (hereinafter referred to as "first sub-pixel boundary region") provided between the corresponding emission regions 100 of the 1-1 sub-pixel SP1_1 and the 1-2 sub-pixel SP1_2. The two connection lines may include a first connection line CNL1 (hereinafter referred to as "1-1 connection line") provided in the 1-1 sub-pixel SP1_1 and a first connection line CNL1 (hereinafter referred to as "1-2 connection line") provided in the 1-2 sub-pixel SP1_2.

[0293] An imaginary line IL extending in a first direction DR1 may be disposed between a first connection line CNL1 and a second connection line CNL1. The first connection line CNL1 and the second connection line CNL1 may form a mirror-symmetrical structure with respect to the imaginary line IL. The first connection line CNL1 may be disposed on an upper side in a second direction DR2 with respect to the imaginary line IL, and the second connection line CNL1 may be disposed on a lower side in the second direction DR2 with respect to the imaginary line IL.

[0294] In an embodiment of the present disclosure, the first connection line CNL1 may be electrically and / or physically connected to a first electrode EL1 disposed in an emission region 100 of the first sub-pixel SP1_1 through a first bridging pattern BRP1. The first connection line CNL1, the first bridging pattern BRP1, and the first electrode EL1 may include the same material and may be disposed on the same plane. The first connection line CNL1, the first bridging pattern BRP1, and the first electrode EL1 may be integral with each other. Here, the first electrode EL1 may include a first electrode EL1_1 and a second electrode EL1_2 that branch upward from the first bridging pattern BRP1 in a second direction DR2.

[0295] In an embodiment of the present disclosure, the second connection line CNL1 may be electrically and / or physically connected to the first electrode EL1 of the second sub-pixel SP1_2 through the first bridging pattern BRP1. Here, the first electrode EL1 of the second sub-pixel SP1_2 may include a first electrode EL1_1 and a second electrode EL1_2 that branch downward from the first bridging pattern BRP1 in a second direction DR2.

[0296] As described above, when the light-emitting element LD is aligned in the corresponding sub-pixel, the first connection line CNL1 and the second connection line CNL1 may transmit the same alignment voltage to the first electrode EL1 of the corresponding sub-pixel, respectively.

[0297] The second connection line CNL2 disposed in the non-emission region 200 of the 1-1st sub-pixel SP1_1 can be electrically and / or physically connected to the second electrode EL2 of the corresponding sub-pixel through the second bridging pattern BRP2. In a plan view, the second connection line CNL2 connected to the second electrode EL2 of the 1-1st sub-pixel SP1_1 can be disposed on the upper side of the 1-1st connection line CNL1 in the second direction DR2. Here, the second electrode EL2 of the 1-1st sub-pixel SP1_1 can include a 2-1st electrode EL2_1, a 2-2nd electrode EL2_2, and a 2-3rd electrode EL2_3, which branch downward from the second bridging pattern BRP2 in the second direction DR2. In this case, the second contact electrode CNE2 can include a 2-1st contact electrode CNE2_1 disposed on the 2-1st electrode EL2_1, a 2-2nd contact electrode CNE2_2 disposed on the 2-2nd electrode EL2_2, and a 2-3rd contact electrode CNE2_3 disposed on the 2-3rd electrode EL2_3.

[0298] In the emission region 100 of the 1-1st sub-pixel SP1_1, the 2-1st electrode EL2_1 and the 2-2nd electrode EL2_2 can be spaced apart from each other, and the 1-1st electrode EL1_1 is interposed therebetween, and the 2-2nd electrode EL2_2 and the 2-3rd electrode EL2_3 can be spaced apart from each other, and the 1-2nd electrode EL1_2 is interposed therebetween. The light-emitting element LD aligned in the emission region 100 of the 1-1st sub-pixel SP1_1 can include a first light-emitting element LD1 aligned between the 2-1st electrode EL2_1 and the 1-1st electrode EL1_1, a second light-emitting element LD2 aligned between the 1-1st electrode EL1_1 and the 2-2nd electrode EL2_2, a third light-emitting element LD3 aligned between the 2-2nd electrode EL2_2 and the 1-2nd electrode EL1_2, and a fourth light-emitting element LD4 aligned between the 1-2nd electrode EL1_2 and the 2-3rd electrode EL2_3.

[0299] The second connection line CNL2 disposed in the non-emission region 200 of the 1-2nd sub-pixel SP1_2 can be electrically and / or physically connected to the second electrode EL2 of the corresponding sub-pixel through the second bridging pattern BRP2. In a plan view, the second connection line CNL2 connected to the second electrode EL2 of the 1-2nd sub-pixel SP1_2 can be disposed on the lower side of the 1-2nd connection line CNL1 in the second direction DR2. Here, the second electrode EL2 of the 1-2nd sub-pixel SP1_2 can include a 2-1st electrode EL2_1, a 2-2nd electrode EL2_2, and a 2-3rd electrode EL2_3, which branch upward from the second bridging pattern BRP2 in the second direction DR2.

[0300] In the emission region 100 of the 1-2nd sub-pixel SP1_2, the 2-1st electrode EL2_1 and the 2-2nd electrode EL2_2 may be spaced apart from each other, and the 1-1st electrode EL1_1 may be interposed therebetween, and the 2-2nd electrode EL2_2 and the 2-3rd electrode EL2_3 may be spaced apart from each other, and the 1-2nd electrode EL1_2 may be interposed therebetween. The light-emitting elements LD aligned in the emission region 100 of the 1-2nd sub-pixel SP1_2 may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a fourth light-emitting element LD4.

[0301] In an embodiment of the present disclosure, a sub-pixel boundary region 300 (hereinafter, referred to as the "second sub-pixel boundary region") may be provided between the corresponding emission regions 100 of the 2-2nd sub-pixel SP2_2 and the 2-3rd sub-pixel SP2_3 that are arranged adjacent to each other in the second direction DR2. Two connection lines may be provided in the second sub-pixel boundary region 300. The two connection lines may include a second connection line CNL2 (hereinafter, referred to as the "2-1st connection line") provided in the 2-2nd sub-pixel SP2_2, and a second connection line CNL2 (hereinafter, referred to as the "2-2nd connection line") provided in the 2-3rd sub-pixel SP2_3.

[0302] An imaginary line IL extending in the first direction DR1 may be provided between the 2-1st connection line CNL2 and the 2-2nd connection line CNL2. The 2-1st connection line CNL2 and the 2-2nd connection line CNL2 may form a mirror-symmetrical structure with respect to the imaginary line IL. The 2-1st connection line CNL2 may be provided on the upper side in the second direction DR2 with respect to the imaginary line IL, and the 2-2nd connection line CNL2 may be provided on the lower side in the second direction DR2 with respect to the imaginary line IL.

[0303] The 2-1st connection line CNL2 may be electrically connected and / or physically connected to the second electrode EL2 of the 2-2nd sub-pixel SP2_2 through a second bridging pattern BRP2. The second electrode EL2 of the 2-2nd sub-pixel SP2_2 may branch upward from the second bridging pattern BRP2 in the second direction DR2, and thus may be provided in the emission region 100 of the corresponding sub-pixel. The second electrode EL2 of the 2-2nd sub-pixel SP2_2 may include a 2-1st electrode EL2_1, a 2-2nd electrode EL2_2, and a 2-3rd electrode EL2_3. The first electrode EL1 of the 2-2nd sub-pixel SP2_2 may include a 1-1st electrode EL1_1 and a 1-2nd electrode EL1_2. The first electrode EL1 and the second electrode EL2 of the 2-2nd sub-pixel SP2_2 may be spaced apart from each other by a predetermined distance and may be provided in the emission region 100 of the corresponding sub-pixel.

[0304] The second - second connection line CNL2 can be electrically and / or physically connected to the second electrode EL2 of the second - third sub - pixel SP2_3 through the second bridging pattern BRP2. The second electrode EL2 of the second - third sub - pixel SP2_3 can branch downward from the second bridging pattern BRP2 in the second direction DR2 and is thus disposed in the emission region 100 of the corresponding sub - pixel. The second electrode EL2 of the second - third sub - pixel SP2_3 can include a second - first electrode EL2_1, a second - second electrode EL2_2, and a second - third electrode EL2_3. The first electrode EL1 of the second - third sub - pixel SP2_3 can include a first - first electrode EL1_1 and a first - second electrode EL1_2. The first electrode EL1 and the second electrode EL2 of the second - third sub - pixel SP2_3 can be spaced apart from each other by a predetermined distance and can be disposed in the emission region 100 of the corresponding sub - pixel.

[0305] When the light - emitting element LD is aligned in the corresponding sub - pixel, each of the second - first connection line CNL2 and the second - second connection line CNL2 disposed in the second sub - pixel boundary region 300 can transmit the same alignment voltage to the second electrode EL2 of the corresponding sub - pixel.

[0306] Figure 12 A display device according to an embodiment of the present disclosure is shown and is a schematic enlarged plan view corresponding to Figure 2 the region EA1 in

[0307] Except that the first electrode connected to the first connection line includes a first - first electrode, a first - second electrode, and a first - third electrode and the second electrode connected to the second connection line includes a second - first electrode and a second - second electrode, Figure 12 the configuration of the display device shown in Figure 11 can be substantially equivalent to or similar to

[0308] Referring to Figure 1a 、 Figure 2 and Figure 12 According to an embodiment of the present disclosure, a display device can include a substrate SUB, on which a first pixel PXL1, a second pixel PXL2, and a third pixel PXL3 are disposed. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be disposed adjacent to each other on the substrate SUB in the second direction DR2. In an embodiment, each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can include at least one sub - pixel.

[0309] The first pixel PXL1 may include a first sub-pixel SP1_1, a second sub-pixel SP2_1, and a third sub-pixel SP3_1. The second pixel PXL2 may include a first sub-pixel SP1_2, a second sub-pixel SP2_2, and a third sub-pixel SP3_2. The third pixel PXL3 may include a first sub-pixel SP1_3, a second sub-pixel SP2_3, and a third sub-pixel SP3_3.

[0310] In an embodiment of the present disclosure, a sub-pixel boundary region 300 is provided in a non-emission region 200 between corresponding emission regions 100 of two sub-pixels arranged adjacent to each other in a second direction DR2. For example, two connection lines may be provided in a sub-pixel boundary region 300 (hereinafter referred to as "first sub-pixel boundary region") provided between the corresponding emission regions 100 of the first sub-pixel SP1_1 and the first sub-pixel SP1_2. The two connection lines may include a second connection line CNL2 provided in the first sub-pixel SP1_1 (hereinafter referred to as "2-1 connection line") and a second connection line CNL2 provided in the first sub-pixel SP1_2 (hereinafter referred to as "2-2 connection line").

[0311] An imaginary line IL extending in a first direction DR1 may be provided between the 2-1 connection line CNL2 and the 2-2 connection line CNL2. The 2-1 connection line CNL2 and the 2-2 connection line CNL2 may form a mirror-symmetric structure with respect to the imaginary line IL. The 2-1 connection line CNL2 may be provided on the upper side in the second direction DR2 with respect to the imaginary line IL, and the 2-2 connection line CNL2 may be provided on the lower side in the second direction DR2 with respect to the imaginary line IL.

[0312] In an embodiment of the present disclosure, the 2-1 connection line CNL2 may be electrically and / or physically connected to a second electrode EL2 of the first sub-pixel SP1_1 through a second bridging pattern BRP2. The 2-1 connection line CNL2, the second bridging pattern BRP2, and the second electrode EL2 may include the same material and may be provided on the same plane. The 2-1 connection line CNL2, the second bridging pattern BRP2, and the second electrode EL2 may be integral with each other. Here, the second electrode EL2 may include a 2-1 electrode EL2_1 and a 2-2 electrode EL2_2, which branch upward from the second bridging pattern BRP2 in the second direction DR2.

[0313] In an embodiment of the present disclosure, the second-to-second connection line CNL2 can be electrically and / or physically connected to the second electrode EL2 of the first-to-second sub-pixel SP1_2 through the second bridging pattern BRP2. Here, the second electrode EL2 of the first-to-second sub-pixel SP1_2 can include a second-to-first electrode EL2_1 and a second-to-second electrode EL2_2, which branch downward from the second bridging pattern BRP2 in the second direction DR2.

[0314] As described above, when the light-emitting element LD is aligned in the corresponding sub-pixel, each of the second-to-first connection line CNL2 and the second-to-second connection line CNL2 provided in the first sub-pixel boundary region 300 can transmit the same alignment voltage to the second electrode EL2 of the corresponding sub-pixel.

[0315] The first connection line CNL1 provided in the non-emission region 200 of the first-to-first sub-pixel SP1_1 can be electrically and / or physically connected to the first electrode EL1 of the corresponding sub-pixel through the first bridging pattern BRP1. Here, the first electrode EL1 of the first-to-first sub-pixel SP1_1 can include a first-to-first electrode EL1_1, a first-to-second electrode EL1_2, and a first-to-third electrode EL1_3, which branch downward from the first bridging pattern BRP1 in the second direction DR2. In this case, the first contact electrode CNE1 can include a first-to-first contact electrode CNE1_1 provided on the first-to-first electrode EL1_1, a first-to-second contact electrode CNE1_2 provided on the first-to-second electrode EL1_2, and a first-to-third contact electrode CNE1_3 provided on the first-to-third electrode EL1_3. The first electrode EL1 and the second electrode EL2 of the first-to-first sub-pixel SP1_1 can be spaced apart from each other by a predetermined distance and can be provided in the emission region 100 of the corresponding sub-pixel.

[0316] The first connection line CNL1 provided in the non-emission region 200 of the first-to-second sub-pixel SP1_2 can be electrically and / or physically connected to the first electrode EL1 of the corresponding sub-pixel through the first bridging pattern BRP1. Here, the first electrode EL1 of the first-to-second sub-pixel SP1_2 can include a first-to-first electrode EL1_1, a first-to-second electrode EL1_2, and a first-to-third electrode EL1_3, which branch upward from the first bridging pattern BRP1 in the second direction DR2. The first electrode EL1 and the second electrode EL2 of the first-to-second sub-pixel SP1_2 can be spaced apart from each other by a predetermined distance and can be provided in the emission region 100 of the corresponding sub-pixel.

[0317] In an embodiment of the present disclosure, a sub-pixel boundary region 300 (hereinafter referred to as the "second sub-pixel boundary region") may be provided between corresponding emission regions 100 of a 2-2 sub-pixel SP2_2 and a 2-3 sub-pixel SP2_3 that are arranged adjacent to each other in a second direction DR2. Two connection lines may be provided in the second sub-pixel boundary region 300. The two connection lines may include a first connection line CNL1 (hereinafter referred to as the "1-1 connection line") provided in the 2-2 sub-pixel SP2_2 and a first connection line CNL1 (hereinafter referred to as the "1-2 connection line") provided in the 2-3 sub-pixel SP2_3.

[0318] An imaginary line IL extending in a first direction DR1 may be provided between the 1-1 connection line CNL1 and the 1-2 connection line CNL1. The 1-1 connection line CNL1 and the 1-2 connection line CNL1 may form a mirror-symmetrical structure with respect to the imaginary line IL. When the light-emitting elements LD are aligned in the corresponding sub-pixels, the 1-1 connection line CNL1 and the 1-2 connection line CNL1 may transmit the same alignment voltage to the first electrodes EL1 of the corresponding sub-pixels, respectively.

[0319] The 1-1 connection line CNL1 may be electrically connected and / or physically connected to the first electrode EL1 of the 2-2 sub-pixel SP2_2 through a first bridging pattern BRP1. The first electrode EL1 of the 2-2 sub-pixel SP2_2 may branch upward from the first bridging pattern BRP1 in the second direction DR2 and is thus provided in the emission region 100 of the corresponding sub-pixel. The first electrode EL1 of the 2-2 sub-pixel SP2_2 may include a 1-1 electrode EL1_1, a 1-2 electrode EL1_2, and a 1-3 electrode EL1_3. The second electrode EL2 of the 2-2 sub-pixel SP2_2 may include a 2-1 electrode EL2_1 and a 2-2 electrode EL2_2. The first electrode EL1 and the second electrode EL2 of the 2-2 sub-pixel SP2_2 may be spaced apart from each other by a predetermined distance and are provided in the emission region 100 of the corresponding sub-pixel.

[0320] The first-second connection line CNL1 can be electrically and / or physically connected to the first electrode EL1 of the second-third sub-pixel SP2_3 through the first bridging pattern BRP1. The first electrode EL1 of the second-third sub-pixel SP2_3 can branch downward from the first bridging pattern BRP1 along the second direction DR2, and is thus disposed in the corresponding sub-pixel. The first electrode EL1 of the second-third sub-pixel SP2_3 can include a first-first electrode EL1_1, a first-second electrode EL1_2, and a first-third electrode EL1_3. The second electrode EL2 of the second-third sub-pixel SP2_3 can include a second-first electrode EL2_1 and a second-second electrode EL2_2. The first electrode EL1 and the second electrode EL2 of the second-third sub-pixel SP2_3 can be spaced apart from each other by a predetermined distance and can be disposed in the emission region 100 of the corresponding sub-pixel.

[0321] Although various embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure.

[0322] Therefore, the embodiments disclosed in this specification are for illustrative purposes only and do not limit the technical spirit of the present disclosure. The scope of the claimed invention disclosed must be defined by the appended claims.

Claims

1. A display device, comprising: A substrate, including a display region and a non-display region; and A plurality of pixels, disposed on the display region, each including a plurality of sub-pixels, each of the plurality of sub-pixels including an emission region and a non-emission region, wherein, Each of the sub-pixels includes a display element layer, and the display element layer includes at least one light-emitting element that emits light, The display element layer includes: A first electrode and a second electrode, spaced apart from each other, and the light-emitting element is disposed between the first electrode and the second electrode; and Connection lines, including a first connection line extending in the row direction of the substrate and connected to the first electrode, and a second connection line extending parallel to the first connection line and connected to the second electrode, and Wherein, two of the connection lines having a symmetric structure are disposed in a region that is between the corresponding emission regions of two adjacent sub-pixels in the column direction of the substrate among the plurality of sub-pixels; Wherein, The region between the corresponding emission regions of the two sub-pixels is the non-emission region, and The two connection lines form a mirror-symmetric structure with respect to an imaginary line extending in the row direction in the region between the corresponding emission regions of the two sub-pixels; Wherein, the two connection lines include: The first connection line disposed in one of the two sub-pixels and connected to the first electrode of the one of the two sub-pixels; and The first connection line disposed in the other of the two sub-pixels and connected to the first electrode of the other of the two sub-pixels; and Wherein, The second electrode of each of the two sub-pixels includes a 2-1 electrode and a 2-2 electrode branched from the second connection line in the corresponding one of the two sub-pixels to the emission region in the corresponding one of the two sub-pixels, The 2-1 electrode and the 2-2 electrode are spaced apart from each other, and The first electrode of the corresponding one of the two sub-pixels is disposed between the 2-1 electrode and the 2-2 electrode.

2. The display device according to claim 1, wherein, The display element layer includes: A first contact electrode connecting one end of the relative ends of the first electrode and the light-emitting element; and A second contact electrode connecting the other end of the relative ends of the second electrode and the light-emitting element.

3. The display device according to claim 2, wherein, Each of the sub-pixels further includes a pixel circuit layer, and the pixel circuit layer includes at least one transistor electrically connected to the light-emitting element.

4. A display device, comprising: A substrate, including a display region and a non-display region; and A plurality of pixels, disposed on the display region, each including a plurality of sub-pixels, each of the plurality of sub-pixels including an emission region and a non-emission region, wherein, Each of the sub-pixels includes a display element layer, and the display element layer includes at least one light-emitting element that emits light, The display element layer includes: A first electrode and a second electrode, spaced apart from each other, and the light-emitting element is disposed between the first electrode and the second electrode; and A connection line includes a first connection line extending in the row direction of the substrate and connected to the first electrode, and a second connection line extending parallel to the first connection line and connected to the second electrode, and wherein, two connection lines having a symmetric structure in the connection lines are disposed in a region that is located between the corresponding emission regions of two sub-pixels adjacent to each other in the column direction of the substrate among the plurality of sub-pixels; wherein, the region between the corresponding emission regions of the two sub-pixels is the non-emission region, and the two connection lines form a mirror symmetric structure with respect to an imaginary line extending in the row direction in the region between the corresponding emission regions of the two sub-pixels; wherein, the two connection lines include: the first connection line disposed in one of the two sub-pixels and connected to the first electrode of the one of the two sub-pixels; and the first connection line disposed in the other of the two sub-pixels and connected to the first electrode of the other of the two sub-pixels; and wherein, the first electrode of each of the two sub-pixels includes a 1-1 electrode and a 1-2 electrode branched from the first connection line of the corresponding one of the two sub-pixels to the emission region of the corresponding one of the two sub-pixels, the 1-1 electrode and the 1-2 electrode are spaced apart from each other, and the second electrode of the corresponding one of the two sub-pixels is disposed between the 1-1 electrode and the 1-2 electrode.

5. The display device according to claim 4, wherein, The second connection line of the one of the two sub-pixels is disposed above the first connection line in the column direction in the one of the two sub-pixels, and the second connection line of the other of the two sub-pixels is disposed below the first connection line in the column direction in the other of the two sub-pixels.

6. The display device according to claim 5, wherein, The second connection lines of each of the two sub-pixels are spaced apart from each other, and the emission region of each of the two sub-pixels is disposed between the second connection lines of each of the two sub-pixels in the column direction.

7. The display device according to claim 6, wherein, The second electrode of each of the two sub-pixels includes a 2-1 electrode, a 2-2 electrode, and a 2-3 electrode branched from the second connection line of the one of the two sub-pixels to the emission region of the one of the two sub-pixels, the 2-1 electrode and the 2-2 electrode are spaced apart from each other, the 1-1 electrode is disposed between the 2-1 electrode and the 2-2 electrode, the 2-2 electrode and the 2-3 electrode are spaced apart from each other, and the 1-2 electrode is disposed between the 2-2 electrode and the 2-3 electrode.

8. The display device according to claim 4, wherein, The display element layer includes: a first contact electrode connecting the first electrode to one end of the opposite ends of the light-emitting element; and A second contact electrode that connects the second electrode to the other end of the opposite end of the light-emitting element.

9. The display device according to claim 8, wherein, Each of the sub-pixels further includes a pixel circuit layer that includes at least one transistor electrically connected to the light-emitting element.

10. A display device, comprising: A substrate including a display area and a non-display area; And A plurality of pixels disposed on the display area, each including a plurality of sub-pixels, each of the plurality of sub-pixels including an emission area and a non-emission area, wherein Each of the sub-pixels includes a display element layer that includes at least one light-emitting element that emits light, The display element layer includes: A first electrode and a second electrode spaced apart from each other, and the light-emitting element is disposed between the first electrode and the second electrode; and Connection lines including a first connection line extending in the row direction of the substrate and connected to the first electrode, and a second connection line extending parallel to the first connection line and connected to the second electrode, and Wherein, two connection lines having a symmetric structure among the connection lines are disposed in a region that is between the corresponding emission areas of two adjacent sub-pixels in the column direction among the plurality of sub-pixels; Wherein, The region between the corresponding emission areas of the two sub-pixels is the non-emission area, and The two connection lines form a mirror-symmetric structure with respect to an imaginary line extending in the row direction in the region between the corresponding emission areas of the two sub-pixels; Wherein, the two connection lines include: The second connection line disposed in one of the two sub-pixels and connected to the second electrode of the one of the two sub-pixels; and The second connection line disposed in the other of the two sub-pixels and connected to the second electrode of the other of the two sub-pixels; and Wherein, The first electrode of each of the two sub-pixels includes a 1-1 electrode and a 1-2 electrode branched from the first connection line of the corresponding one of the two sub-pixels to the emission area of the corresponding one of the two sub-pixels, The 1-1 electrode and the 1-2 electrode are spaced apart from each other, and The second electrode of the corresponding one of the two sub-pixels is disposed between the 1-1 electrode and the 1-2 electrode.

11. The display device according to claim 10, wherein, The display element layer includes: A first contact electrode that connects the first electrode to one end of the opposite end of the light-emitting element; and A second contact electrode that connects the second electrode to the other end of the opposite end of the light-emitting element.

12. The display device according to claim 11, wherein, Each of the sub-pixels further includes a pixel circuit layer that includes at least one transistor electrically connected to the light-emitting element.

13. A display device, comprising: A substrate including a display area and a non-display area; And A plurality of pixels disposed on the display area, each including a plurality of sub-pixels, each of the plurality of sub-pixels including an emission area and a non-emission area, wherein Each of the sub-pixels includes a display element layer, and the display element layer includes at least one light-emitting element that emits light. The display element layer includes: a first electrode and a second electrode, spaced apart from each other, and the light-emitting element is disposed between the first electrode and the second electrode; and connection lines, including a first connection line extending in the row direction of the substrate and connected to the first electrode, and a second connection line extending parallel to the first connection line and connected to the second electrode, and wherein, two connection lines having a symmetric structure among the connection lines are disposed in a region that is between the corresponding emission regions of two adjacent sub-pixels in the column direction of the substrate among the plurality of sub-pixels; wherein, the region between the corresponding emission regions of the two sub-pixels is a non-emission region, and the two connection lines form a mirror-symmetric structure with respect to an imaginary line extending in the row direction in the region between the corresponding emission regions of the two sub-pixels; wherein, the two connection lines include: the second connection line disposed in one of the two sub-pixels and connected to the second electrode of the one of the two sub-pixels; and the second connection line disposed in the other of the two sub-pixels and connected to the second electrode of the other of the two sub-pixels; and wherein, the second electrode of each of the two sub-pixels includes a 2-1 electrode and a 2-2 electrode branched from the second connection line of the corresponding one of the two sub-pixels to the emission region of the corresponding one of the two sub-pixels, and the 2-1 electrode and the 2-2 electrode are spaced apart from each other, and the first electrode of the corresponding one of the two sub-pixels is disposed between the 2-1 electrode and the 2-2 electrode.

14. The display device according to claim 13, wherein, The first connection line of one of the two sub-pixels is disposed above the second connection line in the column direction in the one of the two sub-pixels, and the first connection line of the other of the two sub-pixels is disposed below the second connection line in the column direction in the other of the two sub-pixels.

15. The display device according to claim 14, wherein, The first connection lines of each of the two sub-pixels are spaced apart from each other, and the emission region of each of the two sub-pixels is disposed between the first connection lines of each of the two sub-pixels in the column direction.

16. The display device according to claim 15, wherein, The first electrode of each of the two sub-pixels includes a 1-1 electrode, a 1-2 electrode, and a 1-3 electrode branched from the first connection line of the corresponding first sub-pixel of the two sub-pixels to the emission region of the corresponding first sub-pixel of the two sub-pixels, and the 1-1 electrode and the 1-2 electrode are spaced apart from each other, the 2-1 electrode is disposed between the 1-1 electrode and the 1-2 electrode, The 1-2 electrode and the 1-3 electrode are spaced apart from each other, and The 2-2 electrode is disposed between the 1-2 electrode and the 1-3 electrode.

17. The display device according to claim 13, wherein, The display element layer comprises: a first contact electrode connecting the first electrode to one of the opposite ends of the light emitting element; and A second contact electrode connects the second electrode to the other of the opposite ends of the light emitting element.

18. The display device according to claim 17, wherein, Each of the sub-pixels further includes a pixel circuit layer including at least one transistor electrically connected to the light emitting element.

19. A method of manufacturing a display device, comprising: Providing a substrate on which a plurality of sub-pixels are to be disposed, each of the plurality of sub-pixels comprising an emission region and a non-emission region; as well as A display element layer is formed on the substrate, the display element layer emitting light from the emission region of each of the sub-pixels, wherein Forming the display element layer includes: forming a first electrode and a second electrode spaced apart from each other in the emission region, At the same time, a first metal layer and a second metal layer are formed in the non-emitting region, wherein the first metal layer is connected to the first electrode and extends in one direction, and the second metal layer is connected to the second electrode and extends parallel to the one direction; forming an electric field between the first electrode and the second electrode by applying different alignment voltages to the first metal layer and the second metal layer, and then aligning a plurality of light emitting elements between the first electrode and the second electrode; forming connection lines on the substrate including the light emitting element by removing a portion of one of the first metal layer and the second metal layer, the connection lines including a first connection line connected to the first electrode and a second connection line connected to the second electrode; forming a first contact electrode electrically connecting the first electrode to one of opposite ends of each of the light emitting elements; and forming a second contact electrode electrically connecting the second electrode to the other of the opposite ends of each of the light emitting elements, Aligning the multiple light-emitting elements includes: setting two metal layers in the first metal layer or the second metal layer that are formed on the same layer and to which the same alignment voltage is applied in such an area: the area is located between the corresponding emission areas of two sub-pixels in the sub-pixels that are arranged adjacent to each other in the column direction of the substrate.

20. The method according to claim 19, wherein, The area between the corresponding emission areas of the two sub-pixels is the non-emission area, The method also includes: after aligning the light-emitting element, arranging two of the connecting lines having a mirror-symmetric structure relative to an imaginary line in the area between the corresponding emission areas of the two sub-pixels, wherein the imaginary line extends in a row direction intersecting the column direction.

21. The method according to claim 20, wherein, The two metal layers to which the same alignment voltage is to be applied include: The first metal layer is disposed in one of the two sub-pixels and connected to the first electrode of the one of the two sub-pixels; and The first metal layer disposed in the other sub-pixel of the two sub-pixels and connected to the first electrode of the other sub-pixel of the two sub-pixels.

22. The method according to claim 20, wherein, The two metal layers to which the same alignment voltage is to be applied include: The second metal layer disposed in one sub-pixel of the two sub-pixels and connected to the second electrode of the one sub-pixel of the two sub-pixels; and The second metal layer disposed in the other sub-pixel of the two sub-pixels and connected to the second electrode of the other sub-pixel of the two sub-pixels.

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