Burst error tolerant decoder and related systems, methods and devices

Abstract

The embodiments disclosed in the present disclosure are generally related to systems, methods and devices for correcting burst errors caused during the transmission of coded information blocks. Some embodiments relate to decoders that are configured to test candidate corrections for received information blocks and select candidate corrections that best fit the characteristics of burst errors expected for a type of transmission scheme. Such tested candidate corrections can be selected based on the characteristics of burst errors generally caused for a type of transmission scheme. Some embodiments relate to decoders that are configured to test candidate corrections for correcting burst errors and perform standard error correction techniques, such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems incorporating such decoders, such as serial / deserializer interfaces.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the filing date of U.S. Provisional Patent Application Serial No. 62,739,744, filed on October 1, 2018, entitled “BURST ERROR TOLERANT DECODER AND RELATED SYSTEMS, METHODS, AND DEVICES,” and claims the benefit of the filing date of pending U.S. Patent Application Serial No. 16 / 283,634, filed on February 22, 2019, entitled “BURST ERROR TOLERANT DECODER AND RELATED SYSTEMS, METHODS, AND DEVICES,” the contents and disclosures of each of which are hereby incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate generally to serial communications, and more particularly to errors introduced during communications over a serial communications channel and the correction of those errors. Background Art

[0004] In many embedded systems and other computing systems, the movement of data between peripherals and a host or between peripherals and peripherals can be a large portion of the data traffic on the various buses that may be present in such systems. As data moves through these systems, it is sometimes moved in parallel (i.e., multiple bits are transferred simultaneously) and sometimes moved serially (i.e., one bit is transferred at a time).

[0005] In conventional inter-system communications, a serializer-deserializer ("SerDes") is typically used at the interface between a parallel communication channel and a serial communication channel. In a typical arrangement, a SerDes transmitter will generate a sequence of logic 1s and 0s based on input data, convert them into analog values ​​(e.g., +0.5V and -0.5V, but not limited to), adjust the analog signal based on the medium used for the serial communication channel (e.g., copper wire, printed circuit board wiring, and cable, but not limited to), increase the parallel clock to the frequency of the serial communication channel, and transmit the data out through the serial communication channel. A SerDes receiver receives serial data from the serial communication channel, slows down the data to match the frequency of the parallel communication channel, and then transmits the data through the parallel communication channel.

[0006] Conventional inter-system communication architectures assume few or no bit errors at these interfaces, however, the inventors of the present disclosure recognize that, particularly at high transmission rates, such assumptions do not apply. Therefore, the inventors of the present disclosure recognize the need for robust error correction within communication systems that can account for at least some of these errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] While the present disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features, benefits and / or advantages of the embodiments of the present disclosure will become apparent to those skilled in the art from the following detailed description and accompanying drawings, in which:

[0008] Figure 1 A block diagram of a burst-error tolerant decoder is shown in accordance with one or more embodiments of the present disclosure.

[0009] Figure 2A A block diagram of burst error decoding operations in accordance with one or more embodiments of the present disclosure is shown.

[0010] Figure 2B A block diagram of burst error decoding operations in accordance with one or more embodiments of the present disclosure is shown.

[0011] Figure 3A A decision tree for selecting among candidate corrections according to one or more embodiments of the present disclosure is shown.

[0012] Figure 3B One or more embodiments of the present disclosure are shown. Figure 3A Block diagram of the sorting elements in a decision tree.

[0013] Figure 4 A SerDes interface implementing at least one decoder with burst tolerance is shown in accordance with one or more embodiments of the present disclosure.

[0014] Figure 5 A flow chart of an exemplary error correction process according to one or more embodiments of the present disclosure is shown.

[0015] Figure 6 A block diagram of a decision feedback equalization technique known to the inventors of the present disclosure is shown. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings which form a part thereof, and in which specific exemplary embodiments in which the present disclosure may be practiced are shown by way of example. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0017] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations for describing embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structures or components must be identical in size, composition, configuration, or any other attribute.

[0018] It is readily understood that the components of the embodiments as described herein as a whole and shown in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0019] The following description may include examples to help those of ordinary skill in the art practice the embodiments disclosed in the present invention. The use of the terms "exemplary", "example", "for example", "eg", etc. means that the description is illustrative, and although the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the scope of the embodiments or the present disclosure to the specified components, steps, features, functions, etc.

[0020] In addition, the specific embodiments shown and described are examples only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific embodiments shown and described are exemplary only and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the partitioning of logic between block definitions and individual blocks is an example of a specific embodiment. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0021] It should be understood that any reference to an element using names such as "first", "second", etc. herein does not limit the number or order of these elements, unless such limitations are explicitly stated. On the contrary, these names are used herein as a convenient method to distinguish two or more elements or two or more instances of an element. Therefore, the reference to the first element and the second element does not mean that only two elements can be used, or that the first element must be before the second element in some way. Moreover, unless otherwise stated, a group of elements may include one or more elements. Similarly, an element sometimes mentioned in the singular may also include one or more instances of an element.

[0022] Those of ordinary skill in the art will appreciate that any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout the specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. For clarity of presentation and description, some of the accompanying drawings may show signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a bus of signals, wherein the bus may have various bit widths, and the present disclosure may be implemented on any number of data signals including a single data signal.

[0023] The various illustrative logical blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or implemented using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof.

[0024] A general-purpose processor (also referred to herein as a host processor or just host) may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0025] A general purpose processor can be part of a general purpose computer, which should be considered a special purpose computer when configured to execute instructions (e.g., software code) for executing embodiments of the present disclosure. In addition, when configured according to embodiments of the present disclosure, such special purpose computers improve the functionality of general purpose computers, because in the absence of the present disclosure, general purpose computers will not be able to perform the processes of the present disclosure. The present disclosure also provides meaningful limitations in one or more specific technical environments beyond abstract concepts. For example, embodiments of the present disclosure provide improvements in the field of inter-system communication and error correction technology.

[0026] Moreover, it should be noted that embodiments may be described according to processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operational behaviors as sequential processes, many of these behaviors may be performed in another order, in parallel, or substantially simultaneously. In addition, the order of actions may be rearranged. A process may correspond to a method, a thread, a function, a process, a subroutine, and a subprogram, but is not limited thereto. In addition, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, these functions may be stored or transmitted to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that facilitate the transfer of a computer program from one location to another.

[0027] Any characterization of something as "typical", "conventional" or "known" in this disclosure does not necessarily mean that it is disclosed in the prior art or understood in the prior art for the aspect in question. It also does not necessarily mean that it is well-known, well-understood or commonly used in the relevant art.

[0028] As used herein, a "bit error" means a received digital information bit that is different from the corresponding transmitted bit.

[0029] As used herein, a "symbol" means a unit of information represented by one or more bits. For example, a particular communication system may transmit symbols, and each symbol may be represented by m bits (i.e., m consecutive bits). Symbols may be, for example, human-readable, computer-readable (e.g., encoded), and combinations thereof, but are not limited thereto. An example of a symbol used with the disclosed embodiments is a Reed-Solomon symbol (also commonly referred to as a "Reed-Solomon code").

[0030] As used herein, "symbol error" means that the received symbol is different from the user symbol (ie, the transmitted symbol). An example of a symbol error is that given an m-bit symbol, the symbol contains anywhere from 1 to m bit errors.

[0031] As used herein, "burst error" means two or more bit errors in a sequence. It is not necessary that all bits within a burst error actually constitute a bit error. By way of example, a burst error can be a sequence of bits that begins with a bit error and ends with a final bit error, such that there are enough error-free bits after the final bit error to "clear" the burst error event. A burst error event can be considered cleared (i.e., there are no more bit errors in the sequence of bits associated with the burst error event) when there are no additional bit errors in a sufficiently large window of past bits. As a more specific example, in the case of a burst error caused by a DFE, the burst error event can be considered cleared when all bits within the DFE filter are correct, e.g., for a 4-tap DFE, 4 error-free bits after the final bit error will be detected to determine that the error propagation associated with the DFE has ended. This is shown in the following burst error example with a 4-tap DFE, where the string is a bit error indication, the first of which will be received on the left. The double-underlined portion of the string indicates a bit error, and the single-underlined portion of the string indicates a non-error bit:

[0032] '... 01110000 ...': a 3-bit burst is cleared by 4 consecutive error-free bits. The error events in this example also happen to be consecutive, but this is not a requirement.

[0033] '... 01010000 ...': A 3-bit burst is cleared by 4 consecutive error-free bits.

[0034] '...0 100010000 ...'A 5-bit burst is cleared by 4 consecutive error-free bits. The middle 3 error-free bits (between the "1"s) are not enough to clear the error for the DFE, which must then wait for 4 bits.

[0035] The disclosed embodiments are not limited to systems that receive digital information represented using a binary system, and are applicable to systems that receive digital information represented by more than two levels of information. For example, one of ordinary skill in the art will appreciate that the disclosed embodiments are applicable to systems that receive digital information represented using four levels of information, such as a PAM4 sequence of digital information transmitted as bit pairs (i.e., two digital bits per transmission), where each bit pair represents a specific transmission voltage level; as well as PAM5, PAM8.

[0036] Typical SerDes interfaces known to the inventors of the present disclosure are capable of generating an efficient error-free digital information stream. However, at high transmission rates, bit errors and therefore symbol errors are introduced into the information transmitted by the SerDes transmitter and receiver.

[0037] One cause of bit errors (and therefore symbol errors) is inter-symbol interference (ISI), which is a form of signal distortion in which one bit representing the transmitted information interferes with subsequent bits representing the transmitted information.

[0038] Some conventional communication systems employ a technique known as decision feedback equalization (DFE) to equalize interference generated by previously received bits on currently received information bits. Figure 6 A block diagram of an exemplary filter implementing DFE techniques known to the inventors of the present disclosure and which may be used in conjunction with one or more embodiments of the present disclosure, as further described herein, is shown. Figure 6 In the illustrated embodiment, the input to the filter is from the slicer output, which is 1s and 0s representing the received digital information. The D1 to DN elements are standard D-type flip-flop (DFF) elements, where each flip-flop implements a delay of 1 clock cycle or "user interval" (UI). The shift register of such DFF elements implements a delay row that stores the N values ​​previously received. By way of example, in a typical receiver, N can be any number from 1 to 15, with the most common values ​​ranging from 5 to 8. At each point in the delay chain, the value at that location is multiplied by a multiplier from A1 to AN (i.e., the DFE multiplication value), where DN is multiplied by AN to obtain the DFE correction for each tap of the filter. All weighted taps are summed to obtain the DFE correction for the current symbol (D0 will be the next slicer output).

[0039] Those of ordinary skill in the art will appreciate that other DFE techniques may be used in conjunction with one or more embodiments, sometimes with minor modifications and adjustments to the specific implementation.

[0040] ISI increases significantly with increasing data transmission rates and / or increasing transmission line lengths. In addition, DFE assumes that all previous bits are correct. However, decision errors by the slice elements (e.g., selecting a logic 0 that should be a logic 1, or vice versa) affect the equalization of subsequent bits, which may lead to further bit errors. Therefore, DFE cannot achieve completely error-free transmission at all transmission rates and channels. In addition, received bit errors may lead to erroneous bits in the DFE equalizer, leading to further bit errors. A series of such errors in which the first error event leads to further error events until the final error (after which the bit is correct) is called a burst error.

[0041] In addition to DFE, some conventional communication systems also employ forward error correction (FEC) techniques to correct bit errors at the receiver that are not corrected by DFE. FEC techniques generally involve implementing a form of block coding, such as BCH (Bose, Ray-Chaudhuri, and Hocquenqhem) or RS (Reed-Solomon), which are known to those of ordinary skill in the art to have burst error correction capabilities. In a typical case, redundant data (such as parity symbols) is added to the message, and the receiver can use this redundant data to recover the message even if multiple errors are introduced during transmission (or storage). FEC can correct some bit errors, however, block coding techniques such as RS are limited to correcting t symbol errors in each n-symbol FEC block, where 2t=p, and p is the number of parity symbols. Therefore, for every two (2) parity symbols present in the FEC block, one randomly located symbol error can be located and corrected. In an n-symbol FEC block, if the number of symbol errors is greater than t, then the given FEC block exceeds the correction capability of the standard decoding algorithm and the output "corrected" FEC block may still include errors.

[0042] Therefore, burst errors (including those caused by DFE) can overwhelm the capabilities of conventional error correction techniques used to communicate across transmission interfaces (such as SerDes interfaces). In addition, the rate and size of burst errors will increase with the transmission rate, transmission line length, and transmission line quality. Block coding techniques like RS utilize some parity symbols to locate symbol errors and use other parity symbols to correct these symbol errors (i.e., replace with the correct user symbol).

[0043] Erasure decoding techniques for forward error correction typically involve using extrinsic information to locate symbol errors in the received transmission and thus can correct more symbols using the same number of parity symbols as block coding techniques such as RS. Erasure is the process of indicating one or more locations of information in an information block that are known to be in an error state and therefore can be erased. Erasure correction is the process of correcting those locations of an information block that have been erased.

[0044] For example, a typical erasure process may include the following operations: (i) calculate the syndrome (the syndrome is the result of performing an XOR operation on the parity symbols with the transmitted data symbols); (ii) calculate tau (tau is a polynomial derived from the known error locations); (iii) calculate the Forney modified syndrome (FMS), which combines tau with the calculated syndrome to form a combined syndrome for the decoding operation); (iv) calculate the error locations (e.g., using Berlekamp-Massey) and look for Q=(PE) / 2 errors, but if E=P, the erasure process may skip this step; (v) calculate the errata estimator polynomial Ω and combine the error locator polynomial with the FMS; (vi) find the root of the combination - here the erasure process is looking for the Q root, but if P=E, the erasure process may skip this step; (vii) calculate the errata locator polynomial derived from the error locator polynomial and tau And (viii) using Forney's method to compute the correction symbol for each error location. In the above example, "P" is the number of parity symbols available in the FEC block. "Q" is the number of randomly located errors corrected. "E" is the number of erasure symbols corrected.

[0045] In order to use conventional erasure techniques with block coding, an external indication is required as to which symbol or symbols are in an error state (e.g., the location of one or more symbols, but not limited to this), however, due to the high-power analog architecture commonly adopted, such indication is not available in the SerDes interface and cannot be easily added.

[0046] Therefore, one or more embodiments of the present disclosure as a whole relate to error correction using an erasure technique with a block coding technique such as RS. In one or more embodiments, all possible continuous erasure patterns in an FEC block are attempted. More specifically, for each of the possible continuous erasure patterns, the erasure symbols are arranged in order according to the received bit ordering that forms the FEC block.

[0047] For each erasure pattern, a nominal correction mask is identified. After computing the symbol erasure decoding for all possible erasure patterns, the results are compared to identify the correction pattern (i.e., correction mask) that best matches the burst error output of the SerDes interface. If other error correction possibilities are available (e.g., using standard FEC for RS), those results are compared to the results using the identified correction pattern, and based on the comparison, the other error correction results or the results using the identified correction pattern are selected.

[0048] One or more embodiments of the present disclosure are generally directed to a burst-tolerant decoder, and a SerDes interface and receiver incorporating the decoder. Figure 1 A block diagram of a burst-tolerant decoder 100 according to one or more embodiments of the present disclosure is shown. In one or more embodiments, the decoder 100 includes a standard RS decoder 114, a burst error decoder 104, a selection circuit 110, and a decode selection logic component 118. One or more embodiments of the decoder 100 can be implemented in hardware (e.g., circuits and electronic devices, but not limited thereto), digital logic (e.g., combinational logic gates, but not limited thereto), finite state machines (e.g., combinational logic components and flip-flops, but not limited thereto), and combinations thereof.

[0049] In one or more embodiments, the burst error decoder 104 is generally configured to try (i.e., test) all consecutive erasure patterns referred to in this disclosure as "candidate erasure patterns," and each such erasure pattern is referred to herein as a "candidate erasure pattern." One or more of these candidate erasure patterns may be selected by one or more burst decoder modules 106 (in Figure 1 The burst decoder 104 is configured to perform the candidate corrections 108 in parallel. Each burst decoder module 106 is configured to implement one of the candidate erasure patterns. In one or more embodiments, the burst decoder 104 is configured to output a candidate corrected transport block 122 in response to a test error correction performed using each candidate erasure pattern. Each such result of the subsequent output of the burst decoder module 106 and the burst decoder 104 is referred to herein as a "candidate correction 108."

[0050] In one or more embodiments, selection circuit 110 is generally configured to receive all candidate corrections 108 (ie, all results from trying candidate erasure patterns) from burst decoder 104 and select and output a burst candidate correction 112 .

[0051] The selection circuit 110 selects and outputs a burst candidate correction 112 by comparing the candidate corrections 108 and more generally selecting the candidate correction 108 that best "fits" the receiver or SerDes interface (including the decoder 100). The selection circuit 110 may include selection logic (not shown) for determining the best fit based on the type of receiver. For example, the selection circuit 110 may include SerDes discrimination logic (not shown) that identifies the candidate correction 108 corresponding to the shortest burst error, for example, because SerDes receivers rarely experience long burst errors. In one embodiment, such discrimination logic may define scoring criteria for scoring each candidate correction 108 according to its suitability as a burst error correction solution. For example, the scoring criteria may include one or more of burst error length, weighting factor, burst error grouping, etc. The selection circuit 110 may select the burst candidate correction 112 in response to the scoring criteria. In terms of weight factors, the scores may be weighted to favor corrections that are a better (or more useful) match for the type of error propagation expected for a given transmission scheme (in terms of a SerDes receiver, DFE error propagation). In terms of DFE error propagation, the continuity of a given correction pattern may be used, as well as information about the specific tap weights of the DFE.

[0052] In one or more embodiments, candidate correction 108 may be a binary mask referred to herein as a "correction mask" whose length is equal to the number of parity symbols or parity symbol bits. For example, if a transmission consists of 30 5-bit symbols (e.g., where there are 26 user symbols and 4 parity symbols), then the transmission consists of 150 bits (130 bits of user symbols and 20 bits of parity symbols), and thus the candidate correction mask has a length of 20 bits.

[0053] Notably, in view of "P=E", the resulting burst decoder logic of the disclosed embodiments is area efficient, requiring only a smaller number of logic gates than a standard erasure decoder implementation that must account for the case of P≠E.

[0054] Continuing with this example, when analyzing the candidate correction masks to select the best fit based on the shortest burst error (e.g., for a SerDes receiver), the selection circuit 110 can be configured to identify the first bit to be flipped and the last bit to be flipped in the 20-bit (four 5-bit symbols) correction mask of each candidate correction mask, and determine the difference (in bits) between the positions of these two bits. The difference can be used as a measure of the length of the burst error. The burst error lengths of the candidate correction masks can be compared, and the shortest burst error length can be selected in response to the comparison.

[0055] In one or more embodiments, decoder 100 may be configured to correct input transport block 102 in response to burst candidate correction 112 and output corrected transport block 122 .

[0056] In other embodiments, the decoding selection logic component 118 may be configured to receive the burst candidate correction 112 and the standard candidate correction 116 output by the standard RS decoder 114, select one of the burst candidate correction 112 and the standard candidate correction 116 (in this example, a 2-bit random symbol correction mask), and output the selected correction mask. The error correction circuit 120 may be configured to correct the input transmission block 102 in response to the selected correction mask, and output the corrected transmission block 122 in response to the selected candidate correction. For example, the error correction circuit 120 may be configured to perform an XOR operation on the selected correction mask and the input transmission block 102 to obtain the corrected transmission block 122. It is worth noting that the selected correction mask includes a mask and position information. In other words, by defining the bits to which erasure decoding is to be applied, the selected correction mask implicitly indicates the error position.

[0057] By way of explanation, in some contemplated transmission scenarios, an input transport block 102 may include not one burst error, but two or more independent "partial" burst errors, which may also be characterized as "single symbol" burst errors. A partial burst error occurs when there are a small number of erroneous consecutive bits in a symbol. For example, in an 8-bit symbol used with RS-FEC, burst error events of length 1 to 5 bit errors are limited to a single symbol.

[0058] When a first (in transmission order) partial burst error does not cause a second (in transmission order) partial burst error, the two burst error events (partial or non-partial) are independent. Since a partial burst error may be shorter than a symbol in bit length, and since the two partial burst errors are independent, the burst error decoder 104 may not generate a candidate correction 108 that actually corrects the two partial burst errors in the input transport block 102. In other words, two small independent error events occur, each of which only corrupts one RS symbol.

[0059] In some embodiments, the burst error decoder 104 may be configured to analyze candidate corrections with sufficient granularity to identify partial burst errors that occur in a given transmission scenario. In other embodiments, the decoder 100 may include a standard RS decoder 114 that is configured to use some parity symbols to locate error symbols with partial burst errors and use the remainder of these parity symbols to correct those error symbols. In one or more embodiments of the decoder 100, the RS decoder 114 and the burst decoder 104 may operate in parallel, simultaneously, or independently.

[0060] The decode selection logic 118 may be configured to select between the burst candidate correction 112 provided by the selection circuit 110 and the standard candidate correction 116 provided by the standard RS decoder 114. For example, if the candidate correction 108 is a correction mask and the standard candidate correction 116 is a correction mask, the corrected transport block 122 may be generated by XORing the data portion of the input transport block 102 with the correction mask corresponding to the selected burst candidate correction 112 or the standard candidate correction 116. For example, a binary 1 in the correction mask results in a bit correction at the output of the decoder 100, while a binary 0 in the correction mask will cause the input (and therefore the output) to remain unchanged.

[0061] In one or more embodiments, the corrected transport block 122 may include one or more parity symbols and user symbols, or only user symbols.

[0062] Figure 2A 2 is a diagram of an exemplary process 200 for testing burst error correction on a transport block in accordance with one or more embodiments of the present disclosure. Figure 2A As contemplated in the example shown, process 200 includes using candidate correction patterns 208 (candidate erasure patterns Burst0 to Burst 26 ) perform erasures. Each correction pattern 208 includes some number of symbols in the transport block 202 that are assumed to be erroneous symbols and will be erased (and subsequently corrected). In one embodiment, the number of erased symbols in the candidate correction pattern 208 is equal to the number of parity symbols in the transport block. In this example, the transport block 202 includes four parity symbols 206 (P0, P1, P2, and P3), so each candidate correction pattern 208 erases four consecutive symbols.

[0063] In one or more embodiments, the sequence of erased symbols may be used to fit the candidate correction pattern 208 of the transmission scheme and error distribution. For example, since burst errors (and partial burst errors) caused by DFE will affect consecutive bits and symbols, the erased symbols in each candidate correction pattern 208 are consecutive (i.e., immediately adjacent to each other in the symbol position of the transport block 202). Figure 2A and Figure 2B Other numbers of parity symbols and erasure symbols and their arrangements may be different than those described in the specification, which may fit the particular transmission scheme and / or error distribution of interest.

[0064] Therefore, for Figure 2AIn the example shown, the Burst0 candidate correction mode assumes that S0, S1, S2 and S3 have errors, the Burst1 candidate correction mode assumes that S1, S2, S3 and S4 have errors, the Burst2 candidate correction mode assumes that S2, S3, S4 and S5 have errors, and so on. 26 The candidate correction patterns assume that P0, P1, P2, and P3 have errors.

[0065] Figure 2B A diagram of an exemplary process 210 for performing a burst error decoding operation on a transport block 212 using a candidate correction pattern 214 is shown in accordance with one or more embodiments. Figure 2B In the example shown, the parity symbol is consecutive Figure 2A Compared with the transmission block 202, the parity symbols P0 to P3 are the same as the user symbols S0 to S1 in the transmission block 212. 25 In one or more embodiments, the parity symbol position may be selected for any of a variety of reasons and may be mixed with Figure 2A and Figure 2B For example, in Figure 2B In the example shown, the location of parity symbols P0, P1, P2, and P3 in transport block 212 is based on the SAS 4 protocol and, more specifically, is used to account for baseline wander within the receiver. The present disclosure is not limited to a specific location or positioning scheme for parity symbols in a transport block.

[0066] Figure 3A is an illustration of a decision tree 300 for a candidate correction selection process for selecting among candidate correction modes 208 according to one or more embodiments of the present disclosure. Figure 1 , for selection circuit 110 to select burst candidate correction 112 from candidate corrections 108, the shortest burst error length corrected by burst decoder module 106 is identified. Using an exemplary case, decision tree 300 is used to identify the best score among the 27 possibilities. Figure 3A The complete binary layout of the decision tree 300 is shown, where L1 to L5 represent 5 levels of binary ordering. In this example, the decision tree 300 orders the scores of two candidate correction patterns 208 at a time in the tree element 302, where the candidate correction with the lowest score is selected at each stage and passed to the next stage.

[0067] In one embodiment, the tree ordering element 310 (see Figure 3B) are sorted in parallel until the lowest score is found, which corresponds to the burst candidate correction 112. In one or more embodiments, the final output from the tree can be a score, error location information, and / or the best candidate correction (e.g., a binary correction mask). Those of ordinary skill in the art will appreciate that any of a variety of suitable sorting processes can be used, including merge sort, selection sort, insertion sort, exchange sort, and combinations thereof.

[0068] Figure 3B A tree ordering element 310 configured to make a decision between candidate corrections based on a comparison criterion is shown according to one or more embodiments. In one or more embodiments, the tree ordering element 310 may include a digital comparator 312, a multiplexer (MUX) 316, a MUX 320, and a MUX 324. The digital comparator 312 may be configured to compare with digital values ​​(here, the scores ScoreL and ScoreR of the two candidate corrections), and output a selection signal SEL 314 in response to the comparison result (i.e., which score is smaller or larger), as configured. MUX 316 may be configured to receive two candidate corrections CorrL and CorrR, and output one of the two candidate corrections in response to the selection signal SEL 314 provided by the digital comparator 312. MUX 320 may be configured to receive two index reference values ​​IndexL and IndexR, and output one of the two index reference values ​​in response to the selection signal SEL 318 provided by MUX 316 or the digital comparator 312. In one or more embodiments, IndexL and IndexR provide location information for where to apply correction, for example, providing a starting symbol number for a given correction mask. MUX 324 can be configured to receive two scores ScoreL and ScoreR, and output one of the two scores in response to a selection signal SEL 314. The outputs of the various elements, IndexO, CorrO, and ScoreO, can be provided as input to the next tree sorting element, or if all candidate corrections have been compared, as outputs of a burst candidate correction (e.g., the best candidate correction according to the comparison criteria used). The tree sorting element 310 uses the score to select the winner in each tree element (TE) 302. The selected output includes indexes, scores, and candidate corrections. For convenience only, these indexes, corrections, and scores are referred to as left and right, or "L" and "R" in this article, and other conventions can be used.

[0069] In one or more embodiments, selection is made between the standard candidate correction 116 and the burst candidate correction 112 by calculating a score for the standard candidate correction 116, then comparing the standard score to the score associated with the burst candidate correction 112, and selecting the lowest score to determine the final decoder output by the decode selection logic component 118.

[0070] Exemplary conditions for an embodiment of selecting between the standard decoder method and the burst decoder result method are given in Table 2 below. If the standard decoder fails to decode and indicates that it cannot perform a decoding operation, the burst error decoder output is selected as the decoding method, that is, the best burst error decoder correction mask is selected as the correction mask for the current FEC block. If the standard decoder reports that only a single error symbol is corrected, the standard decoder is selected. If the standard decoder reports that it has corrected 2 error symbols, the decoder selection is performed by comparing the scores of the two methods. For a burst decoder, the score can simply be the length of the proposed burst error correction solution. The score of the standard decoder can be determined by calculating the burst length of each symbol correction, looking up the score value for each burst length (e.g., a lookup table that returns a predetermined score in response to the burst length (actual value or interpolated value)), and then summing the two scores to obtain the total standard decoder score.

[0071]

[0072] Table 1: Decoder method selection .

[0073] In one or more embodiments, three constants may be used to help determine the score of the standard decoder output (i.e., the standard candidate correction 116), one constant for a single bit error symbol correction (S1), one constant for a 2-bit error correction symbol (S2), and another constant for a symbol correction greater than 2 bits (Sn). Exemplary settings for S0, S1, and Sn are S0=2, S1=4, and Sn=8, but these values ​​may be configured via register values ​​in any implementation that allows for fine-tuning based on field operation when operating with a SerDes receiver. In one or more embodiments, the values ​​of S0 to Sn may be selected to represent the relative likelihood that the standard decoder correction mask is superior to a burst error decoder, for example based on the distribution of DFE burst errors. More specifically, such DFE burst errors typically result in single bit error or 2-bit error events, so the likelihood of longer bursts becomes progressively lower. Thus, two single-bit correction masks from a standard decoder may be assigned a low score, two double-bit corrections may be assigned a medium score, and any other correction may be assigned a poor score (two independent error events, 3 bits each, and each event still fitting into a single RS symbol is not a good correction candidate). The given score is compared to the burst length output by the burst decoder to determine the best candidate.

[0074] An example of a choice of mapping correction symbols to score values ​​for a standard decoder is given in Table 2.

[0075]

[0076] Table 2: Score selection table

[0077] In one or more embodiments, a limit may be imposed on the burst length supported by the burst decoder so that very long burst corrections are prevented from being performed and instead a decoding failure is indicated. For example, in the case of SAS 4, the limit may be set to burst length = 12 so that any burst decoder output longer than 12 bits will be marked as a decoding failure.

[0078] One or more embodiments are directed to a SerDes interface (and / or a SerDes receiver) incorporating a burst error tolerant decoder according to one or more embodiments of the present disclosure. Figure 4 A block diagram of an exemplary SerDes interface 400 according to one or more embodiments of the present disclosure is shown. The SerDes interface 400 may be, for example, a SerDes transmission system. In one or more embodiments, the SerDes interface 400 includes a transmitter stage 410, a receiver stage 420, and a channel 416 operably coupled therebetween. In one or more embodiments, the transmitter stage 410 includes a block encoder 412 and a transmitter (TX) 414.

[0079] The block encoder 412 is generally configured to block encode data transmissions, for example, using a block encoding technique such as RS. The TX 414 is generally configured to "serialize" (i.e., take a parallel bus of input bits and drive them serially onto a physical transmission medium such as, but not limited to, a physical wire, a "differential pair" wire, a fiber optic wire, and a cable) of the channel 416 for block encoded bits of information received via the parallel interface 402 and provide a serial data stream to the channel 416. Although not shown, other transmitter functions may also be included in the transmitter stage 410, such as transmitter emphasis (e.g., a 3-tap FIR filter that weights 3 consecutive bits together with a configurable weight value to obtain a desired transmission voltage) and transmission scaling (e.g., adding ± scaling voltages to drive the transmission medium at a selected voltage).

[0080] Channel 416 is the physical medium used to transmit the serial data stream to receiver stage 420. In one or more embodiments, receiver stage 420 includes equalization filter and slicer 422, block formatter 424, and burst error tolerant decoder 426. Equalization filter and slicer 422 is configured to perform decision-based ISI cancellation on the received transmission and then "slice" the transmission signal into 1s and 0s (which are fed back into the equalizer to correct the next bit), as described above with respect to DFE correction. Block formatter 424 is configured to block the transmission of 1s and 0s into transmission blocks according to the convention used by block encoder 412. Burst error tolerant decoder 426 is configured to perform error correction according to one or more embodiments of the present disclosure, including, for example, implementing a burst error decoder as described herein.

[0081] One or more embodiments of the present disclosure are generally directed to communication systems implementing one or more transmission scheme interfaces, such as the SerDes interface 400, and inter-system communications implementing burst error decoding as described herein.

[0082] Figure 5A flow chart of a process 500 for burst error correction according to an embodiment of the present disclosure is shown. In step 502, a received transmission information block is tested for error correction using one or more candidate correction patterns. In one embodiment, the received transmission information block may be FEC encoded. The one or more candidate correction patterns may be erasure patterns, i.e., multiple consecutive symbols or bits of the received block with known starting and ending positions within the received block. In step 504, candidate correction outputs in response to the test error correction of step 502 are compared according to a scoring criterion. Each candidate correction may correspond to one of the candidate correction patterns for test error correction. In one embodiment, the candidate correction may be a bit mask using some predetermined convention to indicate bits to be flipped and bits to remain unchanged within the received block (e.g., "1" indicates flipping, "0" indicates remaining unchanged). In step 506, burst candidate corrections are determined in response to the comparison of the candidate corrections of step 504. In one embodiment, the burst error lengths calculated according to one or more embodiments of the present disclosure for candidate corrections may be compared, and the comparison criteria (e.g., selecting a smaller burst error length) may be used to select the burst candidate correction. The received transmission information block is error corrected using the selected burst candidate correction in step 508. The corrected transmission information block may be output, provided to another functional block for further processing, or otherwise.

[0083] Although single-duplex operation may be described in conjunction with one or more embodiments, the disclosure is not limited thereto. In one or more embodiments, the SerDes interface may implement full-duplex operation (eg, data conversion occurs in both directions simultaneously) and may switch between single-duplex operation and full-duplex operation.

[0084] Although a SerDes interface for converting from parallel transmission to serial transmission and back to parallel transmission may have been described, the present disclosure is not limited thereto. Embodiments of the burst decoder and related decoding techniques described herein may be used in an interface for converting from serial transmission to parallel transmission and then back to serial transmission. Embodiments of the burst decoder and related decoding and error correction techniques described herein may also be used in an interface for converting from parallel transmission to higher / lower bandwidth and then back. Embodiments of the burst decoder and related decoding and error correction techniques described herein may also be used in an interface between purely serial channels.

[0085] Furthermore, the present disclosure is not limited to SerDes interfaces.The burst decoder and associated decoding and error correction techniques may be used in other transmission scheme interfaces, including those for which burst errors are heretofore generally accepted as unavoidable.

[0086] Those skilled in the art will recognize many advantages and benefits from the embodiments of the present disclosure. For example, higher fault tolerance, support for longer transmission links, and more robust operation. In addition, since the decoder according to the embodiments of the present disclosure can correct more errors than conventional decoders, the design constraints on the SerDes interface can be relaxed because the errors can be corrected. By way of example, the design constraints may include the length of the transmission medium, the material used for the transmission medium, shielding from extraneous noise, etc.

[0087] Another advantage of embodiments of the burst error correction techniques of the present disclosure is that they can be implemented in conjunction with other error correction techniques, such as standard error correction techniques (eg, techniques specified in a standard).

[0088] Those skilled in the art will recognize that burst error decoding techniques and burst error decoders have a wide range of applications in addition to those described herein. For example, the burst error decoders described in the present disclosure may be implemented in the following media: storage applications, for example, interfaces implemented in point-to-point serial protocols such as Serial Attached SCSI (e.g., SAS 1, SAS 2, SAS3, and SAS 4), which move data into or out of computer storage elements such as hard disk drives, tape drives, and solid-state drives; Serial ATA, which is a computer bus interface that connects a host bus adapter to mass storage devices (such as hard disk drives, solid-state drives, and tape drives); and PCI and PCI express, which are interfaces for connecting devices to separate serial links of a host. In addition, the burst error decoders described in the present disclosure may be implemented in network switches (e.g., Ethernet switches), wireless routers, fiber optic communication switches, and the like.

[0089] Without departing from the scope of the present disclosure, the features of the various embodiments described herein are not mutually exclusive and may exist in various combinations and arrangements, even if such combinations or arrangements are not explicitly described herein. In fact, those of ordinary skill in the art will recognize variations, modifications, and other specific implementations of what is described herein without departing from the scope of the present disclosure. Therefore, the present invention should not be limited only by the foregoing exemplary description, but only by the appended claims and their legal equivalents.

[0090] Additional non-limiting embodiments of the present disclosure include:

[0091] Embodiment 1: A decoder configured to perform error correction on an information block including user symbols and at least one parity symbol, the decoder comprising: a first error correction circuit configured to output a candidate correction in response to test error correction of the information block using a corresponding candidate correction mode; a selection circuit configured to select a burst candidate correction from the candidate corrections; and a second error correction circuit configured to perform error correction on the information block in response to the selected burst candidate correction.

[0092] Embodiment 2: A decoder according to embodiment 1, wherein the first error correction circuit is configured to perform test error correction on the information block in response to the candidate correction pattern in the following manner: in response to performing a first test error correction on the information block using a first candidate correction pattern among the candidate correction patterns, outputting a first candidate correction; and in response to performing a second test error correction on the information block using a second candidate correction pattern among the candidate correction patterns, outputting a second candidate correction.

[0093] Embodiment 3: A decoder according to any one of embodiments 1 and 2, wherein the selection circuit is configured to select the burst candidate correction from the candidate corrections by: comparing the error lengths of the candidate corrections; and selecting the candidate correction corresponding to the shortest error length to obtain the burst candidate correction.

[0094] Embodiment 4: A decoder according to any one of embodiments 1 to 3, wherein, for a given candidate correction, the selection circuit is configured to: identify a first bit to be corrected and a second bit to be corrected in the information block according to the given candidate correction; and determine a distance in bits between the first bit to be corrected and the second bit to be corrected.

[0095] Embodiment 5: A decoder according to any one of embodiments 1 to 4, wherein the second error correction circuit is configured to correct errors in the information block in response to the selected burst candidate correction in the following manner: correct errors in the information block in response to the selected burst candidate correction.

[0096] Embodiment 6: A decoder according to any one of embodiments 1 to 5, wherein the first error correction circuit is configured to perform test error correction on the information block in response to the candidate correction pattern in the following manner: perform test error correction on the information block in response to one or more candidate erasure patterns, wherein the one or more candidate erasure patterns are continuous.

[0097] Embodiment 7: A decoder according to any one of embodiments 1 to 6, wherein the second error correction circuit is configured to correct the information block in response to the one or more candidate erasure patterns in the following manner: erasing and decoding one or more bits or symbols of the information block using a correction mask corresponding to the selected burst candidate correction, wherein a correction mask in the one or more correction masks has: a length equal to the number of parity symbols associated with the information block, or a length equal to the number of bits of the parity symbol associated with the information block.

[0098] Embodiment 8: A decoder according to any one of embodiments 1 to 7, wherein the first error correction circuit is configured to test error correction on the information block in response to the one or more candidate erasure patterns by calculating one or more symbol erasure decodings in response to the one or more candidate erasure patterns.

[0099] Embodiment 9: A decoder according to any one of Embodiments 1 to 8, further comprising a standard error correction circuit, the standard error correction circuit being configured to output a standard candidate correction in response to performing standard error correction on the information block using a standard error correction protocol.

[0100] Embodiment 10: A decoder according to any one of Embodiments 1 to 9, wherein the selection circuit is configured to select one of the standard candidate correction and the burst candidate correction.

[0101] Embodiment 11: A decoder according to any one of embodiments 1 to 10, wherein the second error correction circuit is configured to correct the information block in response to the selected candidate correction in the following manner: correct the information block in response to a selected one of the standard candidate correction and the burst candidate correction.

[0102] Embodiment 12: A decoder according to any one of embodiments 1 to 11, wherein the selection circuit is configured to select one of the standard candidate correction and the burst candidate correction in the following manner: selecting the burst candidate correction in response to the result of performing standard error correction on the information block, the result indicating that decoding or error correction of the information block failed; selecting the standard candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that only a single error symbol is corrected or can be corrected; selecting the burst candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that two or more error symbols are corrected or can be corrected, and the score of the burst candidate correction is greater than or equal to the score of the standard decoder; and selecting the standard candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that two or more error symbols are corrected or can be corrected, and the score of the standard candidate correction is greater than the score of the standard decoder.

[0103] Embodiment 13: A decoder according to any one of embodiments 1 to 12, wherein the selection circuit is configured to: determine the score of the burst candidate correction in response to the length of the burst candidate correction; and determine the score of the standard candidate correction by: determining one or more standard candidate lengths, each of the one or more standard candidate lengths corresponding to a sign correction of the standard candidate correction; identifying the score associated with the one or more standard candidate lengths in response to a lookup table, wherein the lookup table includes score values ​​associated with the standard candidate lengths; and determining the score of the standard candidate correction in response to the identified score.

[0104] Embodiment 14: A decoder according to any one of Embodiments 1 to 13, wherein the standard error correction circuit is configured to perform standard error correction on the information block by performing forward error correction on the information block.

[0105] Embodiment 15: A decoder according to any one of Embodiments 1 to 14, wherein performing the forward error correction on the information block includes performing Reed-Solomon error correction.

[0106] Embodiment 16: A decoder according to any one of Embodiments 1 to 15, wherein the information block is a forward error correction coded information block.

[0107] Embodiment 17: A burst-tolerant transmission interface, comprising: a transmitter configured to sequentially provide bits of a forward error correction (FEC) encoded transmission block to a physical transmission line; and a receiver configured to: receive transmission bits of the FEC encoded transmission block from the physical transmission line; detect bits in the transmission bits that exhibit characteristics indicating burst errors caused in the FEC encoded transmission block during transmission through the physical transmission line; and change at least some of the detected bits.

[0108] Embodiment 18: A transmission interface according to embodiment 17, wherein the receiver includes a burst error decoder, wherein the burst error decoder is configured to test a correction mode for correcting errors in consecutive bits of received transmission bits in the FEC encoded transmission block.

[0109] Embodiment 19: A transmission interface according to any one of embodiments 17 and 18, wherein the receiver includes a standard error correction circuit, the standard error correction circuit is configured to perform a standard error correction protocol on the received transmission bits in the FEC encoded transmission block, and wherein the receiver is configured to select one of the result of the standard error correction circuit and the result of the burst error decoder.

[0110] Embodiment 20: A transmission interface according to any one of Embodiments 17 to 19, wherein the bits indicating burst errors each indicate a partial burst error.

[0111] Embodiment 21: A method for correcting forward error correction (FEC) encoded information blocks, the method comprising: generating candidate corrections in response to test error correction of the information block using a candidate correction pattern; selecting a burst candidate correction from the candidate corrections; and correcting the information block in response to the selected burst candidate correction.

[0112] Embodiment 22: The method according to Embodiment 21 also includes: generating a first candidate correction in response to performing a first test error correction on the information block using a first candidate correction among the candidate corrections; and generating a second candidate correction in response to performing a second test error correction on the information block using a second candidate correction among the candidate corrections.

[0113] Embodiment 23: A method according to any one of embodiments 21 and 22, wherein the selecting the candidate correction among the candidate corrections includes selecting a burst candidate correction in response to the first candidate correction and the second candidate correction.

[0114] Embodiment 24: A method according to any one of Embodiments 21 to 23, wherein the selecting the burst candidate correction in response to the first candidate correction and the second candidate correction includes selecting one of the first candidate correction and the second candidate correction in response to comparing a first error length corresponding to the first candidate correction and a second error length corresponding to the second candidate correction.

[0115] Embodiment 25: A method according to any one of embodiments 21 to 24, wherein the selection of the burst candidate correction in response to the first candidate correction and the second candidate correction also includes: determining the first error length or the second error length by: identifying a first bit to be corrected and a second bit to be corrected in the information block; and determining the distance in bits between the first bit to be corrected and the second bit to be corrected.

[0116] Embodiment 26: A method according to any one of Embodiments 21 to 25, wherein the selecting one of the first candidate correction and the second candidate correction in response to comparing the first error length corresponding to the first candidate correction and the second error length corresponding to the second candidate correction includes: selecting the first candidate correction in response to the first error length being shorter than the second error length; and selecting the second candidate correction in response to the second error length being shorter than the first error length.

[0117] Embodiment 27: A method according to any one of Embodiments 21 to 26, wherein the test error correction of the information block in response to the candidate correction pattern includes performing test error correction on the information block in response to a candidate erasure pattern, wherein the candidate erasure pattern is continuous within the information block.

[0118] Embodiment 28: A method according to any one of Embodiments 21 to 27, wherein the error correction of the information block in response to the candidate erasure pattern includes: defining a correction mask corresponding to the candidate erasure pattern, wherein the correction mask in the correction mask has a length equal to the number of parity symbols associated with the information block or the bit length of the parity symbols associated with the information block.

[0119] Embodiment 29: A method according to any one of Embodiments 21 to 28, wherein the test error correction of the information block in response to the candidate erasure pattern includes calculating symbol erasure decoding in response to the candidate erasure pattern.

[0120] Embodiment 30: A method according to any one of Embodiments 21 to 29, wherein performing the test error correction on the information block in response to the candidate correction pattern also includes performing standard error correction on the information block in response to a standard error correction protocol.

[0121] Embodiment 31: A method according to any one of Embodiments 21 to 30, wherein the selecting the candidate correction among the candidate corrections includes selecting one of the standard candidate correction and the burst candidate correction.

[0122] Embodiment 32: A method according to any one of Embodiments 21 to 31, wherein the error correction of the information block in response to the selected candidate correction includes error correction of the information block in response to a selected one of the standard candidate correction and the burst candidate correction.

[0123] Embodiment 33: A method according to any one of embodiments 21 to 32, wherein the selecting one of the standard candidate correction and the burst candidate correction includes: selecting the burst candidate correction in response to the result of performing standard error correction on the information block, the result indicating that decoding or error correction of the information block failed; selecting the standard candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that only a single error symbol is corrected or can be corrected; selecting the burst candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that two or more error symbols are corrected or can be corrected, and the score of the burst candidate correction is greater than or equal to the score of the standard decoder; or selecting the standard candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that two or more error symbols are corrected or can be corrected, and the score of the standard candidate correction is greater than the score of the standard decoder.

[0124] Embodiment 34: A method according to any one of embodiments 21 to 33, wherein the selecting one of the standard candidate correction and the burst candidate correction also includes: determining the score of the burst candidate correction in response to the length of the burst candidate correction; and determining the score of the standard candidate correction by: determining a length, each of the lengths corresponding to a sign correction of the standard candidate correction; identifying a score associated with the length in response to a lookup table, wherein the lookup table includes score values ​​associated with the length; and determining the score of the standard candidate correction in response to the identified score.

[0125] Embodiment 35: A method according to any one of Embodiments 21 to 34, wherein performing the standard error correction on the information block in response to the standard candidate correction includes performing forward error correction on the information block.

[0126] Embodiment 36: The method of any one of Embodiments 21 to 35, wherein performing the forward error correction on the information block comprises performing Reed-Solomon error correction on the information block.

Claims

1. A decoder configured to perform error correction on an information block comprising user symbols and at least one parity symbol, the decoder comprising: a first error correction circuit configured to output a candidate correction in response to test error correction of an information block using a corresponding candidate correction pattern, wherein the candidate correction pattern for test error correction of the information block comprises a candidate erasure pattern; a selection circuit configured to select a burst candidate correction from the candidate corrections; and A second error correction circuit is configured to perform error correction on the information block in response to the selected burst candidate correction.

2. The decoder of claim 1 , wherein the first error correction circuit is configured to perform test error correction on the information block in response to the candidate correction pattern by: In response to performing a first test error correction on the information block using a first candidate correction pattern among the candidate correction patterns, outputting a first candidate correction; and In response to performing a second test error correction on the information block using a second candidate correction pattern among the candidate correction patterns, a second candidate correction is output.

3. The decoder of claim 1 , wherein the selection circuit is configured to select the burst candidate correction from the candidate corrections by: comparing the error lengths of the candidate corrections; and The candidate correction corresponding to the shortest error length is selected to obtain the burst of candidate corrections.

4. The decoder according to claim 3, wherein: For a given candidate correction, the selection circuit is configured to: identifying, in the information block, a first bit to be corrected and a second bit to be corrected based on the given candidate correction; and A distance in bits between the first bit to be corrected and the second bit to be corrected is determined.

5. The decoder of claim 1 , wherein the first error correction circuit is configured to test error correct the information block in response to the candidate correction pattern by: testing error correcting the information block in response to one or more candidate erasure patterns, wherein the one or more candidate erasure patterns are consecutive.

6. The decoder of claim 5, wherein the second error correction circuit is configured to correct errors of the information block in response to the one or more candidate erasure patterns by: One or more bits or symbols of the information block are erased and decoded using a correction mask corresponding to the selected burst candidate correction, wherein a correction mask in the one or more correction masks has: a length equal to the number of parity symbols associated with the information block, or a length equal to the number of bits of the parity symbols associated with the information block.

7. The decoder of claim 6, wherein the first error correction circuit is configured to test error correct the information block in response to the one or more candidate erasure patterns by computing one or more symbol erasure decodes in response to the one or more candidate erasure patterns.

8. The decoder of claim 3, further comprising a standard error correction circuit configured to output a standard candidate correction in response to performing standard error correction on the information block using a standard error correction protocol.

9. The decoder of claim 8, wherein the selection circuit is configured to select one of the standard candidate correction and the burst candidate correction.

10. The decoder of claim 9, wherein the second error correction circuit is configured to correct errors on the information block in response to the selected candidate correction by: correcting errors on the information block in response to a selected one of the standard candidate correction and the burst candidate correction.

11. The decoder of claim 9, wherein the selection circuit is configured to select one of the standard candidate correction and the burst candidate correction by: selecting the burst candidate correction in response to a result of performing standard error correction on the information block, the result indicating a decoding or error correction failure on the information block; selecting the standard candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that only a single erroneous symbol is corrected or can be corrected; selecting the burst candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that two or more erroneous symbols are corrected or can be corrected, and the score of the burst candidate correction is greater than or equal to the score of the standard decoder; and The standard candidate correction is selected in response to the result of performing the standard error correction on the information block, the result indicating that two or more erroneous symbols are corrected or can be corrected, and the score of the standard candidate correction is greater than the score of the standard decoder.

12. The decoder of claim 11 , wherein the selection circuit is configured to: determining the score of the burst candidate correction responsive to a length of the burst candidate correction; and The score of the standard candidate correction is determined by: determining one or more standard candidate lengths, each of the one or more standard candidate lengths corresponding to a sign correction of the standard candidate correction; identifying scores associated with the one or more standard candidate lengths in response to a lookup table, wherein the lookup table includes score values ​​associated with standard candidate lengths; and The score of the standard candidate correction is determined responsive to the identified score.

13. The decoder of claim 8, wherein the standard error correction circuit is configured to perform standard error correction on the information block by performing forward error correction on the information block.

14. The decoder of claim 13, wherein performing the forward error correction on the information block comprises performing Reed-Solomon error correction.

15. The decoder of claim 1, wherein the information block is a forward error correction coded information block.

16. A burst-tolerant transmission interface, the transmission interface comprising: a transmitter configured to sequentially provide bits of a forward error correction (FEC) coded transport block to a physical transmission line; and A receiver, the receiver being configured to: receiving transmission bits of the forward error correction (FEC) coded transport block from the physical transmission line; detecting bits of the transmission bits exhibiting characteristics indicative of burst errors induced in the forward error correction (FEC) coded transmission block during transmission over the physical transmission line via test correction using a candidate correction pattern, wherein the candidate correction pattern for test correction comprises a candidate erasure pattern; and At least some of the detected bits are changed.

17. The transmission interface of claim 16, wherein the receiver comprises a burst error decoder, wherein the burst error decoder is configured to test a correction pattern for correcting errors in consecutive bits of received transmission bits in the forward error correction (FEC) coded transport block.

18. The transmission interface of claim 17, wherein the receiver comprises a standard error correction circuit configured to perform a standard error correction protocol on received transmission bits in the forward error correction (FEC) encoded transmission block, and wherein the receiver is configured to select one of a result of the standard error correction circuit and a result of the burst error decoder.

19. The transmission interface of claim 16, wherein the bits indicating a burst error each indicate a partial burst error.

20. A method for correcting errors in a forward error correction (FEC) coded information block, the method comprising: generating a candidate correction in response to testing an error correction on an information block using a candidate correction pattern, wherein the candidate correction pattern for testing an error correction on the information block comprises a candidate erasure pattern; selecting a burst candidate correction from the candidate corrections; and The information block is error corrected in response to the selected burst candidate correction.

21. The method according to claim 20, further comprising: generating a first candidate correction in response to performing a first test error correction on the information block using a first candidate correction of the candidate corrections; as well as A second candidate correction is generated in response to performing a second test error correction on the information block using a second candidate correction of the candidate corrections.

22. The method of claim 21, wherein the selecting the candidate correction of the candidate corrections comprises selecting a burst candidate correction in response to the first candidate correction and the second candidate correction.

23. The method of claim 22, wherein the selecting the burst candidate correction in response to the first candidate correction and the second candidate correction comprises selecting one of the first candidate correction and the second candidate correction in response to comparing a first error length corresponding to the first candidate correction and a second error length corresponding to the second candidate correction.

24. The method of claim 23, wherein the selecting the burst candidate correction in response to the first candidate correction and the second candidate correction further comprises: The first error length or the second error length is determined by: identifying in the information block a first bit to be corrected and a second bit to be corrected; as well as A distance in bits between the first bit to be corrected and the second bit to be corrected is determined.

25. The method of claim 24, wherein the selecting one of the first candidate correction and the second candidate correction in response to comparing the first error length corresponding to the first candidate correction and the second error length corresponding to the second candidate correction comprises: selecting the first candidate correction in response to the first error length being shorter than the second error length; as well as The second candidate correction is selected in response to the second error length being shorter than the first error length.

26. The method of claim 20, wherein performing the test error correction on the information block in response to the candidate correction pattern comprises performing the test error correction on the information block in response to a candidate erasure pattern, wherein the candidate erasure pattern is continuous within the information block.

27. The method of claim 26, wherein performing the error correction on the information block in response to the candidate erasure pattern comprises: A correction mask corresponding to the candidate erasure pattern is defined, wherein a correction mask in the correction mask has a length equal to the number of parity symbols associated with the information block or the length of bits of the parity symbols associated with the information block.

28. The method of claim 26, wherein performing the test error correction on the information block in response to the candidate erasure pattern comprises computing a symbol erasure decoding in response to the candidate erasure pattern.

29. The method of claim 22, wherein performing the test error correction on the information block in response to the candidate correction pattern further comprises performing standard error correction on the information block in response to a standard error correction protocol.

30. The method of claim 29, wherein the selecting the candidate correction of the candidate corrections comprises selecting one of a standard candidate correction and the burst candidate correction.

31. The method of claim 30, wherein performing the error correction on the information block in response to the selected candidate correction comprises performing the error correction on the information block in response to a selected one of the standard candidate correction and the burst candidate correction.

32. The method of claim 30, wherein the selecting one of the standard candidate correction and the burst candidate correction comprises: selecting the burst candidate correction in response to a result of performing standard error correction on the information block, the result indicating a decoding or error correction failure on the information block; selecting the standard candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that only a single erroneous symbol is corrected or can be corrected; selecting the burst candidate correction in response to the result of performing the standard error correction on the information block, the result indicating that two or more erroneous symbols are corrected or can be corrected, and the score of the burst candidate correction is greater than or equal to the score of the standard decoder; or The standard candidate correction is selected in response to the result of performing the standard error correction on the information block, the result indicating that two or more erroneous symbols are corrected or can be corrected, and the score of the standard candidate correction is greater than the score of the standard decoder.

33. The method of claim 32, wherein the selecting one of the standard candidate correction and the burst candidate correction further comprises: determining the score of the burst candidate correction responsive to a length of the burst candidate correction; as well as The score of the standard candidate correction is determined by: determining lengths, each of the lengths corresponding to a sign correction of the standard candidate correction; identifying a score associated with the length in response to a lookup table, wherein the lookup table includes score values ​​associated with lengths; and The score of the standard candidate correction is determined responsive to the identified score.

34. The method of claim 29, wherein performing the standard error correction on the information block in response to the standard error correction protocol comprises performing forward error correction on the information block.

35. The method of claim 34, wherein performing the forward error correction on the information block comprises performing Reed-Solomon error correction on the information block.

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