Resistive memory devices and methods of operating resistive memory devices

Abstract

Resistive memory devices and methods of operating resistive memory are provided. The resistive memory devices include an array of memory cells, control logic, a voltage generator, and a sense circuit. The array of memory cells includes memory cells connected to bit lines. Each memory cell includes a variable resistance element for storing data. The control logic receives a read command and generates, based on the read command, voltage control signals for generating a plurality of read voltages. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signals. The sense circuit is connected to the bit lines. The control logic determines a value of data stored in the memory cell by controlling the sense circuit to sequentially compare values of current sequentially output from the memory cell in response to the plurality of read voltages to a reference current.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0146180, filed on November 14, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a memory device, and more specifically, to a resistive memory device. Background Technology

[0003] Resistive memory devices (such as phase-change random access memory (PRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and flash memory) are non-volatile memory devices. Resistive memory devices not only possess the non-volatile characteristics of flash memory but also the high-speed characteristics of volatile memory devices (such as dynamic random access memory (DRAM)).

[0004] A resistive memory device's memory cell can have one of several different resistances (e.g., in a programming state) depending on the value of the programmed data. When reading data stored in the memory cell, the value of the programmed data can be sensed by applying a voltage to the memory cell and comparing the memory cell's output current with several reference currents. Therefore, several reference currents need to be generated. Summary of the Invention

[0005] Embodiments of the inventive concept provide a resistive memory device for determining a programming state by applying multiple read voltages to bit lines and comparing the multiple read voltages with a reference voltage, and a method for operating the resistive memory device.

[0006] According to an exemplary embodiment of the inventive concept, a resistive memory device is provided, the resistive memory device including a memory cell array, control logic, a voltage generator, and a readout circuit. The memory cell array includes a plurality of memory cells connected to multiple bit lines. Each memory cell includes a variable resistive element for storing data. The control logic is configured to receive a read command and generate a voltage control signal based on the read command to generate a plurality of read voltages. The voltage generator is configured to sequentially apply a plurality of read voltages to the multiple bit lines based on the voltage control signal. The readout circuit is connected to the bit lines. The control logic determines the value of data stored in the plurality of memory cells by controlling the readout circuit to sequentially compare the values ​​of currents sequentially output from the plurality of memory cells in response to the plurality of read voltages with a reference current.

[0007] According to an exemplary embodiment of the inventive concept, a method for operating a resistive memory device is provided, the method comprising: applying a first voltage to a plurality of bit lines of the resistive memory device; sensing a first current from a memory cell array of the resistive memory device in response to the first voltage; determining a first memory cell of the memory cell array having a first programming state in response to the first voltage by comparing the first sensed current with a reference current; applying a second voltage to the plurality of bit lines, the second voltage being different from the first voltage; sensing a second current from the memory cell array in response to the second voltage; and determining a second memory cell having a second programming state by comparing the second sensed current with a reference current.

[0008] According to an exemplary embodiment of the inventive concept, a resistive memory device is provided, the resistive memory device comprising: a memory cell array including a plurality of merged memory cells, each of the plurality of merged memory cells including a resistive memory element and a charge trapping layer; control logic for receiving a read command and generating a voltage control signal for generating a plurality of read voltages based on the read command; a voltage generator configured to sequentially apply a plurality of read voltages to a plurality of bit lines connected to the merged memory cells and to apply a gate voltage to the charge trapping layer based on the voltage control signal; and a readout circuit including a first sense amplifier configured to determine a first programming state of the resistive memory element and a second sense amplifier configured to determine a second programming state of the charge trapping layer. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 This is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

[0012] Figure 3 This is a diagram showing a portion of a memory device according to an exemplary embodiment of the inventive concept;

[0013] Figure 4 This is a diagram illustrating a memory cell according to an exemplary embodiment of the inventive concept;

[0014] Figure 5 It is a graph illustrating set write and reset write of a variable resistive element for a memory cell according to an exemplary embodiment of the inventive concept.

[0015] Figure 6 This is a graph showing the distribution of resistance of a memory cell when the memory cell according to an exemplary embodiment of the inventive concept is a single-layer cell;

[0016] Figure 7 This is a graph showing the distribution of resistance of a memory cell when the memory cell according to an exemplary embodiment of the inventive concept is a multi-layer cell;

[0017] Figure 8 This is a circuit diagram illustrating an array of memory cells according to an exemplary embodiment of the inventive concept;

[0018] Figure 9 This is a cross-sectional view showing an array of memory cells according to an exemplary embodiment of the inventive concept;

[0019] Figure 10 This is a circuit diagram illustrating a unit string according to an exemplary embodiment of the inventive concept;

[0020] Figure 11 This is a circuit diagram illustrating an array of memory cells according to an exemplary embodiment of the inventive concept;

[0021] Figure 12 This is a cross-sectional view showing an array of memory cells according to an exemplary embodiment of the inventive concept;

[0022] Figure 13 This is a circuit diagram illustrating a unit string according to an exemplary embodiment of the inventive concept;

[0023] Figure 14 It is a graph showing the gate voltage-drain current of a memory cell according to an exemplary embodiment of the inventive concept;

[0024] Figure 15 This is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept;

[0025] Figure 16 This is a diagram illustrating a method for determining the programming state of a memory cell according to an exemplary embodiment of the inventive concept;

[0026] Figure 17 This is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept;

[0027] Figure 18A and Figure 18B A method for determining the programming state of a memory cell according to an exemplary embodiment of the inventive concept is shown;

[0028] Figure 19A and Figure 19B This is a diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

[0029] Figure 20 This is a flowchart illustrating an operational control logic method according to an exemplary embodiment of the inventive concept;

[0030] Figure 21 This is a diagram illustrating a memory device according to an exemplary embodiment of the inventive concept;

[0031] Figure 22 This is a flowchart illustrating a method for operation control logic according to an exemplary embodiment of the inventive concept; and

[0032] Figure 23 This is a block diagram illustrating an example of a memory device applied to a solid-state drive (SSD) system according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0033] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 This is a block diagram illustrating an exemplary embodiment of a memory system according to the inventive concept.

[0035] Reference Figure 1 The memory system 10 includes a memory device 100 and a memory controller 200 (e.g., control circuitry), and the memory device 100 may be a non-volatile memory device.

[0036] The memory controller 200 may include a processor, which, under the control of the processor, can use hardware-based, software-based, or combined methods to control various memory operations of the memory device 100. In response to write and / or read requests from the host, the memory controller 200 can control the memory device 100 to read data stored in the memory device 100 and / or write data to the memory device 100.

[0037] Specifically, the memory controller 200 can provide the memory device 100 with an address ADDR, a command CMD, and a control signal CTRL to control programming (or writing), reading, and erasing operations on the memory device 100. Furthermore, the memory controller 200 can send and receive data to be written and data to be read between itself and the memory device 100.

[0038] Although not shown, the memory controller 200 may also include random access memory (RAM), a host interface (e.g., interface circuitry), and a memory interface (e.g., interface circuitry). The RAM can be used as the processor's operating memory. The host interface can support communication protocols for exchanging data between the host and the memory controller 200. The memory controller 200 can communicate with the host via at least one of various protocols and can be configured to communicate with the host via at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect High Speed ​​(PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), and Integrated Drive Electronics (IDE)).

[0039] The memory controller 200 and the memory device 100 can be implemented as separate semiconductor devices. Alternatively, the memory controller 200 and the memory device 100 can be integrated into a single semiconductor device. Exemplarily, the memory controller 200 and the memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 200 and the memory device 100 can be integrated into a single semiconductor device to form a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory (CF) card, a smart media card (SM / SMC), a memory stick, a multimedia card (MMC, reduced-size MMC (RS-MMC), and MMCmicro), an SD card (SD, miniSD, and microSD), or a universal flash memory (UFS).

[0040] The memory device 100 includes a memory cell array 110, a read manager 120, and a voltage generator 130. The memory cell array 110 may include a plurality of resistive memory cells, therefore, the memory device 100 may also be referred to as a "resistive memory device".

[0041] Furthermore, the memory device 100 can be implemented in various forms. As an example, the memory device 100 can be a device implemented as a single memory chip. Alternatively, the memory device 100 can be a device comprising multiple memory chips, and as an example, the memory device 100 can be a memory module in which multiple memory chips are mounted on a board. However, embodiments of the inventive concept are not limited thereto, and the memory device 100 can be implemented in various forms, such as a semiconductor package comprising one or more memory dies.

[0042] According to an exemplary embodiment of the inventive concept, the memory cell array 110 includes a plurality of resistive memory cells (not shown) respectively arranged in regions where multiple word lines WL and multiple bit lines BL intersect each other. Therefore, the memory device 100 may be referred to as "cross-point memory". Reference will be made below. Figures 3 to 7 The memory device 100 is described as an embodiment of a crosspoint memory.

[0043] Each of the multiple resistive memory cells can be a single-level cell (SLC) storing one bit, or a multi-level cell (MLC) capable of storing at least two or more bits of data. Furthermore, the memory cells can have multiple resistance distributions depending on the number of bits stored in each memory cell. As an example, when one bit of data is written to a memory cell, the memory cell can have two resistance distributions (e.g., two possible resistance values ​​or states for representing logic 0 and logic 1), and when two bits of data are stored in a memory cell, the memory cell can have four resistance distributions (e.g., four possible resistance values ​​or states for representing logic 00, logic 01, logic 10, and logic 11).

[0044] Furthermore, the memory cell array 110 may include resistive memory cells, each comprising a variable resistive element (not shown). For example, when the variable resistive element comprises a phase-change material and the resistance of the variable resistive element changes with temperature, the resistive memory device may be referred to as a phase-change random access memory (PRAM). In another example, when the variable resistive element is formed of an upper electrode, a lower electrode, and a composite metal oxide between the upper and lower electrodes, the resistive memory device may be referred to as an RRAM. In another example, when the variable resistive element is formed of an upper electrode of magnetic material, a lower electrode of magnetic material, and a dielectric material between the upper and lower electrodes, the resistive memory device may be referred to as an MRAM. However, the above examples are merely exemplary, and the resistive memory device of the present invention is not limited to the above examples.

[0045] According to an exemplary embodiment of the inventive concept, the memory cell array 110 is a resistive switch-based vertically stacked memory cell array in which a plurality of resistive memory cells are vertically stacked, and may be referred to as A-Vertical NAND (A-VNAND). Reference will be made below. Figures 8 to 10 The memory device 100 is described in an embodiment including a vertical memory cell array in which resistive memory cells are stacked.

[0046] According to an exemplary embodiment of the inventive concept, the memory cell array 110 is a vertically stacked memory cell array based on resistive switches, comprising vertically stacked merged memory cells or hybrid memory cells. For example, each merged memory cell stores data in a resistive memory element and a charge trapping layer. The memory cell array 110 including merged memory cells may be referred to as ACE Vertical NAND (ACE-VNAND). In this specification, a merged memory cell means a memory cell that stores data in two ways within a single memory cell by simultaneously including resistive memory elements and a charge trapping layer. Reference will be made below. Figures 11 to 13 The memory device 100 is described in an embodiment including a vertical memory cell array in which combined memory cells are stacked.

[0047] The read manager 120 (e.g., a processor) can perform data read operations by controlling various configuration elements of the memory device 100. For example, the read manager 120 can be based on data read from... Figure 1 The memory controller 200 receives the command CMD, address ADDR, and control signal CTRL and outputs various control signals for reading data from the memory cell array 110.

[0048] Voltage generator 130 can generate various types of voltages for reading data from memory cell array 110 based on the control of read manager 120. In one example, when a selected memory cell is read, voltage generator 130 generates multiple read voltages for reading data and provides the generated multiple read voltages to the bit lines connected to the selected memory cell.

[0049] According to an exemplary embodiment of the inventive concept, the read manager 120 controls the voltage generator 130 to generate a plurality of read voltages and sequentially applies the plurality of read voltages to bit lines to read data from the memory cell array 110. The memory device 100 determines the value of the read data based on the amount of current that varies according to the plurality of read voltages. By sequentially applying the plurality of read voltages, the memory device 100 can determine the value of the read data using a small amount of reference current. Therefore, the complexity of the circuit elements used to generate the reference current can be reduced.

[0050] Figure 2 This is a block diagram illustrating a memory device according to an exemplary embodiment of the inventive concept. For example, Figure 2 The memory device 100 can be used to implement Figure 1 The memory system 10.

[0051] Reference Figure 2The memory device 100 includes a memory cell array 110, a voltage generator 130, a row decoder 140 (e.g., a decoder circuit), a column decoder 150 (e.g., a decoder circuit), a readout circuit 160, and control logic 170 (e.g., logic circuitry, control circuitry, or a processor). The control logic 170 includes a read manager 120 (e.g., a program stored in the memory of the control logic 170 and executed by the control logic 170).

[0052] As shown above (refer to the reference) Figure 1 As described, the memory cell array 110 may include one of a crosspoint memory cell array (or crosspoint cell array), a memory cell array in which resistive memory cells are stacked vertically, and a memory cell array in which merged memory cells are stacked vertically (or merged memory cell array).

[0053] The row decoder 140 can be connected to the memory cell array 110 via multiple word lines WL, and activates a word line selected from the multiple word lines in response to a row address (e.g., X_ADDR) generated as a result of decoding address ADDR. Hereinafter, in this specification, a selected word line refers to the word line among the multiple word lines that connects to a selected memory cell.

[0054] In response to a row address, the row decoder 140 can control the voltage applied to selected word lines among multiple word lines WL or control the connection relationships between selected word lines. The row decoder 140 may include multiple transistors, and at least one transistor may be connected to a corresponding word line among the multiple word lines. Selected word lines can be activated for write and read operations by turning on or off one or more of the multiple transistors.

[0055] Although not shown, the row decoder 140 can be connected to the memory cell array 110 via a serial select line. The serial select line can refer to a signal line used to select a plurality of cell strings included in the memory cell array 110.

[0056] The column decoder 150 can be connected to the memory cell array 110 via multiple bit lines BL, and activates a selected bit line among the multiple bit lines BL in response to a column address (e.g., Y_ADDR) generated as a result of decoding address ADDR. Hereinafter, in this specification, a selected bit line may refer to a bit line among the multiple bit lines BL that is connected to a selected memory cell.

[0057] In response to the column address, the column decoder 150 can control the voltage applied to selected bit lines among multiple bit lines BL, or control the connection relationship between selected bit lines. Furthermore, under the control of control logic 170, the column decoder 150 can adjust the bit line voltage V...BL Apply to the selected bit line.

[0058] Control logic 170 can perform memory operations (such as data writing and data reading) by controlling various configuration elements of memory device 100. For example, control logic 170 can be based on... Figure 1 The memory controller 200 receives the command CMD, address ADDR, and control signal CTRL and outputs various control signals for writing data to or reading data from the memory cell array 110.

[0059] Various control signals output from control logic 170 can be provided to readout circuit 160, voltage generator 130, row decoder 140, and column decoder 150. In an exemplary embodiment, control logic 170 provides an operation selection signal CTRL_op to readout circuit 160 and a voltage control signal CTRL_vol to voltage generator 130. Furthermore, control logic 170 can provide row address X_ADDR to row decoder 140 and column address Y_ADDR to column decoder 150 by decoding address ADDR.

[0060] When multiple read voltages are sequentially applied to selected bit lines, control logic 170, according to an exemplary embodiment of the inventive concept, deactivates the serial select line connected to the selected memory cell. To this end, control logic 170 can output a serial select line deactivation signal Sig_DS to row decoder 140, thus enabling row decoder 140 to deactivate the serial select line. Reference will be made below. Figures 15 to 1 9. This will be described in detail.

[0061] In one example, when a read operation is performed, control logic 170 controls the word line and bit line selection operations of row decoder 140 and column decoder 150 and the sensing operation of readout circuit 160 to read data from selected memory cells, and controls voltage generator 130 such that the voltages supplied to row decoder 140, column decoder 150 and readout circuit 160 have set voltage levels. According to an exemplary embodiment of the inventive concept, control logic 170 controls voltage generator 130 to generate a plurality of read voltages and sequentially apply the plurality of read voltages to selected bit lines to read data from memory cell array 110.

[0062] Voltage generator 130 can generate various types of voltages for performing write, read, and erase operations on memory cell array 110 based on voltage control signal CTRL_vol. Specifically, voltage generator 130 can generate word line voltages V for driving multiple word lines WL. WL and the bit line voltage V used to drive multiple bit lines BL BLFor example, when performing a read operation, voltage generator 130 can generate a first pre-charge voltage, a discharge voltage, and an on / off voltage for the transistors included in line decoder 140 as word line voltage V. WL It also generates multiple read voltages and a second precharge voltage, clamping voltage, on or off voltage for the transistors of the column decoder 150, as well as a bit line voltage V. BL In addition, voltage generator 130 can generate various voltages (e.g., set write voltage, reset write voltage, or reference voltage) to be supplied to read circuit 160.

[0063] The readout circuit 160 can be selectively connected to bit line BL and / or word line WL, and reads data written to selected memory cells. For example, the readout circuit 160 can determine the programming state of the selected memory cell by detecting the current from the bit line connected to the selected memory cell and comparing that current with a reference current. According to an exemplary embodiment of the inventive concept, the readout circuit 160 includes a plurality of latches LAT1 to LAT3 (e.g., latching circuitry) and stores information about the programming state of the selected memory cell in the plurality of latches LAT1 to LAT3. Although in Figure 2 Three latches LAT1 to LAT3 are shown, but this is only an example because more or fewer latches can be included in the readout circuit 160.

[0064] In a read operation of a memory cell array 110 according to an exemplary embodiment of the inventive concept, multiple read voltages are applied to selected bit lines. For example, the voltage between a selected word line and a selected bit line may have a different level difference for each of the multiple read voltages. After a pre-charge operation has been completed for the selected word line and the selected bit line, the level of the current detected from at least one of the selected word line and the selected bit line may vary depending on the programming state of the selected memory cell.

[0065] In one example, when data sensing is performed using current detected from selected bit lines, the level of the current detected from the selected word lines can vary depending on the programming state of the selected memory cell. For example, when the level of the current detected from the selected word lines is greater than a predetermined reference level, the selected memory cell is in a reset state, and thus a "1" data can be sensed; and when the level of the current detected from the selected word lines is less than the predetermined reference level, the selected memory cell is in a set state, and thus a "0" data can be sensed. In another example, the memory device 100 can be implemented to sense data using voltage detected from selected bit lines.

[0066] Figure 3A portion of a memory device 100 according to an exemplary embodiment of the inventive concept is shown. Figure 4 A memory cell of a memory device according to an exemplary embodiment of the inventive concept is shown. Figure 3 and Figure 4 The illustration shows a case where the memory device 100 is a crosspoint memory and the memory cells (e.g., resistive memory cells) are PRAMs. Figure 3 The memory cell array 110a shown can correspond to a cell block.

[0067] Reference Figure 3 The memory device 100 includes a memory cell array 110a, a row decoder 140, and a column decoder 150. The memory cell array 110a is configured to be adjacent to the row decoder 140 in a first direction (e.g., the X direction) and to be adjacent to the column decoder 150 in a second direction (e.g., the Y direction).

[0068] The memory cell array 110a can be a two-dimensional memory cell array with a horizontal structure, and includes multiple word lines WL0 to WLa, multiple bit lines BL0 to BLb, and multiple memory cells MC. The memory cell array 110a can include multiple memory blocks. Each memory block can have multiple memory cells arranged in rows and columns. Here, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC can be varied according to the embodiment.

[0069] According to an exemplary embodiment of the inventive concept, each of the plurality of memory cells MC includes a variable resistive element and a switching element SW. Here, the variable resistive element VR can be referred to as a variable resistive material, and the switching element SW can be referred to as a selection element.

[0070] According to an exemplary embodiment, a variable resistor element VR is connected between one of the multiple bit lines BL0 to BLb and a switching element SW, and the switching element SW is connected between the variable resistor element VR and one of the multiple word lines WL0 to WLa. However, the inventive concept is not limited thereto; the switching element SW may be connected between one of the multiple bit lines BL0 to BLb and the variable resistor element VR, and the variable resistor element VR may be connected between the switching element SW and one of the multiple word lines WL0 to WLa.

[0071] The switching element SW can be connected between any of the multiple word lines WL0 to WLa and the variable resistor element VR, and the current supply to the variable resistor element VR can be controlled according to the voltage applied to the connected word line and the connected bit line. The switching element SW can be implemented using a bidirectional threshold switch (OTS) material. However, the inventive concept is not limited thereto, and in other embodiments, the switching element SW can be changed to another switchable element (such as a unidirectional diode, a bidirectional diode, and a transistor).

[0072] A voltage can be applied to the variable resistive element VR of the memory cell MC via word lines WL0 to WLa and bit lines BL0 to BLb, thus current can be applied to the variable resistive element VR. For example, the variable resistive element VR may include a phase change material layer capable of reversibly transitioning between a first state and a second state. However, the variable resistive element VR is not limited to this and may include any variable resistive component whose resistance value varies according to the applied voltage. For example, the selected memory cell MC can reversibly change the resistance of the variable resistive element VR between a first state and a second state based on the voltage applied to it.

[0073] Based on the change in resistance of the variable resistor element VR, the memory cell MC can store digital information (such as "0" or "1"), and the digital information can also be erased from the memory cell MC. For example, data can be written to the memory cell MC in a high resistance state "0" or a low resistance state "1". Here, writing from a high resistance state "0" to a low resistance state "1" can be referred to as a "set operation", and writing from a low resistance state "1" to a high resistance state "0" can be referred to as a "reset operation". However, the memory cell MC according to embodiments of the inventive concept is not limited to storing the digital information indicating the high resistance state "0" and the low resistance state "1" shown above, and can store digital information indicating various resistance states.

[0074] A specific memory cell MC can be addressed by selecting one of the multiple word lines WL0 to WLa and one of the multiple bit lines BL0 to BLb, and the memory cell MC can be programmed by applying a predetermined signal (e.g., voltage or current) between one of the multiple word lines WL0 to WLa and one of the multiple bit lines BL0 to BLb. According to an exemplary embodiment of the inventive concept, by measuring the current or voltage through a selected word line among the multiple word lines WL0 to WLa or a selected bit line among the multiple bit lines BL0 to BLb, information (i.e., programming data) regarding the resistance value of the variable resistor element VR according to the selected memory cell MC can be read.

[0075] The switching element SW can be implemented using various components such as transistors and diodes. The variable resistor element VR may include a phase change film 11 (or variable resistance layer) formed of a mixture of germanium, antimony and tellurium (GST, Ge-Sb-Te), an upper electrode 12 formed on the phase change film 11, and a lower electrode 13 formed below the phase change film 11.

[0076] The upper electrode 12 and the lower electrode 13 can be formed of various metals, metal oxides, or metal nitrides. The upper electrode 12 and the lower electrode 13 can be made of aluminum (Al), copper (Cu), titanium nitride (TiN), or titanium aluminum nitride (Ti). x Al y N z It can be formed from iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polycrystalline silicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO2), or strontium zirconate oxide (StZrO3), etc.

[0077] The phase change film 11 can be formed from a bipolar resistive memory material or a unipolar resistive memory material. Bipolar resistive memory materials can be programmed to a set or reset state based on the polarity of the current; perovskite-based materials can be used for bipolar resistive memory materials. Furthermore, unipolar resistive memory materials can also be programmed to a set or reset state even when a current of the same polarity is applied; transition metal oxides (such as NiO) can also be used for this purpose. x or TiO x It can be used as a material for unipolar resistive memory.

[0078] GST materials can be programmed between an amorphous state with relatively high resistance and a crystalline state with relatively low resistance. GST materials can be programmed by heating them. The amount and duration of heating determine whether the GST material remains in an amorphous or crystalline state. High and low resistivity can be represented by programmed values ​​of logic 1 or logic 0, respectively, and can be sensed by measuring the resistivity of the GST material. Conversely, high and low resistivity can also be represented by programmed values ​​of logic 1 or logic 0, respectively.

[0079] Figure 5 It is a graph illustrating set write and reset write of a variable resistive element for a memory cell according to an exemplary embodiment of the inventive concept.

[0080] Reference Figure 5 If a variable resistor element is to be constructed ( Figure 4When a phase change material (VR) is heated to a temperature between its crystallization temperature Tx and melting point Tm for a predetermined time, and then gradually cooled, the VR enters a crystalline state. This crystalline state is called the "set state" and is the state that stores data "0". Conversely, if the VR is heated to a temperature higher than its melting point Tm and then rapidly cooled, it enters an amorphous state. This amorphous state is called the "reset state" and is the state that stores data "1". Therefore, data can be stored by supplying current to the variable resistor element VR, and data can be read by measuring the resistance value of the variable resistor element VR.

[0081] Figure 6 This is a graph showing the distribution of resistance in a memory cell when the memory cell according to an exemplary embodiment of the inventive concept is a single-layer cell. Figure 7 This is a graph showing the distribution of resistance of a memory cell when the memory cell according to an exemplary embodiment of the inventive concept is a multi-layer cell.

[0082] Reference Figure 6 The horizontal axis represents resistance, and the vertical axis represents the number of memory cells (MCs). For example, when a memory cell (MC) is a single-level cell (SLC) programmed with 1 bit, the memory cell (MC) can have a low-resistance state (LRS) or a high-resistance state (HRS).

[0083] The low resistance state LRS and the high resistance state HRS can correspond to either data "0" or data "1". According to an embodiment, the resistance level VR increases in the order of data "0" to data "1". That is, the low resistance state LRS can correspond to data "0", and the high resistance state HRS can correspond to data "1".

[0084] The operation of switching a memory cell MC from a high-resistance state (HRS) to a low-resistance state (LRS) by applying a programming current to the memory cell MC is called a set operation or a set-write operation. Conversely, the operation of switching a memory cell MC from a low-resistance state (LRS) to a high-resistance state (HRS) by applying a programming current to the memory cell MC is called a reset operation or a reset-write operation.

[0085] Reference Figure 7The horizontal axis represents resistance, and the vertical axis represents the number of memory cells MC. For example, when the memory cell MC is a multilayer cell (MLC) programmed with two bits, the memory cell MC can have one of the following resistance states: first resistance state RS1, second resistance state RS2, third resistance state RS3, and fourth resistance state RS4. However, the inventive concept is not limited to this. In another embodiment, the multiple memory cells can include three-layer cells (TLC) storing three bits of data, and therefore, the memory cells can have one of eight resistance states. In another embodiment, the multiple memory cells can include memory cells capable of storing four bits or more bits of data respectively.

[0086] Each of the first to fourth resistance states RS1, RS2, RS3, and RS4 can correspond to any of the data "00", "01", "10", and "11". According to an exemplary embodiment, the resistance level VR increases in the order of data "11", "01", "00", and "10". That is, the first resistance state RS1 corresponds to data "11", the second resistance state RS2 corresponds to data "01", the third resistance state RS3 corresponds to data "00", and the fourth resistance state RS4 corresponds to data "10".

[0087] Figure 8 A circuit diagram of a memory cell array 110b according to an exemplary embodiment of the inventive concept is shown. Figure 9 A cross-sectional view of a memory cell array 110b according to an exemplary embodiment of the inventive concept is shown. In detail, Figure 8 and Figure 9 An embodiment of a resistive vertically stacked memory cell array 110b is shown. For example, memory cell array 110b can be used to implement... Figure 2 The memory cell array 110.

[0088] Reference Figure 8 The memory cell array 110b includes a common-source line CSL, multiple bit lines BL1, BL2, and BL3, and multiple cell strings CSTR1 disposed between the common-source line CSL and the multiple bit lines BL1 to BL3. The multiple cell strings CSTR1 include multiple memory cells MC, each of the multiple memory cells MC including a cell transistor CT controlled by a corresponding word line among the multiple word lines WL1 to WL4, and a variable resistor element VR. The variable resistor element VR can be referenced above. Figures 4 to 7 The described method stores the data.

[0089] Reference Figure 9The common-source line (CSL) is disposed in the substrate 1. The substrate 1 can be the semiconductor substrate itself or an epitaxial semiconductor layer formed on the semiconductor substrate. The common-source line (CSL) can be an impurity implantation region formed in the substrate 1. The common-source line (CSL) can be doped with impurities of a different conductivity type than that of the substrate 1. In one example, the substrate 1 is doped with a P-type impurity. The common-source line (CSL) can be doped with, for example, an N-type impurity.

[0090] The active pillar 32 protrudes from the substrate 1 in a first direction L1. The active pillar 32 may have a hollow structure. The active pillar 32 may be in contact with the substrate 1. The active pillar 32 may comprise, for example, polysilicon doped or undoped with P-type impurities. In an exemplary embodiment, the thickness of the active pillar 32 is less than or equal to 50 nm. With such a thin thickness, an electric field can be effectively applied to the variable resistive film 34 when driving a subsequent resistive memory device.

[0091] Drain region D is disposed in active post 32. Drain region D may be doped with impurities of the same type as those in common source line CSL. Bit lines BL1 to BL3 may be disposed on active post 32 and may be electrically connected to drain region D. Bit lines BL1 to BL3 extend in the second direction L2 and are spaced parallel to each other.

[0092] Multiple cell strings CSTR1 are connected in parallel to the corresponding bit lines BL1 to BL3. The cell strings CSTR1 are also connected in parallel to the common-source line CSL. Each cell string CSTR1 is arranged adjacent to one of the active pillars 32. Each cell string CSTR1 may include a lower selection transistor LST connected to the common-source line CSL, an upper selection transistor SST connected to the corresponding bit line BL1 to BL3, and multiple memory cells MC disposed between the lower selection transistor LST and the upper selection transistor SST. The lower selection transistor LST, the upper selection transistor SST, and the memory cells MC may be connected in series. The channel regions of all lower selection transistors LST, upper selection transistor SST, and memory cells MC may be formed in the active pillar 32.

[0093] The upselect transistor SST can utilize upselect lines USL1 to USL3 as gate electrodes and can include a drain region D. The upselect transistor SST can be located at substantially the same distance from the substrate 1. The upselect lines USL1 to USL3 extend along the third direction L3 and are parallel to each other.

[0094] The lower select transistor LST can utilize lower select lines LSL1 to LSL3 as its gate electrode. The lower select transistor LST can be positioned at approximately the same distance from the substrate 1. The upper select lines USL1 to USL3 extend along the third direction L3 and are parallel to each other.

[0095] Each of the multiple memory cells MC includes a cell transistor CT and a variable resistive film 34. The cell transistor CT may utilize a corresponding word line from word lines WL1 to WL4 as its gate electrode, and may include a field-effect source region and a field-effect drain region formed in an active pillar 32 on both sides of the corresponding word line. The gate electrodes of the cell transistors located at the same height from the substrate 1 may be commonly connected to one of the word lines WL1 to WL4.

[0096] The lower selection transistor LST, the upper selection transistor SST, and the unit transistor CT can be metal-oxide-semiconductor field-effect transistors (MOSFETs) that utilize the active pillar 32 as the channel region.

[0097] The variable resistive film 34 can be in direct contact with the active post 32. In one exemplary embodiment, the variable resistive film 34 can be in contact with one side of the active post 32. The interior of the active post 32 can be filled with a buried insulating film 36. The buried insulating film 36 can include, for example, a silicon oxide-based film material. The variable resistive film 34 is located between the buried insulating film 36 and the active post 32. The variable resistive film 34 can have a cup shape covering the inner bottom and sidewalls of the active post 32. The variable resistive film 34 can vary its resistance value according to given conditions and is used as a variable resistive element VR. In one exemplary embodiment, the resistance of the variable resistive film 34 can be changed based on at least one of oxidation reaction, reduction reaction, and temperature.

[0098] Figure 10 This is a circuit diagram illustrating a unit string CSTR1 according to an exemplary embodiment of the inventive concept. In detail, Figure 10 It shows that it includes Figure 8 A cell string CSTR1 is shown in the memory cell array 110b.

[0099] Reference Figure 10 The cell string CSTR1 may include multiple memory cells. During a read process (e.g., during a read operation), when a first memory cell MC1 included in the cell string CSTR1 is selected, a read voltage Vread is applied to bit line BL. Furthermore, a selection voltage Vsel is applied to the cell transistor CT of the first memory cell MC1, and a non-selection voltage Vunsel is applied to the cell transistors of the other memory cells. The selection voltage Vsel can be a voltage used to turn off the cell transistor CT, and the non-selection voltage Vunsel can be a voltage used to turn on the cell transistor CT. In one example, the selection voltage Vsel has a voltage level lower than the threshold voltage of the cell transistor CT, and the non-selection voltage Vunsel has a voltage level higher than the threshold voltage of the cell transistor CT.

[0100] Based on the applied voltage, all cell transistors except for the cell transistor CT of the selected first memory cell MC1 are turned on, while the cell transistor of the first memory cell MC1 is turned off. Therefore, the current according to the read voltage Vread flows through the variable resistor element VR of the first memory cell MC1, and different current values ​​can be measured according to the variable resistor element VR.

[0101] According to an exemplary embodiment of the inventive concept, the memory device sequentially changes the voltage level of the read voltage Vread, thus allowing the current value of the variable resistor element VR to be measured, and the resistance value of the variable resistor element VR to be measured via the current value. Furthermore, the memory device can determine the programming state by measuring the resistance value of the variable resistor element VR.

[0102] Figure 11 A circuit diagram of a memory cell array 110c according to an exemplary embodiment of the inventive concept is shown. Figure 12 A cross-sectional view of a memory cell array 110c according to an exemplary embodiment of the inventive concept is shown. In detail, Figure 11 and Figure 12 The memory cell array 110c is shown as an embodiment of a vertically stacked memory cell array. For example, Figure 2 The memory cell array 110 can utilize Figure 11 The memory cell array 110c is used instead. This has already been referred to above. Figure 8 and Figure 9 The given description has been omitted.

[0103] Reference Figure 11 The memory cell array 110c includes a common-source line CSL, multiple bit lines BL1 to BL3, and multiple cell strings CSTR2 disposed between the common-source line CSL and the bit lines BL1 to BL3. The multiple cell strings CSTR2 include multiple memory cells MC, each of the multiple memory cells MC including a charge trapping layer CTF and a variable resistor element VR (or resistive memory element VR) controlled by a corresponding word line among the multiple word lines WL1 to WL4.

[0104] According to an embodiment of the inventive concept, the memory cell MC can store first data using a charge trapping layer CTF and store second data using a variable resistive element VR. The memory device can be configured to store data by cutting off the charge trapping layer CTF of the memory cell MC, as described above. Figures 8 to 10 The described method determines the data stored in the variable resistance element VR, and the data stored in the charge trapping layer CTF can be determined by controlling the gate voltage of the memory cell MC.

[0105] Reference Figure 12The charge storage membrane 40 is included to replace Figure 9 The active pillars 32 of the memory cell array 110b. The charge storage film 40 can be used as a charge trapping layer (CTF) for storing data, and when data is stored by trapping charge in the charge storage film 40, the charge storage film 40 can include silicon nitride or a metal oxide. The metal oxide can include, for example, aluminum oxide. As another example, when data is stored by floating charge in the charge storage film 40, the charge storage film 40 can include silicon. The charge storage film 40 can include, for example, doped silicon or undoped silicon. Although not shown, a barrier film and a tunnel insulating film can be further included around the charge storage film 40.

[0106] Figure 13 This is a circuit diagram illustrating a unit string CSTR2 according to an exemplary embodiment of the inventive concept. In detail, Figure 13 It shows that it includes Figure 11 A cell string CSTR2 is shown in the memory cell array 110c.

[0107] Reference Figure 13 The cell string CSTR2 can include multiple memory cells. During the read process, when the second memory cell MC2 included in the cell string CSTR2 is selected, the read voltage Vread is applied to the bit line BL. Additionally, the gate voltage Vg is applied to the charge trapping layer CTF of the second memory cell MC2, and the non-selection voltage Vunsel is applied to the cell transistors of the other memory cells.

[0108] With the applied voltage, all charge trapping layers except the CTF layer of the selected second memory cell MC2 are turned on, and thus, current flows through the second memory cell MC2 according to the read voltage Vread. Depending on the gate voltage Vg, the current can flow along the first path a, or the current can flow along the second path b.

[0109] In one example, when the gate voltage Vg is lower than the minimum turn-on voltage of the charge trapping layer CTF of the second memory cell MC2, the current according to the read voltage Vread flows along the first path a through the resistive memory element VR without flowing through the charge trapping layer CTF, and the data programmed in the resistive memory element VR can be determined. In another example, when the gate voltage Vg is greater than or equal to the minimum turn-on voltage of the charge trapping layer CTF of the second memory cell MC2, the current according to the read voltage Vread flows along the second path b to the charge trapping layer CTF without flowing to the resistive memory element VR, and the data programmed in the charge trapping layer CTF can be determined.

[0110] Figure 14This is a graph showing the gate voltage versus drain current of a memory cell according to an exemplary embodiment of the inventive concept. In detail, Figure 14 The above reference is shown. Figures 11 to 13 The gate voltage-drain current of the merged memory cell is described.

[0111] Reference Figure 13 and Figure 14 When the gate voltage Vg of the memory cell is lower than the minimum turn-on voltage of the charge trapping layer CTF, the charge trapping layer CTF is turned off. Therefore, the resistance levels of the resistive memory element VR can be distinguished. The resistance levels of the resistive memory element VR in the memory cell can be divided into multiple levels.

[0112] The resistance level of a resistive memory element VR can be determined by its drain current Id. For example, the drain current Id can have the following characteristics: Figure 14 Any of the five states shown. Therefore, the resistance level of the resistive memory element VR can be divided into five levels. According to an exemplary embodiment of the inventive concept, the resistance level of the resistive memory element VR is distinguished by applying multiple read voltages with different voltage levels.

[0113] When the gate voltage Vg is higher than the minimum turn-on voltage of the charge trapping layer CTF, the memory cell can be turned off or on according to the charge storage state of the charge trapping layer CTF. In other words, the threshold voltage of the charge trapping layer CTF in the memory cell can be divided into multiple levels.

[0114] The threshold voltage of the charge trapping layer CTF can be distinguished by the voltage with a specific drain current value, i.e., as shown below. Figure 14 As shown, the threshold voltage level can be any of the four levels. Therefore, the threshold voltage of the second data storage structure (i.e., the charge trapping layer CTF) can be divided into four levels.

[0115] Thus, a memory cell according to an exemplary embodiment of the inventive concept includes two data memory elements that store data using different mechanisms within a single memory cell.

[0116] Figure 15 This is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept.

[0117] Reference Figure 2 and Figure 15 The memory device 100 senses a first programming state by applying a first voltage to the bit line BL (S110). In one example, the first programming state corresponds to the resistance value of the resistive memory element of the sensed memory cell selected by the selected word line.

[0118] The memory device 100 disables the string select line corresponding to the sensed memory cell (S120). In one example, when the first memory cell is sensed to be in a first programming state, the string select transistor is turned off by disabling the string select line connected to the first memory cell, and no voltage is applied to the cell string including the first memory cell.

[0119] In embodiments where the memory cell array is a vertically stacked memory cell array, the serial select line can be as referenced above. Figures 8 to 13 The upper select line (USL) or lower select line (LSL) is described. In embodiments where the memory cell array is a cross-point memory cell array, the serial select line may refer to a signal line used to disable the row containing the selected memory cell.

[0120] The memory device 100 senses a second programming state by applying a second voltage to the bit line BL (S130). According to an exemplary embodiment of the inventive concept, the memory device 100 applies multiple read voltages to the bit line to sense multiple programming states and disables the string select line corresponding to a memory cell whose programming state has been determined, thus preventing repeated determination of the programming state. For example, the bit line may be connected to a cell string including a first memory cell connected to a first word line and a second memory cell connected to a second word line, wherein: during step S110, the first memory cell is sensed to be in a first programming state because a first voltage is applied to the bit line; during step S120, the string select line of the first memory cell is disabled because the first memory cell has the first programming state, while the string select line of the second memory cell remains enabled; then, during step S130, the second memory cell is sensed to be in a second programming state because a second voltage is applied to the same bit line.

[0121] Figure 16 This is a diagram illustrating a method for determining the programming state of a memory cell according to an exemplary embodiment of the inventive concept.

[0122] Reference Figure 2 and Figure 16 The memory cells included in the memory cell array 110 may have resistance values ​​corresponding to any of the erase state E and the first programming states P1 to the seventh programming states P7. In one example, multiple memory cells may be programmed such that the resistance value corresponding to the erase state E is minimized and the resistance value corresponding to the seventh programming state P7 is maximized.

[0123] First, the read manager 120 controls the voltage generator 130 to apply a first voltage V1 to the bit line BL. Therefore, an output current can be generated from each of the cell strings included in the memory cell array 110, and the output current corresponding to each of the plurality of memory cells can have a value inversely proportional to the resistance value programmed according to Ohm's law.

[0124] Because the first voltage V1 is applied to bit line BL, the output current corresponding to any of the erase state E and the first programming states P1 to the seventh programming states P7 can be generated from the memory cell, and the output current corresponding to the erase state E with the lowest resistance value has a higher resistance than the reference current I. th The larger the value.

[0125] The read manager 120 compares the output current from multiple memory cells with a reference current I. th A comparison is made to determine the value of the reference current I. th The memory cell with the largest output current is selected, and that memory cell is designated as being in an erase state E. Here, the read manager 120 controls the read circuit 160 to compare the output current from multiple memory cells with the reference current I. th A comparison is made to determine the value of the reference current I. th The memory cell has a large output current. The read manager 120 outputs a string select line deactivation signal Sig_DS to deactivate the string select line corresponding to the memory cell determined to be in erase state E. Therefore, the cell string including the memory cell determined to be in erase state E is deactivated.

[0126] Next, the read manager 120 controls the voltage generator 130 to apply a second voltage V2 to the bit line BL, having a voltage level higher than the first voltage V1. Because the cell string including the memory cell corresponding to the erase state E is deactivated, an output current corresponding to any of the first programming states P1 to the seventh programming states P7 can be generated from the memory cell. Only the output current corresponding to the first programming state P1, which has the lowest resistance value among the first programming states P1 to the seventh programming states P7, can have a higher voltage level than the reference current I. th The larger the value.

[0127] The read manager 120 compares the output current from multiple memory cells with a reference current I. th A comparison is made to determine the value of the reference current I. thThe memory cell with a large output current is identified and is determined to be in a first programming state P1. The read manager 120 outputs a string select line deactivation signal Sig_DS to deactivate the string select line corresponding to the memory cell identified to be in the first programming state P1, thus deactivating the string of cells including the memory cell identified to be in the first programming state P1.

[0128] Next, the read manager 120 controls the voltage generator 130 to apply a third voltage V3 to the bit line BL, which has a higher voltage level than the second voltage V2. Because the cell string including the memory cells corresponding to the erase state E and the cell string including the memory cells corresponding to the first programming state P1 are deactivated, an output current corresponding to any of the second programming states P2 to the seventh programming states P7 can be generated from the memory cells. Only the output current corresponding to the second programming state P2, which has the lowest resistance value among the second programming states P2 to the seventh programming states P7, can have a higher voltage level than the reference current I. th The larger the value.

[0129] The read manager 120 compares the output current from multiple memory cells with a reference current I. th A comparison is made to determine the value of the reference current I. th The memory cell with a large output current is identified and is determined to be in the second programming state P2. The read manager 120 outputs a string select line deactivation signal Sig_DS to deactivate the string select line corresponding to the memory cell identified to be in the second programming state P2. Therefore, the string of cells including the memory cell identified to be in the second programming state P2 is deactivated.

[0130] The memory device 100 can determine the third programming state P3 to the seventh programming state P7 in a manner similar to that described above, and the determined programming state can be output as data DATA to an external device (e.g., Figure 1 (Memory controller 200).

[0131] According to an exemplary embodiment of the inventive concept, the memory device 100 sequentially applies a plurality of read voltages V1 to V4 to the bit line BL, and compares the output current with the reference current I. th The programming state of a memory cell is determined by comparison, and multiple programming states can be determined using only a single reference current I. th To determine.

[0132] exist Figure 16The invention illustrates an embodiment in which eight programming states (erasure states E to the seventh programming state P7) are determined, but the inventive concept can also be applied to situations where more or fewer than eight programming states are determined.

[0133] Figure 17 This is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the inventive concept.

[0134] Reference Figure 2 and Figure 17 The memory device 100 determines the first bit by applying a first determining voltage to the bit line BL to determine the first bit, and stores the first bit in the first latch LAT1 (S210). In one example, the memory device 100 compares the output current generated from the memory cell with a reference current by applying the first determining voltage to the bit line BL to generate a comparison result, and stores "0" or "1" in the first latch LAT1 based on the comparison result.

[0135] Memory device 100 disables the serial select line corresponding to the memory cell having a first value as the first bit (S220). In one example, memory device 100 disables the serial select line corresponding to the memory cell having "0" as the first bit, so the voltage applied to bit line BL is not applied to the memory cell having "0" as the first bit.

[0136] The memory device 100 determines the second bit of the memory cell having a second value as the first bit by applying a second determining voltage to the bit line BL for determining the second bit, and stores the second bit in the second latch LAT2 (S230). In one example, the memory device 100 compares the output current generated from the memory cell having the second value as the first bit with a reference current by applying the second determining voltage to the bit line BL to generate a comparison result, and stores "0" or "1" in the second latch LAT2 based on the comparison result.

[0137] Memory device 100 disables the serial select line corresponding to the memory cell having a second value as the first bit (S240). In one example, memory device 100 disables the serial select line corresponding to the memory cell having "1" as the first bit, therefore, the voltage applied to bit line BL is not applied to the memory cell having "1" as the first bit.

[0138] The memory device 100 determines the second bit of the memory cell having a first value as the first bit by applying a third determining voltage to the bit line BL to determine the second bit, and stores the second bit in the second latch LAT2 (S250). In one example, the memory device 100 compares the output current generated from the memory cell having the first value as the first bit with a reference current by applying the third determining voltage to the bit line BL to generate a comparison result, and stores "0" or "1" in the second latch LAT2 based on the comparison result.

[0139] The memory device 100 according to an exemplary embodiment of the inventive concept applies a plurality of defined voltages to bit lines and disables memory cells for which the corresponding bits have been defined, thereby allowing effective programming state determination.

[0140] Figure 18A and Figure 18B A method for determining the programming state of a memory cell according to an exemplary embodiment of the inventive concept is shown.

[0141] Reference Figure 2 and Figure 18A The memory cells included in the memory cell array 110 may have a resistance value corresponding to one of the erase state E and the first programming states P1 to the seventh programming states P7. In one example, multiple memory cells may be programmed such that the resistance value corresponding to the erase state E is minimized and the resistance value corresponding to the seventh programming state P7 is maximized.

[0142] First, the read manager 120 controls the voltage generator 130 to apply a first predetermined voltage Vd1 to the bit line BL. In one embodiment, the first predetermined voltage Vd1 has a predetermined voltage level that is distinguished from the resistance values ​​corresponding to the erase state E to the third programming state P3 and the resistance values ​​corresponding to the fourth programming state P4 to the seventh programming state P7.

[0143] Because a first determining voltage Vd1 is applied to bit line BL, an output current corresponding to any of the erase state E and the first programming state P1 to the seventh programming state P7 can be generated from the memory cell, and the read manager 120 determines the first bit by comparing the output current with a reference current. In response to the first determining voltage Vd1, memory cells having any of the erase states E to the third programming state P3 generate an output current with a value greater than the reference current, and memory cells having any of the fourth programming states P4 to the seventh programming state P7 generate an output current with a value less than the reference current.

[0144] The read manager 120 can control the read circuit 160 based on the comparison result, thereby writing "1" as the first bit to the first latch LAT1 corresponding to any memory cell having any of the erase states E to the third programming states P3, and writing "0" as the first bit to the first latch LAT1 corresponding to any memory cell having any of the fourth programming states P4 to the seventh programming states P7.

[0145] The read manager 120 controls the line decoder 140 to disable the serial select line corresponding to the memory cell with "0" as the first bit (i.e., the memory cell with any of the fourth programming state P4 to the seventh programming state P7).

[0146] The read manager 120 applies a second determined voltage Vd2 to the bit line BL. In an exemplary embodiment, the second determined voltage Vd2 has a predetermined voltage level that distinguishes the resistance value corresponding to the erase state E and the first programming state P1 from the resistance value corresponding to the second programming state P2 and the third programming state P3. Because the serial select line corresponding to any of the memory cells having any of the fourth programming states P4 to the seventh programming states P7 is disabled, the second determined voltage Vd2 is applied to the memory cells having "1" as the first bit (i.e., the memory cells having any of the erase states E to the third programming states P3).

[0147] Therefore, an output current corresponding to any of the erase states E to the third programming state P3 can be generated from the memory cell, and the read manager 120 compares the output current with a reference current to determine the second bit. In response to the second determination voltage Vd2, a memory cell having any of the erase states E and the first programming state P1 generates an output current with a value greater than the reference current, and a memory cell having any of the second programming states P2 and the third programming state P3 generates an output current with a value less than the reference current.

[0148] The read manager 120 can control the read circuit 160 based on the comparison result, thereby writing "1" to the second latch LAT2 corresponding to the memory cell having either the erase state E or the first programming state P1 as the second bit, and writing "0" to the second latch LAT2 corresponding to the memory cell having either the second programming state P2 or the third programming state P3 as the second bit.

[0149] The read manager 120 controls the line decoder 140 to disable the serial select line corresponding to the memory cell with "1" as the first bit (i.e., the memory cell with any of the erase state E to the third programming state P3).

[0150] The read manager 120 applies a third determined voltage Vd3 to the bit line BL. According to an exemplary embodiment, the third determined voltage Vd3 has a predetermined voltage level that distinguishes the resistance values ​​corresponding to the fourth programming state P4 and the fifth programming state P5 from the resistance values ​​corresponding to the sixth programming state P6 and the seventh programming state P7. Because the serial select line corresponding to any of the memory cells having an erase state E to the third programming state P3 is disabled, the third determined voltage Vd3 can be applied to memory cells having "0" as the first bit (i.e., memory cells having any of the fourth programming states P4 to the seventh programming state P7).

[0151] Therefore, an output current corresponding to any of the fourth programming states P4 to the seventh programming states P7 can be generated from the memory cell, and the read manager 120 can compare the output current with a reference current to determine the second bit. In response to the third determination voltage Vd3, a memory cell having any of the fourth programming states P4 and the fifth programming states P5 generates an output current with a value greater than the reference current, and a memory cell having any of the sixth programming states P6 and the seventh programming states P7 generates an output current with a value less than the reference current.

[0152] The read manager 120 can control the read circuit 160 based on the comparison result, thereby writing "0" to the second latch LAT2 corresponding to any memory cell having a fourth programming state P4 and a fifth programming state P5 as the second bit, and writing "1" to the second latch LAT2 corresponding to any memory cell having a sixth programming state P6 and a seventh programming state P7 as the second bit.

[0153] Reference Figure 2 and Figure 18B The read manager 120 controls the line decoder 140 to disable the serial select line corresponding to any of the memory cells having any of the second programming states P2 to the seventh programming states P7.

[0154] The read manager 120 applies a fourth determination voltage Vd4 to the bit line BL. In an exemplary embodiment, the fourth determination voltage Vd4 has a predetermined voltage level that distinguishes it from the resistance value corresponding to the erase state E and the resistance value corresponding to the first programming state P1. Because the serial select line corresponding to any of the memory cells having any of the second programming states P2 to the seventh programming states P7 is disabled, the fourth determination voltage Vd4 can be applied to memory cells having any of the erase state E and the first programming state P1.

[0155] Therefore, an output current corresponding to either the erase state E or the first programming state P1 can be generated from the memory cell, and the read manager 120 can compare the output current with a reference current to generate a third bit. In response to a fourth determining voltage Vd4, the memory cell in the erase state E generates an output current with a value greater than the reference current, and the memory cell in the first programming state P1 generates an output current with a value less than the reference current.

[0156] The read manager 120 can control the read circuit 160 based on the comparison result, thereby writing "1" to the third latch LAT3 corresponding to the memory cell with the erase state E as the third bit, and writing "0" to the third latch LAT3 corresponding to the memory cell with the first programming state P1 as the third bit.

[0157] The read manager 120 applies multiple defined voltages Vd5 to Vd7 to determine the third bit corresponding to the second programming states P2 to the seventh programming states P7 in a manner similar to the method used to determine the third bit for the erase state E and the first programming state P1, and stores the third bit in the third latch LAT3. The read manager 120 can output data DATA based on the multiple defined bits.

[0158] The memory device 100 according to an exemplary embodiment of the inventive concept efficiently reads data by using a plurality of deterministic voltages to determine a plurality of bits and by using the plurality of bits to distinguish programming states.

[0159] although Figure 18A and Figure 18B An embodiment using eight programming states (erasure state E to seventh programming state P7) is shown, but the inventive concept is not limited thereto and can be applied to situations where more or fewer than eight programming states are determined.

[0160] Figure 19A and Figure 19B This is a diagram illustrating a memory device according to an exemplary embodiment of the inventive concept. Specifically, Figure 19A and Figure 19B An embodiment of a memory device including a combined memory cell array is shown.

[0161] Reference Figure 19A The memory device 100c includes a memory cell array 110c, a first sensing amplifier 161, a second sensing amplifier 162, and control logic 170.

[0162] The memory cell array 110c may include the above reference Figures 11 to 14The description describes multiple merged memory cells. As mentioned above, the multiple merged memory cells can store first data using a variable resistive element VR, and store second data using a charge trapping layer CTF.

[0163] A first sensing amplifier 161 senses and amplifies first data stored in a variable resistive element VR, and outputs the amplified data. The first sensing amplifier 161 is connected to a terminal of the bit line BL via a first sensing switch SS1, which can be turned on or off by control logic 170. For example, when the first sensing switch SS1 is a transistor, the gate terminal of the transistor can receive a control signal from the control logic 170 to turn the first sensing switch SS1 on or off. According to an exemplary embodiment, the control logic 170 connects the first sensing amplifier 161 to the bit line BL by turning on the first sensing switch SS1, and the first sensing amplifier 161 senses the first data from the memory cell array 110c via the bit line BL.

[0164] The second sensing amplifier 162 senses and amplifies the second data stored in the charge trapping layer CTF, and outputs the amplified data. The second sensing amplifier 162 is connected to another terminal of the bit line BL via a second sensing switch SS2, which can be turned on or off by control logic 170. According to an exemplary embodiment, control logic 170 connects the second sensing amplifier 162 to the bit line BL by turning on the second sensing switch SS2, and the second sensing amplifier 162 senses the second data from the memory cell array 110c via the bit line BL.

[0165] The first sensing switch SS1 and the second sensing switch SS2 may include switching elements capable of electrically connecting or disconnecting the bit line BL from the sensing amplifiers 161 and 162. In one example, both the first sensing switch SS1 and the second sensing switch SS2 may include an N-type metal-oxide-semiconductor (NMOS) transistor or a P-type metal-oxide-semiconductor (PMOS) transistor.

[0166] Reference Figure 19B The memory device 100d includes a memory cell array 110c, a first sensing amplifier 161, a second sensing amplifier 162, and control logic 170. Figure 19A Unlike the memory device 100c shown, the memory device 100d includes a first sensing amplifier 161 and a second sensing amplifier 162 that are simultaneously connected to one terminal of the bit line BL. The configuration of the memory device 100d, other than the configuration described above, can be the same as... Figure 19A The configuration of the memory device 100c is the same or similar.

[0167] By extracting data from the memory cell array 110c via different sensing amplifiers, memory devices 100c and 100d, according to exemplary embodiments of the inventive concept, can efficiently manage large amounts of data with limited resources.

[0168] Figure 20 This is a flowchart illustrating a method for operation control logic according to an exemplary embodiment of the inventive concept. In detail, Figure 20 A method for retrieving data from a combined memory cell array is shown.

[0169] Reference Figure 19A , Figure 19B and Figure 20 Control logic 170 turns on the first sensing switch SS1 and turns off the second sensing switch SS2 (S410). According to an embodiment, control logic 170 is connected to the gate terminals of the first sensing switch SS1 and the second sensing switch SS2, applies an on-state voltage to the first sensing switch SS1, and applies an off-state voltage to the second sensing switch SS2.

[0170] Control Logic 170 Control Figure 2 The voltage generator 130 causes a change in the bit line voltage and controls the first sensing amplifier 161 to sense first data from the resistive memory element VR, amplify the first data, and output the amplified first data (S420). According to an exemplary embodiment, the control logic 170 uses the above reference... Figures 1 to 1 The method described in 8 senses first data from a resistive memory element VR.

[0171] After the first data has been sensed, control logic 170 turns off the first sensing switch SS1 and turns on the second sensing switch SS2 (S430). According to an exemplary embodiment, a cutoff voltage is applied to the first sensing switch SS1 and a turn-on voltage is applied to the second sensing switch SS2.

[0172] Control Logic 170 Control Figure 2 The voltage generator 130 changes the gate voltage of the memory cells included in the memory cell array 110c via the word line WL, and controls the second sensing amplifier 162 to sense the second data from the charge trapping layer CTF, amplify the second data, and output the amplified second data (S440).

[0173] Figure 21 This is a diagram illustrating a memory device according to an exemplary embodiment of the inventive concept. In detail, Figure 21 An embodiment of a memory device including a combined memory cell array is shown. (Referring above...) Figure 19A and Figure 19B The given description has been omitted.

[0174] Reference Figure 21 The memory device 100e includes a memory cell array 110c, a common sense amplifier 163, and control logic 170.

[0175] Based on the control of control logic 170, common sensing amplifier 163 senses and amplifies the first data stored in the variable resistive element VR or the second data stored in the charge trapping layer CTF, and outputs the amplified data.

[0176] Control logic 170 can control common sensing amplifier 163 to sense first data from resistive memory cell VR at a first time point, and control common sensing amplifier 163 to sense second data from charge trapping layer CTF at a second time point.

[0177] By extracting first and second data from the memory cell array 110c at different points in time using a common sensing amplifier 163, the memory device 100e according to an exemplary embodiment of the inventive concept can efficiently manage a large amount of data with limited resources.

[0178] Figure 22 This is a flowchart illustrating a method for operation control logic according to an exemplary embodiment of the inventive concept. In detail, Figure 22 A method for retrieving data from a combined memory cell array is shown.

[0179] Reference Figure 21 and Figure 22 Control logic 170 controls at the first time point. Figure 2 The voltage generator 130 causes a change in the bit line voltage and controls the common sense amplifier 163 to sense first data from the resistive memory element VR, amplify the first data, and output the amplified first data (S510). According to an exemplary embodiment, the control logic 170 uses the above reference... Figures 1 to 1 The method described in 8 senses first data from a resistive memory element VR.

[0180] After the first data sensing is completed, control logic 170 controls at the second time point. Figure 2 The voltage generator 130 changes the gate voltage of the memory cells included in the memory cell array 110c via the word line WL, and controls the common sense amplifier 162 to sense the second data from the charge trapping layer CTF, amplify the second data, and output the amplified second data (S520).

[0181] Figure 23 This is a block diagram illustrating an example of a memory device applied to an SSD system according to an exemplary embodiment of the inventive concept.

[0182] Reference Figure 23The SSD system 1000 includes a host 1100 and an SSD 1200. The SSD 1200 exchanges signals SGL with the host 1100 via a signal connector and receives power PWR via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and a plurality of non-volatile memory devices 1230, 1240, and 1250. At least one of the plurality of non-volatile memory devices 1230, 1240, and 1250 may be a resistive memory device, and the memory devices according to the above embodiments of the inventive concept can be applied to one or more of the plurality of non-volatile memory devices 1230, 1240, and 1250.

[0183] SSD controller 1210 can be connected to multiple memory devices 1230, 1240 and 1250 through multiple channels Ch1 to Chn (n is an integer greater than 1), and can store data in or read data from the multiple memory devices 1230, 1240 and 1250.

[0184] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A resistive memory device, comprising: A memory cell array includes multiple memory cells connected to multiple bit lines, wherein each memory cell includes a variable resistive element for storing data; The control logic is configured to receive a read command and generate a voltage control signal based on the read command to generate multiple read voltages; A voltage generator is configured to sequentially apply the plurality of read voltages to each of the plurality of bit lines based on a voltage control signal; and The readout circuit is connected to the multiple bit lines. Specifically, the control logic determines the value of the data stored in the plurality of memory cells by controlling the readout circuit to sequentially compare the values ​​of the currents sequentially output from the plurality of memory cells in response to the plurality of read voltages with the value of a reference current.

2. The resistive memory device according to claim 1, wherein, The memory cell array includes: The active column has a hollow structure; A variable resistive film is configured to contact one side of an active pillar, wherein the resistance of the variable resistive film is configured to change based on at least one of an oxidation reaction, a reduction reaction, and temperature; and A three-dimensional cell array structure, including a gate disposed adjacent to the other side of the active pillar.

3. The resistive memory device according to claim 1 or claim 2, wherein, Each of the plurality of memory cells has any one of the first to Nth resistance values ​​corresponding to different programming states, and Specifically, the control logic generates voltage control signals to determine the first resistance value to the Nth resistance value. Where N is a natural number greater than or equal to 2.

4. The resistive memory device according to claim 3, wherein, The control logic controls the voltage generator to sequentially apply a rising first voltage to the (N-1)th voltage to each of the plurality of bit lines, and In the control based on control logic, the readout circuit determines the programming state of the plurality of memory cells based on the values ​​of the currents output from the plurality of memory cells according to the first voltage to the (N-1)th voltage.

5. The resistive memory device according to claim 4, wherein, The readout circuit determines the programming state of the plurality of memory cells by sequentially comparing the values ​​of the currents output from the plurality of memory cells according to the first voltage to the (N-1)th voltage with the value of the reference current.

6. The resistive memory device according to claim 4, wherein, The control logic will deactivate the serial select line corresponding to the memory cell whose programming state has been determined.

7. The resistive memory device according to claim 4, wherein, The control logic controls the voltage generator to apply the Mth voltage to the multiple bit lines to determine the value of the Mth resistor. The memory cell with the Mth resistance value is determined by comparing the value of a reference current with the value of the current output from the plurality of memory cells through a control readout circuit. Disable the serial select line corresponding to the memory cell with the Mth resistance value. Where M is a natural number greater than 0 and less than N.

8. The resistive memory device according to claim 7, wherein, The memory cell array includes a crosspoint cell array, which comprises multiple resistive memory cells arranged at the locations where the multiple bit lines and multiple word lines of the resistive memory device intersect each other.

9. The resistive memory device according to claim 3, wherein, The programming state of the plurality of memory cells includes multiple bits, and The control logic controls the voltage generator to apply a first determination voltage to the multiple bit lines to determine the first bit of the multiple memory cells.

10. The resistive memory device according to claim 9, wherein, The control logic will activate the serial select lines corresponding to the multiple first memory cells that have a first value as the first bit, and The control voltage generator applies a second determining voltage to the multiple bit lines to determine the second bit of a plurality of second memory cells having a second value as the first bit.

11. The resistive memory device according to claim 10, wherein, The control logic determines the second bit of the plurality of second memory cells, then deactivates the serial select line corresponding to the plurality of second memory cells, and The control voltage generator applies a third determining voltage to the plurality of bit lines to determine the second bit of the plurality of first memory cells.

12. The resistive memory device according to claim 9, wherein, The readout circuit includes a first latch for storing the first bit and a second latch for storing the second bit, and Specifically, after determining the first bit, the control logic stores the first bit in the first latch. The serial select lines corresponding to the plurality of first memory cells having a first value as the first bit are activated, and The control voltage generator applies a second determining voltage to the multiple bit lines to determine the second bit of a plurality of second memory cells having a second value as the first bit.

13. The resistive memory device according to claim 12, wherein, After determining the second bit of the plurality of second memory cells, the control logic stores the second bit in the second latch, and after determining the second bit of the plurality of second memory cells, turns off the string selection transistor corresponding to the plurality of second memory cells. The control voltage generator applies a third determining voltage to the plurality of bit lines to determine the second bit of the plurality of first memory cells.

14. The resistive memory device according to claim 1 or claim 2, wherein, The plurality of memory cells include a plurality of merged memory cells, each of which includes resistive memory elements and a charge trapping layer, and The readout circuit includes a first sensing amplifier and a second sensing amplifier. The first sensing amplifier is configured to determine a first programming state of a resistive memory element included in each of the plurality of merged memory cells, and the second sensing amplifier is configured to determine a second programming state of a charge trapping layer included in each of the plurality of merged memory cells.

15. The resistive memory device according to claim 14, wherein, The readout circuit also includes a first sensing switch and a second sensing switch. The first sensing switch connects or disconnects the first sensing amplifier from the plurality of bit lines, and the second sensing switch connects or disconnects the second sensing amplifier from the plurality of bit lines. The control logic determines a first programming state by turning on the first sensing switch and turning off the second sensing switch, and determines a second programming state by turning off the first sensing switch and turning on the second sensing switch.

16. The resistive memory device according to claim 1 or claim 2, wherein, The plurality of memory cells include a plurality of merged memory cells, each of which includes resistive memory elements and a charge trapping layer. The readout circuit includes a sensing amplifier that determines a first programming state of a resistive memory element included in each of the plurality of merged memory cells and a second programming state of a charge trapping layer included in each of the plurality of merged memory cells. Specifically, the control logic controls the sensing amplifier to determine the first programming state at the first time point, and controls the sensing amplifier to determine the second programming state at the second time point.

17. A method of operating a resistive memory device, the method comprising: A first voltage is applied to multiple bit lines of a resistive memory device; A first current is sensed from the memory cell array of the resistive memory device in response to a first voltage; The first memory cell of the memory cell array that has a first programming state in response to a first voltage is determined by comparing a first current with a reference current. A second voltage, different from the first voltage, is applied to the plurality of bit lines; A second current is sensed from the memory cell array in response to a second voltage; as well as The second memory cell of the memory cell array that has a second programming state in response to a second voltage is determined by comparing the second current with the reference current.

18. The method of claim 17, further comprising: After the first memory cell is determined, the serial select line corresponding to the first memory cell is deactivated.

19. The method according to claim 17 or claim 18, wherein, The first memory cell has a first value representing the first programming state as the first bit, and The method further includes: The first value is stored in the first latch corresponding to the first bit of the first memory cell; and The second value is stored in the first latch corresponding to the first bit of the remaining memory cells in the memory cell array excluding the first memory cell.

20. A resistive memory device, comprising: A memory cell array comprising multiple merged memory cells, each of which includes resistive memory elements and a charge trapping layer; The control logic receives read commands and generates voltage control signals for generating multiple read voltages based on the read commands. A voltage generator is configured to sequentially apply the plurality of read voltages to each of the plurality of bit lines connected to the plurality of merged memory cells based on a voltage control signal and to apply a gate voltage to the charge trapping layer; as well as The readout circuit includes a first sensing amplifier configured to determine a first programming state of a resistive memory element and a second sensing amplifier configured to determine a second programming state of a charge trapping layer.

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