Semiconductor device

Abstract

A semiconductor device includes a gate layer stacked on a substrate, a channel layer extending through the gate layer, a string select gate layer disposed on the channel layer, and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion under the string select gate layer and including a first protruding region, a second portion extending through the string select gate layer, and a third portion over the string select gate layer and including a second protruding region.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices. Background Technology

[0002] Modern semiconductor devices are increasingly required to provide high-speed, advanced data processing capabilities while further reducing their already compact size. Therefore, it is necessary to continue increasing the integration density of the constituent elements and components of semiconductor devices. One technique for increasing the integration density of semiconductor devices is to employ a vertical transistor structure instead of the traditional planar transistor structure. Summary of the Invention

[0003] The example implementation provides a semiconductor device with increased integration density and improved electrical characteristics.

[0004] According to one example embodiment, a semiconductor device includes: an alternating arrangement of a gate layer and an interlayer dielectric layer stacked on a substrate; a channel structure extending vertically through the alternating arrangement of the gate layer and the interlayer dielectric layer; a string select gate layer disposed on the channel structure; and a string select channel layer extending vertically through the string select gate layer to contact the channel structure. The string select channel layer includes a first portion below the string select gate layer, a second portion extending through the string select gate layer, and a third portion above the string select gate layer, at least one of the first portion and the third portion including a protruding region.

[0005] According to one example embodiment, a semiconductor device includes: a gate layer stacked on a substrate, a channel layer extending through the gate layer, a string select gate layer disposed on the channel layer, and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer and including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer and including a second protruding region.

[0006] According to one example embodiment, a semiconductor device includes: a gate layer stacked on a substrate; a channel structure including a channel pad and a channel layer and extending through the gate layer; and a string select gate layer disposed on the channel structure and including a string select channel layer extending through the string select gate layer to contact the channel pad and the channel layer. The string select channel layer includes a first portion below the string select gate layer and including a first protruding region having a first width, a second portion extending through the string select gate layer, and a third portion above the string select gate layer and including a second protruding region having a second width greater than the first width. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor device according to an example implementation.

[0008] Figure 2 This is an equivalent circuit diagram of a cell array of a semiconductor device according to an example embodiment.

[0009] Figure 3 This is a plan view of a semiconductor device according to an example implementation.

[0010] Figure 4A This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0011] Figure 4B and Figure 4C This is a partial enlarged view of a semiconductor device according to an example embodiment.

[0012] Figure 4D This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0013] Figure 5A This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0014] Figure 5B This is a partial enlarged view of a semiconductor device according to an example embodiment.

[0015] Figure 5C This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0016] Figure 6A This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0017] Figure 6B This is a partial enlarged view of a semiconductor device according to an example embodiment.

[0018] Figure 6C This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0019] Figure 7 , Figure 8 and Figure 9 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0020] Figures 10A to 10L (include Figure 10A and Figure 10L ( ) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0021] Figures 11A to 11J (include Figure 11A and Figure 11J ( ) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0022] Figure 12A and Figure 12BThis is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Detailed Implementation

[0023] In the following description, some exemplary embodiments will be described with reference to the accompanying drawings. Throughout the written description and the drawings, the same reference numerals and designations denote the same or similar elements.

[0024] Figure 1 This is a block diagram of a semiconductor device 10 according to an example embodiment.

[0025] Reference Figure 1 The semiconductor device 10 mainly includes a memory cell array 20 and peripheral circuitry 30. The peripheral circuitry 30 may include a row decoder 32, a page buffer 34, an input / output (I / O) buffer 35, control logic 36, and a voltage generator 37.

[0026] The memory cell array 20 may include multiple memory blocks, and each memory block may include multiple memory cells. The multiple memory cells are connected to the row decoder 32 via a serial select line (SSL), a word line (WL), and a ground select line (GSL), and are connected to the page buffer 34 via a bit line (BL). In an example embodiment, multiple memory cells arranged along the same row may be connected to the same word line (WL), and multiple memory cells arranged along the same column may be connected to the same bit line (BL).

[0027] The line decoder 32 can decode the input address ADDR to generate and send drive signals, such as word line voltages. For example, the line decoder 32 can provide the word line voltage generated by the voltage generator 37 to one or more selected word lines WL. Under the control of the control logic 36, an unselected word line WL among the multiple word lines can receive another word line voltage.

[0028] Page buffer 34 can be connected to memory cell array 20 via bit line BL to read (or sense) data stored in memory cells. Alternatively or additionally, depending on the operating mode of the semiconductor device, page buffer 34 can be used to temporarily store write data to be written (or programmed) into memory cells. Page buffer 34 may include a column decoder and a sense amplifier. The column decoder can selectively activate bit line BL of memory cell array 20, and the sense amplifier can sense the voltage on bit line BL selected by the column decoder during a read operation to read data stored in memory cells.

[0029] I / O buffer 35 can receive write data (DATA) and send the write data to page buffer 34 during programming operations. I / O buffer 35 can also output read data (DATA) received from page buffer 34 to an external entity during read operations. I / O buffer 35 can send input addresses or instructions to control logic 36.

[0030] Control logic 36 can control the overall operation of line decoder 32 and page buffer 34. Control logic 36 can receive control signals and external voltages sent from external entities, and can operate depending on the received control signals. Control logic 36 can control read, write, and / or erase operations in response to control signals.

[0031] Voltage generator 37 can use an external voltage to generate the voltages required for internal operations, such as programming voltage, read voltage, and erase voltage. The voltage generated by voltage generator 37 can be transmitted to memory cell array 20 via row decoder 32.

[0032] Figure 2 It is based on the example implementation method. Figure 1 The local equivalent circuit diagram of the memory cell array 20.

[0033] Reference Figure 2 The memory cell array 20 includes multiple memory cell strings S. Each memory cell string S may include memory cells MC connected in series with each other, a ground selection transistor GST connected in series with the opposite end of the memory cells MC, and string selection transistors SST1 and SST2. The multiple memory cell strings S may be connected in parallel to corresponding bit lines BL0 to BL2. The multiple memory cell strings S may be connected together to a common source line CSL. For example, the multiple memory cell strings S may be arranged between multiple bit lines BL0 to BL2 and a single common source line CSL. In an example embodiment, the multiple common source lines CSL may be arranged in two dimensions.

[0034] Memory cells MC connected in series can be controlled by word lines WL0 to WLn for selecting the memory cells MC. Each memory cell MC may include a data storage element. The gate layers of the memory cells MC, located at substantially the same distance from the common source line CSL, can be commonly connected to one of the word lines WL0 to WLn to be at the same potential. Alternatively, even when the gate layers of the memory cells MC are located at substantially the same distance from the common source line CSL, the gate layers located in different rows or columns can be controlled independently.

[0035] The ground select transistor GST can be controlled by the ground select line GSL and can be connected to the common source line CSL. The series select transistors SST1 and SST2 can be controlled by the series select lines SSL1 and SSL2 and can be connected to the bit lines BL0 to BL2. Figure 2 The equivalent circuit diagram shows a structure in which a ground select transistor GST and two string select transistors SST1 and SST2 are connected to multiple memory cells MC connected in series with each other. In the example embodiment, one string select transistor SST1 or SST2 may be connected thereto, or multiple ground select transistors GST may be connected thereto. One or more dummy lines DWL or buffer lines may be further provided between the uppermost word line WLn and the string select lines SSL1 and SSL2 among the word lines WL0 to WLn. In the example embodiment, one or more dummy lines DWL may also be provided between the lowermost word line WL0 and the ground select line GSL.

[0036] When signals are applied to string select transistors SST1 and SST2 via string select lines SSL1 and SSL2, signals applied via bit lines BL0 to BL2 can be sent to memory cells MC connected in series to read and write data. Furthermore, a predetermined erase voltage is applied through the substrate to erase data written to the memory cells MC. In an example embodiment, the memory cell array 20 may include at least one dummy memory cell string electrically isolated from bit lines BL0 to BL2.

[0037] Figure 3 This is a plan view of a semiconductor device 100 according to an example embodiment. Figure 4A It is along Figure 3 A cross-sectional view taken from line I-I' in the diagram. Figure 4B yes Figure 4A A magnified view of region 'A' in the image. Figure 4C yes Figure 4A A magnified view of region 'B' in the image.

[0038] Common Reference Figure 3 , Figure 4A , Figure 4B and Figure 4CThe semiconductor device 100 may include: a substrate 101; gate layers 130 stacked vertically on the substrate 101 and spaced apart from each other; interlayer dielectric layers 120 stacked alternately with the gate layers 130; a channel structure CH extending through the gate layers 130 in a direction perpendicular to the upper surface of the substrate 101 and including a channel layer 140 disposed therein; a string select gate layer 150 on the channel structure CH; a string select channel layer 160 extending through the string select gate layer 150 in a direction perpendicular to the upper surface of the substrate 101 and including a string select channel structure SCH disposed therein; and a separation region SR extending through the stacked structure GS of the interlayer dielectric layer 120 and the gate layer 130. The semiconductor device 100 may further include a gate barrier layer 135 surrounding at least a portion of the gate layer 130, a string select gate insulating layer 155 surrounding the string select channel structure SCH, insulating layers 170L and 170U on the gate layer 130, pillars 180 on the string select channel structure SCH, and a source conductive layer and a source insulating layer disposed in the separation region SR.

[0039] In the semiconductor device 100, a single memory cell string may be formed around each channel layer 140, and multiple memory cell strings may be arranged in rows and columns in a first direction (e.g., the X direction) and a second direction (e.g., the Y direction).

[0040] In this regard, and for example, Figure 3 and Figure 4A As shown, geometric orientations can be assumed in the description and / or illustrations of the exemplary embodiments. That is, a first ('X') direction and a second ('Y') direction can be assumed to describe the horizontal plane relative to the upper surface of the substrate 101, while a third ('Z') direction can be assumed to describe the vertical direction relative to the horizontal plane. Those skilled in the art will recognize that such geometric orientations are inherently arbitrary and descriptive, and are used to more clearly teach the implementation and use of the exemplary embodiments. Further in this regard, certain relative orientation terms (e.g., up / down, above / below, below / above, high / low, height, depth, etc.) can be used to describe certain relative relationships between elements or components.

[0041] Therefore, substrate 101 may have an upper surface extending in a horizontal plane (e.g., a plane in the X / Y direction). Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0042] Gate layers 130 may be vertically stacked on substrate 101 and spaced apart from each other to form a stacked structure GS together with interlayer dielectric layer 120. Gate layers 130 may include lower gate layers 130G constituting the gates of ground select transistors and memory gate layers 130M constituting a plurality of memory cells. The number of memory gate layers 130M constituting memory cells may be determined depending on the capacity of semiconductor device 100. In an example embodiment, one or more lower gate layers 130G constituting ground select transistors may be provided and may have the same or different structure as the gate layers 130 constituting memory cells. A portion of gate layer 130, such as the memory gate layer 130M adjacent to lower gate layer 130G, may be a dummy gate layer.

[0043] Gate layers 130 may be vertically spaced apart on substrate 101 and may be separated from each other in the X direction by partition regions SR extending in the Y direction. Gate layers 130 between a pair of partition regions SR may form a memory block, but the scope of the memory block is not limited thereto. A portion of gate layers 130 (e.g., memory gate layer 130M) may form a single layer in a single memory block.

[0044] Gate layer 130 may include a metallic material, such as tungsten (W). In an example embodiment, gate layer 130 may include polysilicon or a metal silicide material. In an example embodiment, gate layer 130 may further include a diffusion barrier on its outer side. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0045] Interlayer dielectric layers 120 may be disposed between gate layers 130. Similar to gate layers 130, interlayer dielectric layers 120 may be configured to be spaced apart from each other in a direction perpendicular to the top surface of substrate 101. Interlayer dielectric layers 120 may comprise an insulating material such as silicon oxide or silicon nitride. Interlayer dielectric layers 120 may have substantially flat upper and lower surfaces. Side surfaces of interlayer dielectric layers 120 may be coplanar with side surfaces of gate layers 130 in the separation region SR, or may have a structure that protrudes from the side surfaces of gate layers 130 toward the separation region SR.

[0046] The channel structures CH can each form a single memory cell string and can be spaced apart from each other in rows and columns on the substrate 101. The channel structures CH can be arranged in a grid pattern or a zigzag pattern in one direction. The channel structures CH can have a pillar shape and can have sloping side surfaces in such a way that their (horizontal) width decreases in the direction toward the substrate 101 depending on the aspect ratio. In addition to the channel layer 140, the channel structures CH may include a gate dielectric layer 145, a channel insulating layer 146, a channel pad 148, and an epitaxial layer 107.

[0047] The channel layer 140 may be formed annularly to surround the channel insulating layer 146 therein. In some embodiments, the channel layer 140 may have a pillar shape, such as cylindrical or prismatic, without the channel insulating layer 146 therein. The channel layer 140 may be connected to the epitaxial layer 107 provided below it. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type or N-type impurities. The channel structure CH disposed in a straight line in the X direction may be connected to different bit lines depending on the arrangement of the upper interconnect structure connected to the channel pad 148. A portion of the channel structure CH may be a dummy channel not connected to a bit line.

[0048] A gate dielectric layer 145 may be disposed between the gate layer 130 and the channel layer 140. (Refer to...) Figure 4C The gate dielectric layer 145 may include a tunneling layer 142, a data storage layer 143, and a barrier layer 144 sequentially disposed from the channel layer 140. Similar to the channel layer 140, the tunneling layer 142, the data storage layer 143, and the barrier layer 144 may extend in a direction perpendicular to the upper surface of the substrate 101.

[0049] The tunneling layer 142 can utilize the FN tunneling mechanism to allow charge to tunnel to the data storage layer 143. The tunneling layer 142 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or combinations thereof. The data storage layer 143 may be a charge trapping layer and may be formed of silicon nitride. The barrier layer 144 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), a high-k dielectric material, or combinations thereof. A high-k dielectric material refers to a dielectric material having a higher dielectric constant than silicon oxide (SiO2). High-k dielectric materials may be, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfSi) x Oy Lanthanum oxide (La₂O₃), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y Praseodymium oxide (Pr2O3) or combinations thereof.

[0050] Epitaxial layer 107 can be disposed below the channel structure CH on the substrate 101 and can be disposed on the side surface of at least one gate layer 130. Epitaxial layer 107 can be disposed in a recessed region of the substrate 101. The upper surface of epitaxial layer 107 can have a height higher than the upper surface of the lowermost gate layer 130G and lower than the lower surface of the uppermost gate layer 130M, but its height is not limited thereto. Even when the aspect ratio of the channel structure CH increases, the channel layer 140 can be stably electrically connected to the substrate 101 through epitaxial layer 107, and uniform characteristics of the ground selection transistor GST between memory cell strings can be obtained. However, in some embodiments, epitaxial layer 107 can be omitted. In this case, channel layer 140 can be directly connected to substrate 101.

[0051] The channel pad 148 may be disposed on the upper part of the channel layer 140 in the channel structure CH. The channel pad 148 may be configured to cover the upper surface of the channel insulating layer 146 and be electrically connected to the channel layer 140. The channel pad 148 may include, for example, doped polysilicon.

[0052] The string select gate layer 150 can be disposed on the channel structure CH. The string select gate layers 150 constituting the string select line can extend in the Y direction and can be separated from each other at regular intervals in the X direction by upper partition regions 150R. The number of string select gate layers 150 separated by upper partition regions 150R is not limited to the number shown in the figure. The string select gate layers 150 can be separated from each other in the X direction by partition regions SR. The string select gate layer 150 can be the gate electrode of a string select transistor and can correspond to... Figure 2 The implementation shows the string selection lines SSL0 to SSL2. In some implementations, the upper dividing region 150R may be provided as a line or rectangle extending in the Y direction, but may be arranged in a zigzag pattern in one direction.

[0053] The string select gate layer 150 may include a plurality of vias 150H. The plurality of vias 150H may be configured to overlap with the channel structure CH. The arrangement and / or number of the plurality of vias 150H are not limited to the arrangement and / or number shown in the figures. The string select channel structure SCH may be connected to the channel structure CH through the plurality of vias 150H of the string select gate layer 150. Each of the plurality of vias 150H may have a width (in the X direction) greater than the width of each of the string select channel structure SCH in the plurality of vias 150H.

[0054] The string select gate layer 150 may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type and / or N-type impurities.

[0055] A series select gate insulating layer 155 may surround the series select channel layer 160 within a plurality of vias 150H. For example, the series select gate insulating layer 155 may surround a second portion 162 of the series select channel layer 160, which will be described later. The series select gate insulating layer 155 may serve as the gate dielectric layer of a series select transistor. For example, the series select gate insulating layer 155 may insulate the series select gate layer 150 and the series select channel layer 160 from each other. The series select gate insulating layer 155 may have a structure connecting an underlying lower insulating layer 170L and an upper insulating layer 170U, and may comprise the same material as the lower insulating layer 170L and the upper insulating layer 170U.

[0056] The string select channel structure SCH can be arranged in rows and columns on the substrate, spaced apart from each other, and can be arranged to overlap with the channel structure CH. The string select channel structure SCH can be arranged in a grid form or in a zigzag pattern in one direction. The string select channel structure SCH can extend through the string select gate layer 150 and can extend from the channel structure CH in a direction perpendicular to the upper surface of the substrate 101. The string select channel structure SCH can have a pillar shape and can have sloping side surfaces in a manner in which its width depends on the aspect ratio and decreases in the direction toward the substrate 101. The string select channel structure SCH may include: a string select channel layer 160 extending in a direction perpendicular to the upper surface of the substrate 101; a string select insulating layer 166 within the string select channel layer 160; and a string select channel pad 168 having side surfaces and a lower surface surrounded by the string select channel layer 160 and the string select insulating layer 166.

[0057] The string select channel layer 160 may be annularly formed to surround a string select insulating layer 166 therein. In some embodiments, the channel layer 140 may have a pillar shape, such as cylindrical or prismatic, without the string select insulating layer 166. The string select channel layer 160 may be connected to a channel structure CH provided beneath it and may contact a channel pad 148 respectively. The string select channel layer 160 may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type and / or N-type impurities. In an example embodiment, the string select channel layer 160 may include the same material as the channel layer 140.

[0058] Each string select channel layer 160 may include a first portion 161 below the string select gate layer 150, a second portion 162 extending through (or through) the string select gate layer 150, and a third portion 163 above the string select gate layer 150. As will be described below in some additional detail, at least one of the first portion 161 and the third portion 163 of each string select channel layer 160 may include a protruding region of various shapes. In this regard, the term "protruding region" refers to a portion (or region) of the first portion 161 and / or a portion (or region) of the third portion 163 having an inner side surface extending outward from the center of the string select channel layer 160 compared to the inner side surface immediately above and / or below the protruding region. Therefore, assuming a vertically oriented channel structure CH and a string-selected channel layer 160, the protruding region will have a width (measured in the horizontal direction) between the inner side surfaces that is larger than the portion of the string-selected channel layer 160 immediately above and / or below the protruding region.

[0059] Therefore, the first portion 161 can be disposed between the channel structure CH and the string select gate layer 150, and can make electrical contact with the channel structure CH through the lower insulating layer 170L. The first portion 161 may include a first protruding region P1 that protrudes outward from the center of the string select channel layer 160 beyond the tapered sidewall of the first portion 161 above and / or below the first protruding region P1. Therefore, the resulting extended protruding width of the first protruding region P1 can extend in the X direction to be greater than the width of the upper portion of the first portion 161 above the first protruding region P1 and / or the width of the lower portion of the first portion 161 below the first protruding region P1.

[0060] For example, refer to Figure 4BIn the illustrated embodiment, the first width W1 of the first protruding region P1 may be greater than at least one of the second width W2 of the upper portion of the first portion 161 and the third width W3 of the lower portion of the first portion 161. In one embodiment, the first width W1 may be greater than the maximum permissible value of the third width W3. In the example embodiment, it will be understood that the first portion 161 may have multiple regions with different widths.

[0061] The second portion 162 may be disposed within a plurality of vias 150H of the string select gate layer 150 and may be connected to the first portion 161. The second portion 162 may have a width smaller than the width of the plurality of vias 150H. The second portion 162 may be surrounded by a string select gate insulating layer 155 within the plurality of vias 150H.

[0062] The third portion 163 may extend further upward from the string select gate layer 150 to be disposed in the upper insulating layer 170U, and may be connected to the second portion 162. The third portion 163 may include a second protruding region P2 having a width extending outward from the center of the string select channel layer 160 in the X direction. Like the first protruding region P1, the second protruding region P2 may be surrounded by the upper (upper portion) and / or lower (lower portion) portions of the third portion 163 relative to the second protruding region P2.

[0063] For example, the third portion 163 may include a second protruding region P2 having a fourth width W4 that is larger than the fifth width W5 of the lower portion of the third portion 163 extending between the second protruding region P2 and the second portion 162. In one embodiment, the fourth width W4 may be greater than the maximum permissible value of the fifth width W5.

[0064] In one embodiment, each of the first width W1, second width W2, third width W3, fourth width W4, and fifth width W5 described above may fall within the range of about 80 nm to about 120 nm. In this regard, each of the first width W1, second width W2, third width W3, fourth width W4, and fifth width W5 may be a width measured from between the inner side surfaces (or sidewalls) of the string select channel layer 160.

[0065] The string selection insulating layer 166 may be disposed in the string selection channel layer 160 and may have a side surface perpendicular to the upper surface of the substrate 101, or may have an inclined surface in such a way that its width depends on the aspect ratio and decreases in the direction toward the substrate 101. The string selection insulating layer 166 may be disposed in a first portion 161 and a second portion 162, and may have a region in the first protruding region P1 extending in a direction parallel to the upper surface of the substrate 101. The string selection insulating layer 166 may be disposed in a third portion 163, and the top surface of the string selection insulating layer 166 may be configured to be lower than the second protruding region P2. The string selection insulating layer 166 may comprise an insulating material such as silicon oxide or silicon nitride.

[0066] A series select channel pad 168 may be disposed in the second protruding region P2 on the inner side surface of the series select channel layer 160. The series select channel pad 168 may be surrounded by the series select channel layer 160 and the series select insulating layer 166 at its side and bottom surfaces. In one embodiment, the series select channel pad 168 may have a fourth width W4 greater than the fifth width W5. In an example embodiment, the series select channel pad 168 may have a width greater than the width of other components of the series select channel structure SCH. The series select channel pad 168 may be formed of a conductive material, such as doped polysilicon.

[0067] However, when reducing the overall width of the channel structure CH to increase the integration density of semiconductor devices, it can become more difficult to form (and connect) certain upper interconnects with relatively large widths. According to certain embodiments of the present invention, a string select channel pad 168 having a width larger than other portions of the string select channel structure SCH can be disposed in the second protruding region P2, allowing upper interconnects such as pillars 180 to be connected more stably, thereby providing a more reliable connection between the channel layer 140 and the string select channel layer 160. In particular, when the thickness of the pillars 180 is relatively large, the pillars 180 can form a more stable contact with the channel layer 140 through the string select channel layer 160. As a result, the semiconductor device with the aforementioned configuration can exhibit improved electrical characteristics.

[0068] A lower insulating layer 170L may be disposed between the gate layer 130 and the string select gate layer 150, and an upper insulating layer 170U may be disposed on the string select gate layer 150. The lower insulating layer 170L and the upper insulating layer 170U may comprise insulating materials such as silicon oxide or silicon nitride, and may comprise the same material. In an example embodiment, the lower insulating layer 170L and the upper insulating layer 170U may be configured to connect to the string select gate insulating layer 155, and may also be configured to connect to the upper partition region 150R.

[0069] The pillar 180 may be disposed on the string select channel structure SCH and may extend through the upper insulating layer 170U to the upper surface of the string select channel pad 168 in a direction perpendicular to the upper surface of the substrate 101. The pillar 180 may have a side surface perpendicular to the upper surface of the substrate 101, or may have an inclined side surface in such a way that its width decreases in the X direction depending on the aspect ratio. The pillar 180 may be disposed in contact with the upper surface of the string select channel pad 168 and thus may be connected to the string select channel pad 168. The pillar 180 may be disposed by partially recessing the upper portion of the string select channel pad 168, but the depth of the recess may vary depending on the example embodiment. The pillar 180 may include, for example, metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) and / or metallic materials (such as aluminum (Al), tungsten (W), or molybdenum (Mo)).

[0070] Reference Figure 4D , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7 , Figure 8 and Figure 9 Further embodiments of the semiconductor device conceived according to the present invention are described.

[0071] Figure 4D This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 4D It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line II in the diagram.

[0072] Reference Figure 4D And through comparison with reference Figure 4A , Figure 4B and Figure 4C In comparison to the described embodiments, in semiconductor device 100a, the string select channel pad 168 of the string select channel structure SCHa may include an extension portion 168R extending downward from the second protruding region P2. (Referring to the above...) Figure 4B The description differs, but the string select insulating layer 166a filling the interior of the third portion 163 may include a recessed portion that is recessed downward relative to the second protruding region P2. An extension 168R may extend downward within the recessed portion of the string select insulating layer 166a. This structure can be formed during the processes of removing the upper portion of the string select insulating layer 166, filling the interior of the string select channel layer 160, and forming the string select channel pad 168.

[0073] Figure 5AThis is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 5A It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line I-I' in the diagram. Figure 5B This is a partial enlarged view of a semiconductor device according to an example embodiment. Figure 5B It shows Figure 5A The magnified region of region 'C' in the text.

[0074] Reference Figure 5A and Figure 5B By referring to Figure 4A , Figure 4B and Figure 4C In comparison to the described implementation, in semiconductor device 100b, the channel structure CHa may not include the channel pad on the channel insulating layer 146a, and the lower surface of the first portion 161' of the string select channel layer 160 constituting the string select channel structure SCHb may be disposed at a vertical height "lower" than the upper surface of the channel structure CHa (given the geometric assumptions of the implementation).

[0075] That is, the lower base portion of the protruding region P1a of the base shape (hereinafter, "base") can be seated between the inner side surfaces of the channel layer 140 to directly contact the inner side surfaces of the channel layer 140. In this regard, the term "seated between" refers to the physical arrangement between the lower base portion of the protruding region P1a and the upper surface of the channel structure CHa, wherein the lower base portion of the protruding region P1a is disposed below the upper surface of the channel structure CHa and is disposed between (and in contact with) the inner side surfaces of the channel layer 140.

[0076] Therefore, the first portion 161' may include a lower base portion 161a (in the X direction) seated between the inner side surfaces of the channel structure CHa, and an upper base portion 161b disposed on the first base region 161a. The lower base portion 161' may serve as a direct contact point with the channel layer 140, at least through the lower base portion 161a. Here, the lower base portion 161a may have a first region width W1a, and the upper base portion 161b may have a second region width W1b smaller than the first region width W1a. The second width W2 of the upper portion of the first portion 161' between the base protrusion region P1a and the second portion 162 may be smaller than the second region width W1b.

[0077] When reducing the width of the channel structure CHa to increase the integration density of semiconductor devices, it may be difficult to form a channel pad that completely fills its interior without gaps, thereby degrading the electrical performance of the semiconductor device. However, according to certain embodiments of the present invention, instead of forming the channel pad of the channel structure CHa, a portion of the selected channel layer 160 may extend down to the channel layer 140 and serve as a direct contact with the channel layer 140, thereby providing improved electrical characteristics for the semiconductor device.

[0078] Figure 5C This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 5C It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line I-I' in the diagram.

[0079] Reference Figure 5C , and reference Figure 5A and Figure 5B Compared to the described semiconductor device 100b, the string select channel pad 168 of the string select channel structure SCHc further includes an extension 168R extending downward between the channel structure CHa and the second protruding region P2. Because the extension 168R is related to the reference... Figure 4D The extension of the description is the same as 168R, so its description will be omitted.

[0080] Figure 6A This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 6A It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line II in the diagram.

[0081] Figure 6B This is a partial enlarged view of a semiconductor device according to an example embodiment. Figure 6B It shows Figure 6A The magnified area of ​​region 'D' in the text.

[0082] Reference Figure 6A and Figure 6B By referring to Figure 4A , Figure 4B and Figure 4C Compared to the described semiconductor device 100, the channel structure CHa may not include a channel pad on the channel insulating layer 146a, and the lower surface of the first portion 161" of the string select channel layer 160 constituting the string select channel structure SCHd may be configured to be lower than the upper surface of the channel structure CHa. The lower portion of the plug-shaped (hereinafter, "plug") protruding region P1b may extend between the inner side surfaces of the channel layer 140 to serve as a direct contact point with the inner side surfaces of the channel layer 140.

[0083] exist Figure 6BIn the illustrated embodiment, the plug protrusion region P1b may include: (1) a lower portion 161a, seated between the inner side surfaces of the channel layer 140 (i.e., configured to contact and fill the inner side of the inner side surfaces of the channel layer 140); (2) a middle portion 161b, disposed on the lower portion 161a and overlapping the upper surface of the channel layer 140; and (3) an upper portion 161c, disposed on the middle portion 161b. Here, the lower portion 161a may directly contact the inner side surfaces of the channel layer 140, the middle portion 161b may cover the upper surface of the channel layer 140, and the upper portion 161c may be used as a contact with the second portion 162.

[0084] Here, the outer side surface of the intermediate region 161b may protrude outward beyond the boundary between the channel layer 140 and the gate dielectric layer 145, but its location is not limited to this.

[0085] The lower part 161a of the plug protrusion region P1b may have a first region width W1a, the middle part 161b of the plug protrusion region P1b may have a second region width W1c that is greater than the first region width W1a, and the upper part 161c of the plug protrusion region P1b may have a third region width W1b that is less than the second region width W1c. The third region width W1b may also be less than the second width W2.

[0086] As described above, when reducing the width of each channel structure CHa to increase the integration density of semiconductor devices, it may be difficult to form a channel pad that completely fills its interior without gaps. However, according to an embodiment of the present invention, instead of forming a channel pad on the channel structure CHa, a portion of the selected channel layer 160 may extend between the inner side surfaces of the channel layer 140 to directly contact the channel layer 140, thereby providing improved electrical characteristics for the semiconductor device.

[0087] Figure 6C This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 6C It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line I-I' in the diagram.

[0088] Reference Figure 6C Semiconductor device 100e corresponds to an example embodiment, in which, compared with reference to Figure 6A and Figure 6B Compared to the described semiconductor device 100d, the string select channel pad 168 may further include an extension 168R extending downward from the second protruding region P2. Because the extension 168R is consistent with the reference... Figure 4D The extension of the description is the same as 168R, so its description will be omitted.

[0089] Figure 7 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 7 It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line I-I' in the diagram.

[0090] Reference Figure 7 By referring to Figure 4A Compared to the described semiconductor device 100, semiconductor device 100f may include a channel structure CHb that does not include the epitaxial layer 107, and may further include a first conductive layer 104 and a second conductive layer 105 disposed between the substrate 101 and the interlayer dielectric layer 120. Furthermore, the separation region SR may be filled only with a separation insulating layer comprising an insulating material.

[0091] The first conductive layer 104 and the second conductive layer 105 may be stacked on the upper surface of the substrate 101. At least a portion of the first conductive layer 104 and the second conductive layer 105 may serve as a common source line for the semiconductor device 100f. The first conductive layer 104 may be directly connected to the channel layer 140 around the channel structure CHb. The first conductive layer 104 and the second conductive layer 105 may comprise a semiconductor material such as polysilicon. In this case, at least the first conductive layer 104 may be a doped layer, and the second conductive layer 105 may be a doped layer or a layer comprising impurities diffused from the first conductive layer 104.

[0092] exist Figure 7 In the channel structure CHb, the channel layer 140 and the gate dielectric layer 145 can be configured to extend inward into the substrate 101 (i.e., deeper than the upper main surface). A portion of the gate dielectric layer 145 can be removed from its lower end, and the first conductive layer 104 can be connected to the channel layer 140 in the region where the gate dielectric layer 145 has been removed. As described above, the shape of the common source line including the first conductive layer 104 and the second conductive layer 105 can be applied to... Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 6A , Figure 6B and Figure 6C Example implementation.

[0093] Figure 8 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 8 It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line I-I' in the diagram.

[0094] Reference Figure 8The semiconductor device 100g may include a first stacked structure GS1 and a second stacked structure GS2 in which gate layers 130 are vertically stacked, and a first channel structure CH1 and a second channel structure CH2 in which channel structures CHc are vertically stacked. When the number of stacked gate layers 130 is relatively large, the channel structure CHc can be introduced in such a configuration to stably form the channel structure CHc.

[0095] The channel structure CHc can have a pillar shape and can have sloping side surfaces whose width decreases toward the substrate 101 in the Z direction depending on the aspect ratio. Therefore, the widths of the gate layers 130 in the X direction can differ from each other, and the resistance characteristics of the gate layers 130 can vary accordingly. For example, the lower gate layer 130 can have relatively low resistance(s) and can produce memory cells exhibiting improved performance characteristics. The separating region SR can have sloping side surfaces that narrow toward the substrate 101 in the Z direction depending on the aspect ratio. Therefore, the gate layer of the first stacked structure GS1 can have relatively low resistance and provide memory cells exhibiting improved characteristics.

[0096] In the channel structure CHc, the first channel structure CH1 of the first stacked structure GS1 and the second channel structure CH2 of the second stacked structure GS2 can be connected to each other. As a result, the channel structure CHc may include a curved portion formed by a width difference at the connection between the first channel structure CH1 of the first stacked structure GS1 and the second channel structure CH2 of the second stacked structure GS2. The channel layer 140, the gate dielectric layer 145, and the channel insulating layer 146 are connected to each other between the first channel structure CH1 and the second channel structure CH2. The channel pad 148 may be disposed only at the upper end of the upper second channel structure CH2. However, in other embodiments, each of the first channel structure CH1 and the second channel structure CH2 may include a channel pad 148. In this case, the channel pad 148 of the first channel structure CH1 may be connected to the channel layer 140 of the second channel structure CH2. Figure 8 As described in the example embodiment, the semiconductor device 100g may include a first conductive layer 104 and a second conductive layer 105, but is not limited thereto. For example, the semiconductor device 100g may further include a first conductive layer 104 and a second conductive layer 105. Figure 4A The epitaxial layer 107 at the lower end of the channel structure CHb described in the example embodiment is used instead of the first conductive layer 104 and the second conductive layer 105.

[0097] An upper interlayer dielectric layer 125 with relatively large thickness can be disposed on the topmost portion of the first stacked structure GS1. However, according to an example embodiment, the interlayer dielectric layer 120 and the upper interlayer dielectric layer 125 can have various shapes. In an example embodiment, a dummy gate layer can be further disposed on the boundary between the first stacked structure GS1 and the second stacked structure GS2. The dummy gate layer may not be used as an actual memory cell in which data is stored. Descriptions of other components can be referenced above. Figure 3 , Figure 4A , Figure 4B and Figure 4C The descriptions given are the same.

[0098] Figure 9 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 9 It shows the relationship with along Figure 3 The region corresponding to the section intercepted by line I-I' in the diagram.

[0099] Reference Figure 9 The semiconductor device 100h may include a memory cell region CELL vertically stacked on the peripheral circuit region PERI. Therefore, the memory cell region CELL may be disposed above the peripheral circuit region PERI (or at the upper end of the peripheral circuit region PERI). By comparison, Figure 4A The semiconductor device 100 may include a peripheral circuit region PERI disposed on the substrate 101, or as... Figure 9 As shown, the semiconductor device 100h may include a vertically stacked arrangement of memory cell regions (CELL) and peripheral circuit regions (PERI). However, in other embodiments, the cell regions (CELL) may be located below the peripheral circuit regions (PERI). Descriptions of other components can be found in the above references. Figure 3 , Figure 4A , Figure 4B and Figure 4C The descriptions given are the same.

[0100] The peripheral circuit region PERI may include a base substrate 201, circuit elements 220 disposed on the base substrate 201, circuit contact plugs 270, and circuit interconnects 280.

[0101] The base substrate 201 may have an upper surface extending in a horizontal plane (e.g., in the XY direction). An additional device isolation layer may be formed in the base substrate 201 to define an active region. Source / drain regions 205, including impurities, may be disposed within a portion of the active region. The base substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0102] Circuit element 220 may include a horizontal transistor. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed in the base substrate 201 on opposite sides adjacent to the circuit gate electrode 225.

[0103] A peripheral region insulating layer 290 may be disposed on the base substrate 201 on the circuit element 220. A circuit contact plug 270 may pass through the peripheral region insulating layer 290 to connect to the source / drain region 205. Electrical signals may be applied to the circuit element 220 through the circuit contact plug 270. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. Circuit interconnects 280 may be connected to the circuit contact plug 270 and may be configured in multiple layers.

[0104] In semiconductor device 100h, a peripheral circuit region (PERI) can be formed, and then a substrate 101 for a memory cell region (CELL) can be formed thereon. The substrate 101 can be formed to have the same dimensions as or smaller than the base substrate 201. Those skilled in the art will recognize that the memory cell region (CELL) and the peripheral circuit region (PERI) can be interconnected with each other using various vertical and horizontal connections (not shown). For example, one end of the gate layer 130 in the Y direction can be electrically connected to the circuit element 220. The aforementioned configuration of vertically stacked memory cell regions (CELL) and peripheral circuit regions (PERI) can be applied... Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7 and Figure 8 Any of the example implementations.

[0105] Figures 10A to 10L This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0106] Reference Figure 10A A horizontal sacrificial layer 110 and an interlayer dielectric layer 120 can be alternately stacked on a substrate 101 to form a stacked structure.

[0107] The horizontal sacrificial layer 110 can be replaced by the gate layer 130 through subsequent processes. The horizontal sacrificial layer 110 can be formed of a material different from that of the interlayer dielectric layer 120. For example, the interlayer dielectric layer 120 can be formed of at least one of silicon oxide and silicon nitride, and the horizontal sacrificial layer 110 can be formed of a material different from that of the interlayer dielectric layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In the example embodiment, the thickness of the interlayer dielectric layer 120 may not all be the same. For example, the lowermost interlayer dielectric layer 120 can be formed with a relatively small thickness, and the uppermost interlayer dielectric layer 120 can be formed with a relatively large thickness. The thicknesses of the interlayer dielectric layer 120 and the horizontal sacrificial layer 110, as well as the number of constituting layers, can differ from the thicknesses and numbers shown in the figures. A preliminary insulating layer 170' can be formed on the uppermost portion.

[0108] Reference Figure 10B A channel hole CHH can be formed through a stacked structure including a horizontal sacrificial layer 110 and an interlayer dielectric layer 120, and an epitaxial layer 107 can be formed on its lower end.

[0109] The channel via CHH can be formed by anisotropically etching the horizontal sacrificial layer 110 and the interlayer dielectric layer 120, and can be formed into a circular hole shape. Due to the height of the stacked structure, the sidewalls of the channel via CHH may not be perpendicular to the upper surface of the substrate 101. The channel via CHH can be formed such that a portion of the substrate 101 is recessed.

[0110] Epitaxial layer 107 can be formed using selective epitaxial growth (SEG). Epitaxial layer 107 can comprise a single layer or multiple layers. Epitaxial layer 107 can comprise doped or undoped polycrystalline silicon, monocrystalline silicon, polycrystalline germanium, or monocrystalline germanium. However, in the example embodiment, epitaxial layer 107 can be omitted.

[0111] Reference Figure 10C A gate dielectric layer 145, a channel layer 140, a channel insulating layer 146, and a channel pad 148 can be sequentially formed in the channel hole CHH to form a channel structure CH.

[0112] The gate dielectric layer 145 can be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this case, all or a portion of the gate dielectric layer 145 can be formed, and a portion extending along the channel structure CH in a direction perpendicular to the upper surface of the substrate 101 can be formed, for example... Figure 4A The tunneling layer 142, data storage layer 143, and barrier layer 144 are included.

[0113] A channel layer 140 may be formed in a channel via on a gate dielectric layer 145. A channel insulating layer 146 is formed to fill the channel via and may include an insulating material. However, in an example embodiment, the channel via may be filled with a conductive material instead of the channel insulating layer 146. The channel pad 148 may be formed of a conductive material, such as polysilicon.

[0114] Reference Figure 10D A lower insulating layer 170L can be formed to cover the channel structure CH, and a preliminary string select gate layer 150' can be formed on the lower insulating layer 170L.

[0115] The channel structure CH and the initial insulating layer 170' can be covered with an insulating material, which together with the initial insulating layer 170' forms a lower insulating layer 170L. The lower insulating layer 170L can cover the uppermost gate layer 130 and the channel structure CH. The lower insulating layer 170L can include an insulating material such as silicon oxide or silicon nitride.

[0116] The initial string select gate layer 150' may be formed parallel to the substrate 101 and may have an upper surface extending in a horizontal direction. The initial string select gate layer 150' may be formed to be spaced apart from the horizontal sacrificial layer 110 and the channel structure CH by a lower insulating layer 170L. The initial string select gate layer 150' may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type and / or N-type impurities.

[0117] Reference Figure 10E An upper separating region 150R can be formed to separate the initial string select gate layer 150' from each other at regular intervals in the X direction. An upper insulating layer 170U can be formed, and a first hole H1 can be formed in the initial string select gate layer 150'.

[0118] A portion of the initial string select gate layer 150' may be removed to separate the initial string select gate layers 150' from each other at regular intervals in the X direction. The region where the initial string select gate layer 150' has been removed may be a linear region extending in the Y direction, and in some embodiments may be a region extending in a zigzag pattern in one direction. The region where the initial string select gate layer 150' has been removed may be filled with an insulating material to form the upper separating region 150R.

[0119] The upper insulating layer 170U can be formed to cover the initial string select gate layer 150'. The upper insulating layer 170U can be a layer formed on the initial string select gate layer 150' after its upper portion is planarized to form an upper separation region 150R. The upper insulating layer 170U can include an insulating material such as silicon oxide or silicon nitride.

[0120] A first via H1 can be formed to penetrate the upper insulating layer 170U, the lower insulating layer 170L, and the preliminary string select gate layer 150'. The first via H1 can be formed by anisotropically etching the upper insulating layer 170U, the lower insulating layer 170L, and the preliminary string select gate layer 150', and can be formed in a via shape. The first via H1 can be formed to expose the upper surface of the channel structure CH. For example, the first via H1 can be formed to expose a portion of the upper surface of the channel pad 148.

[0121] Reference Figure 10F The first hole H1 can be extended in a direction parallel to the upper surface of the substrate 101 to form a first extended hole EH1.

[0122] The portions of the upper insulating layer 170U and the lower insulating layer 170L adjacent to the first via H1 can be removed, such that the first extended via EH1 can be formed to expose portions of the upper and lower surfaces of the initial string select gate layer 150'. The first extended via EH1 can be formed to further expose the upper surface of the channel structure CH. The first extended via EH1 can be formed using, for example, a wet etching process. Portions of the upper insulating layer 170U and the lower insulating layer 170L can be selectively removed relative to the initial string select gate layer 150' and the channel structure CH using a wet etching process.

[0123] Reference Figure 10G A first insulating pattern 170a can be formed to cover the inner wall of the first expansion hole EH1.

[0124] The first insulating pattern 170a can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first insulating pattern 170a can be formed to cover the upper and side surfaces of the upper insulating layer 170U and the side surface of the lower insulating layer 170L. The first insulating pattern 170a can be formed to cover the upper, lower, and side surfaces of the preliminary string select gate layer 150' exposed by the first expansion via EH1, and to cover the upper surface of the channel structure CH. The first insulating pattern 170a can be formed to have a uniform thickness along the shape of the inner wall of the first expansion via EH1. The first insulating pattern 170a can include the same material as the upper insulating layer 170U and the lower insulating layer 170L. The first insulating pattern 170a can include, for example, an insulating material, such as silicon oxide or silicon nitride.

[0125] Reference Figure 10H Spacers 175 can be formed to cover the first insulating pattern 170a.

[0126] The spacer 175 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The spacer 175 can be formed to have a substantially uniform thickness along the sidewalls of the first insulating pattern 170a. The spacer 175 may comprise a material having etch selectivity relative to the upper insulating layer 170U, the lower insulating layer 170L, and the first insulating pattern 170a. The spacer 175 may comprise, for example, silicon nitride (SiN).

[0127] Reference Figure 10I The lower part of the spacer 175 can be removed to expose the lower part of the first insulating pattern 170a, and the lower part of the first insulating pattern 170a can be recessed to form the second insulating pattern 170b.

[0128] The lower portion of the spacer 175 covering the lower part of the first insulating pattern 170a can be removed by an etch-back process. As a result, the lower portion of the first insulating pattern 170a can be exposed. In the etch-back process, the first insulating pattern 170a covering the upper and side surfaces of the initial string select gate layer 150' can be protected by the spacer 175.

[0129] The lower portion of the first insulating pattern, exposed by the etch-back process, can be recessed to form the second insulating pattern 170b. The second insulating pattern 170b can be formed by removing a portion of the lower portion of the upper surface of the first insulating pattern 170a covering the channel pad 148. A portion of the upper surface of the channel pad 148 can be recessed and exposed. The lower portion of the first insulating pattern 170a can be removed to have a hole shape.

[0130] Reference Figure 10J It can remove spacer 175 and form a preliminary string selective channel layer 160x to cover the second insulating pattern 170b.

[0131] The initial string selection channel layer 160x may be formed to have a substantially uniform thickness along the sidewalls of the second insulating pattern 170b. The initial string selection channel layer 160x may contact a channel pad 148 having a recessed exposed upper surface. The initial string selection channel layer 160x may comprise a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type and / or N-type impurities.

[0132] Reference Figure 10K A string selection insulating layer 166 can be formed to fill the first expansion hole EH1, and a string selection channel pad 168 can be formed on the string selection insulating layer 166.

[0133] After the first expansion via EH1 is filled with an insulating material layer, the upper portion of the insulating material layer can be removed by an etch-back process. A semiconductor material, such as polysilicon, forming the string select channel pad 168, can fill the area removed by the etch-back process, and a chemical mechanical polishing (CMP) process can be performed. The upper insulating layer 170U and the upper surface of the string select channel pad 168 can be planarized by a CMP process. A portion of the upper portion of the initial string select channel layer 160x can be removed to form the string select channel layer 160. Therefore, as... Figure 4A As shown, a series select channel structure SCH can be formed, including a series select channel layer 160, a series select insulating layer 166, and a series select channel pad 168.

[0134] In other embodiments, during the operation of removing the upper portion of the insulating material layer using an etch-back process, the upper portion of the string-selective insulating layer 166 can be further recessed, such that the string-selective insulating layer 166 can be formed with a recessed portion on its upper portion, as shown below. Figure 4D , Figure 5C and Figure 6C As shown. Further processes, as described below, can be performed to manufacture with Figure 4D , Figure 5C and Figure 6C The example implementation corresponds to the semiconductor device.

[0135] Reference Figure 10L An opening OP can be formed to penetrate the stacked structure at predetermined intervals. The horizontal sacrificial layer 110 exposed through the opening OP can then be removed to form a lateral opening.

[0136] In an example implementation, prior to forming the opening OP, an insulating layer may be additionally formed on the upper insulating layer 170U and the string select channel pad 168 to prevent damage to the string select channel pad 168, the string select channel layer 160 provided thereunder, etc. The opening OP can be formed by using a photolithography process to form a mask layer and anisotropically etching a stacked structure of the horizontal sacrificial layer 110 and the interlayer dielectric layer 120. The opening OP can be formed as a trench extending in the Y direction. The initial string select gate layer 150' can be separated by the opening OP to form the string select gate layer 150.

[0137] The horizontal sacrificial layer 110 can be selectively removed relative to the interlayer dielectric layer 120 using, for example, a wet etching process. Therefore, a plurality of lateral openings LT can be formed between the interlayer dielectric layers 120, and portions of the sidewalls of the channel structure CH can be exposed through the lateral openings LT.

[0138] Reference Figure 4A and Figure 10LThe gate layer 130 can be formed by filling the lateral opening with a conductive material. A separating insulating layer and a source conductive layer can be formed in the opening OP, and pillars 180 can be formed to pass through the upper insulating layer 170U and connect to the series select channel pad 168. Before forming the gate layer 130, a gate barrier layer 135 can be formed in the lateral opening LT.

[0139] The conductive material may include metals, polycrystalline silicon, or metal semiconductor compounds. The insulating layer may be formed in the form of spacers in the opening OP. For example, the insulating layer may be formed by depositing an insulating material and removing the insulating material formed on the substrate 101 at the lower part of the opening OP. By depositing a conductive material on the insulating layer, a source conductive layer can be formed to form the separation region SR. However, according to an example embodiment, the separation region SR may only be filled with the insulating layer. The pillar 180 may be formed by forming a hole penetrating the upper insulating layer 170U and filling the hole with a conductive material. As a result, it is possible to manufacture, for example, in… Figure 4A Semiconductor device 100 is shown in the figure.

[0140] Figures 11A to 11J This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment, as another example. Figures 11A to 11J It shows the relationship with Figure 5A The corresponding cross section.

[0141] Reference Figure 11A It can execute the above references Figures 10A to 10B The same process is used to form a stacked structure and to form the channel via CHH and epitaxial layer 107.

[0142] Can be executed in accordance with the above references Figure 10C The same process can be used, but the channel pad 148 may not be formed. A gate dielectric layer 145, a channel layer 140, and a channel insulating layer 146a may be formed in the channel via CHH to form a channel structure CHa.

[0143] Can be executed in accordance with the above references Figure 10D The same process is used to form a lower insulating layer 170L covering the channel structure CHa and to form a preliminary string select gate layer 150' on the lower insulating layer 170L, such as Figure 11A As shown.

[0144] Reference Figure 11B An upper separating region 150R can be formed to separate the initial string select gate layer 150' from each other at regular intervals in the X direction. An upper insulating layer 170U can be formed, and a second hole H2 can be formed in the initial string select gate layer 150'.

[0145] References above Figure 10EThe same description given can be applied to the process of forming the upper separating region 150R and the upper insulating layer 170U.

[0146] A second via H2 can be formed to penetrate the upper insulating layer 170U, the lower insulating layer 170L, and the preliminary string select gate layer 150'. The second via H2 can be formed by anisotropically etching the upper insulating layer 170U, the lower insulating layer 170L, and the preliminary string select gate layer 150', and can be formed in a via shape. The second via H2 can be formed such that its lower surface is disposed between the channel structure CH and the preliminary string select gate layer 150'. For example, the lower surface of the second via H2 can be higher than the upper surface of the channel layer 140. The arrangement and / or number of second vias H2 are not limited thereto.

[0147] Reference Figure 11C The second hole H2 can be extended in a direction parallel to the upper surface of the substrate 101 to form a second extended hole EH2.

[0148] By removing a portion of the second expansion via EH2, the second expansion via EH2 can be formed to expose the upper and lower surfaces of the initial string select gate layer 150'. The second expansion via EH2 can be formed using, for example, a wet etching process. A wet etching process can be used to selectively remove portions of the upper insulating layer 170U and the lower insulating layer 170L relative to the initial string select gate layer 150'.

[0149] Reference Figure 11D A third insulating pattern 170c can be formed to cover the inner wall of the second expansion hole EH2.

[0150] The third insulating pattern 170c can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The third insulating pattern 170c can be formed to cover the upper and side surfaces of the upper insulating layer 170U and the side surface of the lower insulating layer 170L. The third insulating pattern 170c can cover the upper, lower, and side surfaces of the preliminary string select gate layer 150' exposed by the second expansion hole EH2. The third insulating pattern 170c can be formed to have a uniform thickness along the shape of the inner sidewall of the second expansion hole EH2. The third insulating pattern 170c can include the same material as the upper insulating layer 170U and the lower insulating layer 170L. For example, the third insulating pattern 170c can include an insulating material such as silicon oxide or silicon nitride.

[0151] Reference Figure 11E and Figure 11F Spacers 175 can be formed to cover the third insulating pattern 170c, and the lower part of spacers 175 can be removed to expose the lower part of the third insulating pattern 170c.

[0152] References above Figure 10H and Figure 10I The same description given can be applied to the processes of forming spacer 175 and removing a portion of spacer 175.

[0153] Reference Figure 11G While the lower part of the third insulating pattern 170c is recessed to form the fourth insulating pattern 170d, the lower part of the second expansion hole EH2 can be extended in a direction parallel to the surface of the substrate 101 to form the expansion junction region EJ.

[0154] The lower part of the third insulating pattern 170c can be recessed using an etch-back process to form the fourth insulating pattern 170d. The fourth insulating pattern 170d can be formed by removing the portion of the third insulating pattern 170c. Figure 11F It is formed by the exposed lower part and the area adjacent to it.

[0155] The extended junction region EJ can be formed using, for example, a wet etching process. A wet etching process can be used to selectively remove a portion of the lower insulating layer 170L and the upper portion of the channel insulating layer 146 relative to the channel layer 140 and the spacer 175. The extended junction region EJ can be formed by removing a portion of the lower insulating layer 170L in a direction parallel to the upper surface of the substrate 101 while simultaneously recessing the upper portion of the channel insulating layer 146. The extended junction region EJ can be formed such that the inner sidewalls of the channel layer 140 are exposed while simultaneously recessing the upper portion of the channel insulating layer 146. In this operation, as referenced above... Figure 10I The initial string selection gate layer 150' and the fourth insulating pattern 170d can be protected by spacer 175.

[0156] In other embodiments, during the etch-back or wet etching process, the extended junction region EJ may further extend in a direction parallel to the upper surface of the substrate 101 to expose the upper surface of the channel layer 140. Further processes, described later, may be performed such that the string-selective channel layer 160 is formed to cover the upper surface of the channel layer 140. As a result, a composite material can be fabricated... Figure 6A , Figure 6B and Figure 6C The example implementation corresponds to the semiconductor device.

[0157] Reference Figure 11H It can remove spacer 175 and form a preliminary string selection channel layer 160y to cover the fourth insulating pattern 170d and the inner sidewall of the extended junction region EJ.

[0158] The initial string selective channel layer 160y can be formed with a substantially uniform thickness along the sidewalls of the fourth insulating pattern 170d and the inner sidewalls of the extended junction region EJ. The initial string selective channel layer 160y can be formed with respect to the channel layer 140. Figure 11GThe upper direct contacts are exposed during the wet etching process. The initial string selection channel layer 160y may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be an undoped material or a material including P-type and / or N-type impurities.

[0159] Reference Figure 11I A string selection insulating layer 166 can be formed to fill the second expansion hole EH2 and the expansion junction region EJ, and a string selection channel pad 168 can be formed on the string selection insulating layer 166.

[0160] References above Figure 10K The same description can be applied to the process of forming the string select insulating layer 166 and the string select channel pad 168. In this operation, a portion of the upper part of the initial string select channel layer 160y can be removed to form the string select channel layer 160. Therefore, a string select channel structure SCH including the string select channel layer 160, the string select insulating layer 166, and the string select channel pad 168 can be formed, as shown below. Figure 5B As shown.

[0161] Refer to together Figure 11J and Figure 5A The opening OP can be formed to be separated by a predetermined interval and extend through the stacked structure, and the horizontal sacrificial layer 110 exposed through the opening OP can be removed to form a lateral opening LT. The lateral opening LT can be filled with a conductive material to form a gate layer 130, a separating insulating layer and a source conductive layer can be formed in the opening OP, and pillars 180 can be formed to extend through the upper insulating layer 170U and connect to the string select channel pad 168.

[0162] References above Figure 10L The same description can be applied to the process of forming the open-circuit (OP), lateral open-circuit (LT), gate layer 130, spacer insulating layer, source conductive layer, and pillars 180. As a result, it is possible to manufacture... Figure 5A Semiconductor device 100b.

[0163] Figure 12A and Figure 12B This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment, as another example. Figure 12A and Figure 12B It shows the relationship with Figure 7 The corresponding cross section.

[0164] Reference Figure 12A A first source sacrificial layer 111 and a second source sacrificial layer 112 can be formed on the substrate 101, and the horizontal sacrificial layer 110 and the interlayer dielectric layer 120 can be stacked alternately to form a stacked structure.

[0165] The first source sacrificial layer 111 and the second source sacrificial layer 112 may comprise different materials and may be stacked on the substrate 101, such that the first source sacrificial layer 111 is disposed above and below the second source sacrificial layer 112. The first source sacrificial layer 111 and the second source sacrificial layer 112 may be fabricated using subsequent processes. Figure 7 The first conductive layer 104 and the second conductive layer 105 are replaced. For example, the first source sacrificial layer 111 may be formed of the same material as the interlayer dielectric layer 120, and the second source sacrificial layer 112 may be formed of the same material as the horizontal sacrificial layer 110.

[0166] Similar to the above references Figure 10A The given description indicates that a horizontal sacrificial layer 110, an interlayer dielectric layer 120, and a preliminary insulating layer 170' can be formed on the second source sacrificial layer 112.

[0167] Reference Figure 12B It can be executed and referenced. Figures 10B to 10K The same process is used to form the channel structure CH, the initial string-select gate layer 150', and the string-select channel structure SCH. In this embodiment, the channel layer 140 and the gate dielectric layer 145 may be formed on the lower end of the channel via CHH to extend into the interior of the substrate 101.

[0168] like Figure 12B As shown, an opening OP can be formed to penetrate the stacked structure of the horizontal sacrificial layer 110, the first source sacrificial layer 111, the second source sacrificial layer 112, and the interlayer dielectric layer 120. After removing the first source sacrificial layer 111 and the second source sacrificial layer 112 through the opening OP, a first conductive layer 104 and a second conductive layer 105 can be formed.

[0169] In an example implementation, a spacer layer may be formed on the sidewall of the opening OP to protect the horizontal sacrificial layer 110 before removing the first source sacrificial layer 111 and the second source sacrificial layer 112. After removing the second source sacrificial layer 112 through the opening OP, the first source sacrificial layer 111 may be removed. The first source sacrificial layer 111 and the second source sacrificial layer 112 may be removed, for example, by a wet etching process. In the process of removing the first source sacrificial layer 111, a portion of the gate dielectric layer 145, which is exposed in the region where the second source sacrificial layer 112 has been removed, may also be removed. After forming the first conductive layer 104 and the second conductive layer 105 by depositing conductive material in the region where the first source sacrificial layer 111 and the second source sacrificial layer 112 have been removed, the spacer layer may be removed. The first conductive layer 104 may be in direct contact with the channel layer 140 in the region where the gate dielectric layer 145 has been removed.

[0170] For reference Figure 10LThe horizontal sacrificial layer 110 can be removed via the opening OP, and can be performed in accordance with the reference. Figure 4A The same process is used to manufacture Figure 7 100F semiconductor device.

[0171] As described above, the string select channel layer can include multiple regions with different widths from each other. Therefore, the electrical connection characteristics of the string select channel pads and the interconnects can be improved.

[0172] Furthermore, the string-select channel layer can directly contact the channel layer to improve the interconnect characteristics of the transistor. Therefore, semiconductor devices with increased integration density and improved electrical characteristics can be provided.

[0173] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

[0174] This application claims priority to Korean Patent Application No. 10-2019-0145092, filed on November 13, 2019, with the Korean Intellectual Property Office, the subject of which is incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Alternating arrangement of gate layers and interlayer dielectric layers stacked on a substrate; The channel structure extends vertically through the alternating arrangement of the gate layer and the interlayer dielectric layer; A string selection gate layer is disposed on the channel structure; and A string-select channel layer extends vertically through the string-select gate layer to contact the channel structure. The string select channel layer includes a first portion below the string select gate layer, a second portion extending through the string select gate layer, and a third portion above the string select gate layer. At least one of the first portion and the third portion includes a protruding region, and the lower surface of the first portion of the string selection channel layer is disposed below the upper surface of the channel structure.

2. The semiconductor device of claim 1, wherein the first portion includes a first protruding region having a first width, the first width being greater than a second width of the first portion contacting the upper portion of the second portion and a third width of the first portion contacting the lower portion of the channel structure.

3. The semiconductor device of claim 2, wherein the third portion includes a second protruding region having a fourth width, the fourth width being greater than a fifth width of the third portion that contacts the lower portion of the second portion.

4. The semiconductor device according to claim 3, further comprising: A string selection channel pad is seated between the inner side surfaces of the third portion of the string selection channel layer and is disposed in the second protruding region.

5. The semiconductor device of claim 1, wherein the second portion of the string select channel layer extends through a via formed through the string select gate layer, and the second portion has a width smaller than the width of the via.

6. The semiconductor device according to claim 5, further comprising: A string select gate insulating layer surrounds the second portion of the string select channel layer in the via.

7. The semiconductor device of claim 4, wherein the string select channel pad includes a portion extending downward from the second protruding region.

8. The semiconductor device of claim 1, wherein the first portion includes a base protrusion region, the base protrusion region including a lower base portion disposed between the inner side surfaces of the channel structure and an upper base portion disposed on the lower base portion.

9. The semiconductor device of claim 8, wherein the lower base portion has a first region width and the upper base portion has a second region width, the second region width being smaller than the first region width and larger than the width of the first portion of the string select channel layer that contacts the second portion of the string select channel layer.

10. The semiconductor device of claim 1, wherein the first portion includes a plug protrusion region, the plug protrusion region comprising: The lower part is located between the inner side surfaces of the channel structure; The middle portion is disposed on the lower portion and overlaps with the upper surface of the channel structure; as well as The upper part is located on the middle part.

11. The semiconductor device of claim 10, wherein the lower portion has a first region width, the middle portion has a second region width greater than the first region width, and the upper portion has a third region width, the third region width being less than the second region width and greater than the width of the first portion of the string select channel layer contacting the second portion of the string select channel layer.

12. The semiconductor device of claim 11, wherein the channel structure includes a channel layer, and the lower surface of the middle portion of the plug protrusion region contacts the upper surface of the channel layer.

13. The semiconductor device according to claim 1, further comprising: The peripheral circuit region is disposed below the substrate and includes a base substrate and circuit elements disposed on the base substrate.

14. A semiconductor device, comprising: Gate layer, stacked on the substrate; A channel layer that extends through the gate layer; A string-select gate layer is disposed on the channel layer; as well as A string-select channel layer extends through the string-select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer and containing a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer and containing a second protruding region, wherein the lower surface of the first portion of the string select channel layer is disposed below the upper surface of the channel layer.

15. The semiconductor device of claim 14, wherein the first protruding region has a first width, the first width being greater than a second width of the first portion contacting the upper portion of the second portion and a third width of the first portion contacting the lower portion of the channel layer.

16. The semiconductor device of claim 15, wherein the second protruding region has a fourth width, the fourth width being greater than a fifth width of the third portion that contacts the lower portion of the second portion.

17. A semiconductor device, comprising: Gate layer, stacked on the substrate; A channel structure, comprising a channel pad and a channel layer and extending through the gate layer; as well as A string select gate layer is disposed on the channel structure and includes a string select channel layer, the string select channel layer extending through the string select gate layer to contact the channel pad. The string select channel layer includes a first portion below the string select gate layer and containing a first protruding region having a first width, a second portion extending through the string select gate layer, and a third portion above the string select gate layer and containing a second protruding region having a second width greater than the first width.

18. The semiconductor device of claim 17, wherein the first protruding region is one of the base protruding region and the plug protruding region.

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