Semiconductor device and semiconductor system

Abstract

The present application relates to a semiconductor device and a semiconductor system. The present application provides a semiconductor device which is particularly useful for a power device and has excellent semiconductor characteristics. The semiconductor device includes: a crystalline oxide semiconductor layer; and at least one electrode electrically connected to the crystalline oxide semiconductor layer, at least one trench having a bottom surface, a side surface, and at least one circular-arc portion between the bottom surface and the side surface, the circular-arc portion having a radius of curvature in a range from 100 nm to 500 nm, and an angle formed by the side surface and a first surface of the crystalline oxide semiconductor layer being 90° or more.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device useful as a power device or the like, and a semiconductor system provided with the semiconductor device. BACKGROUND

[0002] Gallium oxide is attracting attention as a new-generation semiconductor material. Gallium oxide is expected as a material that has a large band gap and enables a high-voltage and high-current semiconductor device, and various studies are being made to increase the reverse withstand voltage and further reduce the forward rise voltage, and the like.

[0003] In recent years, semiconductor devices having a trench are being studied. As a trench-type semiconductor device of β-Ga2O3, for example, the semiconductor devices described in Patent Documents 1 to 3 are disclosed. In addition, as a trench-type semiconductor device of α-Ga2O3, for example, the semiconductor devices described in Patent Documents 4 and 5 are disclosed.

[0004] However, in the case where a crystalline oxide semiconductor such as gallium oxide is formed with a trench, since it has etching characteristics different from other semiconductor materials, it is difficult to form a circular arc portion having a curvature radius of 100 nm or more, which can be expected to relax the electric field, on the trench bottom surface. For example, when crystalline gallium oxide is forcibly etched under the existing dry etching conditions, since a concave-convex is formed on the trench bottom surface or the width of the inside of the trench is wider than the width of the opening portion of the trench, the electric field relaxation effect cannot be sufficiently exerted, and there are problems such as an increase in on-resistance, and the like.

[0005] Patent Document 1: Japanese Patent Publication No. 2019-036593

[0006] Patent Document 2: Japanese Patent Publication No. 2019-079984

[0007] Patent Document 3: Japanese Patent Publication No. 2019-153645

[0008] Patent Document 4: WO2016 / 013554

[0009] Patent Document 5: WO2019 / 013136 SUMMARY

[0010] An object of the present application is to provide a semiconductor device having a trench having excellent semiconductor characteristics.

[0011] To achieve the above-mentioned objectives, the inventors conducted in-depth research and discovered that by forming trenches in a crystalline oxide semiconductor layer using specific high-pressure dry etching, a semiconductor device was successfully created that includes: a crystalline oxide semiconductor layer; and at least one electrode electrically connected to the crystalline oxide semiconductor layer. The first surface of the crystalline oxide semiconductor layer has at least one trench, the trench including a bottom surface, a side surface, and at least one arcuate portion between the bottom surface and the side surface. The radius of curvature of the arcuate portion is in the range of 100 nm to 500 nm, and the angle between the side surface and the first surface of the crystalline oxide semiconductor layer is 90° or more. Furthermore, this semiconductor device can simultaneously solve the aforementioned existing problems.

[0012] Furthermore, after obtaining the above insights, the inventors conducted further repeated research and completed this invention.

[0013] [1] A semiconductor device includes: a crystalline oxide semiconductor layer; and at least one electrode electrically connected to the crystalline oxide semiconductor layer, wherein a first surface of the crystalline oxide semiconductor layer has at least one trench, the trench including a bottom surface, a side surface and at least one arcuate portion between the bottom surface and the side surface, the radius of curvature of the arcuate portion being in the range of 100 nm to 500 nm, and the angle between the side surface and the first surface of the crystalline oxide semiconductor layer being 90° or more.

[0014] [2] In the semiconductor device according to [1] above, the angle between the side surface and the first surface of the crystalline oxide semiconductor layer is 150° or less.

[0015] [3] In the semiconductor device according to [1] or [2] above, the width of the trench narrows toward the bottom surface of the trench.

[0016] [4] The semiconductor device according to any one of [1] to [3] above, wherein the side of the trench is inclined.

[0017] [5] In the semiconductor device according to [4] above, the angle between the side surface and the first surface of the crystalline oxide semiconductor layer is in the range of greater than 90° and less than 135°.

[0018] [6] The semiconductor device according to any one of [1] to [5] above, wherein the crystalline oxide semiconductor layer comprises at least gallium.

[0019] [7] The semiconductor device according to any one of [1] to [6] above, wherein the crystalline oxide semiconductor layer has a corundum structure.

[0020] [8] The semiconductor device according to any one of [1] to [7] above, wherein the crystalline oxide semiconductor layer comprises two or more of the trenches.

[0021] [9] The semiconductor device according to any one of [1] to [8] above, wherein the width of the trench is 2 μm or less.

[0022]

[10] In the semiconductor device according to [9] above, the crystalline oxide semiconductor layer includes four or more of the trenches.

[0023]

[11] The semiconductor device according to any one of [1] to

[10] above, wherein the semiconductor device is a power device.

[0024]

[12] The semiconductor device according to any one of [1] to

[11] above, wherein the semiconductor device is a vertical device.

[0025]

[13] The semiconductor device according to any one of [1] to

[12] above, wherein the semiconductor device is a diode.

[0026]

[14] The semiconductor device according to any one of [1] to

[12] above, wherein the semiconductor device is a transistor.

[0027]

[15] The semiconductor device according to any one of [1] to

[12] above, wherein the semiconductor device is a junction barrier Schottky diode.

[0028]

[16] A semiconductor system comprising a semiconductor device, wherein the semiconductor device is any one of the semiconductor devices described in [1] to

[15] above.

[0029] The semiconductor device of the present invention has at least one arcuate portion between the bottom surface and the side surface of the trench, wherein the radius of curvature of the arcuate portion is in the range of 100nm to 500nm, thereby exhibiting excellent semiconductor characteristics. Attached Figure Description

[0030] Figure 1 This is a schematic diagram illustrating one embodiment of a junction barrier Schottky diode (JBS) as an example of the semiconductor device of the present invention.

[0031] Figure 2 This is a diagram illustrating the radius of curvature of the arc portion in an embodiment of the present invention.

[0032] Figure 3 This is a diagram that schematically represents an example of a power supply system.

[0033] Figure 4This is a diagram that schematically represents an example of a system device.

[0034] Figure 5 This is a schematic diagram illustrating an example of a power supply circuit diagram for a power supply device.

[0035] Figure 6 This is a general structural diagram of the film-forming apparatus (atomized CVD (chemical vapor deposition) apparatus) used in the embodiments of the present invention.

[0036] Figure 7 This is a cross-sectional photograph showing the trench of Example 1.

[0037] Figure 8 This is a cross-sectional photograph showing the trench in Example 2.

[0038] Figure 9 This is a schematic diagram illustrating one embodiment of a Schottky barrier diode (SBD) as an example of the semiconductor device of the present invention.

[0039] Figure 10 This is a schematic diagram illustrating one embodiment of a trench MOS-type Schottky barrier diode (SBD) as an example of the semiconductor device of the present invention.

[0040] Figure 11 This is a schematic diagram illustrating one embodiment of a junction barrier Schottky diode (JBS) as an example of the semiconductor device of the present invention.

[0041] Figure 12 This is a diagram schematically illustrating a MOSFET as an example of an embodiment of the semiconductor device of the present invention.

[0042] Figure 13 This is a diagram schematically illustrating a MOSFET as an example of an embodiment of the semiconductor device of the present invention.

[0043] Figure 14 This is a diagram illustrating the angle formed by the side surface of the trench and the first surface of the crystalline oxide semiconductor layer in an embodiment of the present invention.

[0044] Figure 15 This is a diagram illustrating the tilt angle when the side of the groove in an embodiment of the present invention is tilted.

[0045] Figure 16-a This is a cross-sectional photograph showing the trench of Example 3.

[0046] Figure 16-b This is an explanatory diagram showing the structure of the trench in Example 3. Detailed Implementation

[0047] The semiconductor device in the embodiments of the present invention is characterized in that it includes: a crystalline oxide semiconductor layer; and at least one electrode electrically connected to the crystalline oxide semiconductor layer, wherein a first surface of the crystalline oxide semiconductor layer has at least one trench, the trench including a bottom surface, a side surface and at least one arcuate portion between the bottom surface and the side surface, the radius of curvature of the arcuate portion being in the range of 100 nm to 500 nm, and the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer being 90° or more.

[0048] "Radius of curvature" refers to the radius of the contact circle of the curve relative to the arc portion in the groove cross-section. The "arc portion" is not only a part of a perfect circle but also includes a part of an ellipse; the entire arc portion can be circularly curved, for example, it can be a part of a shape such as a rounded corner of a polygon. That is, the arc portion in the groove cross-section can be a curved portion, as long as it is located at least a portion between the side surface and the bottom surface. For example, an example of an arc portion is shown in... Figure 2 . Figure 2 The described crystalline oxide semiconductor has an arcuate portion 7c having two radii of curvature. Figure 2 In this embodiment, the radii of curvature of R1 and R2 are both in the range of 100 nm to 500 nm. In this embodiment of the invention, by setting the radii of curvature within this range, excellent electric field mitigation effects can be achieved, resulting in a reduction in on-resistance. Furthermore, in this embodiment of the invention, the trench may also have an arcuate portion throughout the entire portion between the bottom surface 7b and the side surface 7a. Additionally, in this embodiment of the invention, it is preferable that the difference between the radius of curvature R1 of the first arcuate portion 7ca located between the bottom surface 7b and the first side surface 7aa of the trench 7 and the radius of curvature R2 of the second arcuate portion 7cb located between the bottom surface 7b and the second side surface 7ab of the trench 7 is in the range of 0 to 200 nm, more preferably in the range of 0 to 50 nm. In this embodiment of the invention, it is most preferable that the radius of curvature R1 of the first arcuate portion 7ca and the radius of curvature R2 of the second arcuate portion 7cb are equal.

[0049] "The angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer" refers to the angle formed by the side surface 7a of the trench located on the first surface 3a side of the crystalline oxide semiconductor layer 3 and the first surface 3a of the crystalline oxide semiconductor layer 3 in the cross-section of the trench 7. In embodiments of the present invention, it is typically about 90° or more. Examples of such "angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer" include... Figure 14 and Figure 16-bThe angles θ (θ1, θ2) represent the angles. In this invention, by having the angle θ1 formed by the first side surface 7aa of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer 3, and the angle θ2 formed by the second side surface 7ab of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer 3, an excellent electric field mitigation effect can be achieved, resulting in a reduction in on-resistance. Furthermore, the upper limit of the angle between the side surface and the first surface of the crystalline oxide semiconductor layer is not limited as long as it does not hinder the purpose of this invention, and is preferably 150°. In addition, in embodiments of this invention, it is preferable that, in the cross-section of the trench, the angle (θ1) formed by the first side surface 7aa of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer is equal to the angle (θ2) formed by the second side surface 7ab of the trench and the first surface 3a of the crystalline oxide semiconductor layer.

[0050] The trenches are formed on the crystalline oxide semiconductor layer and are not particularly limited as long as they do not hinder the purpose of the present invention. The depth of the trenches is also not particularly limited, but in the present invention, the depth of the trenches in the trench cross-section is generally 200 nm or more, preferably 500 nm or more, and more preferably 1 μm or more. Furthermore, the upper limit of the trench depth is not particularly limited, but is preferably 100 μm, and more preferably 10 μm. Additionally, the width of the trenches in the trench cross-section is not particularly limited, but is generally 200 nm or more, and preferably 500 nm or more. Furthermore, the upper limit of the trench width is not particularly limited, but is preferably 100 μm, and more preferably 10 μm. Trenches within this preferred range can exhibit superior semiconductor characteristics as semiconductor devices such as power devices. Furthermore, in the trench cross-section, as an embodiment of the present invention, a trench cross-section in which the width of the trench narrows towards the bottom surface is listed as a suitable example. According to this suitable example, a good interface can be formed, and better electrical characteristics can be obtained, and therefore it is preferred. Furthermore, it is preferable that the side surface of the trench is inclined, and the side surface has an inclination angle relative to the first surface of the crystalline oxide semiconductor layer. Moreover, the inclination angle refers to the angle formed between the imaginary surface and the side surface of the trench (which is inclined) when the first surface of the crystalline oxide semiconductor layer and an imaginary surface perpendicular to the first surface (with an inclination angle of 0° due to the absence of inclination) are defined in the trench cross-section. Examples of such inclination angles include... Figure 15 The angle is represented by θ (θ3, θ4). In this invention, the tilt angle is preferably in the range of greater than 0° and less than 45°. That is, the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer is preferably (e.g., by...). Figure 14 and Figure 16-bThe angles θ1 and θ2 shown are in the range of greater than 90° and less than 135°. Due to this preferred tilt angle, a better channel can be formed, which in turn can further reduce the on-resistance.

[0051] Furthermore, the electrode can be a known electrode, such as a Schottky electrode, an ohmic electrode, a gate electrode, a drain electrode, or a source electrode. The electrode can be a known electrode appropriately chosen according to the type of semiconductor device, and the electrode material can be, for example, bulk metal. Alternatively, the electrode can be an electrode called a barrier electrode. The barrier electrode is not particularly limited as long as it forms a Schottky barrier with a predetermined barrier height at the interface of the semiconductor field. The electrode material of the barrier electrode is not particularly limited as long as it is a material suitable for use as a barrier electrode; it can be a conductive inorganic material or a conductive organic material. In this invention, the electrode material is preferably a metal. The metal is not particularly limited, but at least one metal selected from Groups 4 to 11 of the periodic table is suitable, for example. Examples of Group 4 metals include titanium (Ti), zirconium (Zr), and hafnium (Hf), with Ti being preferred. Examples of metals belonging to Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals belonging to Group 6 of the periodic table include one or more metals selected from chromium (Cr), molybdenum (Mo), and tungsten (W), but in this invention, Cr is preferred because it exhibits better semiconductor properties, such as switching characteristics. Examples of metals belonging to Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals belonging to Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals belonging to Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals belonging to Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt), with Pt being preferred. Examples of metals belonging to Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). Methods for forming the barrier electrode include known methods, and more specifically, dry or wet methods. Dry methods include known methods such as sputtering, vacuum evaporation, and CVD. Wet methods include screen printing or die coating.

[0052] Regarding the crystalline oxide semiconductor layer, it is not particularly limited as long as a semiconductor region is formed in the semiconductor device. The crystalline oxide semiconductor layer (hereinafter referred to as the "semiconductor region") is not particularly limited as long as it is primarily composed of semiconductors. In this invention, it is preferable that the semiconductor region contains a crystalline oxide semiconductor as its primary component, more preferably an n-type semiconductor region containing an n-type semiconductor as its primary component. The crystalline oxide semiconductor preferably has a β-gallia structure or a corundum structure, more preferably a corundum structure. Furthermore, the semiconductor region preferably contains at least gallium, more preferably a gallium compound as its primary component, further preferably an InAlGaO-type semiconductor as its primary component, and most preferably α-Ga₂O₃ or a mixture thereof as its primary component. In addition, in the case where the crystalline oxide semiconductor is, for example, α-Ga₂O₃, "primary component" means that α-Ga₂O₃ is contained at a ratio of 0.5 or more of gallium atoms in the metal elements of the semiconductor region. In this invention, it is preferable that the ratio of gallium atoms in the metal elements of the semiconductor region is 0.7 or more, more preferably 0.8 or more. Furthermore, the semiconductor region is typically a single-phase region, but it may further include a second semiconductor region composed of different semiconductor phases or other equivalent phases, provided that this does not hinder the purpose of the invention. Additionally, the semiconductor region is typically in the form of a film, which may be a semiconductor film. The thickness of the semiconductor film in the semiconductor region is not particularly limited; it may be less than 1 μm or more than 1 μm, but in the present invention, it is preferably 1 μm to 40 μm, more preferably 1 μm to 25 μm. The crystalline oxide semiconductor layer can improve its withstand voltage, for example, by making it a thick film or reducing the carrier concentration. On the other hand, there is a trade-off problem, such as the on-resistance increasing due to increased thickness or reduced carrier concentration. According to an embodiment of the invention, since the gallium oxide-based crystalline oxide semiconductor layer containing α-Ga₂O₃ or β-Ga₂O₃ has trenches containing arcuate portions with a radius of curvature in the range of 100 nm to 500 nm, and the angle between the side of the trench and the first surface of the crystalline oxide semiconductor layer is in the range of greater than 90° and less than 135°, a sufficient electric field mitigation effect can be obtained. According to embodiments of the present invention, since the electric field mitigation effect can be sufficiently obtained as described above, the thickness of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be reduced (e.g., 10 μm or less), and even with this thickness, a semiconductor device with high withstand voltage (e.g., 3000 V or more) can be realized. Furthermore, according to embodiments of the present invention, the thickness of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be further reduced (e.g., 2.0 μm or less), and even with this thickness, a semiconductor device with high withstand voltage (e.g., 600 V or more) can be realized.Furthermore, in embodiments of the present invention, the carrier concentration of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be set to 5.0 × 10⁻⁶. 16 / cm 3 The preferred setting is 3.0 × 10. 17 / cm 3 The above describes the process. While the thickness of the crystalline oxide layer or the carrier concentration can be adjusted appropriately according to the required withstand voltage, in embodiments of the present invention, as described above, high withstand voltage can be achieved even with a thinner thickness or a higher carrier concentration than before, thus reducing on-resistance. Furthermore, the surface area of ​​the semiconductor film is not particularly limited and can be as small as 1 mm. 2 The above can also be 1mm. 2 The crystalline oxide semiconductor is typically monocrystalline, but can also be polycrystalline. Furthermore, the semiconductor film can be a single-layer film or a multilayer film. When the semiconductor film is a multilayer film, it is preferable that the thickness of the multilayer film is 40 μm or less. Additionally, when the semiconductor film is a multilayer film comprising at least a first semiconductor layer and a second semiconductor layer, and a Schottky electrode is provided on the first semiconductor layer, it is preferable that the carrier concentration of the first semiconductor layer is less than the carrier concentration of the second semiconductor layer. Furthermore, in this case, the second semiconductor layer typically contains dopant, and the carrier concentration of the semiconductor layer (including the first and second semiconductor layers) can be appropriately set by adjusting the doping amount.

[0053] The semiconductor film preferably contains a dopant. The dopant is not particularly limited and can be any known dopant. Examples of dopants include n-type or p-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. In this invention, the dopant is preferably Sn, Ge, or Si. The dopant content in the composition of the semiconductor film is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic%, and most preferably 0.00001 atomic% to 10 atomic%. Furthermore, in this invention, the dopant used in the first semiconductor layer is germanium, silicon, titanium, zirconium, vanadium, or niobium, and the dopant used in the second semiconductor layer is tin, which is preferred because it further enhances the semiconductor properties without compromising adhesion.

[0054] For example, the semiconductor film is formed using methods such as atomization CVD. More specifically, for example, the raw material solution is atomized to generate atomized droplets (atomization process), the atomized droplets (containing mist) are transported to the substrate using a carrier gas (transportation process), and then the atomized droplets are thermally reacted in a film-forming chamber to deposit a semiconductor film containing crystalline oxide semiconductor as the main component on the substrate (film-forming process), thereby appropriately forming a semiconductor film.

[0055] (Atomization process)

[0056] Regarding the atomization process, atomized droplets are generated by atomizing the raw material solution and suspending the atomized droplets. The atomization method for the raw material solution is not particularly limited as long as it can atomize the solution; any known method can be used. However, in this invention, an ultrasonic atomization method is preferred. The atomized droplets obtained using ultrasound have an initial velocity of zero and are suspended in the air. Therefore, this is preferable because, unlike spraying, the atomized droplets are not blown out but suspended in space and can be transported as gas, thus avoiding damage due to collision energy. The droplet size is not particularly limited and can be a few millimeters in size, preferably less than 50 μm, and more preferably 100 nm to 10 μm.

[0057] (Raw material solution)

[0058] The raw material solution can be atomized and is not particularly limited as long as it contains raw materials that can form semiconductor regions. It can be inorganic or organic materials. However, in this invention, it is preferred that the raw material is a metal or metal compound, and more preferably it contains one or more metals selected from gallium, iron, indium, aluminum, vanadium, titanium, chromium, rhodium, nickel, cobalt, zinc, magnesium, calcium, silicon, yttrium, strontium and barium.

[0059] In this invention, the raw material solution may be a solution prepared by dissolving or dispersing the metal in an organic solvent or water in the form of a complex or salt. Examples of complex forms include acetylacetone complexes, carbonyl complexes, amine complexes, and hydride complexes. Examples of salt forms include organometallic salts (e.g., metal acetate, metal oxalate, metal citrate), metal sulfide salts, metal nitrate salts, metal phosphates, and metal halide salts (e.g., metal chloride, metal bromide, metal iodide).

[0060] Furthermore, it is preferable to mix additives such as hydrohalates and oxidants into the raw material solution. Examples of hydrohalates include hydrobromic acid, hydrochloric acid, and hydroiodic acid, but hydrobromic acid or hydroiodic acid is preferred for the purpose of obtaining a higher quality membrane. Examples of oxidants include peroxides such as hydrogen peroxide (H₂O₂), sodium peroxide (Na₂O₂), barium peroxide (BaO₂), or benzoyl peroxide (C₆H₅CO)₂O₂, as well as organic peroxides such as hypochlorite (HClO), perchloric acid, nitric acid, ozone water, peracetic acid, and nitrobenzene.

[0061] The raw material solution may also contain dopants. Since the raw material solution contains dopants, doping can be performed effectively. The dopants are not particularly limited as long as they do not hinder the purpose of the invention. Examples of such dopants include n-type or p-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. The concentration of the dopants is typically about 1 × 10⁻⁶. 16 / cm 3 ~1×10 22 / cm 3 Furthermore, the concentration of the dopant can be set, for example, to approximately 1 × 10⁻⁶. 17 / cm 3 The following low concentrations. Furthermore, according to further embodiments of the present invention, approximately 1 × 10⁻⁶ can also be used. 20 / cm 3 The above high concentrations contain dopants. In embodiments of the present invention, a concentration of 1×10⁻⁶ is preferred. 17 / cm 3 The above carrier concentrations contain dopants. Furthermore, as an embodiment of the present invention, it is possible to set the carrier concentration of a gallium oxide-based crystalline oxide semiconductor layer to 1 × 10⁻⁶ in a semiconductor device with a withstand voltage of 600V. 17 / cm 3 Above and 3×10 17 / cm 3 the following.

[0062] The solvent in the raw material solution is not particularly limited; it can be an inorganic solvent such as water, an organic solvent such as ethanol, or a mixture of inorganic and organic solvents. In this invention, it is preferred that the solvent contains water, and more preferably water or a mixture of water and ethanol.

[0063] (Transportation process)

[0064] In the transport process, the atomized droplets are transported into the film-forming chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not hinder the purpose of the invention; suitable examples include inert gases such as oxygen, ozone, nitrogen, or argon, or reducing gases such as hydrogen and synthesis gases. Furthermore, the carrier gas can be one type or two or more types, and a dilution gas with a reduced flow rate (e.g., a 10-fold dilution gas) can be further used as a second carrier gas. Additionally, the carrier gas can be supplied from more than one location, or from two or more locations. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, more preferably 1 to 10 L / min. In the case of a dilution gas, a flow rate of 0.001 to 2 L / min is preferred, more preferably 0.1 to 1 L / min.

[0065] (Film forming process)

[0066] In the film-forming process, the semiconductor film is formed on the substrate by subjecting the atomized droplets to a thermal reaction in a film-forming chamber. Regarding the thermal reaction, any reaction of the atomized droplets using heat is acceptable, and the reaction conditions are not particularly limited as long as they do not hinder the purpose of this invention. In this process, the thermal reaction is typically carried out at a temperature above the solvent's evaporation temperature, but preferably at a temperature below a certain level (e.g., 1000°C), more preferably below 650°C, and most preferably between 300°C and 650°C. Furthermore, the thermal reaction can be carried out under any of the following atmospheres—vacuum, oxygen-free atmosphere, reducing gas atmosphere, and oxygen atmosphere—as long as it does not hinder the purpose of this invention, but it is preferred to carry out the thermal reaction under an oxygen-free atmosphere or an oxygen atmosphere. Additionally, the thermal reaction can be carried out under any of the following conditions—atmospheric pressure, pressurized atmosphere, and depressurized atmosphere—but in this invention, it is preferred to carry out the thermal reaction under atmospheric pressure. Furthermore, the film thickness can be set by adjusting the film-forming time.

[0067] (Matrix)

[0068] The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is also not particularly limited as long as it does not hinder the purpose of the invention; it can be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate can be any shape, and all shapes are applicable. Examples include plate-shaped (such as flat plates or discs), fibrous, rod-shaped, cylindrical, square prism-shaped, tubular, spiral, spherical, and annular shapes, but a substrate is preferred in embodiments of the invention. The thickness of the substrate is not particularly limited in the invention.

[0069] The substrate is plate-shaped and is not particularly limited as long as it serves as a support for the semiconductor film. The substrate can be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate, but it is preferred to be an insulating substrate, and more preferably a substrate with a metal film on its surface. Examples of such substrates include a substrate containing a substrate material having a corundum structure as its main component, a substrate containing a substrate material having a β-gallia structure as its main component, or a substrate containing a substrate material having a hexagonal crystal structure as its main component. Here, "main component" refers to a substrate material having the aforementioned specific crystal structure, preferably comprising 50% or more, more preferably 70% or more, and even more preferably 90% or more, in atomic ratio relative to all components of the substrate material; it can also be 100%.

[0070] The substrate material is not particularly limited as long as it does not hinder the purpose of this invention, and can be any known substrate material. Examples of suitable substrate materials having the corundum structure include α-Al₂O₃ (sapphire substrate) or α-Ga₂O₃. More suitable examples include a-plane sapphire substrates, m-plane sapphire substrates, r-plane sapphire substrates, c-plane sapphire substrates, or α-type gallium oxide substrates (a-plane, m-plane, or r-plane). Examples of substrates whose main component is a substrate material having a β-gallium structure include β-Ga₂O₃ substrates, or mixed crystal substrates containing Ga₂O₃ and Al₂O₃, where Al₂O₃ is greater than 0% by weight and less than 60% by weight. Furthermore, examples of substrates whose main component is a substrate material having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates.

[0071] In this invention, annealing can also be performed after the film-forming process. The annealing temperature is not particularly limited as long as it does not hinder the purpose of this invention, and is typically 300°C to 650°C, preferably 350°C to 550°C. Furthermore, the annealing time is typically 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. Moreover, annealing can be performed in any atmosphere as long as it does not hinder the purpose of this invention, preferably in an oxygen-free atmosphere, and more preferably in a nitrogen atmosphere.

[0072] Alternatively, in embodiments of the present invention, the semiconductor film can be directly deposited on the substrate, or it can be deposited via other layers such as a buffer layer or a stress relaxation layer. The method for forming each layer is not particularly limited and can be a known method; however, in embodiments of the present invention, atomization CVD is preferred.

[0073] Furthermore, as an embodiment of the present invention, it is preferable that the crystalline oxide semiconductor layer contains at least gallium. Additionally, as a suitable embodiment of the present invention, it is preferable that the crystalline oxide semiconductor layer has a corundum structure. In embodiments of the present invention, the semiconductor film can be used as the semiconductor region in a semiconductor device after using known methods such as peeling the semiconductor film from the substrate, or it can be directly used as the semiconductor region in a semiconductor device. Furthermore, as a suitable embodiment of the present invention, it is preferable that the crystalline oxide semiconductor layer includes two or more trenches. Additionally, as a suitable embodiment of the present invention, it is preferable that the width of the trenches is 2 μm or less, and it is preferable that the crystalline oxide semiconductor layer includes four or more trenches. The plurality of trenches are spaced apart from each other and arranged on the first surface side of the crystalline oxide semiconductor. According to this embodiment, it becomes a semiconductor device more suitable for use as a power device, and superior semiconductor characteristics can be obtained. Furthermore, it becomes more efficient for miniaturization of semiconductor devices. Furthermore, the crystalline oxide semiconductor layer has at least one arcuate portion between the bottom and side surfaces of the trench, and the radius of curvature of the arcuate portion is in the range of 100 nm to 500 nm. However, if the crystalline oxide semiconductor layer has two or more arcuate portions, it is sufficient that the radius of curvature of at least one arcuate portion is in the range of 100 nm to 500 nm. In this invention, when the crystalline oxide semiconductor layer has two or more arcuate portions, it is preferable that the radius of curvature of the two or more arcuate portions is in the range of 100 nm to 500 nm, and more preferably that the radius of curvature of all arcuate portions is in the range of 100 nm to 500 nm.

[0074] For example, the trenches can be formed using high-pressure dry etching or similar methods. More specifically, methods include, for example, etching crystalline oxides using plasma-enhanced etching gas, with examples of etching methods where the etching gas pressure is between 1 Pa and 10 Pa. In such etching methods, the etching gas pressure is preferably 2 Pa or higher. Furthermore, the plasma-enhanced etching gas preferably contains at least a halogen. It is also preferable that the plasma-enhanced etching gas contains at least gallium. Furthermore, it is preferable that the etching is performed in an inert gas atmosphere. Furthermore, it is preferable that the inert gas is argon. Furthermore, it is also preferable that the etching is performed in a halogen gas atmosphere. It is also preferable that the plasma bias voltage of the etching gas is 25 W or higher. Because of this preferred high-pressure etching method, the trenches can be easily formed.

[0075] The embodiments of the present invention will now be described in more detail with reference to the accompanying drawings, but the present invention is not limited to these embodiments.

[0076] In an embodiment of the present invention, at least one trench 7 is provided on the first surface 3a side of the crystalline oxide semiconductor layer 3 (also referred to as the semiconductor region). The trench 7 includes a bottom surface, a side surface, and at least one arcuate portion between the bottom surface and the side surface. Furthermore, the crystalline oxide semiconductor layer 3 is electrically connected to an electrode. Embodiments of the present invention can be applied to semiconductor devices including trenches. For example, Figure 1 This refers to a junction barrier Schottky diode (JBS) as one embodiment of the present invention. Figure 1 The semiconductor device includes: a semiconductor region 3; a barrier electrode 2 disposed on the semiconductor region and capable of forming a Schottky barrier between the barrier electrode 2 and the semiconductor region; and a barrier height adjustment region 1 disposed between the barrier electrode 2 and the semiconductor region 3, capable of forming a Schottky barrier between the barrier height adjustment region and the semiconductor region 3 with a barrier height greater than the barrier height of the Schottky barrier of the barrier electrode 2. Furthermore, the barrier height adjustment region 1 is embedded in a trench 7 disposed on the first surface 3a side of the semiconductor region 3. In embodiments of the present invention, preferably, a plurality of trenches 7 and a plurality of barrier height adjustment regions 1 disposed within the plurality of trenches 7 are arranged at predetermined intervals; more preferably, the barrier height adjustment regions are respectively disposed between the two ends of the barrier electrode and the semiconductor region. Furthermore, Figure 1 The diagram shows a cross-sectional view of the JBS, where the multiple barrier height adjustment regions are connected, for example, in a planar view. According to this preferred approach, the JBS is constructed to offer superior thermal stability and sealing, further reduced leakage current, and improved semiconductor properties such as withstand voltage. Furthermore, Figure 1 The semiconductor device has an ohmic electrode 4 on the second surface 3b side of the semiconductor region 3. Figure 1 The semiconductor device has an arc portion 7c between the bottom surface 7a and the side surface 7b of the trench 7. The radius of curvature of the arc portion is in the range of 100nm to 500nm, which has an excellent electric field mitigation effect and can reduce the on-resistance.

[0077] Figure 1 The method for forming each layer of the semiconductor device is not particularly limited as long as it does not hinder the purpose of the present invention, and can be a known method. For example, the following method can be listed: that is, after forming a film by vacuum evaporation, CVD, sputtering or various coating techniques, patterning is directly performed by photolithography and using patterning methods or printing techniques.

[0078] Figure 9 An example of a Schottky barrier diode (SBD) illustrating an embodiment of the present invention. Figure 9 The SBD includes an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a dielectric layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. Additionally,Figure 9 The SBD has a groove 7 with the arc portion, and a p-type semiconductor layer 102 is embedded in the groove 7.

[0079] The materials for Schottky electrodes and ohmic electrodes can also be known electrode materials. Examples of such electrode materials include metals or alloys thereof such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag; metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO); and organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof.

[0080] For example, Schottky electrodes and ohmic electrodes can be formed using known methods such as vacuum evaporation or sputtering. More specifically, for example, in the case of forming a Schottky electrode, a layer made of Mo and a layer made of Al are stacked, and the layers made of Mo and Al are patterned using photolithography to form the Schottky electrode.

[0081] In the Figure 9 When a reverse bias is applied to the SBD, the depletion layer (not shown) expands well into the n-type semiconductor layer 101a, which is a crystalline oxide semiconductor layer, due to the stress relaxation effect of the arc portion of the trench 7, thus becoming a high-voltage SBD. Furthermore, when a forward bias is applied, electrons flow from the ohmic electrode 105b located on the second side of the crystalline oxide semiconductor layer opposite to the first side to the Schottky electrode 105a located on the first side of the crystalline oxide semiconductor layer. The SBD using this semiconductor structure is excellent for high voltage / high current applications, has a fast switching speed, and also exhibits excellent voltage withstand capability and reliability.

[0082] Examples of materials that can be used as the dielectric layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO4, AlN, Hf2O3, SiN, SiON, Al2O3, MgO, GdO, SiO2, or Si3N4. By using such an insulator in the insulating layer, the semiconductor properties at the interface can be well utilized. The dielectric layer 104 is disposed between the n-type semiconductor layer 101a and the Schottky electrode 105a. For example, the insulating layer can be formed by known methods such as sputtering, vacuum evaporation, or CVD.

[0083] Figure 10An example of a trench-type Schottky barrier diode (SBD) includes: an n-type semiconductor layer 101a, which is a crystalline oxide semiconductor layer and has two or more trenches 7 disposed on the first side of the n-type semiconductor layer 101a; an n+ type semiconductor layer 101b; a dielectric layer 104; a Schottky electrode 105a; and an ohmic electrode 105b. Figure 10 The trench-type SBD has a trench structure with the aforementioned arc portion. According to this trench-type SBD, leakage current can be significantly reduced while maintaining higher withstand voltage, resulting in a significantly lower on-resistance.

[0084] Figure 11 This illustrates an example of a junction barrier Schottky diode (JBS) comprising an n-type semiconductor layer 101a, an n+ type semiconductor layer 101b, a p-type semiconductor layer 102, a dielectric layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. Figure 11 The JBS has a trench 7 with the aforementioned arc portion, and a p-type semiconductor layer 102 is embedded within this trench 7. According to this JBS, while maintaining a certain ratio... Figure 10 With the higher withstand voltage of the trench-type SBD, leakage current can be significantly reduced, resulting in a greater reduction in on-resistance.

[0085] An example of the semiconductor device of the present invention being a MOSFET is shown below. Figure 12 . Figure 12 The MOSFET is a trench MOSFET and includes: an n-type semiconductor layer 131a, which is a crystalline oxide semiconductor layer and includes a trench 7; n+ type semiconductor layers 131b and 131c; a gate insulating film 134; a gate electrode 135a; a source electrode 135b; and a drain electrode 135c.

[0086] An n+ type semiconductor layer 131b with a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135c, and an n- type semiconductor layer 131a with a thickness of, for example, 100 nm to 100 μm is formed on the n+ type semiconductor layer 131b. Furthermore, an n+ type semiconductor layer 131c is formed on the n- type semiconductor layer 131a, and the drain electrode 135b is formed on the n+ type semiconductor layer 131c.

[0087] Furthermore, the n+ type semiconductor layer 131c extends through the n-type semiconductor layer 131a and the n+ type semiconductor layer 131c, and a plurality of trenches 7 are formed at a depth intermediate to reach the n-type semiconductor layer 131a. Each of these trenches 7 has an arcuate portion between its bottom and side surfaces. Within the trenches 7, a gate electrode 135a is formed, for example, by embedding a gate insulating film 134 with a thickness of 10 nm to 1 μm.

[0088] exist Figure 12 When the MOSFET is in the ON state, if a voltage is applied between the source electrode 135b and the drain electrode 135c, and a voltage positive relative to the source electrode 135b is applied to the gate electrode 135a, a channel layer is formed on the side of the n-type semiconductor layer 131a, and electrons are injected into the n-type semiconductor layer, thus turning it on. Since the voltage of the gate electrode is set to 0V, it is impossible to form a channel layer, and the OFF state is when the n-type semiconductor layer is filled with a depletion layer, thus being in the OFF state.

[0089] exist Figure 12 In the manufacture of the MOSFET, known methods can be appropriately used. For example, an etching mask is provided on a defined area of ​​the n-type semiconductor layer 131a and the n+ type semiconductor layer 131c, and etching is performed by the preferred high-pressure dry etching method described above, forming a trench 7 with a depth extending from the surface of the n+ type semiconductor layer 131c to the middle of the n-type semiconductor layer 131a together with the arc portion. Next, after forming a gate insulating film 134 with a thickness of, for example, 50 nm to 1 μm on the side and bottom surfaces of the trench 7 using known methods such as thermal oxidation, vacuum evaporation, sputtering, and CVD, a gate electrode material such as polysilicon is formed in the trench 7 to a thickness of less than or equal to that of the n-type semiconductor layer using CVD, vacuum evaporation, sputtering, etc. Furthermore, by using known methods such as vacuum evaporation, sputtering, and CVD, a source electrode 135b is formed on the n+ type semiconductor layer 131c, and a drain electrode 135c is formed on the n+ type semiconductor layer 131b, thereby enabling the fabrication of a power MOSFET. In addition, the electrode materials for the source and drain electrodes can be known electrode materials, such as metals or alloys thereof (e.g., Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag), metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof.

[0090] The resulting MOSFET exhibits significantly superior breakdown voltage compared to existing trench MOSFETs. Furthermore, Figure 12 This example illustrates a trench-type vertical MOSFET, but the invention is not limited to this and can be applied to various trench-type MOSFET configurations. For example, it can also be achieved by... Figure 12The trench 7 is dug to a depth reaching the bottom surface of the n-type semiconductor layer 131a, thereby reducing the series resistance. Additionally, an example of another trench-type MOSFET is shown below. Figure 13 .

[0091] Figure 13 This illustrates an example of a metal-oxide-semiconductor field-effect transistor (MOSFET) comprising an n-type semiconductor layer 131a, a first n+ type semiconductor layer 131b, a second n+ type semiconductor layer 131c, a p-type semiconductor layer 132, a p+ type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Furthermore, the p+ type semiconductor layer 132a may also be a p-type semiconductor layer, or it may be the same as the p-type semiconductor layer 132.

[0092] The semiconductor device is particularly useful for power devices. Furthermore, as an embodiment of the invention, the semiconductor device is preferably a vertically oriented device. Examples of the semiconductor device include diodes or transistors (e.g., MESFETs, etc.), but diodes are preferred, and junction barrier Schottky diodes (JBS) are more preferred.

[0093] Based on the above, the semiconductor device of the present invention further utilizes known methods, making it suitable for use as a power module, inverter, or converter, and thus adaptable for applications such as semiconductor systems using power supply devices. The power supply device can be manufactured by or made into the semiconductor device by using known methods and wiring patterns, etc. Figure 3 The power system 170 is constructed using multiple power supply devices 171, 172 and control circuit 173. For example... Figure 4 As shown, the power supply system can combine electronic circuit 181 and power supply system 182 and be used in system device 180. Furthermore, an example of a power supply circuit diagram of the power supply device is shown below. Figure 5 . Figure 5 The power supply circuit, comprising a power circuit and a control circuit, converts DC voltage to AC using a frequency converter 192 (composed of MOSFETs A to D) with a high-frequency wave. It then uses a transformer 193 for insulation and voltage transformation. After rectification by rectifier MOSFETs 194 (A to B'), the voltage is smoothed by DCL 195 (smoothing coils L1 and L2) to output a DC voltage. At this point, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the frequency converter 192 and the rectifier MOSFETs 194 to achieve the desired output voltage.

[0094] [Example]

[0095] (Example 1)

[0096] 1. Formation of semiconductor layer

[0097] 1-1. Film forming apparatus

[0098] use Figure 6 The atomizing CVD device 19 used in the embodiments will be described. Figure 6 The film-forming apparatus 19 includes: a carrier gas source 22a for supplying carrier gas; a flow regulating valve 23a for adjusting the flow rate of the carrier gas supplied from the carrier gas source 22a; a carrier gas (dilution) source 22b for supplying carrier gas (dilution); a flow regulating valve 23b for adjusting the flow rate of the carrier gas (dilution) supplied from the carrier gas (dilution) source 22b; an atomizing source 24 for receiving the raw material solution 24a; a container 25 for holding water 25a; an ultrasonic transducer 26 mounted on the bottom surface of the container 25; a film-forming chamber 30; a quartz supply pipe 27 for connecting the atomizing source 24 to the film-forming chamber 30; and a hot plate (heater) 28 disposed within the film-forming chamber. A substrate 20 is disposed on the hot plate 28.

[0099] 1-2. Preparation of raw material solution

[0100] Prepare a 0.1M aqueous solution of gallium bromide containing 10% hydrobromic acid by volume, and use this solution as the raw material solution.

[0101] 1-3. Film Formation Preparation

[0102] The raw material solution 24a obtained in steps 1-2 above is collected into the atomization source 24. Next, a sapphire substrate 20 is placed on a hot plate 28, and the temperature inside the film-forming chamber 30 is raised to 630°C by operating the hot plate 28. Then, by opening the flow regulating valves 23a and 23b, carrier gas is supplied into the film-forming chamber 30 from the carrier gas supply mechanisms 22a and 22b, which serve as carrier gas sources. After the atmosphere in the film-forming chamber 30 is fully replaced by the carrier gas, the flow rate of the carrier gas is adjusted to 1 L / min, and the flow rate of the carrier gas (diluted) is adjusted to 2 L / min. Nitrogen is used as the carrier gas.

[0103] 1-4. Formation of Semiconductor Films

[0104] Next, the ultrasonic transducer 26 is vibrated at 2.4 MHz, and this vibration is propagated through water 25a to the raw material solution 24a, thereby atomizing the raw material solution 24a to generate mist. This mist is introduced into the film-forming chamber 30 via a carrier gas, where it reacts at atmospheric pressure and 630°C to form a semiconductor film on the substrate 20. Furthermore, the film thickness is 4.1 μm, and the film formation time is 105 minutes.

[0105] 1-5. Evaluation

[0106] The phase of the film obtained in 1-4 above was analyzed using an XRD diffraction apparatus, and the resulting film was α-Ga2O3.

[0107] 2. Etching

[0108] Trenches were formed on semiconductor films using an ICP-RIE apparatus under the conditions described in Table 1 below. The trenches in all examples have arcuate portions, with radii of curvature ranging from 100 nm to 500 nm. A cross-sectional photograph of the trench formed as in Example 1 is shown below. Figure 7 Regarding the radius of curvature in Example 1, as follows: Figure 7 Thus, R1 (left side) is 140nm and R2 (right side) is 160nm. Additionally, the trench sides have a 60° tilt angle. (As from...) Figure 7 It is clear that such a well-formed trench has been created.

[0109] [Table 1]

[0110]

[0111] (Example 2)

[0112] In addition to etching under the conditions shown in Table 1, trenches were formed in the same manner as in Example 1. Cross-sectional photographs of the resulting trenches are shown below. Figure 8 Regarding the radius of curvature of the arc portion of the groove, such as... Figure 8 As shown, R1 (left side) is 125nm, and R2 (right side) is 298nm. (The last sentence appears to be incomplete and possibly refers to a diagram or graph.) Figure 8 As can be clearly seen, a groove with a high-quality rounded section is formed.

[0113] [Table 2]

[0114]

[0115] (Example 3)

[0116] In addition to etching under the conditions shown in Table 2, trenches were formed on the semiconductor film (referred to as the crystalline oxide semiconductor layer) in the same manner as in Example 1. Cross-sectional photographs of the resulting trenches are shown below. Figure 16-a .in addition, Figure 16-bThis is an explanatory diagram showing the use of the same cross-sectional photograph. The radius of curvature R1 (left side) of the first arc portion 7ca of trench 7 is 220 nm, and the radius of curvature R2 (right side) of the second arc portion 7cb is also 220 nm. Although multiple trenches 7 are formed on the crystalline oxide semiconductor layer 3, each trench 7 has a first arc portion 7ca and a second arc portion 7cb with equal radii of curvature. The width of the trench 7 narrows towards the bottom surface. In the cross-section of the trench, the angle formed by the side surface 7a (first side surface 7aa) of the trench and the first surface 3a of the crystalline oxide semiconductor layer 3 is ( Figure 16-b The angle θ1 shown is in the range of greater than 90° and less than 135°, which is the angle formed by the side surface 7a (second side surface 7ab) of the trench and the first surface 3a of the crystalline oxide semiconductor layer 3. Figure 16-b The θ2 shown is in the range greater than 90° and less than 135°. Furthermore, Figure 16-b The SiO2 shown is a mask placed on the crystalline oxide semiconductor layer 3 for etching to form trenches, and is therefore eventually removed. Furthermore, by changing the flow rate of BCl3 to obtain the crystalline oxide semiconductor layer, it was found that by setting the BCl3 flow rate in the range of 50 sccm to 100 sccm, trenches with better rounded portions could be obtained.

[0117] According to embodiments 1 to 3 of the present invention, in the trench cross-section, a trench having an arcuate portion including a radius of curvature in the range of 100 nm to 500 nm, and the angle formed by the side of the trench and the first surface of the crystalline oxide semiconductor layer being in the range of greater than 90° and less than 135°, can sufficiently achieve an electric field mitigation effect. As a result, the on-resistance of the semiconductor device having a gallium oxide-based crystalline oxide semiconductor layer can be reduced. Furthermore, according to embodiment 3, since a trench with an arcuate portion having a bilaterally symmetrical radius of curvature can be formed in the gallium oxide-based crystalline oxide semiconductor layer, it is expected that the on-resistance of the semiconductor device can be further reduced.

[0118] (Comparative Example 1)

[0119] In addition to etching under the conditions shown in Table 1, the trenches were formed in the same manner as in Example 1. The resulting trenches had a convex bottom surface and corners between the bottom and side surfaces, resulting in substandard trenches.

[0120] (Comparative Example 2)

[0121] In addition to etching under the conditions shown in Table 1, the trenches were formed in the same manner as in Example 1. The sides of the resulting trenches were cut open in a reverse inclined state, resulting in the width inside the trench being wider than the width of the trench opening. Furthermore, although an arc portion was formed between the bottom surface and the side surface, the arc portion bulged excessively, and the radius of curvature was more than 1 μm, resulting in a substandard trench.

[0122] Industrial availability

[0123] The semiconductor device of the present invention can be used in all fields of semiconductors (e.g., compound semiconductor electronic devices, etc.), electronic components and electrical machine components, optical and electronic photographic related devices and industrial components, and is particularly useful for power devices.

[0124] Explanation of reference numerals in the attached figures

[0125] 1 Barrier Height Adjustment Area

[0126] 2 Barrier Electrode

[0127] 3. Crystalline oxide semiconductor layer (semiconductor region)

[0128] 3a First page

[0129] 3b Second page

[0130] 4 Ohm electrode

[0131] 7. Trench

[0132] 7a Side of the trench

[0133] 7aa The first side of the groove

[0134] 7ab second side surface of the groove

[0135] 7b The bottom surface of the trench

[0136] 7c The arc portion of the groove

[0137] The first arc of the 7ca groove

[0138] The second arc of the 7cb groove

[0139] 19. Atomized CVD Unit (Film Forming Unit)

[0140] 20 substrate

[0141] 22a Carrier gas supply mechanism

[0142] 22b Carrier gas (dilution) supply mechanism

[0143] 23a Carrier gas flow regulating valve

[0144] 23b Carrier gas (dilution) flow regulating valve

[0145] 24. Atomization Source

[0146] 24a Raw material solution

[0147] 25 containers

[0148] 25a Water

[0149] 26. Ultrasonic transducer

[0150] 27 Supply Management

[0151] 28 Heaters

[0152] 29 Exhaust port

[0153] 30 film-forming chambers

[0154] 101a n-type semiconductor layer

[0155] 101b n+ type semiconductor layer

[0156] 102 p-type semiconductor layer

[0157] 103 Metal Layer

[0158] 104 Dielectric Layer

[0159] 105a Schottky electrode

[0160] 105b Ohmic Electrode

[0161] 131a n-type semiconductor layer

[0162] 131b First n+ type semiconductor layer

[0163] 131c Second n+ type semiconductor layer

[0164] 132 P-type semiconductor layer

[0165] 132a p + Type semiconductor layer

[0166] 134 Gate insulating film

[0167] 135a gate electrode

[0168] 135b source electrode

[0169] 135c drain electrode

[0170] 170 Power System

[0171] 171 Power Supply Unit

[0172] 172 Power Supply Unit

[0173] 173 Control Circuit

[0174] 180 System Device

[0175] 181 Electronic Circuits

[0176] 182 Power System

[0177] 192 Frequency Inverter

[0178] 193 Transformer

[0179] 194 Rectifier MOSFET

[0180] 195 DCL

[0181] 196 PWM control circuit

[0182] 197 Voltage comparator

Claims

1. A semiconductor device comprising: A crystalline oxide semiconductor layer; and at least one electrode electrically connected to the crystalline oxide semiconductor layer, the crystalline oxide semiconductor layer comprising α-Ga2O3, having at least one trench including a bottom surface, a side surface, and at least one circular-arc portion between the bottom surface and the side surface, a radius of curvature of the circular-arc portion being in a range from 100 nm to 500 nm, and an angle between the side surface and a first surface of the crystalline oxide semiconductor layer being 90° or more.

2. The semiconductor device according to claim 1, wherein the angle between the side surface and the first surface of the crystalline oxide semiconductor layer is 150° or less.

3. The semiconductor device according to claim 1 or 2, wherein a width of the trench is narrower toward the bottom surface of the trench.

4. The semiconductor device according to claim 1 or 2, wherein the side surface of the trench is inclined.

5. The semiconductor device according to claim 4, wherein the angle between the side surface and the first surface of the crystalline oxide semiconductor layer is in a range from more than 90° to 135° or less.

6. The semiconductor device according to claim 1 or 2, wherein the crystalline oxide semiconductor layer includes two or more of the trenches.

7. The semiconductor device according to claim 1 or 2, wherein a width of the trench is 2 μm or less.

8. The semiconductor device according to claim 7, wherein the crystalline oxide semiconductor layer includes four or more of the trenches.

9. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a power device.

10. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a vertical device.

11. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a diode.

12. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a transistor.

13. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a junction barrier Schottky diode.

14. A semiconductor system comprising a semiconductor device, the semiconductor device being the semiconductor device according to any one of claims 1 to 13.

Images