Display Devices

Abstract

A display device is disclosed, comprising: a display area; a pair of first color sub-pixels, which are continuously arranged in the display area in a first direction, and each of the first color sub-pixels includes at least one first color light-emitting element; and a bank configured to surround the pair of first color sub-pixels at the same time. The bank includes at least two regions with different widths in corresponding regions corresponding to each of the pair of first color sub-pixels.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device. Background Art

[0002] Recently, a technology has been developed for manufacturing ultra-small light-emitting elements using materials having a reliable inorganic crystal structure and manufacturing a display device using the light-emitting elements. For example, a technology has been developed for manufacturing ultra-small light-emitting elements having a small size corresponding to a range from a nanometer size to a micrometer size and forming pixels of a display device using the ultra-small light-emitting elements. Summary of the invention

[0003] Technical issues

[0004] Various embodiments of the present disclosure relate to a display device having a high resolution.

[0005] Technical Solution

[0006] According to one aspect of the present disclosure, a display device may include: a display area; a pair of first color sub-pixels, which are continuously arranged in the display area in a first direction, and each first color sub-pixel includes at least one first color light-emitting element; and a embankment, which is configured to simultaneously surround the pair of first color sub-pixels, wherein the embankment may include at least two regions with different widths in corresponding regions corresponding to each first color sub-pixel in the pair of first color sub-pixels.

[0007] The pair of first color sub-pixels may include at least two regions having different widths in each emission region surrounded by the bank, and may be arranged to contact each other in a portion having a maximum width of the emission region.

[0008] The first direction may be a vertical direction of the display area, and the bank may have an up-and-down symmetrical shape.

[0009] The pair of first color sub-pixels may include emission areas having a triangular shape and an inverted triangular shape, respectively, and the bank may have a quadrilateral shape surrounding the emission areas of the pair of first color sub-pixels at the same time.

[0010] The pair of first color sub-pixels may be symmetrically arranged in the first direction while each first color sub-pixel has an emission area in an isosceles triangle shape, and the bank may have a rhombus shape to surround the emission areas of the pair of first color sub-pixels.

[0011] Each of the pair of first color subpixels may include a polygonal emission region having a symmetrical structure in a second direction intersecting the first direction, and the bank may have a polygonal shape having a symmetrical structure in both the first and second directions.

[0012] Each of the first color sub-pixels in the pair of first color sub-pixels may include a stepped emission region.

[0013] The display device may also include: a second color sub-pixel, which is arranged to be adjacent to any one of the pair of first color sub-pixels in a second direction intersecting the first direction, and includes at least one second color light-emitting element; and a third color sub-pixel, which is arranged to be adjacent to the second color sub-pixel in the second direction, and includes at least one third color light-emitting element.

[0014] The second color sub-pixel may include an emission area, the emission area of ​​the second color sub-pixel having a shape in which the emission area of ​​any one of the above-mentioned first color sub-pixels is inverted in the first direction, and the third color sub-pixel may include an emission area, the emission area of ​​the third color sub-pixel having the same shape as the emission area of ​​any one of the above-mentioned first color sub-pixels.

[0015] The second color subpixel may be disposed between any of the first and third color subpixels. The emission region of each of the first and third color subpixels may have a triangular shape, and the emission region of the second color subpixel may have an inverted triangular shape.

[0016] The display device may include a trapezoidal pixel including any one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel.

[0017] The second color sub-pixel may include an emission area, the emission area of ​​the second color sub-pixel having a shape in which the emission area of ​​any one of the above-mentioned first color sub-pixels is inverted in the second direction, and the third color sub-pixel may include an emission area, the emission area of ​​the third color sub-pixel having a shape in which the emission area of ​​the second color sub-pixel is inverted in the first direction and the second direction.

[0018] Each first color sub-pixel in the above-mentioned pair of first color sub-pixels may also include: a first electrode, arranged in each emission area and connected to the first end of the first color light-emitting element; and a second electrode, arranged in each emission area to be separated from the first electrode and connected to the second end of the first color light-emitting element.

[0019] The first electrodes disposed in the pair of first color sub-pixels may have the same shape, and the second electrodes disposed in the pair of first color sub-pixels may have the same shape.

[0020] The first electrodes provided in the pair of first color sub-pixels may have shapes in which they are symmetrical to each other, and the second electrodes provided in the pair of first color sub-pixels may have shapes in which they are symmetrical to each other.

[0021] The first electrodes of the pair of first color sub-pixels may be spaced apart from each other, and the second electrodes of the pair of first color sub-pixels may be connected to each other.

[0022] Each first color sub-pixel in the above-mentioned pair of first color sub-pixels may also include: a first partition wall, arranged between the substrate and the first electrode; a second partition wall, arranged between the substrate and the second electrode; a first contact electrode, arranged on the first end of the first color light-emitting element and a portion of the first electrode to electrically connect the first end to the first electrode; and a second contact electrode, arranged on the second end of the first color light-emitting element and a portion of the second electrode to electrically connect the second end to the second electrode.

[0023] The display device may include: a display area; a pair of emission areas arranged to contact each other in the display area, and each emission area includes a first electrode, a second electrode, and at least one first color light emitting element connected between the first electrode and the second electrode; and a bank configured to surround the pair of emission areas at the same time. The bank may include at least two areas with different widths in respective areas corresponding to each of the pair of emission areas, and may have a maximum width in an area where the emission areas contact each other.

[0024] The pair of emission regions may be arranged to vertically contact each other in the display region, and the bank may have an up-and-down symmetrical shape.

[0025] The first electrodes of the pair of emission regions may be spaced apart from each other.

[0026] Beneficial effects

[0027] According to various embodiments of the present disclosure, a display device with high resolution may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 5a to Figure 5c are circuit diagrams each showing a sub-pixel according to an embodiment of the present disclosure.

[0033] Figure 6 is a cross-sectional view illustrating a method of supplying and aligning a light emitting element according to an embodiment of the present disclosure.

[0034] Figure 7 and Figure 8 are plan views each showing a display area according to an embodiment of the present disclosure.

[0035] Figure 9a and Figure 9b It shows that according to Figure 7 and Figure 8 A plan view of the difference in resolution of the embodiments.

[0036] Fig.10a , Fig.10b and Fig.11 are plan views each showing a sub-pixel according to an embodiment of the present disclosure.

[0037] Fig.12 and Fig.13 are cross-sectional views each showing a structure of a sub-pixel according to an embodiment of the present disclosure. For example, Fig.12 and Fig.13 According to different implementation methods Fig.10a A cross-sectional view taken along line II'.

[0038] Figures 14 to 16 are plan views each showing a display area according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Reference will now be made in detail to various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below, as various modifications may be made to the embodiments of the present disclosure in many different forms. However, the present disclosure is not limited to the following embodiments and may be modified into various forms.

[0040] Some elements that are not directly related to the features of the present disclosure may be omitted in the accompanying drawings to clearly explain the present disclosure. In addition, the sizes, ratios, etc. of some elements in the accompanying drawings may be slightly enlarged. It should be noted that throughout the accompanying drawings, the same reference numerals are used to represent the same or similar elements, and repeated descriptions will be omitted.

[0041] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It should also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, it is specified that the stated features, integers, steps, operations, elements, parts and / or combinations thereof exist, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or combinations thereof are not excluded. In addition, when a first component or part is disposed on a second component or part, the first component or part can not only be directly on the second component or part, but a third component or part can also be inserted between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or orientations depending on the viewing angle or direction.

[0042] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings to describe the present disclosure in detail so that a person skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not particularly mentioned in a sentence.

[0043] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 is a perspective view and a cross-sectional view showing a light emitting element LD according to an embodiment of the present disclosure. Figures 1a to 3b , a rod-type light emitting element LD having a cylindrical shape is shown in FIG. 1 , but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0044] First, refer to Figure 1a and Figure 1b , the light emitting element LD according to the embodiment of the present disclosure includes a first conductive type semiconductor layer 11, a second conductive type semiconductor layer 13, and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting element LD may be composed of a stacked body formed by sequentially stacking the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13 in a longitudinal direction.

[0045] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end with respect to the longitudinal direction.

[0046] In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a first end of the light emitting element LD, and the other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a second end of the light emitting element LD.

[0047] In an embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. In this specification, the term "rod-type" includes a rod-like shape and a strip-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), such as a cylindrical shape and a prismatic shape, and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0048] In an embodiment, the light emitting element LD may have a small size corresponding to the nanometer level to the micrometer level, for example, a diameter D and / or a length L corresponding to the nanometer level to the micrometer level range. However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (for example, display devices) that adopt the light emitting device using the light emitting element LD as a light source.

[0049] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0050] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12.

[0051] If an electric field of a predetermined voltage or more is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by combining electron-hole pairs in the active layer 12. Since light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0052] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a different type from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant such as Mg. However, the material forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0053] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12. In addition, the insulating film INF may also surround a region of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. The insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the respective opposite ends of the light emitting element LD with respect to the longitudinal direction, for example, each of the top surface and the bottom surface of the cylinder may be exposed instead of covering it.

[0054] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF may be formed of various well-known insulating materials.

[0055] In an embodiment, the light emitting element LD may further include other components as well as the first conductive semiconductor layer 11, the active layer 12, and the second conductive semiconductor layer 13 and / or the insulating film INF. For example, the light emitting element LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer disposed on one end of the first conductive semiconductor layer 11, the active layer 12, and / or the second conductive semiconductor layer 13.

[0056] For example, Figure 2a and Figure 2b As shown in , the light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. In an embodiment, as Figure 3aand Figure 3b As shown in , the light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11 .

[0057] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO, and oxides or alloys thereof may be used alone or in combination with each other. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside of the light emitting element LD after passing through the electrode layers 14 and 15.

[0058] In an embodiment, the insulating film INF may at least partially surround the outer surfaces of the electrode layers 14 and 15, or may not surround them. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD that may have different polarities, for example, at least one region of each of the electrode layers 14 and 15 may be exposed. Alternatively, in yet another embodiment, the insulating film INF may not be provided.

[0059] If the insulating film INF is provided on the surface of the light emitting element LD, particularly on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode (not shown) (e.g., at least one of the contact electrodes connected to the opposite ends of the light emitting element LD, etc.). Therefore, the electrical stability of the light emitting element LD can be ensured.

[0060] In addition, due to the insulating film INF formed on the surface of the light emitting element LD, the occurrence of defects on the surface of the light emitting element LD can be minimized, so that the life and efficiency of the light emitting element LD can be improved. In addition, if the insulating film INF is formed on each light emitting element LD, even in the case where a plurality of light emitting elements LD are disposed adjacent to each other, the light emitting element LD can be prevented from being unexpectedly short-circuited.

[0061] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light emitting element LD. For example, the light emitting element LD may be surface treated (e.g., by a coating process) so that when a plurality of light emitting elements LD are mixed with a fluid solution and then supplied to each emission region (e.g., the emission region of each pixel), the light emitting elements LD may be uniformly distributed rather than unevenly aggregated in the solution.

[0062] The light-emitting device including the above-mentioned light-emitting element LD can be used in various devices that may require a light source, including a display device. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD) can be arranged in each sub-pixel region of the display panel to form a light source (or light source unit) for each sub-pixel. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in various devices that require a light source, such as lighting equipment.

[0063] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device, in particular, a display panel PNL provided in the display device is shown as a reference that can be used Figures 1a to 3b The light emitting element LD is described as an example of a device of a light source. For the sake of explanation, Figure 4 The structure of the display panel PNL according to the embodiment is shown focusing only on the display area DA. In some embodiments, although not shown, at least one driving circuit component (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0064] refer to Figure 4 , the display panel PNL according to an embodiment of the present disclosure may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. In detail, the display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA having the pixels PXL and a non-display area NDA formed in a predetermined area except the display area DA.

[0065] In an embodiment, the display area DA may be disposed in the central portion of the display panel PNL, and the non-display area NDA may be disposed in the peripheral portion of the display panel PNL in a manner surrounding the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may vary.

[0066] The substrate SUB may form a base member of the display panel PNL. In an embodiment, the substrate SUB may be a rigid substrate or a flexible substrate, and its material or properties are not particularly limited. For example, the substrate SUB may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the substrate SUB may be a transparent substrate, but it is not limited thereto. For example, the substrate SUB may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0067] An area on the substrate SUB may be defined as a display area DA in which the pixels PXL are disposed, and another area thereof may be defined as a non-display area NDA. For example, the substrate SUB may include a display area DA including a plurality of pixel areas on which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuit units connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0068] Each of the pixels PXL may include at least one light emitting element LD (eg, Figures 1a to 3b At least one rod-type light emitting diode of any one of the embodiments of the present invention. For example, each of the pixels PXL may include a plurality of rod-type light emitting diodes, each of which has a small size ranging from nanometer to micrometer and is connected in parallel to each other in each sub-pixel region. The plurality of rod-type light emitting diodes may form the light source of each pixel PXL or sub-pixel.

[0069] In addition, each of the pixels PXL may include a plurality of sub-pixels. For example, each pixel PXL may include a first color sub-pixel SPX1, a second color sub-pixel SPX2, and a third color sub-pixel SPX3 that emit light of different colors. For example, the first color sub-pixel SPX1 may be a red sub-pixel for emitting red light, the second color sub-pixel SPX2 may be a green sub-pixel for emitting green light, and the third color sub-pixel SPX3 may be a blue sub-pixel for emitting blue light. However, the color, type, and / or number of sub-pixels forming each pixel PXL are not particularly limited. For example, the color of light emitted from each sub-pixel may be changed in various ways. Although in Figure 4 2 shows an embodiment in which the pixels PXL (or sub-pixels) are arranged in a stripe shape in the display area DA, but the present disclosure is not limited thereto. For example, the display area DA may have various well-known pixel arrangement structures.

[0070] In an embodiment, each pixel PXL (or each sub-pixel) may be formed by an active pixel. However, the type, structure and / or driving method of the pixel PXL applicable to the display device according to the present disclosure are not particularly limited. For example, each pixel PXL may have the same structure as that of various known passive or active light-emitting display devices.

[0071] Figure 5a to Figure 5c are circuit diagrams each showing a sub-pixel SPX according to an embodiment of the present disclosure, for example, to show Figure 4 Any one of the first color sub-pixel SPX1, the second color sub-pixel SPX2 and the third color sub-pixel SPX3 shown in FIG.

[0072] More specifically, Figure 5a to Figure 5c 1 shows different embodiments of sub-pixels SPX that can be provided in an active display device (eg, an active light emitting display device). Figure 5a to Figure 5c Each sub-pixel SPX shown in FIG. 1 may be arranged in Figure 4 Any one of the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 in the display panel PNL. The structures of the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 may be substantially the same or similar to each other. Hereinafter, when any one or all of the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 are mentioned, they will be referred to as "sub-pixel SPX".

[0073] refer to Figure 5a , the sub-pixel SPX according to an embodiment of the present disclosure may include a light source unit LSU generating light having brightness corresponding to a data signal and a pixel circuit PXC driving the light source unit LSU.

[0074] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD connected in parallel to each other between a first power source VDD and a second power source VSS. Here, the first power source VDD and the second power source VSS may have different potentials so that the light emitting element LD may emit light. For example, the first power source VDD may be set as a high potential power source, and the second power source VSS may be set as a low potential power source. Here, the potential difference between the first power source VDD and the second power source VSS may be set to a threshold voltage or more of the light emitting element LD during a light emitting period of at least each sub-pixel SPX.

[0075] although Figure 5a An embodiment is shown in which the light emitting elements LD of the light source unit LSU forming each sub-pixel SPX are connected in parallel to each other in the same direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS, but the present disclosure is not limited thereto. For example, in another embodiment, some of the light emitting elements LD may be connected to each other in the forward direction between the first power supply VDD and the second power supply VSS, and the other light emitting elements LD may be connected to each other in the reverse direction. Alternatively, in an embodiment, at least one sub-pixel SPX may include a single light emitting element LD.

[0076] In an embodiment, the first end of the light emitting element LD forming each light source unit LSU may be commonly connected to the corresponding pixel circuit PXC through the first electrode of the corresponding light source unit LSU, and may be connected to the first power supply VDD through the pixel circuit PXC. In addition, the second end of the light emitting element LD may be commonly connected to the second power supply VSS through the second electrode of the light source unit LSU.

[0077] Each light source unit LSU may emit light having brightness corresponding to a driving current supplied thereto through a corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0078] The pixel circuit PXC may be connected to a scan line (e.g., the i-th scan line Si) and a data line (e.g., the j-th data line Dj) of the corresponding sub-pixel SPX. For example, if the sub-pixel SPX is disposed on the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0079] The first transistor (driving transistor) T1 is connected between the first power source VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the driving current supplied to the light source unit LSU in response to the voltage of the first node N1.

[0080] The second transistor (switching transistor) T2 is connected between the data line (eg, the j-th data line Dj) and the first node N1. A gate electrode of the second transistor T2 is connected to the scan line (eg, the i-th scan line Si).

[0081] When a scan signal of a gate-on voltage (e.g., a low voltage) is supplied from a scan line (e.g., the i-th scan line Si), the second transistor T2 is turned on to electrically connect the first node N1 to the data line (e.g., the j-th data line Dj). During each frame period, a data signal of a corresponding frame is supplied to the data line (e.g., the j-th data line Dj). The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0082] The first electrode of the storage capacitor Cst is connected to the first power source VDD, and the second electrode thereof is connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1 during each frame period and maintains the charged voltage until a data signal of the next frame is supplied.

[0083] Despite Figure 5a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, any one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0084] For example, Figure 5b As shown in , both the first transistor T1 and the second transistor T2 can be formed by N-type transistors. Except that the connection positions of some circuit elements have been changed according to the change of the type of transistor, Figure 5b The configuration and operation of the sub-pixel SPX shown in FIG. Figure 5a The pixel circuit PXC is basically similar to those of FIG. Therefore, Figure 5b Detailed description of the sub-pixel SPX.

[0085] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b In other words, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. Figure 5c The embodiment shown in FIG. 1 is configured in the same manner.

[0086] refer to Figure 5c , the pixel circuit PXC may be connected not only to the scan line of the corresponding horizontal line (e.g., the i-th scan line Si), but also to at least another scan line (or control line). For example, the pixel circuit PXC of the sub-pixel SPX arranged on the i-th row of the display area DA may also be connected to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In an embodiment, the pixel circuit PXC may be connected not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC may also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0087] The first transistor T1 is connected between the first power source VDD and the first electrode of the light source unit LSU. A gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls a driving current supplied to the light source unit LSU in response to a voltage of the first node N1.

[0088] The second transistor T2 is connected between the data line (e.g., the jth data line Dj) and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line (e.g., the i-th scan line Si). In the case where a scan signal of a gate-on voltage is supplied from the scan line (e.g., the i-th scan line Si), the second transistor T2 can be turned on to electrically connect the data line (e.g., the j-th data line Dj) to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line (e.g., the j-th data line Dj) is transmitted to the first transistor T1.

[0089] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line (e.g., the i-th scan line Si). In the case where a scan signal of a gate-on voltage is supplied from the scan line (e.g., the i-th scan line Si), the third transistor T3 is turned on, thereby connecting the first transistor T1 in the form of a diode.

[0090] The fourth transistor T4 is connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal of the gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 is turned on, so that the voltage of the initialization power supply Vint is transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be the minimum voltage of the data signal or less.

[0091] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 can be turned off when an emission control signal of a gate cut-off voltage (for example, a high voltage) is supplied to the emission control line (for example, the i-th emission control line Ei), and can be turned on in other cases.

[0092] The sixth transistor T6 is connected between the first transistor T1 and the second node N2 (which is connected to the first electrode of the light source unit LSU). The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 is turned off when the emission control signal of the gate-off voltage is supplied to the emission control line (for example, the i-th emission control line Ei), and is turned on in other cases.

[0093] The seventh transistor T7 is connected between the first electrode of the light source unit LSU and the initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the next stage, for example, to the i+1th scan line Si+1. When a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 is turned on, so that the voltage of the initialization power supply Vint is supplied to the first electrode of the light source unit LSU.

[0094] The storage capacitor Cst is connected between the first power source VDD and the first node N1. The storage capacitor Cst stores a voltage corresponding to both the threshold voltage of the first transistor T1 and the data signal supplied to the first node N1 during each frame period.

[0095] Despite Figure 5c , the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0096] In addition, the structure of the sub-pixel SPX that can be applied to the present disclosure is not limited to Figure 5a to Figure 5c , and each sub-pixel SPX may have various well-known structures. For example, the pixel circuit PXC included in each sub-pixel SPX may be formed by a well-known pixel circuit that may have various structures and / or be operated by various driving methods. In another embodiment of the present disclosure, each sub-pixel SPX may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first pixel electrode and the second pixel electrode of the light source unit LSU may be directly connected to a scan line (e.g., the i-th scan line Si), a data line (e.g., the j-th data line Dj), a power line, and / or a control line.

[0097] Figure 6 is a cross-sectional view illustrating a method of supplying and aligning a light emitting element LD according to an embodiment of the present disclosure.

[0098] refer to Figure 6 , the sub-pixel SPX according to an embodiment of the present disclosure includes corresponding emission areas divided by the bank BNK. For example, the first color sub-pixel SPX1 may include a first emission area EMA1, the second color sub-pixel SPX2 may include a second emission area EMA2, and the third color sub-pixel SPX3 may include a third emission area EMA3. Hereinafter, when any one or all of the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3 are mentioned, they will be referred to as "emission area EMA".

[0099] In an embodiment, the bank BNK may be disposed between the emission areas EMA to surround the emission areas EMA. At least one pair of the first electrode ELT1 and the second electrode ELT2 spaced apart from each other may be disposed in each emission area EMA.

[0100] In an embodiment of the present disclosure, the light emitting element LD may be supplied to each emission area EMA by an inkjet printing method. For example, at least one first color light emitting element LD1 may be supplied to the first emission area EMA1 by disposing a first nozzle NOZ1 containing a first LED solution SOL1 in which a plurality of first color light emitting elements LD1 (e.g., red light emitting elements) are dispersed above the first emission area EMA1 and dropping a droplet DRL of the first LED solution SOL1 into the first emission area EMA1.

[0101] Likewise, at least one second color light emitting element LD2 may be supplied to the second emission area EMA2 by disposing a second nozzle NOZ2 including a second LED solution SOL2 in which a plurality of second color light emitting elements LD2 (e.g., green light emitting elements) are dispersed therein above the second emission area EMA2 and dropping droplets DRL of the second LED solution SOL2 into the second emission area EMA2. Furthermore, at least one third color light emitting element LD3 may be supplied to the third emission area EMA3 by disposing a third nozzle NOZ3 including a third LED solution SOL3 in which a plurality of third color light emitting elements LD3 (e.g., blue light emitting elements) are dispersed therein above the third emission area EMA3 and dropping droplets DRL of the third LED solution SOL3 into the third emission area EMA3.

[0102] Hereinafter, when any one or all of the first color light emitting element LD1, the second color light emitting element LD2, and the third color light emitting element LD3 are mentioned, they will be referred to as "light emitting element LD". Hereinafter, when any one or all of the first LED solution SOL1, the second LED solution SOL2, and the third LED solution SOL3 are mentioned, they will be referred to as "LED solution SOL".

[0103] In an embodiment, each LED solution SOL may be in the form of ink or slurry, but the present disclosure is not limited thereto. As a solvent, a photoresist or an organic layer containing a solvent may be used. However, the present disclosure is not limited thereto. In addition, in an embodiment, the solvent may be a volatile solvent, but the present disclosure is not limited thereto.

[0104] After supplying at least one light emitting element LD to each emission region EMA or simultaneously with the supply of the light emitting element LD, a voltage (e.g., a specific AC voltage) may be applied between the first electrode ELT1 and the second electrode ELT2 of each emission region EMA to form an electric field. In this case, when dielectrophoresis of the light emitting element LD occurs, the light emitting element LD is self-aligned between the first electrode ELT1 and the second electrode ELT2 of each emission region EMA.

[0105] Subsequently, if the solvent of the LED solution SOL dripped to each emission area EMA is removed, the light emitting element LD is stably arranged in the emission area EMA of each sub-pixel SPX. In an embodiment, the solvent of the LED solution SOL may be formed of a volatile material so that the solvent can be easily removed. However, the constituent material and / or removal method of the solvent are not limited thereto.

[0106] Figure 7 and Figure 8 are plan views each showing a display area DA according to an embodiment of the present disclosure. For example, Figure 7 and Figure 8 Shows the application Figure 4 Different embodiments of the pixel arrangement structure of the display area DA. In the embodiment, Figure 7 and Figure 8 A sub-pixel SPX is shown based on each emission area EMA.

[0107] First, refer to Figures 4 to 6 and Figure 7 , each pixel PXL may include a plurality of sub-pixels SPX emitting light of different colors, for example, a first color sub-pixel SPX1 emitting light of a first color, a second color sub-pixel SPX2 emitting light of a second color, and a third color sub-pixel SPX3 emitting light of a third color. In an embodiment, the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 may be a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, respectively, but the present disclosure is not limited thereto.

[0108] In an embodiment, the pixels PXL may be arranged in a strip shape in the display area DA. For example, sub-pixels SPX of the same color (i.e., any type of sub-pixel SPX among the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3) may be arranged in a line in a first direction DR1 (e.g., a column direction) on each pixel column. In addition, a plurality of sub-pixels SPX may be repeatedly arranged in a second direction DR2 (e.g., a row direction) intersecting the first direction DR1 on each pixel row in the order of the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3. Here, the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 continuously arranged in each pixel row form a group having three members to constitute each pixel PXL.

[0109] In an embodiment, each of the pixels PXL may have a quadrilateral shape. For example, each sub-pixel SPX (particularly the emission area EMA of each sub-pixel SPX) may have a rectangular shape, and each pixel PXL (particularly the emission area EMA of each pixel PXL) may have a quadrilateral shape including the sub-pixels SPX constituting the pixel PXL. In an embodiment, the sub-pixels SPX may have substantially the same shape and / or size. Similarly, the pixels PXL may have substantially the same shape and / or size.

[0110] Each sub-pixel SPX may be surrounded by a bank BNK. For example, the bank BNK may be disposed between the sub-pixels SPX to surround the sub-pixels SPX, particularly, the emission area EMA of each sub-pixel SPX.

[0111] In an embodiment, the bank BNK may define a sub-pixel region in which each sub-pixel SPX is formed, in particular, an emission area EMA of each sub-pixel SPX. For example, the bank BNK may be a pixel defining layer. In addition, the bank BNK may also serve as a dam structure in an inkjet printing process for supplying at least one light emitting element LD to each sub-pixel SPX.

[0112] In an embodiment, the bank BNK may include a light shielding material to prevent light leakage between adjacent sub-pixels SPX. For example, the bank BNK may include a black matrix material such as carbon black. In the present disclosure, the constituent material of the bank BNK is not particularly limited and may be variously changed.

[0113] refer to Figures 4 to 8, the shape and / or size of each pixel PXL and / or sub-pixel SPX (particularly, the emission area EMA of each pixel PXL and / or sub-pixel SPX) may be changed. In an embodiment, each sub-pixel SPX may include at least two regions with different widths in each emission area EMA surrounded by the bank BNK. For example, each sub-pixel SPX may have an emission area EMA of a shape (e.g., a triangular shape or an inverted triangular shape) whose width in the second direction DR2 gradually changes along the first direction DR1.

[0114] In addition, in an embodiment of the present disclosure, a plurality of sub-pixels SPX emitting light of the same color (e.g., two sub-pixels SPX of the same color) continuously arranged in the display area DA in the first direction DR1 form a symmetrically arranged pair. In an embodiment, a pair of sub-pixels SPX may be arranged to contact each other in an area having a maximum width. For example, a pair of sub-pixels SPX may be arranged to contact each other in an area where the width of each emission area EMA surrounded by the embankment BNK is the largest (e.g., in an area where the horizontal width of each emission area EMA along the second direction DR2 is the largest), and the emission areas EMA of a pair of sub-pixels SPX may be surrounded by the embankment BNK at the same time.

[0115] For example, it is assumed that the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 are respectively arranged on the 3k-2 (k is a natural number) pixel column, the 3k-1 pixel column, and the 3k pixel column. In this case, in each 3k-2 pixel column, two first color sub-pixels SPX1 that are continuously arranged vertically in the first direction DR1 (for example, in the vertical direction of the display area DA) and each include at least one first color light emitting element LD1 (for example, at least one first color rod-type light emitting diode having a size of nanometer to micrometer) may form a pair. In an embodiment, one of a pair of first color sub-pixels SPX1 may have a 1_1 emission area EMA1_1 in a triangular shape, and the other may have a 1_2 emission area EMA1_2 in an inverted triangular shape, wherein in the 1_2 emission area EMA1_2 in the inverted triangular shape, the triangular shape is inverted in the first direction DR1. The present disclosure is not limited thereto, and the shape of each of the sub-pixels SPX and / or its emission area EMA may be changed differently.

[0116] In an embodiment, a pair of first color sub-pixels SPX1 may be symmetrically arranged while being arranged to contact each other in an area having a maximum width in the second direction DR2. For example, a pair of first color sub-pixels SPX1 having each emission area EMA in a triangular shape and an inverted triangular shape may be symmetrically arranged in a vertical direction so that the bases of the sub-pixels contact each other.

[0117] For example, a first color sub-pixel SPX1 (hereinafter referred to as "R1" pixel) having a 1_1 emission area EMA1_1 in a triangular shape and a first color sub-pixel SPX1 (hereinafter referred to as "R2" pixel) in contact with the R1 pixel through each base and having a 1_2 emission area EMA1_2 in an inverted triangular shape can be alternately arranged on each pixel column in which the first color sub-pixel SPX1 is arranged, wherein, in the 1_2 emission area EMA1_2 in the inverted triangular shape, the R1 pixel (particularly the 1_1 emission area EMA1_1 of the R1 pixel) is turned upside down. A pair of R1 pixels and R2 pixels can be surrounded by the embankment BNK at the same time. For example, a pair of the 1_1 emission area EMA1_1 and the 1_2 emission area EMA1_2 can be surrounded by the embankment BNK at the same time.

[0118] Likewise, in each 3k-1 pixel column, two second color sub-pixels SPX2 that are vertically arranged continuously in the first direction DR1 and each include at least one second color light emitting element LD2 (e.g., at least one second color rod-type light emitting diode having a size of nanometer to micrometer) may form a pair. In an embodiment, a pair of second color sub-pixels SPX2 (particularly, a pair of second emission areas EMA2 of the second color sub-pixels SPX2) may have a triangular shape and an inverted triangular shape that are inverted relative to each other in the vertical direction. However, the present disclosure is not limited thereto.

[0119] In an embodiment, a pair of second color sub-pixels SPX2 may be symmetrically arranged while being arranged to contact each other in a region having a maximum width in the second direction DR2. For example, a pair of second color sub-pixels SPX2 each having a triangular shape and an inverted triangular shape may be symmetrically arranged in a vertical direction so that the bases of the sub-pixels contact each other.

[0120] For example, a second color sub-pixel SPX2 (hereinafter referred to as a "G1" pixel) having a 2_1 emission area EMA2_1 in a triangular shape and a second color sub-pixel SPX2 (hereinafter referred to as a "G2" pixel) in contact with the G1 pixel through each base and having a 2_2 emission area EMA2_2 in an inverted triangular shape can be alternately arranged on each pixel column in which the second color sub-pixel SPX2 is arranged, wherein, in the 2_2 emission area EMA2_2 in the inverted triangular shape, the 2_1 emission area EMA2_1 of the G1 pixel is turned upside down. A pair of G1 pixels and G2 pixels can be surrounded by the embankment BNK at the same time. For example, a pair of the 2_1 emission area EMA2_1 and the 2_2 emission area EMA2_2 can be surrounded by the embankment BNK at the same time.

[0121] In addition, in each 3k-th pixel column, two third color sub-pixels SPX3 that are vertically arranged continuously in the first direction DR1 and each include at least one third color light emitting element LD3 (for example, at least one third color rod-type light emitting diode having a size of nanometer to micrometer level) may form a pair. In an embodiment, a pair of third color sub-pixels SPX3 (particularly, third emission areas EMA3 of a pair of third color sub-pixels SPX3) may have a triangular shape and an inverted triangular shape that are inverted relative to each other in the vertical direction. However, the present disclosure is not limited thereto.

[0122] In an embodiment, a pair of third color sub-pixels SPX3 may be symmetrically arranged while being arranged to contact each other in a region having a maximum width in the second direction DR2. For example, a pair of third color sub-pixels SPX3 each having a triangular shape and an inverted triangular shape may be symmetrically arranged in a vertical direction so that the bases of the sub-pixels contact each other.

[0123] For example, a third color sub-pixel SPX3 (hereinafter referred to as "B1" pixel) having a 3_1 emission area EMA3_1 in a triangular shape and a third color sub-pixel SPX3 (hereinafter referred to as "B2" pixel) in contact with the B1 pixel through each base and having a 3_2 emission area EMA3_2 in an inverted triangular shape can be alternately arranged on each pixel column in which the third color sub-pixel SPX3 is arranged, wherein, in the 3_2 emission area EMA3_2 in the inverted triangular shape, the 3_1 emission area EMA3_1 of the B1 pixel is turned upside down. A pair of B1 pixels and B2 pixels can be surrounded by the embankment BNK at the same time. For example, a pair of 3_1 emission areas EMA3_1 and 3_2 emission areas EMA3_2 can be surrounded by the embankment BNK at the same time.

[0124] In addition, in an embodiment, sub-pixels SPX having an inverted shape (e.g., a triangular shape and an inverted triangular shape) may be alternately arranged in the first direction DR1 and the second direction DR2 in the display area DA. For example, a triangular R1 pixel, an inverted triangular G2 pixel, a triangular B1 pixel, an inverted triangular R2 pixel, a triangular G1 pixel, and an inverted triangular B2 pixel may be sequentially arranged in odd rows of the display area DA, and the sub-pixels SPX may be repeatedly arranged in the same manner. In this case, an inverted triangular R2 pixel, a triangular G1 pixel, an inverted triangular B2 pixel, a triangular R1 pixel, an inverted triangular G2 pixel, and a triangular B1 pixel may be sequentially arranged in even rows of the display area DA, and the sub-pixels SPX may be repeatedly arranged in the same manner. Therefore, the sub-pixels SPX may be more closely arranged in the display area DA.

[0125] For example, in each row of the display area DA, a first color sub-pixel SPX1 having a predetermined shape, a second color sub-pixel SPX2 having a shape in which the first color sub-pixel SPX1 is vertically inverted in the first direction DR1 and disposed adjacent to the first color sub-pixel SPX1 in the second direction DR2, and a third color sub-pixel SPX3 having the same shape as the first color sub-pixel SPX1 and disposed adjacent to the second color sub-pixel SPX2 in the second direction DR2 may be arranged in sequence. In addition, one first color sub-pixel SPX1, one second color sub-pixel SPX2, and one third color sub-pixel SPX3 arranged in sequence may form each pixel PXL.

[0126] For example, a trapezoidal first pixel PXL1 including a triangular R1 pixel, an inverted triangular G2 pixel, and a triangular B1 pixel and an inverted trapezoidal second pixel PXL2 including an inverted triangular R2 pixel, a triangular G1 pixel, and an inverted triangular B2 pixel may be alternately arranged in each row of the display area DA. Hereinafter, when any one or both of the first pixel PXL1 and the second pixel PXL2 are mentioned, they will be referred to as “pixel PXL”.

[0127] In an embodiment, the bank BNK may be formed to completely surround a pair of sub-pixels SPX (particularly, emission areas EMA of a pair of sub-pixels SPX). For example, the bank BNK may simultaneously surround the 1_1 emission area EMA1_1 and the 1_2 emission area EMA1_2 of a pair of first color sub-pixels SPX1. Similarly, the bank BNK may be formed to simultaneously surround the 2_1 emission area EMA2_1 and the 2_2 emission area EMA2_2 of a pair of second color sub-pixels SPX2, and to simultaneously surround the 3_1 emission area EMA3_1 and the 3_2 emission area EMA3_2 of a pair of third color sub-pixels SPX3.

[0128] In addition, the bank BNK may include at least two regions of different widths in a region corresponding to each of a pair of sub-pixels SPX (e.g., a region corresponding to each of the emission regions EMA of the sub-pixels SPX). For example, the bank BNK may have a first bank width Wb1 in a portion of the region corresponding to each sub-pixel SPX, and a second bank width Wb2 different from the first bank width Wb1 in another portion of the region.

[0129] For example, in the case where a pair of sub-pixels SPX are continuously arranged in each pixel column so that their bases contact each other while each having a triangular and inverted triangular emission area EMA, the bank BNK may be provided to simultaneously surround the emission area EMA of the pair of sub-pixels SPX while having a quadrilateral shape in an area corresponding to the pair of sub-pixels SPX. In this case, the bank BNK may have a shape in which the width in the second direction DR2 gradually changes in the first direction DR1.

[0130] For example, in the case where a pair of sub-pixels SPX are symmetrically arranged in the first direction DR1 while each having an emission area EMA in an isosceles triangle shape symmetrical in the second direction DR2, the bank BNK may have a rhombus shape completely surrounding the emission area EMA of the pair of sub-pixels SPX. In addition, in an embodiment, the bank BNK may have a shape in which the bank BNK is connected in one piece throughout the entire display area DA. For example, the bank BNK may be formed into a mesh pattern including rhombus-shaped openings corresponding to the pair of sub-pixels SPX.

[0131] exist Figure 8 In an embodiment, the sub-pixel SPX can be divided into Figure 7 Compared with the embodiment of the present invention, the sub-pixel SPX can be compactly arranged in the display area DA while ensuring the width of the sub-pixel SPX (especially the width of each emission area EMA supplied by the light-emitting element LD) to accommodate the droplet DRL including the light-emitting element LD. Therefore, a display device with high resolution can be realized.

[0132] Figure 9a and Figure 9b It shows that according to Figure 7 and Figure 8 More specifically, Figure 9a It is shown that the size of the droplet DRL can be taken into account and formed therein Figure 7 The pixel area of ​​one pixel PXL shown in FIG. Figure 9b Shown according to Figure 8 The implementation method can be set in the Figure 9aThe plurality of pixels PXL in the area occupied by the pixel PXL.

[0133] First, refer to Figures 4 to 7 and Figure 9a , Figure 7 Each pixel PXL shown in the figure can be formed in a unit pixel area having a predetermined vertical length L1 in the first direction DR1 (e.g., the length of the pixel PXL) and a predetermined horizontal length L2 in the second direction DR2 (e.g., the width of the pixel PXL). The area of ​​the unit pixel area (e.g., L1*L2) can be set in various ways according to the resolution of the display device and / or the structure of the pixel PXL. The width Ws of each sub-pixel SPX (particularly the emission area EMA of each sub-pixel SPX) in the second direction DR2 can be set to accommodate the droplets DRL of the LED solution SOL supplied to each sub-pixel SPX. For example, in a case where the droplets DRL including the light-emitting element LD have an average first width W1 and the sum of the first width W1 and the error range (e.g., the dripping error range) is the second width W2, the emission area EMA of each sub-pixel SPX can be designed to have a width Ws of the second width W2 or greater.

[0134] In other words, in the case where at least one light emitting element LD is supplied to each emission area EMA by an inkjet printing method, the emission area EMA of each sub-pixel SPX should have a width Ws greater than the first width W1 of the droplet DRL including the at least one light emitting element LD. In addition, the first width W1 of the droplet DRL can be set to be at least greater than the length L of the light emitting element LD. For example, the droplet DRL of the LED solution SOL should be dropped into each emission area EMA, which is large enough to supply multiple light emitting elements LD to each emission area EMA. Therefore, due to the length L of the light emitting element LD and / or the size of the droplet DRL used to supply the light emitting element LD to each emission area EMA, there may be a limitation in reducing the width Ws of the sub-pixel SPX (especially the emission area EMA).

[0135] refer to Figures 4 to 9bAccording to an embodiment of the present disclosure, the bank BNK may be formed in a polygonal shape that is symmetrical up and down in the first direction DR1, and a pair of sub-pixels SPX that are adjacent to each other in the vertical direction and have the same color may be arranged in the bank BNK in the first direction DR1. In an embodiment, each of the pair of sub-pixels SPX having the same color (particularly the emission area EMA of the pair of sub-pixels SPX having the same color) may have a shape in which the width in the second direction DR2 gradually changes in the first direction DR1, such as a triangular shape (or an inverted triangular shape). In addition, the pair of sub-pixels SPX having the same color may be arranged symmetrically while contacting each other in an area having the maximum width (for example, in a base where each emission area EMA has the maximum width). The bank BNK may have a quadrilateral shape, such as a rhombus shape, which surrounds the emission area EMA of the pair of sub-pixels SPX having the same color. For example, the bank BNK may be formed in a mesh pattern including a rhombus-shaped opening corresponding to a pair of emission areas EMA corresponding to the pair of sub-pixels SPX having the same color.

[0136] In the above-described embodiment, a display device having a high resolution can be realized while maintaining a width Ws of each sub-pixel SPX of a size sufficient to accommodate the droplet DRL including the light emitting element LD. Figure 9a In the embodiment of FIG. 1 , one sub-pixel SPX is provided in each unit region (ie, each sub-pixel region) surrounded by the bank BNK. Figure 9b In the embodiment, each unit region surrounded by the bank BNK having a symmetrical shape in the vertical direction is divided into two regions, and emission regions EMA of two sub-pixels SPX having the same color and arranged continuously in the first direction DR1 are formed in the unit region. Figure 9a Compared with the implementation method of Figure 9b In the embodiment, a larger number of sub-pixels SPX, for example, twice the number of sub-pixels SPX, may be arranged in the first direction DR1.

[0137] exist Figure 9a In the embodiment of FIG. 1 , each sub-pixel SPX and the bank BNK are arranged in a quadrilateral shape. Figure 9b In the embodiment of FIG. 1 , two sub-pixels SPX of a triangular shape (or an inverted triangular shape) symmetrical with respect to each other so that their bases are in contact with each other are arranged in the rhombus-shaped bank BNK. Figure 9a Compared with the implementation method of Figure 9b In the embodiment, a larger number of sub-pixels SPX, for example, twice the number of sub-pixels SPX, may be arranged in the second direction DR2.

[0138] In other words, Figure 9aCompared with the implementation method of Figure 9b In the embodiment of FIG. 1 , a larger number of sub-pixels SPX, for example, four times the number of sub-pixels SPX, can be arranged in the same area L1*L2. Figure 9b In the case of the embodiment of the present invention, a display device with high resolution can be manufactured. For example, assuming that the display area DA has the same area and the width Ws of each sub-pixel SPX (particularly the emission area EMA) is set to be the same, the use Figure 9b The display device of the embodiment can be manufactured to have up to Figure 9a The pixel density of the display device of an embodiment is twice the pixel density ppi.

[0139] Furthermore, the bank BNK is formed to completely surround the emission area EMA of a pair of sub-pixels SPX having the same color and including the same color light emitting elements LD, so that a space having a width Ws sufficient to accommodate a droplet DRL including a light emitting element LD in each unit area defined by the bank BNK can be ensured.

[0140] In addition, in an embodiment of the present disclosure, each subpixel SPX may include a light source unit LSU including at least one light emitting element LD. In addition, the at least one light emitting element LD may be connected between the first electrode ELT1 and the second electrode ELT2 disposed in each emission area EMA to be driven.

[0141] In addition, in an embodiment of the present disclosure, even if a pair of emission areas EMA corresponding to a pair of sub-pixels SPX are not divided by the bank BNK but are completely surrounded by the bank BNK, the first electrode ELT1 and / or the second electrode ELT2 may be formed separately for each emission area EMA. In this case, each of the pair of sub-pixels SPX may be driven separately. In other words, each of the sub-pixels SPX may form a single sub-pixel SPX that may be driven independently.

[0142] Fig.10a , Fig.10b and Fig.11 are plan views each showing a sub-pixel SPX according to an embodiment of the present disclosure. More specifically, Fig.10a , Fig.10b and Fig.11 It shows that according to Figure 8A plan view of any pair of sub-pixels SPXp disposed in the display area DA according to an embodiment of the present invention. For example, a pair of sub-pixels SPXp may be any pair of a pair of first color sub-pixels SPX1, a pair of second color sub-pixels SPX2, and a pair of third color sub-pixels SPX3, and the pair of first color sub-pixels SPX1, the pair of second color sub-pixels SPX2, and the pair of third color sub-pixels SPX3 may have substantially the same or similar structures. In an embodiment, Fig.10a , Fig.10b and Fig.11 The structure of a pair of sub-pixels SPXp is shown focusing on the emission area EMA in which the light emitting element LD of each sub-pixel SPX is arranged.

[0143] First, refer to Figures 4 to 10a , a pair of sub-pixels SPXp may include two sub-pixels SPXa and SPXb symmetrically arranged in each emission area EMA surrounded by the bank BNK. For example, a pair of sub-pixels SPXp may include a triangular sub-pixel (hereinafter referred to as "SPXa pixel") and an inverted triangular sub-pixel symmetrical to the SPXa pixel (hereinafter referred to as "SPXb pixel").

[0144] When describing the embodiments of the present disclosure, for convenience, the shape of the sub-pixel SPX will be described by focusing on the emission area EMA in which the light emitting element LD of each sub-pixel SPX is arranged. For example, the SPXa pixel may have a triangular emission area EMAa, and the SPXb pixel may have an inverted triangular emission area EMAb.

[0145] Meanwhile, in an embodiment, each sub-pixel SPX may further include a pixel circuit region in which each pixel circuit PXC is formed. The pixel circuit region may have a shape that is the same as or different from the shape of the emission region EMA of the corresponding sub-pixel SPX, and each pixel circuit region may at least partially overlap with each emission region EMA.

[0146] In an embodiment, each sub-pixel SPX may include at least one pair of first electrodes ELT1 and second electrodes ELT2 disposed in each emission region EMA and at least one light emitting element LD connected between the first electrode ELT1 and the second electrode ELT2. For example, each first color sub-pixel SPX1 may include at least one pair of first electrodes ELT1 and second electrodes ELT2 disposed in each emission region EMA and a plurality of first color light emitting elements LD1 connected in parallel between the first electrode ELT1 and the second electrode ELT2. Similarly, each second color sub-pixel SPX2 may include at least one pair of first electrodes ELT1 and second electrodes ELT2 disposed in each emission region EMA and a plurality of second color light emitting elements LD2 connected in parallel between the first electrode ELT1 and the second electrode ELT2, and each third color sub-pixel SPX3 may include at least one pair of first electrodes ELT1 and second electrodes ELT2 disposed in each emission region EMA and a plurality of third color light emitting elements LD3 connected in parallel between the first electrode ELT1 and the second electrode ELT2.

[0147] In addition, in an embodiment, each sub-pixel SPX may further include a first partition wall PW1 and a first contact electrode CNE1 overlapping each first electrode ELT1, and a second partition wall PW2 and a second contact electrode CNE2 overlapping each second electrode ELT2. In addition, each sub-pixel SPX may further include a first connection electrode CNL1 connected to the first electrode ELT1 and a second connection electrode CNL2 connected to the second electrode ELT2.

[0148] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be arranged to be spaced apart from each other in each emission area EMA, and arranged so that at least a portion thereof faces each other. For example, the first electrode ELT1 and the second electrode ELT2 may be arranged to extend in a first direction DR1 in each emission area EMA, and may be arranged side by side to be spaced apart from each other by a predetermined distance in a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto. For example, the shapes and / or mutual arrangement relationships of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0149] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a single layer structure or a multilayer structure. For example, each first electrode ELT1 may have a multilayer structure including a first reflective electrode and a first conductive cover layer, and each second electrode ELT2 may have a multilayer structure including a second reflective electrode and a second conductive cover layer.

[0150] In an embodiment, the first electrode ELT1 may be connected to the first connection electrode CNL1. For example, the first electrode ELT1 may be integrally connected to the first connection electrode CNL1. For example, the first electrode ELT1 may be formed by at least one branch branched from the first connection electrode CNL1. In the case where the first electrode ELT1 and the first connection electrode CNL1 are integrated with each other, the first connection electrode CNL1 may be regarded as a region of the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first electrode ELT1 and the first connection electrode CNL1 may be formed separately from each other and electrically connected to each other through, for example, at least one contact hole or through-hole (not shown).

[0151] In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions in the corresponding emission area EMA. For example, in the case where the first electrode ELT1 extends in the first direction DR1, the first connection electrode CNL1 may extend in the second direction DR2 intersecting the first direction DR1. In an embodiment, the first connection electrode CNL1 may have a single-layer structure or a multi-layer structure. For example, the first connection electrode CNL1 may have the same cross-sectional shape as the first electrode ELT1.

[0152] In an implementation, the first electrode ELT1 and the first connection electrode CNL1 may be connected to the pixel circuit PXC of each sub-pixel SPX through the first contact hole CH1, for example, Figure 5a to Figure 5c . In an embodiment, the first contact hole CH1 may be disposed in the periphery of each emission area EMA. For example, the first contact hole CH1 may be disposed around the corresponding emission area EMA to overlap with the bank BNK. In this case, it is possible to prevent the pattern from being reflected when the first contact hole CH1 is covered by the bank BNK. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, at least one first contact hole CH1 may be disposed in the emission area EMA.

[0153] In an embodiment, each pixel circuit PXC may be disposed under the light emitting element LD disposed in the corresponding emission area EMA. For example, each pixel circuit PXC may be formed in a pixel circuit layer under the light emitting element LD to be connected to the first electrode ELT1 through the first contact hole CH1.

[0154] In an embodiment, the second electrode ELT2 may be connected to the second connection electrode CNL2. For example, the second electrode ELT2 may be integrally connected to the second connection electrode CNL2. For example, the second electrode ELT2 may be formed by at least one branch branched from the second connection electrode CNL2. In the case where the second electrode ELT2 and the second connection electrode CNL2 are integrally formed, the second connection electrode CNL2 may be regarded as a region of the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the second electrode ELT2 and the second connection electrode CNL2 may be formed separately from each other and electrically connected to each other by, for example, at least one contact hole or through-hole (not shown).

[0155] In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions in the corresponding emission area EMA. For example, in the case where the second electrode ELT2 extends in the first direction DR1, the second connection electrode CNL2 may extend in the second direction DR2 intersecting the first direction DR1. In an embodiment, the second connection electrode CNL2 may have a single-layer structure or a multi-layer structure. For example, the second connection electrode CNL2 may have the same cross-sectional shape as the second electrode ELT2.

[0156] In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may be connected to a second power supply VSS. For example, the second electrode ELT2 and the second connection electrode CNL2 may be connected to the second power supply VSS via a second contact hole CH2 and a power line (not shown) connected to the second contact hole CH2. In an embodiment, the second contact hole CH2 may be disposed in the periphery of each emission area EMA. For example, the second contact hole CH2 may be disposed around the corresponding emission area EMA to overlap with the embankment BNK. In this case, the pattern may be prevented from being reflected when the second contact hole CH2 is covered by the embankment BNK. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, at least one second contact hole CH2 may be disposed in the emission area EMA.

[0157] In an embodiment, a region of a power line for supplying a second power source VSS may be provided in a pixel circuit layer below the light emitting element LD. For example, the power line may be provided in a pixel circuit layer below the light emitting element LD to be connected to the second electrode ELT2 through a second contact hole CH2. However, the present disclosure is not limited thereto, and the position of the power line may be changed variously.

[0158] In an embodiment, the first partition wall PW1 may be disposed below the first electrode ELT1 to overlap with the region of the first electrode ELT1. The second partition wall PW2 may be disposed below the second electrode ELT2 to overlap with the region of the second electrode ELT2. The first partition wall PW1 and the second partition wall PW2 may be disposed at positions spaced apart from each other in each emission area EMA, and the regions of the first electrode ELT1 and the second electrode ELT2 may protrude upward, respectively. For example, the first electrode ELT1 may be disposed on the first partition wall PW1 so as to protrude in the height direction through the first partition wall PW1. The second electrode ELT2 may be disposed on the second partition wall PW2 so as to protrude in the height direction through the second partition wall PW2.

[0159] In an embodiment, at least one light emitting element LD (for example, a plurality of light emitting elements LD) may be arranged between the first electrode ELT1 and the second electrode ELT2 of each sub-pixel SPX. For example, at least one first color light emitting element LD1 may be disposed between the first electrode ELT1 and the second electrode ELT2 of the first color sub-pixel SPX1. At least one second color light emitting element LD2 may be disposed between the first electrode ELT1 and the second electrode ELT2 of the second color sub-pixel SPX2. At least one third color light emitting element LD3 may be disposed between the first electrode ELT1 and the second electrode ELT2 of the third color sub-pixel SPX3. For example, in each emission area EMA, a plurality of light emitting elements LD may be connected in parallel in an area where the first electrode ELT1 and the second electrode ELT2 are disposed to face each other.

[0160] Despite Fig.10a In the embodiment, all of the light emitting elements LD have been shown to be arranged in the second direction DR2 (eg, in the horizontal direction), but the arrangement direction of the light emitting elements LD is not limited thereto. For example, at least one of the light emitting elements LD may be arranged in a diagonal direction.

[0161] The light emitting element LD is electrically connected between the first electrode ELT1 and the second electrode ELT2 of the corresponding sub-pixel SPX. For example, the first end EP1 of each light emitting element LD can be electrically connected to the first electrode ELT1 of the corresponding sub-pixel SPX, and the second end EP2 of the light emitting element LD can be electrically connected to the second electrode ELT2 of the corresponding sub-pixel SPX.

[0162] In an embodiment, the first end EP1 of the light emitting element LD may be electrically connected to the corresponding first electrode ELT1 through at least one contact electrode (e.g., the first contact electrode CNE1) rather than being directly disposed on the first electrode ELT1. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first end EP1 of the light emitting element LD may be in direct contact with the corresponding first electrode ELT1 and electrically connected to the first electrode ELT1.

[0163] Similarly, the second end EP2 of the light emitting element LD can be electrically connected to the corresponding second electrode ELT2 through at least one contact electrode (e.g., the second contact electrode CNE2), rather than being directly disposed on the second electrode ELT2. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the second end EP2 of the light emitting element LD can be in direct contact with the corresponding second electrode ELT2 and electrically connected to the second electrode ELT2.

[0164] In an embodiment, each of the light emitting elements LD may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size, for example, in the range of nanometer scale to micrometer scale. For example, each of the first color light emitting element LD1, the second color light emitting element LD2, and the third color light emitting element LD3 may be formed of an ultra-small rod-type light emitting diode in the range of nanometer scale to micrometer scale. Figure 1a and Figure 1b , Figure 2a and Figure 2b as well as Figure 3a and Figure 3b any one of which is shown.

[0165] In an embodiment, the light emitting element LD may be prepared in a diffused form in the LED solution SOL, and then supplied to each emission area EMA by an inkjet printing method or the like. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to each emission area EMA. Here, if a predetermined voltage is supplied through the first electrode ELT1 and the second electrode ELT2 of each sub-pixel SPX, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting element LD is aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting element LD has been aligned, the solvent may be removed by a volatilization method or other methods. In this way, the light emitting element LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, since the first contact electrode CNE1 and the second contact electrode CNE2 are respectively formed on the first end EP1 and the second end EP2 of the light emitting element LD, the light emitting element LD may be reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0166] In an embodiment, each first contact electrode CNE1 is formed on both the first end EP1 of the light emitting element LD and at least a portion of the corresponding first electrode ELT1, whereby the first end EP1 of the light emitting element LD is physically and / or electrically connected to the first electrode ELT1. Similarly, each second contact electrode CNE2 is formed on both the second end EP2 of the light emitting element LD and at least a portion of the corresponding second electrode ELT2, whereby the second end EP2 of the light emitting element LD is physically and / or electrically connected to the second electrode ELT2.

[0167] The light emitting elements LD disposed in each emission area EMA may be aggregated to form a light source unit LSU of a corresponding sub-pixel SPX. For example, if a driving current flows through at least one sub-pixel SPX during each frame period, the light emitting element LD connected between the first electrode ELT1 and the second electrode ELT2 of the sub-pixel SPX in a forward direction may emit light having a brightness corresponding to the driving current.

[0168] In an embodiment, a pair of emission areas EMA corresponding to a pair of sub-pixels SPXp may be completely surrounded by the bank BNK. The first electrode ELT1 and / or the second electrode ELT2 of each sub-pixel SPX may be individually formed for each emission area EMA.

[0169] For example, the first electrode ELT1 of each of the SPXa pixel and the SPXb pixel constituting any pair of sub-pixels SPXp may be separated from each other. For example, the first electrodes ELT1 of the sub-pixels SPX (including the SPXa pixel and the SPXb pixel) disposed in the display area DA may be integrated with each other to be supplied with an alignment voltage during the alignment process of the light-emitting element LD, and then divided into separate patterns for each emission area EMA. Therefore, the first electrode ELT1 of the SPXa pixel may be separately disposed in the emission area EMAa corresponding to the SPXa pixel, and the first electrode ELT1 of the SPXb pixel may be separately disposed in the emission area EMAb corresponding to the SPXb pixel.

[0170] Meanwhile, the second electrodes ELT2 of the sub-pixels SPX may be separated from each other or connected to each other. For example, the second electrodes ELT2 of the sub-pixels SPX may be directly / indirectly connected to each other throughout the entire display area DA.

[0171] In an embodiment of the present disclosure, the first electrode ELT1 and the second electrode ELT2 of each of the sub-pixels SPX may be repeated in a substantially constant pattern regardless of the shape of the corresponding emission area EMA. For example, the first electrode ELT1 provided in a pair of sub-pixels SPXp (i.e., the first electrode ELT1 of the SPXa pixel and the first electrode ELT1 of the SPXb pixel) may have substantially the same shape. In addition, the second electrode ELT2 provided in a pair of sub-pixels SPXp (i.e., the second electrode ELT2 of the SPXa pixel and the second electrode ELT2 of the SPXb pixel) may have substantially the same shape. At the same time, the first connection electrode CNL1 and the second connection electrode CNL2 of each of the sub-pixels SPX may be repeated in a constant pattern regardless of the shape of the corresponding emission area EMA, or may have a length matching the shape of the corresponding emission area EMA. For example, the first connection electrode CNL1 of the SPXa pixel may be shorter than the first connection electrode CNL1 of the SPXb pixel, and the second connection electrode CNL2 of the SPXa pixel may be longer than the second connection electrode CNL2 of the SPXb pixel.

[0172] However, the present disclosure is not limited thereto. In other words, the shapes of the first electrode ELT1 and / or the second electrode ELT2 may be variously changed.

[0173] For example, Fig.10b As shown in, in another embodiment of the present disclosure, the first electrode ELT1 and the second electrode ELT2 and / or the first connection electrode CNL1 and the second connection electrode CNL2 arranged in a pair of sub-pixels SPXp may have a shape in which they are symmetrical to each other to match the shape of each emission area EMA. For example, the first electrode ELT1 and the first connection electrode CNL1 arranged in a pair of sub-pixels SPXp (i.e., the first electrode ELT1 and the first connection electrode CNL1 of the SPXa pixel and the first electrode ELT1 and the first connection electrode CNL1 of the SPXb pixel) may have a shape in which they are symmetrical to each other relative to a boundary line, along which a pair of sub-pixels SPXp (particularly, their emission areas EMA) are in contact with each other. Similarly, the second electrode ELT2 and the second connection electrode CNL2 arranged in a pair of sub-pixels SPXp (i.e., the second electrode ELT2 and the second connection electrode CNL2 of the SPXa pixel and the second electrode ELT2 and the second connection electrode CNL2 of the SPXb pixel) may have a shape in which they are symmetrical to each other relative to a boundary line, along which a pair of sub-pixels SPXp are in contact with each other.

[0174] at the same time, Fig.10a and Fig.10bThe following embodiment is shown: the first electrode ELT1 extending in the first direction DR1 and the first connection electrode CNL1 extending in the second direction DR2 are integrally connected to each other, and similarly, the second electrode ELT2 extending in the first direction DR1 and the second connection electrode CNL2 extending in the second direction DR2 are integrally connected to each other. However, the present disclosure is not limited thereto. For example, Fig.11 As shown in , each first electrode ELT1 and / or each second electrode ELT2 may have a strip shape extending in any one direction (e.g., the first direction DR1). In an embodiment, the first electrode ELT1 and the second electrode ELT2 disposed in each emission area EMA may be arranged in parallel with each other. However, the present disclosure is not limited thereto.

[0175] In addition, in an embodiment, the first electrodes ELT1 provided in each emission area EMA may be separated from each other and connected to each pixel circuit PXC through each first contact hole CH1 in each sub-pixel SPX. In addition, the second electrodes ELT2 of a plurality of sub-pixels SPX may be formed to be connected to each other. In this case, a second contact hole CH2 for connecting the second electrode ELT2 to a second power line or the like may be formed for each sub-pixel SPX, or one second contact hole may be formed for each of the plurality of sub-pixels SPX. Alternatively, in yet another embodiment, the second contact hole CH2 may be formed outside the display area DA. In other words, in the present disclosure, the internal structure of the sub-pixel SPX may be changed variously.

[0176] Fig.12 and Fig.13 are cross-sectional views each showing a structure of a sub-pixel SPX according to an embodiment of the present disclosure. For example, Fig.12 and Fig.13 According to different implementation methods Fig.10a More specifically, Fig.12 and Fig.13 Various embodiments regarding the shapes of the first and second partition walls PW1 and PW2 and the bank BNK are shown.

[0177] In an embodiment, Fig.12 and Fig.13 Shows Fig.10a The cross-sectional structure of the sub-pixel SPXa of the display area DA is taken as an example of any one sub-pixel SPX. The cross-sectional structures of the sub-pixels SPX arranged in the display area DA may be substantially the same or similar to each other. Therefore, for convenience, Fig.12 and Fig.13 Through Fig.10a The cross section of the SPXa pixel corresponding to the line II' fully shows the structure of each sub-pixel SPX.

[0178] refer to Fig.12 and Fig.13 as well as Figures 1a to 11 , the pixel circuit layer PCL and the display element layer LDL may be sequentially placed on the substrate SUB of the display panel PNL. In an embodiment, the pixel circuit layer PCL and the display element layer LDL may be formed throughout the entire display area DA.

[0179] In an embodiment, the pixel circuit layer PCL may include circuit elements forming the pixel circuit PXC of each of the sub-pixels SPX. The display element layer LDL may include a light emitting element LD of each of the sub-pixels SPX.

[0180] In an embodiment, the pixel circuit layer PCL includes a plurality of circuit elements disposed in the display area DA. For example, the pixel circuit layer PCL may include a plurality of circuit elements formed in each emission area EMA and / or in a peripheral area PA of the emission area EMA to constitute a pixel circuit PXC of each sub-pixel SPX. For example, the pixel circuit layer PCL may include a plurality of transistors disposed in each emission area EMA and / or in a peripheral area PA thereof, such as Figure 5a and Figure 5b The first transistor T1 and the second transistor T2. Fig.12 and Fig.13 , but the pixel circuit layer PCL may include a storage capacitor Cst disposed in each sub-pixel region (e.g., a region including an emission region EMA of each sub-pixel SPX and a pixel circuit region), various signal lines (e.g., Figure 5a and Figure 5b Scan lines (e.g., the i-th scan line Si) and data lines (e.g., the j-th data line Dj) and various power lines (e.g., a first power line (not shown) and a second power line PL for transmitting a first power supply VDD and a second power supply VSS, respectively) connected to the pixel circuit PXC and / or the light emitting element LD.

[0181] In an embodiment, a plurality of transistors (e.g., a first transistor T1 and a second transistor T2) provided in each pixel circuit PXC may have substantially the same or similar cross-sectional structures. However, the present disclosure is not limited thereto. In another embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0182] In addition, the pixel circuit layer PCL includes a plurality of insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the substrate SUB.

[0183] In an embodiment, the buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two layers. In the case where the buffer layer BFL has a multilayer structure, the corresponding layers may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0184] In an embodiment, each of the first transistor T1 and the second transistor T2 includes a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Fig.12 and Fig.13 It is shown that each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL, but the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 provided in at least one transistor forming each pixel circuit PXC may be integrally formed with the corresponding semiconductor layer SCL.

[0185] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the substrate SUB on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0186] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0187] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD to overlap at least a portion of the semiconductor layer SCL.

[0188] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL and the gate electrode GE, with at least one interlayer insulating layer ILD interposed therebetween. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be connected to the first region and the second region of the semiconductor layer SCL, respectively, through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0189] In an embodiment, at least one transistor (eg, Figure 5a and Figure 5b Any one of the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 of the passivation layer may be electrically connected to the first electrode ELT1 of the light source unit LSU disposed on the passivation layer PSV through the first contact hole CH1 passing through the passivation layer PSV.

[0190] In an embodiment, at least one signal line and / or power line connected to each sub-pixel SPX may be provided on the same layer as the layer of one electrode of each of the circuit elements forming the pixel circuit PXC. For example, the second power line PL for supplying the second power source VSS may be provided on the same layer as the layer of the gate electrode GE of the first transistor T1 and the second transistor T2, and is electrically connected to the second electrode ELT2 of the light source unit LSU provided on the passivation layer PSV through both the bridge pattern BRP provided on the same layer as the layer of the first transistor electrode ET1 and the second transistor electrode ET2 and through at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL, etc. may be changed in various ways.

[0191] In an embodiment, the display element layer LDL may include a plurality of light emitting elements LD disposed over the pixel circuit layer PCL in each emission area EMA. In addition, the display element layer LDL may further include at least one insulating layer and / or insulating pattern disposed around the light emitting element LD.

[0192] For example, the display element layer LDL may include a first electrode ELT1 and a second electrode ELT2 disposed in each emission region EMA, a light emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2 corresponding to each other, and a first contact electrode CNE1 and a second contact electrode CNE2 disposed on a first end EP1 and a second end EP2 of the light emitting element LD, respectively. In addition, the display element layer LDL may further include, for example, at least one conductive layer and / or at least one insulating layer (or insulating pattern). For example, the display element layer LDL may further include a first partition wall PW1 and a second partition wall PW2, a bank BNK, and at least one of a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, and a fourth insulating layer INS4.

[0193] In an implementation, the first partition wall PW1 and the second partition wall PW2 may be disposed on the pixel circuit layer PCL. For example, the first partition wall PW1 and the second partition wall PW2 may be disposed in the corresponding emission area EMA to be spaced apart from each other by a predetermined distance.

[0194] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material having an inorganic material or an organic material. In addition, each of the first partition wall PW1 and the second partition wall PW2 may have a single-layer structure or a multi-layer structure. In other words, the material and / or stacking structure of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without particular limitation.

[0195] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may have various shapes. Fig.12 As shown in , each of the first partition wall PW1 and the second partition wall PW2 may have a semicircular or semi-elliptical cross-section, the width of which gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side. Alternatively, as Fig.13 As shown in , each of the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side. In other words, in the present disclosure, the shape of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited.

[0196] In an embodiment, the first and second electrodes ELT1 and ELT2 and the first and second connection electrodes CNL1 and CNL2 may be disposed in each emission area EMA where the first and second partition walls PW1 and PW2 are disposed.

[0197] In an embodiment, the first electrode ELT1 and the second electrode ELT2 may be disposed at positions spaced apart from each other by a predetermined distance on a substrate SUB on which a pixel circuit layer PCL and / or first and second partition walls PW1 and PW2 have been formed. The first connection electrode CNL1 and the second connection electrode CNL2 may be integrally connected to the first electrode ELT1 and the second electrode ELT2, respectively.

[0198] In an embodiment, the first electrode ELT1 may be disposed on the corresponding first partition wall PW1, and the second electrode ELT2 may be disposed on the corresponding second partition wall PW2. In an embodiment, any one of the first electrode ELT1 and the second electrode ELT2 may be an anode electrode, and the other may be a cathode electrode.

[0199] The first electrode ELT1 and the second electrode ELT2 may have shapes corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively. For example, each first electrode ELT1 may protrude in the height direction of the substrate SUB through the corresponding first partition wall PW1, and have a curved surface or an inclined surface corresponding to the cross section of the first partition wall PW1. In addition, each first electrode ELT1 may be formed of a single-layer structure or a multi-layer structure. For example, each first electrode ELT1 may include a first reflective electrode REF1 and a first conductive cover layer CPL1, the first reflective electrode REF1 protruding in the height direction of the substrate SUB through the first partition wall PW1 disposed therebelow, and facing the first end EP1 of the adjacent light emitting element LD, the first conductive cover layer CPL1 being selectively disposed above the first reflective electrode REF1. In an embodiment, the first reflective electrode REF1 may include at least one reflective conductive layer. In addition, the first reflective electrode REF1 may also selectively include another conductive layer, such as at least one transparent electrode layer.

[0200] Likewise, each second electrode ELT2 may protrude in the height direction of the substrate SUB through the corresponding second partition wall PW2, and have a curved surface or an inclined surface corresponding to the cross section of the second partition wall PW2. For example, each second electrode ELT2 may include a second reflective electrode REF2 and a second conductive cover layer CPL2, the second reflective electrode REF2 protruding in the height direction of the substrate SUB through the second partition wall PW2 disposed therebelow, and facing the second end EP2 of the adjacent light emitting element LD, the second conductive cover layer CPL2 being selectively disposed above the second reflective electrode REF2. In an embodiment, the second reflective electrode REF2 may include at least one reflective conductive layer. In addition, the second reflective electrode REF2 may also selectively include another conductive layer, such as at least one transparent electrode layer.

[0201] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may have the same height H1, so that the first electrode ELT1 and the second electrode ELT2 may have the same height. Therefore, if the first electrode ELT1 and the second electrode ELT2 have the same height, the light emitting element LD can be more reliably connected between the first electrode ELT1 and the second electrode ELT2. However, the present disclosure is not limited thereto. For example, the shape, structure and / or mutual arrangement relationship of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0202] In an embodiment, each of the first reflective electrode REF1 and the second reflective electrode REF2 may include a conductive material having a predetermined reflectivity. For example, each of the first reflective electrode REF1 and the second reflective electrode REF2 may include at least one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and alloys thereof; however, the present disclosure is not limited thereto. In other words, each of the first reflective electrode REF1 and the second reflective electrode REF2 may include various reflective conductive materials.

[0203] The first reflective electrode REF1 and the second reflective electrode REF2 allow light emitted from opposite ends of each light emitting element LD (i.e., the first end EP1 and the second end EP2 of each light emitting element LD) to propagate in a direction in which an image is displayed (e.g., in a front direction of the display panel PNL). Specifically, if each of the first reflective electrode REF1 and the second reflective electrode REF2 has a curved surface or an inclined surface corresponding to the shape of a corresponding one of the first partition wall PW1 and the second partition wall PW2, light emitted from the first end EP1 and the second end EP2 of each light emitting element LD may be reflected by the first reflective electrode REF1 and the second reflective electrode REF2, whereby the light may propagate more efficiently in a front direction of the display panel PNL (e.g., an upward direction of the substrate SUB). Thus, the efficiency of light emitted from the light emitting element LD may be improved.

[0204] The first conductive cover layer CPL1 and the second conductive cover layer CPL2 may be selectively disposed over the first reflective electrode REF1 and the second reflective electrode REF2. For example, the first conductive cover layer CPL1 may be disposed on the first reflective electrode REF1 to cover the first reflective electrode REF1, and the second conductive cover layer CPL2 may be disposed on the second reflective electrode REF2 to cover the second reflective electrode REF2.

[0205] Each of the first conductive cover layer CPL1 and the second conductive cover layer CPL2 may be formed of a transparent conductive material such as ITO or IZO to minimize the loss of light emitted from the light emitting element LD. However, the present disclosure is not limited thereto. For example, the materials of the first conductive cover layer CPL1 and the second conductive cover layer CPL2 may be changed in various ways.

[0206] The first conductive cover layer CPL1 and the second conductive cover layer CPL2 may prevent the first reflective electrode REF1 and the second reflective electrode REF2 from being damaged due to a failure that may occur during a process of manufacturing the display panel PNL, etc. In addition, the first conductive cover layer CPL1 and the second conductive cover layer CPL2 may enhance adhesion between the substrate SUB provided with the pixel circuit layer PCL, etc. and the first reflective electrode REF1 and the second reflective electrode REF2. In an embodiment, at least one of the first conductive cover layer CPL1 and the second conductive cover layer CPL2 may be omitted.

[0207] In an embodiment, a first insulating layer INS1 may be provided in each emission region EMA in which the first electrode ELT1 and the second electrode ELT2 are provided. In an embodiment, the first insulating layer INS1 may be provided between the pixel circuit layer PCL and the light emitting element LD. The first insulating layer INS1 may be used to stably support the light emitting element LD and prevent the light emitting element LD from shifting from its correct position. In an embodiment, the first insulating layer INS1 may be formed in an independent pattern on a portion of the emission region EMA (e.g., a portion between the first electrode ELT1 and the second electrode ELT2), but the present disclosure is not limited thereto.

[0208] In an embodiment, at least one light emitting element LD (e.g., a plurality of light emitting elements LD) may be supplied and aligned in each emission region EMA in which the first insulating layer INS1 is disposed. In an embodiment, when a predetermined voltage is applied to the first electrode ELT1 and the second electrode ELT2, the light emitting element LD may be self-aligned by an electric field formed between the first electrode ELT1 and the second electrode ELT2. Therefore, the light emitting element LD may be arranged between the first electrode ELT1 and the second electrode ELT2 of the corresponding emission region EMA.

[0209] The shape and / or structure of each of the light emitting elements LD is not limited to Fig.12 and Fig.13 For example, each light emitting element LD may have various well-known shapes, cross-sectional structures and / or connection structures.

[0210] In an embodiment, a second insulating layer INS2 covering a portion of a corresponding upper surface of the light emitting element LD may be disposed in each emission region EMA in which the light emitting element LD is disposed. In an embodiment, the second insulating layer INS2 may be selectively disposed only on an upper portion of the light emitting element LD without covering at least opposite ends of the light emitting element LD, i.e., the first end EP1 and the second end EP2. The second insulating layer INS2 may be formed on a portion of the emission region EMA in an independent pattern; however, the present disclosure is not limited thereto.

[0211] In an embodiment, the first contact electrode CNE1 may be disposed in each emission region EMA in which the second insulating layer INS2 is disposed. In an embodiment, the first contact electrode CNE1 may be disposed on the first electrode ELT1 to contact a portion of the first electrode ELT1 disposed in the corresponding emission region EMA. In addition, the first contact electrode CNE1 may be disposed on the first end EP1 of at least one light emitting element LD disposed in the corresponding emission region EMA to contact the first end EP1. Due to the first contact electrode CNE1, the first end EP1 of at least one light emitting element LD disposed in each emission region EMA may be electrically connected to the first electrode ELT1 disposed in the corresponding emission region EMA.

[0212] In an embodiment, a third insulating layer INS3 may be disposed in each emission area EMA in which the first contact electrode CNE1 is disposed. In an embodiment, the third insulating layer INS3 may be formed on the second insulating layer INS2 and the first contact electrode CNE1 disposed in the corresponding emission area EMA.

[0213] In an embodiment, a second contact electrode CNE2 may be provided in each emission region EMA in which the third insulating layer INS3 is provided. In an embodiment, the second contact electrode CNE2 may be provided on the second electrode ELT2 provided in the corresponding emission region EMA to contact a portion of the second electrode ELT2. In addition, the second contact electrode CNE2 may be provided on the second end EP2 of at least one light emitting element LD provided in the corresponding emission region EMA to contact the second end EP2. Due to the second contact electrode CNE2, the second end EP2 of at least one light emitting element LD provided in each emission region EMA may be electrically connected to the second electrode ELT2 provided in the corresponding emission region EMA.

[0214] Meanwhile, the bank BNK may be disposed on the substrate SUB on which the first electrode ELT1 and the second electrode ELT2 are formed. For example, the bank BNK may be formed to surround a pair of emission areas EMA corresponding to a pair of sub-pixels SPXp, respectively, thereby forming a pixel defining layer that divides each pair of emission areas EMA based on a pair of sub-pixels SPXp.

[0215] In an embodiment, the bank BNK may be formed to have a height H2 higher than the height H1 of the first partition wall PW1 and the second partition wall PW2. Such a bank BNK may serve as a dam structure that prevents the LED solution SOL supplied to a pair of emission areas EMA corresponding to any pair of sub-pixels SPXp from being introduced into other adjacent emission areas EMA in the step of supplying the light emitting element LD to the corresponding emission areas EMA, or controls a predetermined amount of solution to be supplied to any pair of emission areas EMA.

[0216] In an embodiment of the present disclosure, any pair of sub-pixels SPXp may be composed of two sub-pixels SPX having the same color. Therefore, the same type of LED solution SOL (e.g., a first LED solution SOL1 in which a plurality of first color light-emitting elements LD1 are diffused) may be supplied to a pair of emission regions EMA (e.g., two emission regions EMA) corresponding to any pair of sub-pixels SPXp. According to an embodiment, even if a pair of emission regions EMA is surrounded by a bank BNK, a desired type of light-emitting element LD may be supplied to a pair of emission regions EMA.

[0217] The bank BNK may have various shapes according to the embodiment. Fig.12 As shown in FIG. 1 , the bank BNK has a curved cross section such as a semicircular cross section or a semi-elliptical cross section, the width of which decreases toward the top. In another embodiment, the bank BNK may be as shown in FIG. Fig.13 In other words, in an embodiment, the bank BNK may have a shape in which the width decreases toward the top, and the shape may be changed in various ways.

[0218] Meanwhile, a fourth insulating layer INS4 may be disposed on the substrate SUB on which the first and second electrodes ELT1 and ELT2, the light emitting element LD, the first and second contact electrodes CNE1 and CNE2, and the bank BNK are disposed. For example, the fourth insulating layer INS4 may be formed in the entire display area DA to cover the upper surface of the substrate SUB on which the first and second electrodes ELT1 and ELT2, the light emitting element LD, the first and second contact electrodes CNE1 and CNE2, and the bank BNK are disposed. In an embodiment, the fourth insulating layer INS4 may include not only at least one inorganic layer and / or organic layer (e.g., an encapsulation layer) for protecting components of the display element layer LDL, but may also include various functional layers, etc.

[0219] Figures 14 to 16 are plan views each showing a display area DA according to an embodiment of the present disclosure. More specifically, Figures 14 to 16Different embodiments related to the shape and arrangement structure of the sub-pixel SPX are shown. For example, Figures 14 to 16 Shown with Figure 8 Different modifications related to the implementation methods of Figures 14 to 16 In the embodiment of the present invention, similar reference numerals are used to represent Figure 8 The components of the embodiments are the same or similar, and their detailed description will be omitted.

[0220] refer to Figures 14 to 16 The shape of each sub-pixel SPX and / or the bank BNK may be changed in various ways. Fig.14 As shown in , the emission area EMA of each sub-pixel SPX or at least one side of the emission area EMA may have a stepped shape. For example, each emission area EMA may have a stepped shape, and for each area in the first direction DR1, the stepped shape has different widths in the second direction DR2. The first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 arranged continuously in the second direction DR2 may form one pixel PXL. In addition, in this embodiment, the bank BNK may also have a stepped shape matching the shape of each sub-pixel SPX (particularly the emission area EMA of the sub-pixel SPX). For example, the bank BNK may be formed as a mesh pattern with a stepped opening.

[0221] In addition, according to an embodiment, each sub-pixel SPX may have a polygonal shape other than a triangular shape. Fig.15 As shown in , each sub-pixel SPX may have an emission area EMA of a polygonal shape, for example, an isosceles trapezoidal shape having a symmetrical structure in the second direction DR2. The first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 arranged continuously in the second direction DR2 may form one pixel PXL having a trapezoidal or inverted trapezoidal shape.

[0222] In addition, a pair of sub-pixels SPX completely surrounded by the bank BNK may be arranged to have a symmetrical structure in the first direction DR1. In this case, the bank BNK may have a polygonal shape, for example, a hexagonal shape having a symmetrical structure in both the first direction DR1 and the second direction DR2. For example, the bank BNK may be formed in a mesh pattern including hexagonal openings.

[0223] In addition, in an embodiment, each sub-pixel SPX may be symmetrical with another adjacent sub-pixel SPX in the first direction DR1, and may be symmetrical with another adjacent sub-pixel SPX in the second direction DR2. Fig.16As shown in , assuming that the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 that are continuously arranged in the second direction DR2 form one pixel PXL, the second color sub-pixel SPX2 may have an emission area EMA2_1 or EMA2_2, the emission area EMA2_1 or EMA2_2 having a shape inverted in the second direction DR2 of the emission area EMA1_1 or EMA1_2 of the first color sub-pixel SPX1, and the third color sub-pixel SPX3 may have an emission area EMA3_1 or EMA3_2, the emission area EMA3_1 or EMA3_2 having a shape inverted in the first direction DR1 and the second direction DR2 of the emission area EMA2_1 or EMA2_2 of the second color sub-pixel SPX2. For example, the first color sub-pixel SPX1, the second color sub-pixel SPX2, and the third color sub-pixel SPX3 may each have an emission area EMA having a right-angled trapezoidal shape having a symmetrical structure in the first direction DR1 and / or the second direction DR2. In this case, the bank BNK may have a pentagonal shape having a symmetrical structure in the first direction DR1. For example, the bank BNK may be formed in a mesh pattern including pentagonal openings, and two openings adjacent to each other in the first direction DR1 may be symmetrical to each other in the first direction DR1. In addition, a pair of openings adjacent to each other in the second direction DR2 may be symmetrical to each other in the second direction DR2.

[0224] As described above, the display device according to various embodiments of the present disclosure may include a plurality of sub-pixels SPX, each of which has various polygonal shapes, such as a triangular shape (or an inverted triangular shape) or a trapezoidal shape (or an inverted trapezoidal shape) or a stepped shape based thereon. In addition, each sub-pixel SPX may be arranged to be symmetrical (e.g., vertically symmetrical) with another sub-pixel SPX of the same color adjacent to the first direction DR1 in the first direction DR1. The bank BNK may have a shape that can completely surround a pair of sub-pixels SPX of the same color (particularly, their emission areas EMA), such as various polygonal shapes, such as a rhombus shape having a vertically symmetrical structure in the first direction DR1 or a stepped shape based thereon.

[0225] According to an embodiment of the present disclosure, the sub-pixel SPX can be divided into smaller sizes to be compactly arranged in the display area DA while ensuring that the width Ws of the sub-pixel SPX is sufficient to accommodate the droplet DRL including the light emitting element LD. Therefore, a display device with high resolution can be realized.

[0226] In addition, in an embodiment of the present disclosure, each pixel PXL can form each unit light emitting device, and each sub-pixel SPX can form each sub-light emitting unit. For example, the first color sub-pixel SPX1 can form a first color sub-light emitting unit, the second color sub-pixel SPX2 can form a second color sub-light emitting unit, and the third color sub-pixel SPX3 can form a third color sub-light emitting unit. In addition, the full-color pixel PXL including the first color sub-pixel SPX1, the second color sub-pixel SPX2 and the third color sub-pixel SPX3 can form a full-color unit light emitting device. In other words, the embodiments of the present disclosure can be applied to display devices, but the scope of application of the present disclosure is not limited to display devices. For example, the embodiments of the present disclosure can be widely applied to other types of devices that require light sources.

[0227] Although the spirit and scope of the present disclosure are described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and replacements may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0228] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. Display equipment, including: Display area; a pair of first color sub-pixels, arranged continuously in the display area in a first direction, and each of the first color sub-pixels includes a first electrode, a second electrode, and a first color light emitting element connected between the first electrode and the second electrode and spaced apart from each other; as well as a bank configured to simultaneously surround the pair of first color sub-pixels arranged consecutively, wherein the bank includes at least two regions having different widths in a corresponding region corresponding to each first color sub-pixel in the pair of first color sub-pixels, Each of the first color sub-pixels in the pair of first color sub-pixels can be driven independently.

2. The display device according to claim 1, wherein: The pair of first color sub-pixels include at least two regions having different widths in each emission region surrounded by the bank, and are arranged to contact each other in a portion having a maximum width of the emission region.

3. The display device according to claim 1, in, The first direction is the vertical direction of the display area, and Wherein, the embankment has a vertically symmetrical shape.

4. The display device according to claim 1, in, The pair of first color sub-pixels include emission areas having a triangular shape and an inverted triangular shape, respectively, and The bank has a quadrilateral shape that surrounds the emission regions of the pair of first color sub-pixels at the same time.

5. The display device according to claim 4, in, The pair of first color sub-pixels are symmetrically arranged in the first direction, and each first color sub-pixel has an emission area in the shape of an isosceles triangle, and The bank has a diamond shape to surround the emission areas of the pair of first color sub-pixels.

6. The display device according to claim 1, in, Each of the pair of first color sub-pixels includes a polygonal emission region having a symmetrical structure in a second direction intersecting the first direction, and The bank has a polygonal shape having a symmetrical structure in both the first direction and the second direction.

7. The display device according to claim 1, wherein: Each of the pair of first color sub-pixels includes a stepped emission region.

8. The display device according to claim 1, further comprising: A second color sub-pixel, arranged to be adjacent to any one of the pair of first color sub-pixels in a second direction intersecting the first direction, and comprising at least one second color light emitting element; as well as The third color sub-pixel is arranged adjacent to the second color sub-pixel in the second direction and includes at least one third color light emitting element.

9. The display device according to claim 8, in, The second color sub-pixel includes an emission area, the emission area of ​​the second color sub-pixel has a shape in which the emission area of ​​any one of the first color sub-pixels is inverted in the first direction, and The third color sub-pixel includes an emission area, and the emission area of ​​the third color sub-pixel has the same shape as the emission area of ​​any one of the first color sub-pixels.

10. The display device according to claim 8, in, The second color sub-pixel is arranged between any one of the first color sub-pixels and the third color sub-pixel, and The emission area of ​​each of the any one first color sub-pixel and the third color sub-pixel has a triangular shape, and the emission area of ​​the second color sub-pixel has an inverted triangular shape.

11. The display device according to claim 10, comprising a trapezoidal pixel including the any one first color sub-pixel, the second color sub-pixel and the third color sub-pixel.

12. The display device according to claim 8, in, The second color sub-pixel includes an emission area, the emission area of ​​the second color sub-pixel has a shape in which the emission area of ​​any one of the first color sub-pixels is inverted in the second direction, and The third color sub-pixel includes an emission area, and the emission area of ​​the third color sub-pixel has a shape in which the emission area of ​​the second color sub-pixel is inverted in the first direction and the second direction.

13. The display device according to claim 1, wherein: The first electrode is disposed in each emission region and connected to a first end of the first color light emitting element; and The second electrode is disposed in each emission region to be spaced apart from the first electrode and connected to a second end of the first color light emitting element.

14. The display device according to claim 13, in, The first electrodes disposed in the pair of first color sub-pixels have the same shape, and Wherein, the second electrodes arranged in the pair of first color sub-pixels have the same shape.

15. The display device according to claim 13, in, The first electrodes disposed in the pair of first color sub-pixels have shapes symmetrical to each other, and The second electrodes disposed in the pair of first color sub-pixels have shapes that are symmetrical to each other.

16. The display device according to claim 13, in, The first electrodes of the pair of first color sub-pixels are spaced apart from each other, and Wherein, the second electrodes of the pair of first color sub-pixels are connected to each other.

17. The display device according to claim 13, wherein: Each first color sub-pixel in the pair of first color sub-pixels further includes: A first partition wall is disposed between the substrate and the first electrode; a second partition wall disposed between the substrate and the second electrode; A first contact electrode is provided on the first end of the first color light emitting element and a portion of the first electrode to electrically connect the first end to the first electrode; and A second contact electrode is provided on the second end of the first color light emitting element and a portion of the second electrode to electrically connect the second end to the second electrode.

18. Display equipment, including: Display area; a pair of emission regions arranged in contact with each other in the display region, and each emission region includes a first electrode, a second electrode, and a first color light emitting element connected between the first electrode and the second electrode and spaced apart from each other; as well as a bank configured to simultaneously surround the pair of emission regions arranged in contact with each other, wherein the bank includes at least two regions having different widths in respective regions corresponding to each of the pair of emission regions, and has a maximum width in a region where the emission regions contact each other, Wherein, each emission area in the pair of emission areas can be driven independently.

19. The display device according to claim 18, in, The pair of emission regions are arranged to vertically contact each other in the display region, and Wherein, the embankment has a vertically symmetrical shape.

20. The display device according to claim 18, wherein: The first electrodes of the pair of emission regions are spaced apart from each other.

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